1 /* 2 * Copyright (C) 2013, 2014 ARM Limited, All Rights Reserved. 3 * Author: Marc Zyngier <marc.zyngier@arm.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program. If not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #define pr_fmt(fmt) "GICv3: " fmt 19 20 #include <linux/acpi.h> 21 #include <linux/cpu.h> 22 #include <linux/cpu_pm.h> 23 #include <linux/delay.h> 24 #include <linux/interrupt.h> 25 #include <linux/irqdomain.h> 26 #include <linux/of.h> 27 #include <linux/of_address.h> 28 #include <linux/of_irq.h> 29 #include <linux/percpu.h> 30 #include <linux/slab.h> 31 32 #include <linux/irqchip.h> 33 #include <linux/irqchip/arm-gic-common.h> 34 #include <linux/irqchip/arm-gic-v3.h> 35 #include <linux/irqchip/irq-partition-percpu.h> 36 37 #include <asm/cputype.h> 38 #include <asm/exception.h> 39 #include <asm/smp_plat.h> 40 #include <asm/virt.h> 41 42 #include "irq-gic-common.h" 43 44 struct redist_region { 45 void __iomem *redist_base; 46 phys_addr_t phys_base; 47 bool single_redist; 48 }; 49 50 struct gic_chip_data { 51 struct fwnode_handle *fwnode; 52 void __iomem *dist_base; 53 struct redist_region *redist_regions; 54 struct rdists rdists; 55 struct irq_domain *domain; 56 u64 redist_stride; 57 u32 nr_redist_regions; 58 unsigned int irq_nr; 59 struct partition_desc *ppi_descs[16]; 60 }; 61 62 static struct gic_chip_data gic_data __read_mostly; 63 static struct static_key supports_deactivate = STATIC_KEY_INIT_TRUE; 64 65 static struct gic_kvm_info gic_v3_kvm_info; 66 67 #define gic_data_rdist() (this_cpu_ptr(gic_data.rdists.rdist)) 68 #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base) 69 #define gic_data_rdist_sgi_base() (gic_data_rdist_rd_base() + SZ_64K) 70 71 /* Our default, arbitrary priority value. Linux only uses one anyway. */ 72 #define DEFAULT_PMR_VALUE 0xf0 73 74 static inline unsigned int gic_irq(struct irq_data *d) 75 { 76 return d->hwirq; 77 } 78 79 static inline int gic_irq_in_rdist(struct irq_data *d) 80 { 81 return gic_irq(d) < 32; 82 } 83 84 static inline void __iomem *gic_dist_base(struct irq_data *d) 85 { 86 if (gic_irq_in_rdist(d)) /* SGI+PPI -> SGI_base for this CPU */ 87 return gic_data_rdist_sgi_base(); 88 89 if (d->hwirq <= 1023) /* SPI -> dist_base */ 90 return gic_data.dist_base; 91 92 return NULL; 93 } 94 95 static void gic_do_wait_for_rwp(void __iomem *base) 96 { 97 u32 count = 1000000; /* 1s! */ 98 99 while (readl_relaxed(base + GICD_CTLR) & GICD_CTLR_RWP) { 100 count--; 101 if (!count) { 102 pr_err_ratelimited("RWP timeout, gone fishing\n"); 103 return; 104 } 105 cpu_relax(); 106 udelay(1); 107 }; 108 } 109 110 /* Wait for completion of a distributor change */ 111 static void gic_dist_wait_for_rwp(void) 112 { 113 gic_do_wait_for_rwp(gic_data.dist_base); 114 } 115 116 /* Wait for completion of a redistributor change */ 117 static void gic_redist_wait_for_rwp(void) 118 { 119 gic_do_wait_for_rwp(gic_data_rdist_rd_base()); 120 } 121 122 #ifdef CONFIG_ARM64 123 124 static u64 __maybe_unused gic_read_iar(void) 125 { 126 if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_23154)) 127 return gic_read_iar_cavium_thunderx(); 128 else 129 return gic_read_iar_common(); 130 } 131 #endif 132 133 static void gic_enable_redist(bool enable) 134 { 135 void __iomem *rbase; 136 u32 count = 1000000; /* 1s! */ 137 u32 val; 138 139 rbase = gic_data_rdist_rd_base(); 140 141 val = readl_relaxed(rbase + GICR_WAKER); 142 if (enable) 143 /* Wake up this CPU redistributor */ 144 val &= ~GICR_WAKER_ProcessorSleep; 145 else 146 val |= GICR_WAKER_ProcessorSleep; 147 writel_relaxed(val, rbase + GICR_WAKER); 148 149 if (!enable) { /* Check that GICR_WAKER is writeable */ 150 val = readl_relaxed(rbase + GICR_WAKER); 151 if (!(val & GICR_WAKER_ProcessorSleep)) 152 return; /* No PM support in this redistributor */ 153 } 154 155 while (--count) { 156 val = readl_relaxed(rbase + GICR_WAKER); 157 if (enable ^ (bool)(val & GICR_WAKER_ChildrenAsleep)) 158 break; 159 cpu_relax(); 160 udelay(1); 161 }; 162 if (!count) 163 pr_err_ratelimited("redistributor failed to %s...\n", 164 enable ? "wakeup" : "sleep"); 165 } 166 167 /* 168 * Routines to disable, enable, EOI and route interrupts 169 */ 170 static int gic_peek_irq(struct irq_data *d, u32 offset) 171 { 172 u32 mask = 1 << (gic_irq(d) % 32); 173 void __iomem *base; 174 175 if (gic_irq_in_rdist(d)) 176 base = gic_data_rdist_sgi_base(); 177 else 178 base = gic_data.dist_base; 179 180 return !!(readl_relaxed(base + offset + (gic_irq(d) / 32) * 4) & mask); 181 } 182 183 static void gic_poke_irq(struct irq_data *d, u32 offset) 184 { 185 u32 mask = 1 << (gic_irq(d) % 32); 186 void (*rwp_wait)(void); 187 void __iomem *base; 188 189 if (gic_irq_in_rdist(d)) { 190 base = gic_data_rdist_sgi_base(); 191 rwp_wait = gic_redist_wait_for_rwp; 192 } else { 193 base = gic_data.dist_base; 194 rwp_wait = gic_dist_wait_for_rwp; 195 } 196 197 writel_relaxed(mask, base + offset + (gic_irq(d) / 32) * 4); 198 rwp_wait(); 199 } 200 201 static void gic_mask_irq(struct irq_data *d) 202 { 203 gic_poke_irq(d, GICD_ICENABLER); 204 } 205 206 static void gic_eoimode1_mask_irq(struct irq_data *d) 207 { 208 gic_mask_irq(d); 209 /* 210 * When masking a forwarded interrupt, make sure it is 211 * deactivated as well. 212 * 213 * This ensures that an interrupt that is getting 214 * disabled/masked will not get "stuck", because there is 215 * noone to deactivate it (guest is being terminated). 216 */ 217 if (irqd_is_forwarded_to_vcpu(d)) 218 gic_poke_irq(d, GICD_ICACTIVER); 219 } 220 221 static void gic_unmask_irq(struct irq_data *d) 222 { 223 gic_poke_irq(d, GICD_ISENABLER); 224 } 225 226 static int gic_irq_set_irqchip_state(struct irq_data *d, 227 enum irqchip_irq_state which, bool val) 228 { 229 u32 reg; 230 231 if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */ 232 return -EINVAL; 233 234 switch (which) { 235 case IRQCHIP_STATE_PENDING: 236 reg = val ? GICD_ISPENDR : GICD_ICPENDR; 237 break; 238 239 case IRQCHIP_STATE_ACTIVE: 240 reg = val ? GICD_ISACTIVER : GICD_ICACTIVER; 241 break; 242 243 case IRQCHIP_STATE_MASKED: 244 reg = val ? GICD_ICENABLER : GICD_ISENABLER; 245 break; 246 247 default: 248 return -EINVAL; 249 } 250 251 gic_poke_irq(d, reg); 252 return 0; 253 } 254 255 static int gic_irq_get_irqchip_state(struct irq_data *d, 256 enum irqchip_irq_state which, bool *val) 257 { 258 if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */ 259 return -EINVAL; 260 261 switch (which) { 262 case IRQCHIP_STATE_PENDING: 263 *val = gic_peek_irq(d, GICD_ISPENDR); 264 break; 265 266 case IRQCHIP_STATE_ACTIVE: 267 *val = gic_peek_irq(d, GICD_ISACTIVER); 268 break; 269 270 case IRQCHIP_STATE_MASKED: 271 *val = !gic_peek_irq(d, GICD_ISENABLER); 272 break; 273 274 default: 275 return -EINVAL; 276 } 277 278 return 0; 279 } 280 281 static void gic_eoi_irq(struct irq_data *d) 282 { 283 gic_write_eoir(gic_irq(d)); 284 } 285 286 static void gic_eoimode1_eoi_irq(struct irq_data *d) 287 { 288 /* 289 * No need to deactivate an LPI, or an interrupt that 290 * is is getting forwarded to a vcpu. 291 */ 292 if (gic_irq(d) >= 8192 || irqd_is_forwarded_to_vcpu(d)) 293 return; 294 gic_write_dir(gic_irq(d)); 295 } 296 297 static int gic_set_type(struct irq_data *d, unsigned int type) 298 { 299 unsigned int irq = gic_irq(d); 300 void (*rwp_wait)(void); 301 void __iomem *base; 302 303 /* Interrupt configuration for SGIs can't be changed */ 304 if (irq < 16) 305 return -EINVAL; 306 307 /* SPIs have restrictions on the supported types */ 308 if (irq >= 32 && type != IRQ_TYPE_LEVEL_HIGH && 309 type != IRQ_TYPE_EDGE_RISING) 310 return -EINVAL; 311 312 if (gic_irq_in_rdist(d)) { 313 base = gic_data_rdist_sgi_base(); 314 rwp_wait = gic_redist_wait_for_rwp; 315 } else { 316 base = gic_data.dist_base; 317 rwp_wait = gic_dist_wait_for_rwp; 318 } 319 320 return gic_configure_irq(irq, type, base, rwp_wait); 321 } 322 323 static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu) 324 { 325 if (vcpu) 326 irqd_set_forwarded_to_vcpu(d); 327 else 328 irqd_clr_forwarded_to_vcpu(d); 329 return 0; 330 } 331 332 static u64 gic_mpidr_to_affinity(unsigned long mpidr) 333 { 334 u64 aff; 335 336 aff = ((u64)MPIDR_AFFINITY_LEVEL(mpidr, 3) << 32 | 337 MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 | 338 MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | 339 MPIDR_AFFINITY_LEVEL(mpidr, 0)); 340 341 return aff; 342 } 343 344 static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) 345 { 346 u32 irqnr; 347 348 do { 349 irqnr = gic_read_iar(); 350 351 if (likely(irqnr > 15 && irqnr < 1020) || irqnr >= 8192) { 352 int err; 353 354 if (static_key_true(&supports_deactivate)) 355 gic_write_eoir(irqnr); 356 357 err = handle_domain_irq(gic_data.domain, irqnr, regs); 358 if (err) { 359 WARN_ONCE(true, "Unexpected interrupt received!\n"); 360 if (static_key_true(&supports_deactivate)) { 361 if (irqnr < 8192) 362 gic_write_dir(irqnr); 363 } else { 364 gic_write_eoir(irqnr); 365 } 366 } 367 continue; 368 } 369 if (irqnr < 16) { 370 gic_write_eoir(irqnr); 371 if (static_key_true(&supports_deactivate)) 372 gic_write_dir(irqnr); 373 #ifdef CONFIG_SMP 374 /* 375 * Unlike GICv2, we don't need an smp_rmb() here. 376 * The control dependency from gic_read_iar to 377 * the ISB in gic_write_eoir is enough to ensure 378 * that any shared data read by handle_IPI will 379 * be read after the ACK. 380 */ 381 handle_IPI(irqnr, regs); 382 #else 383 WARN_ONCE(true, "Unexpected SGI received!\n"); 384 #endif 385 continue; 386 } 387 } while (irqnr != ICC_IAR1_EL1_SPURIOUS); 388 } 389 390 static void __init gic_dist_init(void) 391 { 392 unsigned int i; 393 u64 affinity; 394 void __iomem *base = gic_data.dist_base; 395 396 /* Disable the distributor */ 397 writel_relaxed(0, base + GICD_CTLR); 398 gic_dist_wait_for_rwp(); 399 400 /* 401 * Configure SPIs as non-secure Group-1. This will only matter 402 * if the GIC only has a single security state. This will not 403 * do the right thing if the kernel is running in secure mode, 404 * but that's not the intended use case anyway. 405 */ 406 for (i = 32; i < gic_data.irq_nr; i += 32) 407 writel_relaxed(~0, base + GICD_IGROUPR + i / 8); 408 409 gic_dist_config(base, gic_data.irq_nr, gic_dist_wait_for_rwp); 410 411 /* Enable distributor with ARE, Group1 */ 412 writel_relaxed(GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G1A | GICD_CTLR_ENABLE_G1, 413 base + GICD_CTLR); 414 415 /* 416 * Set all global interrupts to the boot CPU only. ARE must be 417 * enabled. 418 */ 419 affinity = gic_mpidr_to_affinity(cpu_logical_map(smp_processor_id())); 420 for (i = 32; i < gic_data.irq_nr; i++) 421 gic_write_irouter(affinity, base + GICD_IROUTER + i * 8); 422 } 423 424 static int gic_populate_rdist(void) 425 { 426 unsigned long mpidr = cpu_logical_map(smp_processor_id()); 427 u64 typer; 428 u32 aff; 429 int i; 430 431 /* 432 * Convert affinity to a 32bit value that can be matched to 433 * GICR_TYPER bits [63:32]. 434 */ 435 aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 24 | 436 MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 | 437 MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | 438 MPIDR_AFFINITY_LEVEL(mpidr, 0)); 439 440 for (i = 0; i < gic_data.nr_redist_regions; i++) { 441 void __iomem *ptr = gic_data.redist_regions[i].redist_base; 442 u32 reg; 443 444 reg = readl_relaxed(ptr + GICR_PIDR2) & GIC_PIDR2_ARCH_MASK; 445 if (reg != GIC_PIDR2_ARCH_GICv3 && 446 reg != GIC_PIDR2_ARCH_GICv4) { /* We're in trouble... */ 447 pr_warn("No redistributor present @%p\n", ptr); 448 break; 449 } 450 451 do { 452 typer = gic_read_typer(ptr + GICR_TYPER); 453 if ((typer >> 32) == aff) { 454 u64 offset = ptr - gic_data.redist_regions[i].redist_base; 455 gic_data_rdist_rd_base() = ptr; 456 gic_data_rdist()->phys_base = gic_data.redist_regions[i].phys_base + offset; 457 pr_info("CPU%d: found redistributor %lx region %d:%pa\n", 458 smp_processor_id(), mpidr, i, 459 &gic_data_rdist()->phys_base); 460 return 0; 461 } 462 463 if (gic_data.redist_regions[i].single_redist) 464 break; 465 466 if (gic_data.redist_stride) { 467 ptr += gic_data.redist_stride; 468 } else { 469 ptr += SZ_64K * 2; /* Skip RD_base + SGI_base */ 470 if (typer & GICR_TYPER_VLPIS) 471 ptr += SZ_64K * 2; /* Skip VLPI_base + reserved page */ 472 } 473 } while (!(typer & GICR_TYPER_LAST)); 474 } 475 476 /* We couldn't even deal with ourselves... */ 477 WARN(true, "CPU%d: mpidr %lx has no re-distributor!\n", 478 smp_processor_id(), mpidr); 479 return -ENODEV; 480 } 481 482 static void gic_cpu_sys_reg_init(void) 483 { 484 /* 485 * Need to check that the SRE bit has actually been set. If 486 * not, it means that SRE is disabled at EL2. We're going to 487 * die painfully, and there is nothing we can do about it. 488 * 489 * Kindly inform the luser. 490 */ 491 if (!gic_enable_sre()) 492 pr_err("GIC: unable to set SRE (disabled at EL2), panic ahead\n"); 493 494 /* Set priority mask register */ 495 gic_write_pmr(DEFAULT_PMR_VALUE); 496 497 /* 498 * Some firmwares hand over to the kernel with the BPR changed from 499 * its reset value (and with a value large enough to prevent 500 * any pre-emptive interrupts from working at all). Writing a zero 501 * to BPR restores is reset value. 502 */ 503 gic_write_bpr1(0); 504 505 if (static_key_true(&supports_deactivate)) { 506 /* EOI drops priority only (mode 1) */ 507 gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop); 508 } else { 509 /* EOI deactivates interrupt too (mode 0) */ 510 gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop_dir); 511 } 512 513 /* ... and let's hit the road... */ 514 gic_write_grpen1(1); 515 } 516 517 static int gic_dist_supports_lpis(void) 518 { 519 return !!(readl_relaxed(gic_data.dist_base + GICD_TYPER) & GICD_TYPER_LPIS); 520 } 521 522 static void gic_cpu_init(void) 523 { 524 void __iomem *rbase; 525 526 /* Register ourselves with the rest of the world */ 527 if (gic_populate_rdist()) 528 return; 529 530 gic_enable_redist(true); 531 532 rbase = gic_data_rdist_sgi_base(); 533 534 /* Configure SGIs/PPIs as non-secure Group-1 */ 535 writel_relaxed(~0, rbase + GICR_IGROUPR0); 536 537 gic_cpu_config(rbase, gic_redist_wait_for_rwp); 538 539 /* Give LPIs a spin */ 540 if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis()) 541 its_cpu_init(); 542 543 /* initialise system registers */ 544 gic_cpu_sys_reg_init(); 545 } 546 547 #ifdef CONFIG_SMP 548 549 static int gic_starting_cpu(unsigned int cpu) 550 { 551 gic_cpu_init(); 552 return 0; 553 } 554 555 static u16 gic_compute_target_list(int *base_cpu, const struct cpumask *mask, 556 unsigned long cluster_id) 557 { 558 int next_cpu, cpu = *base_cpu; 559 unsigned long mpidr = cpu_logical_map(cpu); 560 u16 tlist = 0; 561 562 while (cpu < nr_cpu_ids) { 563 /* 564 * If we ever get a cluster of more than 16 CPUs, just 565 * scream and skip that CPU. 566 */ 567 if (WARN_ON((mpidr & 0xff) >= 16)) 568 goto out; 569 570 tlist |= 1 << (mpidr & 0xf); 571 572 next_cpu = cpumask_next(cpu, mask); 573 if (next_cpu >= nr_cpu_ids) 574 goto out; 575 cpu = next_cpu; 576 577 mpidr = cpu_logical_map(cpu); 578 579 if (cluster_id != (mpidr & ~0xffUL)) { 580 cpu--; 581 goto out; 582 } 583 } 584 out: 585 *base_cpu = cpu; 586 return tlist; 587 } 588 589 #define MPIDR_TO_SGI_AFFINITY(cluster_id, level) \ 590 (MPIDR_AFFINITY_LEVEL(cluster_id, level) \ 591 << ICC_SGI1R_AFFINITY_## level ##_SHIFT) 592 593 static void gic_send_sgi(u64 cluster_id, u16 tlist, unsigned int irq) 594 { 595 u64 val; 596 597 val = (MPIDR_TO_SGI_AFFINITY(cluster_id, 3) | 598 MPIDR_TO_SGI_AFFINITY(cluster_id, 2) | 599 irq << ICC_SGI1R_SGI_ID_SHIFT | 600 MPIDR_TO_SGI_AFFINITY(cluster_id, 1) | 601 tlist << ICC_SGI1R_TARGET_LIST_SHIFT); 602 603 pr_debug("CPU%d: ICC_SGI1R_EL1 %llx\n", smp_processor_id(), val); 604 gic_write_sgi1r(val); 605 } 606 607 static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) 608 { 609 int cpu; 610 611 if (WARN_ON(irq >= 16)) 612 return; 613 614 /* 615 * Ensure that stores to Normal memory are visible to the 616 * other CPUs before issuing the IPI. 617 */ 618 smp_wmb(); 619 620 for_each_cpu(cpu, mask) { 621 unsigned long cluster_id = cpu_logical_map(cpu) & ~0xffUL; 622 u16 tlist; 623 624 tlist = gic_compute_target_list(&cpu, mask, cluster_id); 625 gic_send_sgi(cluster_id, tlist, irq); 626 } 627 628 /* Force the above writes to ICC_SGI1R_EL1 to be executed */ 629 isb(); 630 } 631 632 static void gic_smp_init(void) 633 { 634 set_smp_cross_call(gic_raise_softirq); 635 cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_GIC_STARTING, 636 "irqchip/arm/gicv3:starting", 637 gic_starting_cpu, NULL); 638 } 639 640 static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, 641 bool force) 642 { 643 unsigned int cpu = cpumask_any_and(mask_val, cpu_online_mask); 644 void __iomem *reg; 645 int enabled; 646 u64 val; 647 648 if (cpu >= nr_cpu_ids) 649 return -EINVAL; 650 651 if (gic_irq_in_rdist(d)) 652 return -EINVAL; 653 654 /* If interrupt was enabled, disable it first */ 655 enabled = gic_peek_irq(d, GICD_ISENABLER); 656 if (enabled) 657 gic_mask_irq(d); 658 659 reg = gic_dist_base(d) + GICD_IROUTER + (gic_irq(d) * 8); 660 val = gic_mpidr_to_affinity(cpu_logical_map(cpu)); 661 662 gic_write_irouter(val, reg); 663 664 /* 665 * If the interrupt was enabled, enabled it again. Otherwise, 666 * just wait for the distributor to have digested our changes. 667 */ 668 if (enabled) 669 gic_unmask_irq(d); 670 else 671 gic_dist_wait_for_rwp(); 672 673 return IRQ_SET_MASK_OK_DONE; 674 } 675 #else 676 #define gic_set_affinity NULL 677 #define gic_smp_init() do { } while(0) 678 #endif 679 680 #ifdef CONFIG_CPU_PM 681 /* Check whether it's single security state view */ 682 static bool gic_dist_security_disabled(void) 683 { 684 return readl_relaxed(gic_data.dist_base + GICD_CTLR) & GICD_CTLR_DS; 685 } 686 687 static int gic_cpu_pm_notifier(struct notifier_block *self, 688 unsigned long cmd, void *v) 689 { 690 if (cmd == CPU_PM_EXIT) { 691 if (gic_dist_security_disabled()) 692 gic_enable_redist(true); 693 gic_cpu_sys_reg_init(); 694 } else if (cmd == CPU_PM_ENTER && gic_dist_security_disabled()) { 695 gic_write_grpen1(0); 696 gic_enable_redist(false); 697 } 698 return NOTIFY_OK; 699 } 700 701 static struct notifier_block gic_cpu_pm_notifier_block = { 702 .notifier_call = gic_cpu_pm_notifier, 703 }; 704 705 static void gic_cpu_pm_init(void) 706 { 707 cpu_pm_register_notifier(&gic_cpu_pm_notifier_block); 708 } 709 710 #else 711 static inline void gic_cpu_pm_init(void) { } 712 #endif /* CONFIG_CPU_PM */ 713 714 static struct irq_chip gic_chip = { 715 .name = "GICv3", 716 .irq_mask = gic_mask_irq, 717 .irq_unmask = gic_unmask_irq, 718 .irq_eoi = gic_eoi_irq, 719 .irq_set_type = gic_set_type, 720 .irq_set_affinity = gic_set_affinity, 721 .irq_get_irqchip_state = gic_irq_get_irqchip_state, 722 .irq_set_irqchip_state = gic_irq_set_irqchip_state, 723 .flags = IRQCHIP_SET_TYPE_MASKED, 724 }; 725 726 static struct irq_chip gic_eoimode1_chip = { 727 .name = "GICv3", 728 .irq_mask = gic_eoimode1_mask_irq, 729 .irq_unmask = gic_unmask_irq, 730 .irq_eoi = gic_eoimode1_eoi_irq, 731 .irq_set_type = gic_set_type, 732 .irq_set_affinity = gic_set_affinity, 733 .irq_get_irqchip_state = gic_irq_get_irqchip_state, 734 .irq_set_irqchip_state = gic_irq_set_irqchip_state, 735 .irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity, 736 .flags = IRQCHIP_SET_TYPE_MASKED, 737 }; 738 739 #define GIC_ID_NR (1U << gic_data.rdists.id_bits) 740 741 static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq, 742 irq_hw_number_t hw) 743 { 744 struct irq_chip *chip = &gic_chip; 745 746 if (static_key_true(&supports_deactivate)) 747 chip = &gic_eoimode1_chip; 748 749 /* SGIs are private to the core kernel */ 750 if (hw < 16) 751 return -EPERM; 752 /* Nothing here */ 753 if (hw >= gic_data.irq_nr && hw < 8192) 754 return -EPERM; 755 /* Off limits */ 756 if (hw >= GIC_ID_NR) 757 return -EPERM; 758 759 /* PPIs */ 760 if (hw < 32) { 761 irq_set_percpu_devid(irq); 762 irq_domain_set_info(d, irq, hw, chip, d->host_data, 763 handle_percpu_devid_irq, NULL, NULL); 764 irq_set_status_flags(irq, IRQ_NOAUTOEN); 765 } 766 /* SPIs */ 767 if (hw >= 32 && hw < gic_data.irq_nr) { 768 irq_domain_set_info(d, irq, hw, chip, d->host_data, 769 handle_fasteoi_irq, NULL, NULL); 770 irq_set_probe(irq); 771 } 772 /* LPIs */ 773 if (hw >= 8192 && hw < GIC_ID_NR) { 774 if (!gic_dist_supports_lpis()) 775 return -EPERM; 776 irq_domain_set_info(d, irq, hw, chip, d->host_data, 777 handle_fasteoi_irq, NULL, NULL); 778 } 779 780 return 0; 781 } 782 783 static int gic_irq_domain_translate(struct irq_domain *d, 784 struct irq_fwspec *fwspec, 785 unsigned long *hwirq, 786 unsigned int *type) 787 { 788 if (is_of_node(fwspec->fwnode)) { 789 if (fwspec->param_count < 3) 790 return -EINVAL; 791 792 switch (fwspec->param[0]) { 793 case 0: /* SPI */ 794 *hwirq = fwspec->param[1] + 32; 795 break; 796 case 1: /* PPI */ 797 *hwirq = fwspec->param[1] + 16; 798 break; 799 case GIC_IRQ_TYPE_LPI: /* LPI */ 800 *hwirq = fwspec->param[1]; 801 break; 802 default: 803 return -EINVAL; 804 } 805 806 *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; 807 return 0; 808 } 809 810 if (is_fwnode_irqchip(fwspec->fwnode)) { 811 if(fwspec->param_count != 2) 812 return -EINVAL; 813 814 *hwirq = fwspec->param[0]; 815 *type = fwspec->param[1]; 816 return 0; 817 } 818 819 return -EINVAL; 820 } 821 822 static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, 823 unsigned int nr_irqs, void *arg) 824 { 825 int i, ret; 826 irq_hw_number_t hwirq; 827 unsigned int type = IRQ_TYPE_NONE; 828 struct irq_fwspec *fwspec = arg; 829 830 ret = gic_irq_domain_translate(domain, fwspec, &hwirq, &type); 831 if (ret) 832 return ret; 833 834 for (i = 0; i < nr_irqs; i++) 835 gic_irq_domain_map(domain, virq + i, hwirq + i); 836 837 return 0; 838 } 839 840 static void gic_irq_domain_free(struct irq_domain *domain, unsigned int virq, 841 unsigned int nr_irqs) 842 { 843 int i; 844 845 for (i = 0; i < nr_irqs; i++) { 846 struct irq_data *d = irq_domain_get_irq_data(domain, virq + i); 847 irq_set_handler(virq + i, NULL); 848 irq_domain_reset_irq_data(d); 849 } 850 } 851 852 static int gic_irq_domain_select(struct irq_domain *d, 853 struct irq_fwspec *fwspec, 854 enum irq_domain_bus_token bus_token) 855 { 856 /* Not for us */ 857 if (fwspec->fwnode != d->fwnode) 858 return 0; 859 860 /* If this is not DT, then we have a single domain */ 861 if (!is_of_node(fwspec->fwnode)) 862 return 1; 863 864 /* 865 * If this is a PPI and we have a 4th (non-null) parameter, 866 * then we need to match the partition domain. 867 */ 868 if (fwspec->param_count >= 4 && 869 fwspec->param[0] == 1 && fwspec->param[3] != 0) 870 return d == partition_get_domain(gic_data.ppi_descs[fwspec->param[1]]); 871 872 return d == gic_data.domain; 873 } 874 875 static const struct irq_domain_ops gic_irq_domain_ops = { 876 .translate = gic_irq_domain_translate, 877 .alloc = gic_irq_domain_alloc, 878 .free = gic_irq_domain_free, 879 .select = gic_irq_domain_select, 880 }; 881 882 static int partition_domain_translate(struct irq_domain *d, 883 struct irq_fwspec *fwspec, 884 unsigned long *hwirq, 885 unsigned int *type) 886 { 887 struct device_node *np; 888 int ret; 889 890 np = of_find_node_by_phandle(fwspec->param[3]); 891 if (WARN_ON(!np)) 892 return -EINVAL; 893 894 ret = partition_translate_id(gic_data.ppi_descs[fwspec->param[1]], 895 of_node_to_fwnode(np)); 896 if (ret < 0) 897 return ret; 898 899 *hwirq = ret; 900 *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; 901 902 return 0; 903 } 904 905 static const struct irq_domain_ops partition_domain_ops = { 906 .translate = partition_domain_translate, 907 .select = gic_irq_domain_select, 908 }; 909 910 static int __init gic_init_bases(void __iomem *dist_base, 911 struct redist_region *rdist_regs, 912 u32 nr_redist_regions, 913 u64 redist_stride, 914 struct fwnode_handle *handle) 915 { 916 u32 typer; 917 int gic_irqs; 918 int err; 919 920 if (!is_hyp_mode_available()) 921 static_key_slow_dec(&supports_deactivate); 922 923 if (static_key_true(&supports_deactivate)) 924 pr_info("GIC: Using split EOI/Deactivate mode\n"); 925 926 gic_data.fwnode = handle; 927 gic_data.dist_base = dist_base; 928 gic_data.redist_regions = rdist_regs; 929 gic_data.nr_redist_regions = nr_redist_regions; 930 gic_data.redist_stride = redist_stride; 931 932 /* 933 * Find out how many interrupts are supported. 934 * The GIC only supports up to 1020 interrupt sources (SGI+PPI+SPI) 935 */ 936 typer = readl_relaxed(gic_data.dist_base + GICD_TYPER); 937 gic_data.rdists.id_bits = GICD_TYPER_ID_BITS(typer); 938 gic_irqs = GICD_TYPER_IRQS(typer); 939 if (gic_irqs > 1020) 940 gic_irqs = 1020; 941 gic_data.irq_nr = gic_irqs; 942 943 gic_data.domain = irq_domain_create_tree(handle, &gic_irq_domain_ops, 944 &gic_data); 945 gic_data.rdists.rdist = alloc_percpu(typeof(*gic_data.rdists.rdist)); 946 947 if (WARN_ON(!gic_data.domain) || WARN_ON(!gic_data.rdists.rdist)) { 948 err = -ENOMEM; 949 goto out_free; 950 } 951 952 set_handle_irq(gic_handle_irq); 953 954 if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis()) 955 its_init(handle, &gic_data.rdists, gic_data.domain); 956 957 gic_smp_init(); 958 gic_dist_init(); 959 gic_cpu_init(); 960 gic_cpu_pm_init(); 961 962 return 0; 963 964 out_free: 965 if (gic_data.domain) 966 irq_domain_remove(gic_data.domain); 967 free_percpu(gic_data.rdists.rdist); 968 return err; 969 } 970 971 static int __init gic_validate_dist_version(void __iomem *dist_base) 972 { 973 u32 reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK; 974 975 if (reg != GIC_PIDR2_ARCH_GICv3 && reg != GIC_PIDR2_ARCH_GICv4) 976 return -ENODEV; 977 978 return 0; 979 } 980 981 static int get_cpu_number(struct device_node *dn) 982 { 983 const __be32 *cell; 984 u64 hwid; 985 int i; 986 987 cell = of_get_property(dn, "reg", NULL); 988 if (!cell) 989 return -1; 990 991 hwid = of_read_number(cell, of_n_addr_cells(dn)); 992 993 /* 994 * Non affinity bits must be set to 0 in the DT 995 */ 996 if (hwid & ~MPIDR_HWID_BITMASK) 997 return -1; 998 999 for (i = 0; i < num_possible_cpus(); i++) 1000 if (cpu_logical_map(i) == hwid) 1001 return i; 1002 1003 return -1; 1004 } 1005 1006 /* Create all possible partitions at boot time */ 1007 static void __init gic_populate_ppi_partitions(struct device_node *gic_node) 1008 { 1009 struct device_node *parts_node, *child_part; 1010 int part_idx = 0, i; 1011 int nr_parts; 1012 struct partition_affinity *parts; 1013 1014 parts_node = of_find_node_by_name(gic_node, "ppi-partitions"); 1015 if (!parts_node) 1016 return; 1017 1018 nr_parts = of_get_child_count(parts_node); 1019 1020 if (!nr_parts) 1021 return; 1022 1023 parts = kzalloc(sizeof(*parts) * nr_parts, GFP_KERNEL); 1024 if (WARN_ON(!parts)) 1025 return; 1026 1027 for_each_child_of_node(parts_node, child_part) { 1028 struct partition_affinity *part; 1029 int n; 1030 1031 part = &parts[part_idx]; 1032 1033 part->partition_id = of_node_to_fwnode(child_part); 1034 1035 pr_info("GIC: PPI partition %s[%d] { ", 1036 child_part->name, part_idx); 1037 1038 n = of_property_count_elems_of_size(child_part, "affinity", 1039 sizeof(u32)); 1040 WARN_ON(n <= 0); 1041 1042 for (i = 0; i < n; i++) { 1043 int err, cpu; 1044 u32 cpu_phandle; 1045 struct device_node *cpu_node; 1046 1047 err = of_property_read_u32_index(child_part, "affinity", 1048 i, &cpu_phandle); 1049 if (WARN_ON(err)) 1050 continue; 1051 1052 cpu_node = of_find_node_by_phandle(cpu_phandle); 1053 if (WARN_ON(!cpu_node)) 1054 continue; 1055 1056 cpu = get_cpu_number(cpu_node); 1057 if (WARN_ON(cpu == -1)) 1058 continue; 1059 1060 pr_cont("%s[%d] ", cpu_node->full_name, cpu); 1061 1062 cpumask_set_cpu(cpu, &part->mask); 1063 } 1064 1065 pr_cont("}\n"); 1066 part_idx++; 1067 } 1068 1069 for (i = 0; i < 16; i++) { 1070 unsigned int irq; 1071 struct partition_desc *desc; 1072 struct irq_fwspec ppi_fwspec = { 1073 .fwnode = gic_data.fwnode, 1074 .param_count = 3, 1075 .param = { 1076 [0] = 1, 1077 [1] = i, 1078 [2] = IRQ_TYPE_NONE, 1079 }, 1080 }; 1081 1082 irq = irq_create_fwspec_mapping(&ppi_fwspec); 1083 if (WARN_ON(!irq)) 1084 continue; 1085 desc = partition_create_desc(gic_data.fwnode, parts, nr_parts, 1086 irq, &partition_domain_ops); 1087 if (WARN_ON(!desc)) 1088 continue; 1089 1090 gic_data.ppi_descs[i] = desc; 1091 } 1092 } 1093 1094 static void __init gic_of_setup_kvm_info(struct device_node *node) 1095 { 1096 int ret; 1097 struct resource r; 1098 u32 gicv_idx; 1099 1100 gic_v3_kvm_info.type = GIC_V3; 1101 1102 gic_v3_kvm_info.maint_irq = irq_of_parse_and_map(node, 0); 1103 if (!gic_v3_kvm_info.maint_irq) 1104 return; 1105 1106 if (of_property_read_u32(node, "#redistributor-regions", 1107 &gicv_idx)) 1108 gicv_idx = 1; 1109 1110 gicv_idx += 3; /* Also skip GICD, GICC, GICH */ 1111 ret = of_address_to_resource(node, gicv_idx, &r); 1112 if (!ret) 1113 gic_v3_kvm_info.vcpu = r; 1114 1115 gic_set_kvm_info(&gic_v3_kvm_info); 1116 } 1117 1118 static int __init gic_of_init(struct device_node *node, struct device_node *parent) 1119 { 1120 void __iomem *dist_base; 1121 struct redist_region *rdist_regs; 1122 u64 redist_stride; 1123 u32 nr_redist_regions; 1124 int err, i; 1125 1126 dist_base = of_iomap(node, 0); 1127 if (!dist_base) { 1128 pr_err("%s: unable to map gic dist registers\n", 1129 node->full_name); 1130 return -ENXIO; 1131 } 1132 1133 err = gic_validate_dist_version(dist_base); 1134 if (err) { 1135 pr_err("%s: no distributor detected, giving up\n", 1136 node->full_name); 1137 goto out_unmap_dist; 1138 } 1139 1140 if (of_property_read_u32(node, "#redistributor-regions", &nr_redist_regions)) 1141 nr_redist_regions = 1; 1142 1143 rdist_regs = kzalloc(sizeof(*rdist_regs) * nr_redist_regions, GFP_KERNEL); 1144 if (!rdist_regs) { 1145 err = -ENOMEM; 1146 goto out_unmap_dist; 1147 } 1148 1149 for (i = 0; i < nr_redist_regions; i++) { 1150 struct resource res; 1151 int ret; 1152 1153 ret = of_address_to_resource(node, 1 + i, &res); 1154 rdist_regs[i].redist_base = of_iomap(node, 1 + i); 1155 if (ret || !rdist_regs[i].redist_base) { 1156 pr_err("%s: couldn't map region %d\n", 1157 node->full_name, i); 1158 err = -ENODEV; 1159 goto out_unmap_rdist; 1160 } 1161 rdist_regs[i].phys_base = res.start; 1162 } 1163 1164 if (of_property_read_u64(node, "redistributor-stride", &redist_stride)) 1165 redist_stride = 0; 1166 1167 err = gic_init_bases(dist_base, rdist_regs, nr_redist_regions, 1168 redist_stride, &node->fwnode); 1169 if (err) 1170 goto out_unmap_rdist; 1171 1172 gic_populate_ppi_partitions(node); 1173 gic_of_setup_kvm_info(node); 1174 return 0; 1175 1176 out_unmap_rdist: 1177 for (i = 0; i < nr_redist_regions; i++) 1178 if (rdist_regs[i].redist_base) 1179 iounmap(rdist_regs[i].redist_base); 1180 kfree(rdist_regs); 1181 out_unmap_dist: 1182 iounmap(dist_base); 1183 return err; 1184 } 1185 1186 IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init); 1187 1188 #ifdef CONFIG_ACPI 1189 static struct 1190 { 1191 void __iomem *dist_base; 1192 struct redist_region *redist_regs; 1193 u32 nr_redist_regions; 1194 bool single_redist; 1195 u32 maint_irq; 1196 int maint_irq_mode; 1197 phys_addr_t vcpu_base; 1198 } acpi_data __initdata; 1199 1200 static void __init 1201 gic_acpi_register_redist(phys_addr_t phys_base, void __iomem *redist_base) 1202 { 1203 static int count = 0; 1204 1205 acpi_data.redist_regs[count].phys_base = phys_base; 1206 acpi_data.redist_regs[count].redist_base = redist_base; 1207 acpi_data.redist_regs[count].single_redist = acpi_data.single_redist; 1208 count++; 1209 } 1210 1211 static int __init 1212 gic_acpi_parse_madt_redist(struct acpi_subtable_header *header, 1213 const unsigned long end) 1214 { 1215 struct acpi_madt_generic_redistributor *redist = 1216 (struct acpi_madt_generic_redistributor *)header; 1217 void __iomem *redist_base; 1218 1219 redist_base = ioremap(redist->base_address, redist->length); 1220 if (!redist_base) { 1221 pr_err("Couldn't map GICR region @%llx\n", redist->base_address); 1222 return -ENOMEM; 1223 } 1224 1225 gic_acpi_register_redist(redist->base_address, redist_base); 1226 return 0; 1227 } 1228 1229 static int __init 1230 gic_acpi_parse_madt_gicc(struct acpi_subtable_header *header, 1231 const unsigned long end) 1232 { 1233 struct acpi_madt_generic_interrupt *gicc = 1234 (struct acpi_madt_generic_interrupt *)header; 1235 u32 reg = readl_relaxed(acpi_data.dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK; 1236 u32 size = reg == GIC_PIDR2_ARCH_GICv4 ? SZ_64K * 4 : SZ_64K * 2; 1237 void __iomem *redist_base; 1238 1239 redist_base = ioremap(gicc->gicr_base_address, size); 1240 if (!redist_base) 1241 return -ENOMEM; 1242 1243 gic_acpi_register_redist(gicc->gicr_base_address, redist_base); 1244 return 0; 1245 } 1246 1247 static int __init gic_acpi_collect_gicr_base(void) 1248 { 1249 acpi_tbl_entry_handler redist_parser; 1250 enum acpi_madt_type type; 1251 1252 if (acpi_data.single_redist) { 1253 type = ACPI_MADT_TYPE_GENERIC_INTERRUPT; 1254 redist_parser = gic_acpi_parse_madt_gicc; 1255 } else { 1256 type = ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR; 1257 redist_parser = gic_acpi_parse_madt_redist; 1258 } 1259 1260 /* Collect redistributor base addresses in GICR entries */ 1261 if (acpi_table_parse_madt(type, redist_parser, 0) > 0) 1262 return 0; 1263 1264 pr_info("No valid GICR entries exist\n"); 1265 return -ENODEV; 1266 } 1267 1268 static int __init gic_acpi_match_gicr(struct acpi_subtable_header *header, 1269 const unsigned long end) 1270 { 1271 /* Subtable presence means that redist exists, that's it */ 1272 return 0; 1273 } 1274 1275 static int __init gic_acpi_match_gicc(struct acpi_subtable_header *header, 1276 const unsigned long end) 1277 { 1278 struct acpi_madt_generic_interrupt *gicc = 1279 (struct acpi_madt_generic_interrupt *)header; 1280 1281 /* 1282 * If GICC is enabled and has valid gicr base address, then it means 1283 * GICR base is presented via GICC 1284 */ 1285 if ((gicc->flags & ACPI_MADT_ENABLED) && gicc->gicr_base_address) 1286 return 0; 1287 1288 return -ENODEV; 1289 } 1290 1291 static int __init gic_acpi_count_gicr_regions(void) 1292 { 1293 int count; 1294 1295 /* 1296 * Count how many redistributor regions we have. It is not allowed 1297 * to mix redistributor description, GICR and GICC subtables have to be 1298 * mutually exclusive. 1299 */ 1300 count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR, 1301 gic_acpi_match_gicr, 0); 1302 if (count > 0) { 1303 acpi_data.single_redist = false; 1304 return count; 1305 } 1306 1307 count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT, 1308 gic_acpi_match_gicc, 0); 1309 if (count > 0) 1310 acpi_data.single_redist = true; 1311 1312 return count; 1313 } 1314 1315 static bool __init acpi_validate_gic_table(struct acpi_subtable_header *header, 1316 struct acpi_probe_entry *ape) 1317 { 1318 struct acpi_madt_generic_distributor *dist; 1319 int count; 1320 1321 dist = (struct acpi_madt_generic_distributor *)header; 1322 if (dist->version != ape->driver_data) 1323 return false; 1324 1325 /* We need to do that exercise anyway, the sooner the better */ 1326 count = gic_acpi_count_gicr_regions(); 1327 if (count <= 0) 1328 return false; 1329 1330 acpi_data.nr_redist_regions = count; 1331 return true; 1332 } 1333 1334 static int __init gic_acpi_parse_virt_madt_gicc(struct acpi_subtable_header *header, 1335 const unsigned long end) 1336 { 1337 struct acpi_madt_generic_interrupt *gicc = 1338 (struct acpi_madt_generic_interrupt *)header; 1339 int maint_irq_mode; 1340 static int first_madt = true; 1341 1342 /* Skip unusable CPUs */ 1343 if (!(gicc->flags & ACPI_MADT_ENABLED)) 1344 return 0; 1345 1346 maint_irq_mode = (gicc->flags & ACPI_MADT_VGIC_IRQ_MODE) ? 1347 ACPI_EDGE_SENSITIVE : ACPI_LEVEL_SENSITIVE; 1348 1349 if (first_madt) { 1350 first_madt = false; 1351 1352 acpi_data.maint_irq = gicc->vgic_interrupt; 1353 acpi_data.maint_irq_mode = maint_irq_mode; 1354 acpi_data.vcpu_base = gicc->gicv_base_address; 1355 1356 return 0; 1357 } 1358 1359 /* 1360 * The maintenance interrupt and GICV should be the same for every CPU 1361 */ 1362 if ((acpi_data.maint_irq != gicc->vgic_interrupt) || 1363 (acpi_data.maint_irq_mode != maint_irq_mode) || 1364 (acpi_data.vcpu_base != gicc->gicv_base_address)) 1365 return -EINVAL; 1366 1367 return 0; 1368 } 1369 1370 static bool __init gic_acpi_collect_virt_info(void) 1371 { 1372 int count; 1373 1374 count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT, 1375 gic_acpi_parse_virt_madt_gicc, 0); 1376 1377 return (count > 0); 1378 } 1379 1380 #define ACPI_GICV3_DIST_MEM_SIZE (SZ_64K) 1381 #define ACPI_GICV2_VCTRL_MEM_SIZE (SZ_4K) 1382 #define ACPI_GICV2_VCPU_MEM_SIZE (SZ_8K) 1383 1384 static void __init gic_acpi_setup_kvm_info(void) 1385 { 1386 int irq; 1387 1388 if (!gic_acpi_collect_virt_info()) { 1389 pr_warn("Unable to get hardware information used for virtualization\n"); 1390 return; 1391 } 1392 1393 gic_v3_kvm_info.type = GIC_V3; 1394 1395 irq = acpi_register_gsi(NULL, acpi_data.maint_irq, 1396 acpi_data.maint_irq_mode, 1397 ACPI_ACTIVE_HIGH); 1398 if (irq <= 0) 1399 return; 1400 1401 gic_v3_kvm_info.maint_irq = irq; 1402 1403 if (acpi_data.vcpu_base) { 1404 struct resource *vcpu = &gic_v3_kvm_info.vcpu; 1405 1406 vcpu->flags = IORESOURCE_MEM; 1407 vcpu->start = acpi_data.vcpu_base; 1408 vcpu->end = vcpu->start + ACPI_GICV2_VCPU_MEM_SIZE - 1; 1409 } 1410 1411 gic_set_kvm_info(&gic_v3_kvm_info); 1412 } 1413 1414 static int __init 1415 gic_acpi_init(struct acpi_subtable_header *header, const unsigned long end) 1416 { 1417 struct acpi_madt_generic_distributor *dist; 1418 struct fwnode_handle *domain_handle; 1419 size_t size; 1420 int i, err; 1421 1422 /* Get distributor base address */ 1423 dist = (struct acpi_madt_generic_distributor *)header; 1424 acpi_data.dist_base = ioremap(dist->base_address, 1425 ACPI_GICV3_DIST_MEM_SIZE); 1426 if (!acpi_data.dist_base) { 1427 pr_err("Unable to map GICD registers\n"); 1428 return -ENOMEM; 1429 } 1430 1431 err = gic_validate_dist_version(acpi_data.dist_base); 1432 if (err) { 1433 pr_err("No distributor detected at @%p, giving up", 1434 acpi_data.dist_base); 1435 goto out_dist_unmap; 1436 } 1437 1438 size = sizeof(*acpi_data.redist_regs) * acpi_data.nr_redist_regions; 1439 acpi_data.redist_regs = kzalloc(size, GFP_KERNEL); 1440 if (!acpi_data.redist_regs) { 1441 err = -ENOMEM; 1442 goto out_dist_unmap; 1443 } 1444 1445 err = gic_acpi_collect_gicr_base(); 1446 if (err) 1447 goto out_redist_unmap; 1448 1449 domain_handle = irq_domain_alloc_fwnode(acpi_data.dist_base); 1450 if (!domain_handle) { 1451 err = -ENOMEM; 1452 goto out_redist_unmap; 1453 } 1454 1455 err = gic_init_bases(acpi_data.dist_base, acpi_data.redist_regs, 1456 acpi_data.nr_redist_regions, 0, domain_handle); 1457 if (err) 1458 goto out_fwhandle_free; 1459 1460 acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, domain_handle); 1461 gic_acpi_setup_kvm_info(); 1462 1463 return 0; 1464 1465 out_fwhandle_free: 1466 irq_domain_free_fwnode(domain_handle); 1467 out_redist_unmap: 1468 for (i = 0; i < acpi_data.nr_redist_regions; i++) 1469 if (acpi_data.redist_regs[i].redist_base) 1470 iounmap(acpi_data.redist_regs[i].redist_base); 1471 kfree(acpi_data.redist_regs); 1472 out_dist_unmap: 1473 iounmap(acpi_data.dist_base); 1474 return err; 1475 } 1476 IRQCHIP_ACPI_DECLARE(gic_v3, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 1477 acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V3, 1478 gic_acpi_init); 1479 IRQCHIP_ACPI_DECLARE(gic_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 1480 acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V4, 1481 gic_acpi_init); 1482 IRQCHIP_ACPI_DECLARE(gic_v3_or_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 1483 acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_NONE, 1484 gic_acpi_init); 1485 #endif 1486