1 /* 2 * Copyright (C) 2013, 2014 ARM Limited, All Rights Reserved. 3 * Author: Marc Zyngier <marc.zyngier@arm.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program. If not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #define pr_fmt(fmt) "GICv3: " fmt 19 20 #include <linux/acpi.h> 21 #include <linux/cpu.h> 22 #include <linux/cpu_pm.h> 23 #include <linux/delay.h> 24 #include <linux/interrupt.h> 25 #include <linux/irqdomain.h> 26 #include <linux/of.h> 27 #include <linux/of_address.h> 28 #include <linux/of_irq.h> 29 #include <linux/percpu.h> 30 #include <linux/slab.h> 31 32 #include <linux/irqchip.h> 33 #include <linux/irqchip/arm-gic-common.h> 34 #include <linux/irqchip/arm-gic-v3.h> 35 #include <linux/irqchip/irq-partition-percpu.h> 36 37 #include <asm/cputype.h> 38 #include <asm/exception.h> 39 #include <asm/smp_plat.h> 40 #include <asm/virt.h> 41 42 #include "irq-gic-common.h" 43 44 struct redist_region { 45 void __iomem *redist_base; 46 phys_addr_t phys_base; 47 bool single_redist; 48 }; 49 50 struct gic_chip_data { 51 struct fwnode_handle *fwnode; 52 void __iomem *dist_base; 53 struct redist_region *redist_regions; 54 struct rdists rdists; 55 struct irq_domain *domain; 56 u64 redist_stride; 57 u32 nr_redist_regions; 58 unsigned int irq_nr; 59 struct partition_desc *ppi_descs[16]; 60 }; 61 62 static struct gic_chip_data gic_data __read_mostly; 63 static struct static_key supports_deactivate = STATIC_KEY_INIT_TRUE; 64 65 static struct gic_kvm_info gic_v3_kvm_info; 66 67 #define gic_data_rdist() (this_cpu_ptr(gic_data.rdists.rdist)) 68 #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base) 69 #define gic_data_rdist_sgi_base() (gic_data_rdist_rd_base() + SZ_64K) 70 71 /* Our default, arbitrary priority value. Linux only uses one anyway. */ 72 #define DEFAULT_PMR_VALUE 0xf0 73 74 static inline unsigned int gic_irq(struct irq_data *d) 75 { 76 return d->hwirq; 77 } 78 79 static inline int gic_irq_in_rdist(struct irq_data *d) 80 { 81 return gic_irq(d) < 32; 82 } 83 84 static inline void __iomem *gic_dist_base(struct irq_data *d) 85 { 86 if (gic_irq_in_rdist(d)) /* SGI+PPI -> SGI_base for this CPU */ 87 return gic_data_rdist_sgi_base(); 88 89 if (d->hwirq <= 1023) /* SPI -> dist_base */ 90 return gic_data.dist_base; 91 92 return NULL; 93 } 94 95 static void gic_do_wait_for_rwp(void __iomem *base) 96 { 97 u32 count = 1000000; /* 1s! */ 98 99 while (readl_relaxed(base + GICD_CTLR) & GICD_CTLR_RWP) { 100 count--; 101 if (!count) { 102 pr_err_ratelimited("RWP timeout, gone fishing\n"); 103 return; 104 } 105 cpu_relax(); 106 udelay(1); 107 }; 108 } 109 110 /* Wait for completion of a distributor change */ 111 static void gic_dist_wait_for_rwp(void) 112 { 113 gic_do_wait_for_rwp(gic_data.dist_base); 114 } 115 116 /* Wait for completion of a redistributor change */ 117 static void gic_redist_wait_for_rwp(void) 118 { 119 gic_do_wait_for_rwp(gic_data_rdist_rd_base()); 120 } 121 122 #ifdef CONFIG_ARM64 123 static DEFINE_STATIC_KEY_FALSE(is_cavium_thunderx); 124 125 static u64 __maybe_unused gic_read_iar(void) 126 { 127 if (static_branch_unlikely(&is_cavium_thunderx)) 128 return gic_read_iar_cavium_thunderx(); 129 else 130 return gic_read_iar_common(); 131 } 132 #endif 133 134 static void gic_enable_redist(bool enable) 135 { 136 void __iomem *rbase; 137 u32 count = 1000000; /* 1s! */ 138 u32 val; 139 140 rbase = gic_data_rdist_rd_base(); 141 142 val = readl_relaxed(rbase + GICR_WAKER); 143 if (enable) 144 /* Wake up this CPU redistributor */ 145 val &= ~GICR_WAKER_ProcessorSleep; 146 else 147 val |= GICR_WAKER_ProcessorSleep; 148 writel_relaxed(val, rbase + GICR_WAKER); 149 150 if (!enable) { /* Check that GICR_WAKER is writeable */ 151 val = readl_relaxed(rbase + GICR_WAKER); 152 if (!(val & GICR_WAKER_ProcessorSleep)) 153 return; /* No PM support in this redistributor */ 154 } 155 156 while (count--) { 157 val = readl_relaxed(rbase + GICR_WAKER); 158 if (enable ^ (bool)(val & GICR_WAKER_ChildrenAsleep)) 159 break; 160 cpu_relax(); 161 udelay(1); 162 }; 163 if (!count) 164 pr_err_ratelimited("redistributor failed to %s...\n", 165 enable ? "wakeup" : "sleep"); 166 } 167 168 /* 169 * Routines to disable, enable, EOI and route interrupts 170 */ 171 static int gic_peek_irq(struct irq_data *d, u32 offset) 172 { 173 u32 mask = 1 << (gic_irq(d) % 32); 174 void __iomem *base; 175 176 if (gic_irq_in_rdist(d)) 177 base = gic_data_rdist_sgi_base(); 178 else 179 base = gic_data.dist_base; 180 181 return !!(readl_relaxed(base + offset + (gic_irq(d) / 32) * 4) & mask); 182 } 183 184 static void gic_poke_irq(struct irq_data *d, u32 offset) 185 { 186 u32 mask = 1 << (gic_irq(d) % 32); 187 void (*rwp_wait)(void); 188 void __iomem *base; 189 190 if (gic_irq_in_rdist(d)) { 191 base = gic_data_rdist_sgi_base(); 192 rwp_wait = gic_redist_wait_for_rwp; 193 } else { 194 base = gic_data.dist_base; 195 rwp_wait = gic_dist_wait_for_rwp; 196 } 197 198 writel_relaxed(mask, base + offset + (gic_irq(d) / 32) * 4); 199 rwp_wait(); 200 } 201 202 static void gic_mask_irq(struct irq_data *d) 203 { 204 gic_poke_irq(d, GICD_ICENABLER); 205 } 206 207 static void gic_eoimode1_mask_irq(struct irq_data *d) 208 { 209 gic_mask_irq(d); 210 /* 211 * When masking a forwarded interrupt, make sure it is 212 * deactivated as well. 213 * 214 * This ensures that an interrupt that is getting 215 * disabled/masked will not get "stuck", because there is 216 * noone to deactivate it (guest is being terminated). 217 */ 218 if (irqd_is_forwarded_to_vcpu(d)) 219 gic_poke_irq(d, GICD_ICACTIVER); 220 } 221 222 static void gic_unmask_irq(struct irq_data *d) 223 { 224 gic_poke_irq(d, GICD_ISENABLER); 225 } 226 227 static int gic_irq_set_irqchip_state(struct irq_data *d, 228 enum irqchip_irq_state which, bool val) 229 { 230 u32 reg; 231 232 if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */ 233 return -EINVAL; 234 235 switch (which) { 236 case IRQCHIP_STATE_PENDING: 237 reg = val ? GICD_ISPENDR : GICD_ICPENDR; 238 break; 239 240 case IRQCHIP_STATE_ACTIVE: 241 reg = val ? GICD_ISACTIVER : GICD_ICACTIVER; 242 break; 243 244 case IRQCHIP_STATE_MASKED: 245 reg = val ? GICD_ICENABLER : GICD_ISENABLER; 246 break; 247 248 default: 249 return -EINVAL; 250 } 251 252 gic_poke_irq(d, reg); 253 return 0; 254 } 255 256 static int gic_irq_get_irqchip_state(struct irq_data *d, 257 enum irqchip_irq_state which, bool *val) 258 { 259 if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */ 260 return -EINVAL; 261 262 switch (which) { 263 case IRQCHIP_STATE_PENDING: 264 *val = gic_peek_irq(d, GICD_ISPENDR); 265 break; 266 267 case IRQCHIP_STATE_ACTIVE: 268 *val = gic_peek_irq(d, GICD_ISACTIVER); 269 break; 270 271 case IRQCHIP_STATE_MASKED: 272 *val = !gic_peek_irq(d, GICD_ISENABLER); 273 break; 274 275 default: 276 return -EINVAL; 277 } 278 279 return 0; 280 } 281 282 static void gic_eoi_irq(struct irq_data *d) 283 { 284 gic_write_eoir(gic_irq(d)); 285 } 286 287 static void gic_eoimode1_eoi_irq(struct irq_data *d) 288 { 289 /* 290 * No need to deactivate an LPI, or an interrupt that 291 * is is getting forwarded to a vcpu. 292 */ 293 if (gic_irq(d) >= 8192 || irqd_is_forwarded_to_vcpu(d)) 294 return; 295 gic_write_dir(gic_irq(d)); 296 } 297 298 static int gic_set_type(struct irq_data *d, unsigned int type) 299 { 300 unsigned int irq = gic_irq(d); 301 void (*rwp_wait)(void); 302 void __iomem *base; 303 304 /* Interrupt configuration for SGIs can't be changed */ 305 if (irq < 16) 306 return -EINVAL; 307 308 /* SPIs have restrictions on the supported types */ 309 if (irq >= 32 && type != IRQ_TYPE_LEVEL_HIGH && 310 type != IRQ_TYPE_EDGE_RISING) 311 return -EINVAL; 312 313 if (gic_irq_in_rdist(d)) { 314 base = gic_data_rdist_sgi_base(); 315 rwp_wait = gic_redist_wait_for_rwp; 316 } else { 317 base = gic_data.dist_base; 318 rwp_wait = gic_dist_wait_for_rwp; 319 } 320 321 return gic_configure_irq(irq, type, base, rwp_wait); 322 } 323 324 static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu) 325 { 326 if (vcpu) 327 irqd_set_forwarded_to_vcpu(d); 328 else 329 irqd_clr_forwarded_to_vcpu(d); 330 return 0; 331 } 332 333 static u64 gic_mpidr_to_affinity(unsigned long mpidr) 334 { 335 u64 aff; 336 337 aff = ((u64)MPIDR_AFFINITY_LEVEL(mpidr, 3) << 32 | 338 MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 | 339 MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | 340 MPIDR_AFFINITY_LEVEL(mpidr, 0)); 341 342 return aff; 343 } 344 345 static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) 346 { 347 u32 irqnr; 348 349 do { 350 irqnr = gic_read_iar(); 351 352 if (likely(irqnr > 15 && irqnr < 1020) || irqnr >= 8192) { 353 int err; 354 355 if (static_key_true(&supports_deactivate)) 356 gic_write_eoir(irqnr); 357 358 err = handle_domain_irq(gic_data.domain, irqnr, regs); 359 if (err) { 360 WARN_ONCE(true, "Unexpected interrupt received!\n"); 361 if (static_key_true(&supports_deactivate)) { 362 if (irqnr < 8192) 363 gic_write_dir(irqnr); 364 } else { 365 gic_write_eoir(irqnr); 366 } 367 } 368 continue; 369 } 370 if (irqnr < 16) { 371 gic_write_eoir(irqnr); 372 if (static_key_true(&supports_deactivate)) 373 gic_write_dir(irqnr); 374 #ifdef CONFIG_SMP 375 /* 376 * Unlike GICv2, we don't need an smp_rmb() here. 377 * The control dependency from gic_read_iar to 378 * the ISB in gic_write_eoir is enough to ensure 379 * that any shared data read by handle_IPI will 380 * be read after the ACK. 381 */ 382 handle_IPI(irqnr, regs); 383 #else 384 WARN_ONCE(true, "Unexpected SGI received!\n"); 385 #endif 386 continue; 387 } 388 } while (irqnr != ICC_IAR1_EL1_SPURIOUS); 389 } 390 391 static void __init gic_dist_init(void) 392 { 393 unsigned int i; 394 u64 affinity; 395 void __iomem *base = gic_data.dist_base; 396 397 /* Disable the distributor */ 398 writel_relaxed(0, base + GICD_CTLR); 399 gic_dist_wait_for_rwp(); 400 401 /* 402 * Configure SPIs as non-secure Group-1. This will only matter 403 * if the GIC only has a single security state. This will not 404 * do the right thing if the kernel is running in secure mode, 405 * but that's not the intended use case anyway. 406 */ 407 for (i = 32; i < gic_data.irq_nr; i += 32) 408 writel_relaxed(~0, base + GICD_IGROUPR + i / 8); 409 410 gic_dist_config(base, gic_data.irq_nr, gic_dist_wait_for_rwp); 411 412 /* Enable distributor with ARE, Group1 */ 413 writel_relaxed(GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G1A | GICD_CTLR_ENABLE_G1, 414 base + GICD_CTLR); 415 416 /* 417 * Set all global interrupts to the boot CPU only. ARE must be 418 * enabled. 419 */ 420 affinity = gic_mpidr_to_affinity(cpu_logical_map(smp_processor_id())); 421 for (i = 32; i < gic_data.irq_nr; i++) 422 gic_write_irouter(affinity, base + GICD_IROUTER + i * 8); 423 } 424 425 static int gic_populate_rdist(void) 426 { 427 unsigned long mpidr = cpu_logical_map(smp_processor_id()); 428 u64 typer; 429 u32 aff; 430 int i; 431 432 /* 433 * Convert affinity to a 32bit value that can be matched to 434 * GICR_TYPER bits [63:32]. 435 */ 436 aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 24 | 437 MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 | 438 MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | 439 MPIDR_AFFINITY_LEVEL(mpidr, 0)); 440 441 for (i = 0; i < gic_data.nr_redist_regions; i++) { 442 void __iomem *ptr = gic_data.redist_regions[i].redist_base; 443 u32 reg; 444 445 reg = readl_relaxed(ptr + GICR_PIDR2) & GIC_PIDR2_ARCH_MASK; 446 if (reg != GIC_PIDR2_ARCH_GICv3 && 447 reg != GIC_PIDR2_ARCH_GICv4) { /* We're in trouble... */ 448 pr_warn("No redistributor present @%p\n", ptr); 449 break; 450 } 451 452 do { 453 typer = gic_read_typer(ptr + GICR_TYPER); 454 if ((typer >> 32) == aff) { 455 u64 offset = ptr - gic_data.redist_regions[i].redist_base; 456 gic_data_rdist_rd_base() = ptr; 457 gic_data_rdist()->phys_base = gic_data.redist_regions[i].phys_base + offset; 458 pr_info("CPU%d: found redistributor %lx region %d:%pa\n", 459 smp_processor_id(), mpidr, i, 460 &gic_data_rdist()->phys_base); 461 return 0; 462 } 463 464 if (gic_data.redist_regions[i].single_redist) 465 break; 466 467 if (gic_data.redist_stride) { 468 ptr += gic_data.redist_stride; 469 } else { 470 ptr += SZ_64K * 2; /* Skip RD_base + SGI_base */ 471 if (typer & GICR_TYPER_VLPIS) 472 ptr += SZ_64K * 2; /* Skip VLPI_base + reserved page */ 473 } 474 } while (!(typer & GICR_TYPER_LAST)); 475 } 476 477 /* We couldn't even deal with ourselves... */ 478 WARN(true, "CPU%d: mpidr %lx has no re-distributor!\n", 479 smp_processor_id(), mpidr); 480 return -ENODEV; 481 } 482 483 static void gic_cpu_sys_reg_init(void) 484 { 485 /* 486 * Need to check that the SRE bit has actually been set. If 487 * not, it means that SRE is disabled at EL2. We're going to 488 * die painfully, and there is nothing we can do about it. 489 * 490 * Kindly inform the luser. 491 */ 492 if (!gic_enable_sre()) 493 pr_err("GIC: unable to set SRE (disabled at EL2), panic ahead\n"); 494 495 /* Set priority mask register */ 496 gic_write_pmr(DEFAULT_PMR_VALUE); 497 498 if (static_key_true(&supports_deactivate)) { 499 /* EOI drops priority only (mode 1) */ 500 gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop); 501 } else { 502 /* EOI deactivates interrupt too (mode 0) */ 503 gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop_dir); 504 } 505 506 /* ... and let's hit the road... */ 507 gic_write_grpen1(1); 508 } 509 510 static int gic_dist_supports_lpis(void) 511 { 512 return !!(readl_relaxed(gic_data.dist_base + GICD_TYPER) & GICD_TYPER_LPIS); 513 } 514 515 static void gic_cpu_init(void) 516 { 517 void __iomem *rbase; 518 519 /* Register ourselves with the rest of the world */ 520 if (gic_populate_rdist()) 521 return; 522 523 gic_enable_redist(true); 524 525 rbase = gic_data_rdist_sgi_base(); 526 527 /* Configure SGIs/PPIs as non-secure Group-1 */ 528 writel_relaxed(~0, rbase + GICR_IGROUPR0); 529 530 gic_cpu_config(rbase, gic_redist_wait_for_rwp); 531 532 /* Give LPIs a spin */ 533 if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis()) 534 its_cpu_init(); 535 536 /* initialise system registers */ 537 gic_cpu_sys_reg_init(); 538 } 539 540 #ifdef CONFIG_SMP 541 542 static int gic_starting_cpu(unsigned int cpu) 543 { 544 gic_cpu_init(); 545 return 0; 546 } 547 548 static u16 gic_compute_target_list(int *base_cpu, const struct cpumask *mask, 549 unsigned long cluster_id) 550 { 551 int cpu = *base_cpu; 552 unsigned long mpidr = cpu_logical_map(cpu); 553 u16 tlist = 0; 554 555 while (cpu < nr_cpu_ids) { 556 /* 557 * If we ever get a cluster of more than 16 CPUs, just 558 * scream and skip that CPU. 559 */ 560 if (WARN_ON((mpidr & 0xff) >= 16)) 561 goto out; 562 563 tlist |= 1 << (mpidr & 0xf); 564 565 cpu = cpumask_next(cpu, mask); 566 if (cpu >= nr_cpu_ids) 567 goto out; 568 569 mpidr = cpu_logical_map(cpu); 570 571 if (cluster_id != (mpidr & ~0xffUL)) { 572 cpu--; 573 goto out; 574 } 575 } 576 out: 577 *base_cpu = cpu; 578 return tlist; 579 } 580 581 #define MPIDR_TO_SGI_AFFINITY(cluster_id, level) \ 582 (MPIDR_AFFINITY_LEVEL(cluster_id, level) \ 583 << ICC_SGI1R_AFFINITY_## level ##_SHIFT) 584 585 static void gic_send_sgi(u64 cluster_id, u16 tlist, unsigned int irq) 586 { 587 u64 val; 588 589 val = (MPIDR_TO_SGI_AFFINITY(cluster_id, 3) | 590 MPIDR_TO_SGI_AFFINITY(cluster_id, 2) | 591 irq << ICC_SGI1R_SGI_ID_SHIFT | 592 MPIDR_TO_SGI_AFFINITY(cluster_id, 1) | 593 tlist << ICC_SGI1R_TARGET_LIST_SHIFT); 594 595 pr_debug("CPU%d: ICC_SGI1R_EL1 %llx\n", smp_processor_id(), val); 596 gic_write_sgi1r(val); 597 } 598 599 static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) 600 { 601 int cpu; 602 603 if (WARN_ON(irq >= 16)) 604 return; 605 606 /* 607 * Ensure that stores to Normal memory are visible to the 608 * other CPUs before issuing the IPI. 609 */ 610 smp_wmb(); 611 612 for_each_cpu(cpu, mask) { 613 unsigned long cluster_id = cpu_logical_map(cpu) & ~0xffUL; 614 u16 tlist; 615 616 tlist = gic_compute_target_list(&cpu, mask, cluster_id); 617 gic_send_sgi(cluster_id, tlist, irq); 618 } 619 620 /* Force the above writes to ICC_SGI1R_EL1 to be executed */ 621 isb(); 622 } 623 624 static void gic_smp_init(void) 625 { 626 set_smp_cross_call(gic_raise_softirq); 627 cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_GICV3_STARTING, 628 "AP_IRQ_GICV3_STARTING", gic_starting_cpu, 629 NULL); 630 } 631 632 static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, 633 bool force) 634 { 635 unsigned int cpu = cpumask_any_and(mask_val, cpu_online_mask); 636 void __iomem *reg; 637 int enabled; 638 u64 val; 639 640 if (gic_irq_in_rdist(d)) 641 return -EINVAL; 642 643 /* If interrupt was enabled, disable it first */ 644 enabled = gic_peek_irq(d, GICD_ISENABLER); 645 if (enabled) 646 gic_mask_irq(d); 647 648 reg = gic_dist_base(d) + GICD_IROUTER + (gic_irq(d) * 8); 649 val = gic_mpidr_to_affinity(cpu_logical_map(cpu)); 650 651 gic_write_irouter(val, reg); 652 653 /* 654 * If the interrupt was enabled, enabled it again. Otherwise, 655 * just wait for the distributor to have digested our changes. 656 */ 657 if (enabled) 658 gic_unmask_irq(d); 659 else 660 gic_dist_wait_for_rwp(); 661 662 return IRQ_SET_MASK_OK_DONE; 663 } 664 #else 665 #define gic_set_affinity NULL 666 #define gic_smp_init() do { } while(0) 667 #endif 668 669 #ifdef CONFIG_CPU_PM 670 static int gic_cpu_pm_notifier(struct notifier_block *self, 671 unsigned long cmd, void *v) 672 { 673 if (cmd == CPU_PM_EXIT) { 674 gic_enable_redist(true); 675 gic_cpu_sys_reg_init(); 676 } else if (cmd == CPU_PM_ENTER) { 677 gic_write_grpen1(0); 678 gic_enable_redist(false); 679 } 680 return NOTIFY_OK; 681 } 682 683 static struct notifier_block gic_cpu_pm_notifier_block = { 684 .notifier_call = gic_cpu_pm_notifier, 685 }; 686 687 static void gic_cpu_pm_init(void) 688 { 689 cpu_pm_register_notifier(&gic_cpu_pm_notifier_block); 690 } 691 692 #else 693 static inline void gic_cpu_pm_init(void) { } 694 #endif /* CONFIG_CPU_PM */ 695 696 static struct irq_chip gic_chip = { 697 .name = "GICv3", 698 .irq_mask = gic_mask_irq, 699 .irq_unmask = gic_unmask_irq, 700 .irq_eoi = gic_eoi_irq, 701 .irq_set_type = gic_set_type, 702 .irq_set_affinity = gic_set_affinity, 703 .irq_get_irqchip_state = gic_irq_get_irqchip_state, 704 .irq_set_irqchip_state = gic_irq_set_irqchip_state, 705 .flags = IRQCHIP_SET_TYPE_MASKED, 706 }; 707 708 static struct irq_chip gic_eoimode1_chip = { 709 .name = "GICv3", 710 .irq_mask = gic_eoimode1_mask_irq, 711 .irq_unmask = gic_unmask_irq, 712 .irq_eoi = gic_eoimode1_eoi_irq, 713 .irq_set_type = gic_set_type, 714 .irq_set_affinity = gic_set_affinity, 715 .irq_get_irqchip_state = gic_irq_get_irqchip_state, 716 .irq_set_irqchip_state = gic_irq_set_irqchip_state, 717 .irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity, 718 .flags = IRQCHIP_SET_TYPE_MASKED, 719 }; 720 721 #define GIC_ID_NR (1U << gic_data.rdists.id_bits) 722 723 static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq, 724 irq_hw_number_t hw) 725 { 726 struct irq_chip *chip = &gic_chip; 727 728 if (static_key_true(&supports_deactivate)) 729 chip = &gic_eoimode1_chip; 730 731 /* SGIs are private to the core kernel */ 732 if (hw < 16) 733 return -EPERM; 734 /* Nothing here */ 735 if (hw >= gic_data.irq_nr && hw < 8192) 736 return -EPERM; 737 /* Off limits */ 738 if (hw >= GIC_ID_NR) 739 return -EPERM; 740 741 /* PPIs */ 742 if (hw < 32) { 743 irq_set_percpu_devid(irq); 744 irq_domain_set_info(d, irq, hw, chip, d->host_data, 745 handle_percpu_devid_irq, NULL, NULL); 746 irq_set_status_flags(irq, IRQ_NOAUTOEN); 747 } 748 /* SPIs */ 749 if (hw >= 32 && hw < gic_data.irq_nr) { 750 irq_domain_set_info(d, irq, hw, chip, d->host_data, 751 handle_fasteoi_irq, NULL, NULL); 752 irq_set_probe(irq); 753 } 754 /* LPIs */ 755 if (hw >= 8192 && hw < GIC_ID_NR) { 756 if (!gic_dist_supports_lpis()) 757 return -EPERM; 758 irq_domain_set_info(d, irq, hw, chip, d->host_data, 759 handle_fasteoi_irq, NULL, NULL); 760 } 761 762 return 0; 763 } 764 765 static int gic_irq_domain_translate(struct irq_domain *d, 766 struct irq_fwspec *fwspec, 767 unsigned long *hwirq, 768 unsigned int *type) 769 { 770 if (is_of_node(fwspec->fwnode)) { 771 if (fwspec->param_count < 3) 772 return -EINVAL; 773 774 switch (fwspec->param[0]) { 775 case 0: /* SPI */ 776 *hwirq = fwspec->param[1] + 32; 777 break; 778 case 1: /* PPI */ 779 *hwirq = fwspec->param[1] + 16; 780 break; 781 case GIC_IRQ_TYPE_LPI: /* LPI */ 782 *hwirq = fwspec->param[1]; 783 break; 784 default: 785 return -EINVAL; 786 } 787 788 *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; 789 return 0; 790 } 791 792 if (is_fwnode_irqchip(fwspec->fwnode)) { 793 if(fwspec->param_count != 2) 794 return -EINVAL; 795 796 *hwirq = fwspec->param[0]; 797 *type = fwspec->param[1]; 798 return 0; 799 } 800 801 return -EINVAL; 802 } 803 804 static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, 805 unsigned int nr_irqs, void *arg) 806 { 807 int i, ret; 808 irq_hw_number_t hwirq; 809 unsigned int type = IRQ_TYPE_NONE; 810 struct irq_fwspec *fwspec = arg; 811 812 ret = gic_irq_domain_translate(domain, fwspec, &hwirq, &type); 813 if (ret) 814 return ret; 815 816 for (i = 0; i < nr_irqs; i++) 817 gic_irq_domain_map(domain, virq + i, hwirq + i); 818 819 return 0; 820 } 821 822 static void gic_irq_domain_free(struct irq_domain *domain, unsigned int virq, 823 unsigned int nr_irqs) 824 { 825 int i; 826 827 for (i = 0; i < nr_irqs; i++) { 828 struct irq_data *d = irq_domain_get_irq_data(domain, virq + i); 829 irq_set_handler(virq + i, NULL); 830 irq_domain_reset_irq_data(d); 831 } 832 } 833 834 static int gic_irq_domain_select(struct irq_domain *d, 835 struct irq_fwspec *fwspec, 836 enum irq_domain_bus_token bus_token) 837 { 838 /* Not for us */ 839 if (fwspec->fwnode != d->fwnode) 840 return 0; 841 842 /* If this is not DT, then we have a single domain */ 843 if (!is_of_node(fwspec->fwnode)) 844 return 1; 845 846 /* 847 * If this is a PPI and we have a 4th (non-null) parameter, 848 * then we need to match the partition domain. 849 */ 850 if (fwspec->param_count >= 4 && 851 fwspec->param[0] == 1 && fwspec->param[3] != 0) 852 return d == partition_get_domain(gic_data.ppi_descs[fwspec->param[1]]); 853 854 return d == gic_data.domain; 855 } 856 857 static const struct irq_domain_ops gic_irq_domain_ops = { 858 .translate = gic_irq_domain_translate, 859 .alloc = gic_irq_domain_alloc, 860 .free = gic_irq_domain_free, 861 .select = gic_irq_domain_select, 862 }; 863 864 static int partition_domain_translate(struct irq_domain *d, 865 struct irq_fwspec *fwspec, 866 unsigned long *hwirq, 867 unsigned int *type) 868 { 869 struct device_node *np; 870 int ret; 871 872 np = of_find_node_by_phandle(fwspec->param[3]); 873 if (WARN_ON(!np)) 874 return -EINVAL; 875 876 ret = partition_translate_id(gic_data.ppi_descs[fwspec->param[1]], 877 of_node_to_fwnode(np)); 878 if (ret < 0) 879 return ret; 880 881 *hwirq = ret; 882 *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; 883 884 return 0; 885 } 886 887 static const struct irq_domain_ops partition_domain_ops = { 888 .translate = partition_domain_translate, 889 .select = gic_irq_domain_select, 890 }; 891 892 static void gicv3_enable_quirks(void) 893 { 894 #ifdef CONFIG_ARM64 895 if (cpus_have_cap(ARM64_WORKAROUND_CAVIUM_23154)) 896 static_branch_enable(&is_cavium_thunderx); 897 #endif 898 } 899 900 static int __init gic_init_bases(void __iomem *dist_base, 901 struct redist_region *rdist_regs, 902 u32 nr_redist_regions, 903 u64 redist_stride, 904 struct fwnode_handle *handle) 905 { 906 struct device_node *node; 907 u32 typer; 908 int gic_irqs; 909 int err; 910 911 if (!is_hyp_mode_available()) 912 static_key_slow_dec(&supports_deactivate); 913 914 if (static_key_true(&supports_deactivate)) 915 pr_info("GIC: Using split EOI/Deactivate mode\n"); 916 917 gic_data.fwnode = handle; 918 gic_data.dist_base = dist_base; 919 gic_data.redist_regions = rdist_regs; 920 gic_data.nr_redist_regions = nr_redist_regions; 921 gic_data.redist_stride = redist_stride; 922 923 gicv3_enable_quirks(); 924 925 /* 926 * Find out how many interrupts are supported. 927 * The GIC only supports up to 1020 interrupt sources (SGI+PPI+SPI) 928 */ 929 typer = readl_relaxed(gic_data.dist_base + GICD_TYPER); 930 gic_data.rdists.id_bits = GICD_TYPER_ID_BITS(typer); 931 gic_irqs = GICD_TYPER_IRQS(typer); 932 if (gic_irqs > 1020) 933 gic_irqs = 1020; 934 gic_data.irq_nr = gic_irqs; 935 936 gic_data.domain = irq_domain_create_tree(handle, &gic_irq_domain_ops, 937 &gic_data); 938 gic_data.rdists.rdist = alloc_percpu(typeof(*gic_data.rdists.rdist)); 939 940 if (WARN_ON(!gic_data.domain) || WARN_ON(!gic_data.rdists.rdist)) { 941 err = -ENOMEM; 942 goto out_free; 943 } 944 945 set_handle_irq(gic_handle_irq); 946 947 node = to_of_node(handle); 948 if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis() && 949 node) /* Temp hack to prevent ITS init for ACPI */ 950 its_init(node, &gic_data.rdists, gic_data.domain); 951 952 gic_smp_init(); 953 gic_dist_init(); 954 gic_cpu_init(); 955 gic_cpu_pm_init(); 956 957 return 0; 958 959 out_free: 960 if (gic_data.domain) 961 irq_domain_remove(gic_data.domain); 962 free_percpu(gic_data.rdists.rdist); 963 return err; 964 } 965 966 static int __init gic_validate_dist_version(void __iomem *dist_base) 967 { 968 u32 reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK; 969 970 if (reg != GIC_PIDR2_ARCH_GICv3 && reg != GIC_PIDR2_ARCH_GICv4) 971 return -ENODEV; 972 973 return 0; 974 } 975 976 static int get_cpu_number(struct device_node *dn) 977 { 978 const __be32 *cell; 979 u64 hwid; 980 int i; 981 982 cell = of_get_property(dn, "reg", NULL); 983 if (!cell) 984 return -1; 985 986 hwid = of_read_number(cell, of_n_addr_cells(dn)); 987 988 /* 989 * Non affinity bits must be set to 0 in the DT 990 */ 991 if (hwid & ~MPIDR_HWID_BITMASK) 992 return -1; 993 994 for (i = 0; i < num_possible_cpus(); i++) 995 if (cpu_logical_map(i) == hwid) 996 return i; 997 998 return -1; 999 } 1000 1001 /* Create all possible partitions at boot time */ 1002 static void __init gic_populate_ppi_partitions(struct device_node *gic_node) 1003 { 1004 struct device_node *parts_node, *child_part; 1005 int part_idx = 0, i; 1006 int nr_parts; 1007 struct partition_affinity *parts; 1008 1009 parts_node = of_find_node_by_name(gic_node, "ppi-partitions"); 1010 if (!parts_node) 1011 return; 1012 1013 nr_parts = of_get_child_count(parts_node); 1014 1015 if (!nr_parts) 1016 return; 1017 1018 parts = kzalloc(sizeof(*parts) * nr_parts, GFP_KERNEL); 1019 if (WARN_ON(!parts)) 1020 return; 1021 1022 for_each_child_of_node(parts_node, child_part) { 1023 struct partition_affinity *part; 1024 int n; 1025 1026 part = &parts[part_idx]; 1027 1028 part->partition_id = of_node_to_fwnode(child_part); 1029 1030 pr_info("GIC: PPI partition %s[%d] { ", 1031 child_part->name, part_idx); 1032 1033 n = of_property_count_elems_of_size(child_part, "affinity", 1034 sizeof(u32)); 1035 WARN_ON(n <= 0); 1036 1037 for (i = 0; i < n; i++) { 1038 int err, cpu; 1039 u32 cpu_phandle; 1040 struct device_node *cpu_node; 1041 1042 err = of_property_read_u32_index(child_part, "affinity", 1043 i, &cpu_phandle); 1044 if (WARN_ON(err)) 1045 continue; 1046 1047 cpu_node = of_find_node_by_phandle(cpu_phandle); 1048 if (WARN_ON(!cpu_node)) 1049 continue; 1050 1051 cpu = get_cpu_number(cpu_node); 1052 if (WARN_ON(cpu == -1)) 1053 continue; 1054 1055 pr_cont("%s[%d] ", cpu_node->full_name, cpu); 1056 1057 cpumask_set_cpu(cpu, &part->mask); 1058 } 1059 1060 pr_cont("}\n"); 1061 part_idx++; 1062 } 1063 1064 for (i = 0; i < 16; i++) { 1065 unsigned int irq; 1066 struct partition_desc *desc; 1067 struct irq_fwspec ppi_fwspec = { 1068 .fwnode = gic_data.fwnode, 1069 .param_count = 3, 1070 .param = { 1071 [0] = 1, 1072 [1] = i, 1073 [2] = IRQ_TYPE_NONE, 1074 }, 1075 }; 1076 1077 irq = irq_create_fwspec_mapping(&ppi_fwspec); 1078 if (WARN_ON(!irq)) 1079 continue; 1080 desc = partition_create_desc(gic_data.fwnode, parts, nr_parts, 1081 irq, &partition_domain_ops); 1082 if (WARN_ON(!desc)) 1083 continue; 1084 1085 gic_data.ppi_descs[i] = desc; 1086 } 1087 } 1088 1089 static void __init gic_of_setup_kvm_info(struct device_node *node) 1090 { 1091 int ret; 1092 struct resource r; 1093 u32 gicv_idx; 1094 1095 gic_v3_kvm_info.type = GIC_V3; 1096 1097 gic_v3_kvm_info.maint_irq = irq_of_parse_and_map(node, 0); 1098 if (!gic_v3_kvm_info.maint_irq) 1099 return; 1100 1101 if (of_property_read_u32(node, "#redistributor-regions", 1102 &gicv_idx)) 1103 gicv_idx = 1; 1104 1105 gicv_idx += 3; /* Also skip GICD, GICC, GICH */ 1106 ret = of_address_to_resource(node, gicv_idx, &r); 1107 if (!ret) 1108 gic_v3_kvm_info.vcpu = r; 1109 1110 gic_set_kvm_info(&gic_v3_kvm_info); 1111 } 1112 1113 static int __init gic_of_init(struct device_node *node, struct device_node *parent) 1114 { 1115 void __iomem *dist_base; 1116 struct redist_region *rdist_regs; 1117 u64 redist_stride; 1118 u32 nr_redist_regions; 1119 int err, i; 1120 1121 dist_base = of_iomap(node, 0); 1122 if (!dist_base) { 1123 pr_err("%s: unable to map gic dist registers\n", 1124 node->full_name); 1125 return -ENXIO; 1126 } 1127 1128 err = gic_validate_dist_version(dist_base); 1129 if (err) { 1130 pr_err("%s: no distributor detected, giving up\n", 1131 node->full_name); 1132 goto out_unmap_dist; 1133 } 1134 1135 if (of_property_read_u32(node, "#redistributor-regions", &nr_redist_regions)) 1136 nr_redist_regions = 1; 1137 1138 rdist_regs = kzalloc(sizeof(*rdist_regs) * nr_redist_regions, GFP_KERNEL); 1139 if (!rdist_regs) { 1140 err = -ENOMEM; 1141 goto out_unmap_dist; 1142 } 1143 1144 for (i = 0; i < nr_redist_regions; i++) { 1145 struct resource res; 1146 int ret; 1147 1148 ret = of_address_to_resource(node, 1 + i, &res); 1149 rdist_regs[i].redist_base = of_iomap(node, 1 + i); 1150 if (ret || !rdist_regs[i].redist_base) { 1151 pr_err("%s: couldn't map region %d\n", 1152 node->full_name, i); 1153 err = -ENODEV; 1154 goto out_unmap_rdist; 1155 } 1156 rdist_regs[i].phys_base = res.start; 1157 } 1158 1159 if (of_property_read_u64(node, "redistributor-stride", &redist_stride)) 1160 redist_stride = 0; 1161 1162 err = gic_init_bases(dist_base, rdist_regs, nr_redist_regions, 1163 redist_stride, &node->fwnode); 1164 if (err) 1165 goto out_unmap_rdist; 1166 1167 gic_populate_ppi_partitions(node); 1168 gic_of_setup_kvm_info(node); 1169 return 0; 1170 1171 out_unmap_rdist: 1172 for (i = 0; i < nr_redist_regions; i++) 1173 if (rdist_regs[i].redist_base) 1174 iounmap(rdist_regs[i].redist_base); 1175 kfree(rdist_regs); 1176 out_unmap_dist: 1177 iounmap(dist_base); 1178 return err; 1179 } 1180 1181 IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init); 1182 1183 #ifdef CONFIG_ACPI 1184 static struct 1185 { 1186 void __iomem *dist_base; 1187 struct redist_region *redist_regs; 1188 u32 nr_redist_regions; 1189 bool single_redist; 1190 u32 maint_irq; 1191 int maint_irq_mode; 1192 phys_addr_t vcpu_base; 1193 } acpi_data __initdata; 1194 1195 static void __init 1196 gic_acpi_register_redist(phys_addr_t phys_base, void __iomem *redist_base) 1197 { 1198 static int count = 0; 1199 1200 acpi_data.redist_regs[count].phys_base = phys_base; 1201 acpi_data.redist_regs[count].redist_base = redist_base; 1202 acpi_data.redist_regs[count].single_redist = acpi_data.single_redist; 1203 count++; 1204 } 1205 1206 static int __init 1207 gic_acpi_parse_madt_redist(struct acpi_subtable_header *header, 1208 const unsigned long end) 1209 { 1210 struct acpi_madt_generic_redistributor *redist = 1211 (struct acpi_madt_generic_redistributor *)header; 1212 void __iomem *redist_base; 1213 1214 redist_base = ioremap(redist->base_address, redist->length); 1215 if (!redist_base) { 1216 pr_err("Couldn't map GICR region @%llx\n", redist->base_address); 1217 return -ENOMEM; 1218 } 1219 1220 gic_acpi_register_redist(redist->base_address, redist_base); 1221 return 0; 1222 } 1223 1224 static int __init 1225 gic_acpi_parse_madt_gicc(struct acpi_subtable_header *header, 1226 const unsigned long end) 1227 { 1228 struct acpi_madt_generic_interrupt *gicc = 1229 (struct acpi_madt_generic_interrupt *)header; 1230 u32 reg = readl_relaxed(acpi_data.dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK; 1231 u32 size = reg == GIC_PIDR2_ARCH_GICv4 ? SZ_64K * 4 : SZ_64K * 2; 1232 void __iomem *redist_base; 1233 1234 redist_base = ioremap(gicc->gicr_base_address, size); 1235 if (!redist_base) 1236 return -ENOMEM; 1237 1238 gic_acpi_register_redist(gicc->gicr_base_address, redist_base); 1239 return 0; 1240 } 1241 1242 static int __init gic_acpi_collect_gicr_base(void) 1243 { 1244 acpi_tbl_entry_handler redist_parser; 1245 enum acpi_madt_type type; 1246 1247 if (acpi_data.single_redist) { 1248 type = ACPI_MADT_TYPE_GENERIC_INTERRUPT; 1249 redist_parser = gic_acpi_parse_madt_gicc; 1250 } else { 1251 type = ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR; 1252 redist_parser = gic_acpi_parse_madt_redist; 1253 } 1254 1255 /* Collect redistributor base addresses in GICR entries */ 1256 if (acpi_table_parse_madt(type, redist_parser, 0) > 0) 1257 return 0; 1258 1259 pr_info("No valid GICR entries exist\n"); 1260 return -ENODEV; 1261 } 1262 1263 static int __init gic_acpi_match_gicr(struct acpi_subtable_header *header, 1264 const unsigned long end) 1265 { 1266 /* Subtable presence means that redist exists, that's it */ 1267 return 0; 1268 } 1269 1270 static int __init gic_acpi_match_gicc(struct acpi_subtable_header *header, 1271 const unsigned long end) 1272 { 1273 struct acpi_madt_generic_interrupt *gicc = 1274 (struct acpi_madt_generic_interrupt *)header; 1275 1276 /* 1277 * If GICC is enabled and has valid gicr base address, then it means 1278 * GICR base is presented via GICC 1279 */ 1280 if ((gicc->flags & ACPI_MADT_ENABLED) && gicc->gicr_base_address) 1281 return 0; 1282 1283 return -ENODEV; 1284 } 1285 1286 static int __init gic_acpi_count_gicr_regions(void) 1287 { 1288 int count; 1289 1290 /* 1291 * Count how many redistributor regions we have. It is not allowed 1292 * to mix redistributor description, GICR and GICC subtables have to be 1293 * mutually exclusive. 1294 */ 1295 count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR, 1296 gic_acpi_match_gicr, 0); 1297 if (count > 0) { 1298 acpi_data.single_redist = false; 1299 return count; 1300 } 1301 1302 count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT, 1303 gic_acpi_match_gicc, 0); 1304 if (count > 0) 1305 acpi_data.single_redist = true; 1306 1307 return count; 1308 } 1309 1310 static bool __init acpi_validate_gic_table(struct acpi_subtable_header *header, 1311 struct acpi_probe_entry *ape) 1312 { 1313 struct acpi_madt_generic_distributor *dist; 1314 int count; 1315 1316 dist = (struct acpi_madt_generic_distributor *)header; 1317 if (dist->version != ape->driver_data) 1318 return false; 1319 1320 /* We need to do that exercise anyway, the sooner the better */ 1321 count = gic_acpi_count_gicr_regions(); 1322 if (count <= 0) 1323 return false; 1324 1325 acpi_data.nr_redist_regions = count; 1326 return true; 1327 } 1328 1329 static int __init gic_acpi_parse_virt_madt_gicc(struct acpi_subtable_header *header, 1330 const unsigned long end) 1331 { 1332 struct acpi_madt_generic_interrupt *gicc = 1333 (struct acpi_madt_generic_interrupt *)header; 1334 int maint_irq_mode; 1335 static int first_madt = true; 1336 1337 /* Skip unusable CPUs */ 1338 if (!(gicc->flags & ACPI_MADT_ENABLED)) 1339 return 0; 1340 1341 maint_irq_mode = (gicc->flags & ACPI_MADT_VGIC_IRQ_MODE) ? 1342 ACPI_EDGE_SENSITIVE : ACPI_LEVEL_SENSITIVE; 1343 1344 if (first_madt) { 1345 first_madt = false; 1346 1347 acpi_data.maint_irq = gicc->vgic_interrupt; 1348 acpi_data.maint_irq_mode = maint_irq_mode; 1349 acpi_data.vcpu_base = gicc->gicv_base_address; 1350 1351 return 0; 1352 } 1353 1354 /* 1355 * The maintenance interrupt and GICV should be the same for every CPU 1356 */ 1357 if ((acpi_data.maint_irq != gicc->vgic_interrupt) || 1358 (acpi_data.maint_irq_mode != maint_irq_mode) || 1359 (acpi_data.vcpu_base != gicc->gicv_base_address)) 1360 return -EINVAL; 1361 1362 return 0; 1363 } 1364 1365 static bool __init gic_acpi_collect_virt_info(void) 1366 { 1367 int count; 1368 1369 count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT, 1370 gic_acpi_parse_virt_madt_gicc, 0); 1371 1372 return (count > 0); 1373 } 1374 1375 #define ACPI_GICV3_DIST_MEM_SIZE (SZ_64K) 1376 #define ACPI_GICV2_VCTRL_MEM_SIZE (SZ_4K) 1377 #define ACPI_GICV2_VCPU_MEM_SIZE (SZ_8K) 1378 1379 static void __init gic_acpi_setup_kvm_info(void) 1380 { 1381 int irq; 1382 1383 if (!gic_acpi_collect_virt_info()) { 1384 pr_warn("Unable to get hardware information used for virtualization\n"); 1385 return; 1386 } 1387 1388 gic_v3_kvm_info.type = GIC_V3; 1389 1390 irq = acpi_register_gsi(NULL, acpi_data.maint_irq, 1391 acpi_data.maint_irq_mode, 1392 ACPI_ACTIVE_HIGH); 1393 if (irq <= 0) 1394 return; 1395 1396 gic_v3_kvm_info.maint_irq = irq; 1397 1398 if (acpi_data.vcpu_base) { 1399 struct resource *vcpu = &gic_v3_kvm_info.vcpu; 1400 1401 vcpu->flags = IORESOURCE_MEM; 1402 vcpu->start = acpi_data.vcpu_base; 1403 vcpu->end = vcpu->start + ACPI_GICV2_VCPU_MEM_SIZE - 1; 1404 } 1405 1406 gic_set_kvm_info(&gic_v3_kvm_info); 1407 } 1408 1409 static int __init 1410 gic_acpi_init(struct acpi_subtable_header *header, const unsigned long end) 1411 { 1412 struct acpi_madt_generic_distributor *dist; 1413 struct fwnode_handle *domain_handle; 1414 size_t size; 1415 int i, err; 1416 1417 /* Get distributor base address */ 1418 dist = (struct acpi_madt_generic_distributor *)header; 1419 acpi_data.dist_base = ioremap(dist->base_address, 1420 ACPI_GICV3_DIST_MEM_SIZE); 1421 if (!acpi_data.dist_base) { 1422 pr_err("Unable to map GICD registers\n"); 1423 return -ENOMEM; 1424 } 1425 1426 err = gic_validate_dist_version(acpi_data.dist_base); 1427 if (err) { 1428 pr_err("No distributor detected at @%p, giving up", 1429 acpi_data.dist_base); 1430 goto out_dist_unmap; 1431 } 1432 1433 size = sizeof(*acpi_data.redist_regs) * acpi_data.nr_redist_regions; 1434 acpi_data.redist_regs = kzalloc(size, GFP_KERNEL); 1435 if (!acpi_data.redist_regs) { 1436 err = -ENOMEM; 1437 goto out_dist_unmap; 1438 } 1439 1440 err = gic_acpi_collect_gicr_base(); 1441 if (err) 1442 goto out_redist_unmap; 1443 1444 domain_handle = irq_domain_alloc_fwnode(acpi_data.dist_base); 1445 if (!domain_handle) { 1446 err = -ENOMEM; 1447 goto out_redist_unmap; 1448 } 1449 1450 err = gic_init_bases(acpi_data.dist_base, acpi_data.redist_regs, 1451 acpi_data.nr_redist_regions, 0, domain_handle); 1452 if (err) 1453 goto out_fwhandle_free; 1454 1455 acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, domain_handle); 1456 gic_acpi_setup_kvm_info(); 1457 1458 return 0; 1459 1460 out_fwhandle_free: 1461 irq_domain_free_fwnode(domain_handle); 1462 out_redist_unmap: 1463 for (i = 0; i < acpi_data.nr_redist_regions; i++) 1464 if (acpi_data.redist_regs[i].redist_base) 1465 iounmap(acpi_data.redist_regs[i].redist_base); 1466 kfree(acpi_data.redist_regs); 1467 out_dist_unmap: 1468 iounmap(acpi_data.dist_base); 1469 return err; 1470 } 1471 IRQCHIP_ACPI_DECLARE(gic_v3, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 1472 acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V3, 1473 gic_acpi_init); 1474 IRQCHIP_ACPI_DECLARE(gic_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 1475 acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V4, 1476 gic_acpi_init); 1477 IRQCHIP_ACPI_DECLARE(gic_v3_or_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 1478 acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_NONE, 1479 gic_acpi_init); 1480 #endif 1481