1 /* 2 * Copyright (C) 2013-2017 ARM Limited, All Rights Reserved. 3 * Author: Marc Zyngier <marc.zyngier@arm.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program. If not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #define pr_fmt(fmt) "GICv3: " fmt 19 20 #include <linux/acpi.h> 21 #include <linux/cpu.h> 22 #include <linux/cpu_pm.h> 23 #include <linux/delay.h> 24 #include <linux/interrupt.h> 25 #include <linux/irqdomain.h> 26 #include <linux/of.h> 27 #include <linux/of_address.h> 28 #include <linux/of_irq.h> 29 #include <linux/percpu.h> 30 #include <linux/slab.h> 31 32 #include <linux/irqchip.h> 33 #include <linux/irqchip/arm-gic-common.h> 34 #include <linux/irqchip/arm-gic-v3.h> 35 #include <linux/irqchip/irq-partition-percpu.h> 36 37 #include <asm/cputype.h> 38 #include <asm/exception.h> 39 #include <asm/smp_plat.h> 40 #include <asm/virt.h> 41 42 #include "irq-gic-common.h" 43 44 struct redist_region { 45 void __iomem *redist_base; 46 phys_addr_t phys_base; 47 bool single_redist; 48 }; 49 50 struct gic_chip_data { 51 struct fwnode_handle *fwnode; 52 void __iomem *dist_base; 53 struct redist_region *redist_regions; 54 struct rdists rdists; 55 struct irq_domain *domain; 56 u64 redist_stride; 57 u32 nr_redist_regions; 58 bool has_rss; 59 unsigned int irq_nr; 60 struct partition_desc *ppi_descs[16]; 61 }; 62 63 static struct gic_chip_data gic_data __read_mostly; 64 static struct static_key supports_deactivate = STATIC_KEY_INIT_TRUE; 65 66 static struct gic_kvm_info gic_v3_kvm_info; 67 static DEFINE_PER_CPU(bool, has_rss); 68 69 #define MPIDR_RS(mpidr) (((mpidr) & 0xF0UL) >> 4) 70 #define gic_data_rdist() (this_cpu_ptr(gic_data.rdists.rdist)) 71 #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base) 72 #define gic_data_rdist_sgi_base() (gic_data_rdist_rd_base() + SZ_64K) 73 74 /* Our default, arbitrary priority value. Linux only uses one anyway. */ 75 #define DEFAULT_PMR_VALUE 0xf0 76 77 static inline unsigned int gic_irq(struct irq_data *d) 78 { 79 return d->hwirq; 80 } 81 82 static inline int gic_irq_in_rdist(struct irq_data *d) 83 { 84 return gic_irq(d) < 32; 85 } 86 87 static inline void __iomem *gic_dist_base(struct irq_data *d) 88 { 89 if (gic_irq_in_rdist(d)) /* SGI+PPI -> SGI_base for this CPU */ 90 return gic_data_rdist_sgi_base(); 91 92 if (d->hwirq <= 1023) /* SPI -> dist_base */ 93 return gic_data.dist_base; 94 95 return NULL; 96 } 97 98 static void gic_do_wait_for_rwp(void __iomem *base) 99 { 100 u32 count = 1000000; /* 1s! */ 101 102 while (readl_relaxed(base + GICD_CTLR) & GICD_CTLR_RWP) { 103 count--; 104 if (!count) { 105 pr_err_ratelimited("RWP timeout, gone fishing\n"); 106 return; 107 } 108 cpu_relax(); 109 udelay(1); 110 }; 111 } 112 113 /* Wait for completion of a distributor change */ 114 static void gic_dist_wait_for_rwp(void) 115 { 116 gic_do_wait_for_rwp(gic_data.dist_base); 117 } 118 119 /* Wait for completion of a redistributor change */ 120 static void gic_redist_wait_for_rwp(void) 121 { 122 gic_do_wait_for_rwp(gic_data_rdist_rd_base()); 123 } 124 125 #ifdef CONFIG_ARM64 126 127 static u64 __maybe_unused gic_read_iar(void) 128 { 129 if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_23154)) 130 return gic_read_iar_cavium_thunderx(); 131 else 132 return gic_read_iar_common(); 133 } 134 #endif 135 136 static void gic_enable_redist(bool enable) 137 { 138 void __iomem *rbase; 139 u32 count = 1000000; /* 1s! */ 140 u32 val; 141 142 rbase = gic_data_rdist_rd_base(); 143 144 val = readl_relaxed(rbase + GICR_WAKER); 145 if (enable) 146 /* Wake up this CPU redistributor */ 147 val &= ~GICR_WAKER_ProcessorSleep; 148 else 149 val |= GICR_WAKER_ProcessorSleep; 150 writel_relaxed(val, rbase + GICR_WAKER); 151 152 if (!enable) { /* Check that GICR_WAKER is writeable */ 153 val = readl_relaxed(rbase + GICR_WAKER); 154 if (!(val & GICR_WAKER_ProcessorSleep)) 155 return; /* No PM support in this redistributor */ 156 } 157 158 while (--count) { 159 val = readl_relaxed(rbase + GICR_WAKER); 160 if (enable ^ (bool)(val & GICR_WAKER_ChildrenAsleep)) 161 break; 162 cpu_relax(); 163 udelay(1); 164 }; 165 if (!count) 166 pr_err_ratelimited("redistributor failed to %s...\n", 167 enable ? "wakeup" : "sleep"); 168 } 169 170 /* 171 * Routines to disable, enable, EOI and route interrupts 172 */ 173 static int gic_peek_irq(struct irq_data *d, u32 offset) 174 { 175 u32 mask = 1 << (gic_irq(d) % 32); 176 void __iomem *base; 177 178 if (gic_irq_in_rdist(d)) 179 base = gic_data_rdist_sgi_base(); 180 else 181 base = gic_data.dist_base; 182 183 return !!(readl_relaxed(base + offset + (gic_irq(d) / 32) * 4) & mask); 184 } 185 186 static void gic_poke_irq(struct irq_data *d, u32 offset) 187 { 188 u32 mask = 1 << (gic_irq(d) % 32); 189 void (*rwp_wait)(void); 190 void __iomem *base; 191 192 if (gic_irq_in_rdist(d)) { 193 base = gic_data_rdist_sgi_base(); 194 rwp_wait = gic_redist_wait_for_rwp; 195 } else { 196 base = gic_data.dist_base; 197 rwp_wait = gic_dist_wait_for_rwp; 198 } 199 200 writel_relaxed(mask, base + offset + (gic_irq(d) / 32) * 4); 201 rwp_wait(); 202 } 203 204 static void gic_mask_irq(struct irq_data *d) 205 { 206 gic_poke_irq(d, GICD_ICENABLER); 207 } 208 209 static void gic_eoimode1_mask_irq(struct irq_data *d) 210 { 211 gic_mask_irq(d); 212 /* 213 * When masking a forwarded interrupt, make sure it is 214 * deactivated as well. 215 * 216 * This ensures that an interrupt that is getting 217 * disabled/masked will not get "stuck", because there is 218 * noone to deactivate it (guest is being terminated). 219 */ 220 if (irqd_is_forwarded_to_vcpu(d)) 221 gic_poke_irq(d, GICD_ICACTIVER); 222 } 223 224 static void gic_unmask_irq(struct irq_data *d) 225 { 226 gic_poke_irq(d, GICD_ISENABLER); 227 } 228 229 static int gic_irq_set_irqchip_state(struct irq_data *d, 230 enum irqchip_irq_state which, bool val) 231 { 232 u32 reg; 233 234 if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */ 235 return -EINVAL; 236 237 switch (which) { 238 case IRQCHIP_STATE_PENDING: 239 reg = val ? GICD_ISPENDR : GICD_ICPENDR; 240 break; 241 242 case IRQCHIP_STATE_ACTIVE: 243 reg = val ? GICD_ISACTIVER : GICD_ICACTIVER; 244 break; 245 246 case IRQCHIP_STATE_MASKED: 247 reg = val ? GICD_ICENABLER : GICD_ISENABLER; 248 break; 249 250 default: 251 return -EINVAL; 252 } 253 254 gic_poke_irq(d, reg); 255 return 0; 256 } 257 258 static int gic_irq_get_irqchip_state(struct irq_data *d, 259 enum irqchip_irq_state which, bool *val) 260 { 261 if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */ 262 return -EINVAL; 263 264 switch (which) { 265 case IRQCHIP_STATE_PENDING: 266 *val = gic_peek_irq(d, GICD_ISPENDR); 267 break; 268 269 case IRQCHIP_STATE_ACTIVE: 270 *val = gic_peek_irq(d, GICD_ISACTIVER); 271 break; 272 273 case IRQCHIP_STATE_MASKED: 274 *val = !gic_peek_irq(d, GICD_ISENABLER); 275 break; 276 277 default: 278 return -EINVAL; 279 } 280 281 return 0; 282 } 283 284 static void gic_eoi_irq(struct irq_data *d) 285 { 286 gic_write_eoir(gic_irq(d)); 287 } 288 289 static void gic_eoimode1_eoi_irq(struct irq_data *d) 290 { 291 /* 292 * No need to deactivate an LPI, or an interrupt that 293 * is is getting forwarded to a vcpu. 294 */ 295 if (gic_irq(d) >= 8192 || irqd_is_forwarded_to_vcpu(d)) 296 return; 297 gic_write_dir(gic_irq(d)); 298 } 299 300 static int gic_set_type(struct irq_data *d, unsigned int type) 301 { 302 unsigned int irq = gic_irq(d); 303 void (*rwp_wait)(void); 304 void __iomem *base; 305 306 /* Interrupt configuration for SGIs can't be changed */ 307 if (irq < 16) 308 return -EINVAL; 309 310 /* SPIs have restrictions on the supported types */ 311 if (irq >= 32 && type != IRQ_TYPE_LEVEL_HIGH && 312 type != IRQ_TYPE_EDGE_RISING) 313 return -EINVAL; 314 315 if (gic_irq_in_rdist(d)) { 316 base = gic_data_rdist_sgi_base(); 317 rwp_wait = gic_redist_wait_for_rwp; 318 } else { 319 base = gic_data.dist_base; 320 rwp_wait = gic_dist_wait_for_rwp; 321 } 322 323 return gic_configure_irq(irq, type, base, rwp_wait); 324 } 325 326 static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu) 327 { 328 if (vcpu) 329 irqd_set_forwarded_to_vcpu(d); 330 else 331 irqd_clr_forwarded_to_vcpu(d); 332 return 0; 333 } 334 335 static u64 gic_mpidr_to_affinity(unsigned long mpidr) 336 { 337 u64 aff; 338 339 aff = ((u64)MPIDR_AFFINITY_LEVEL(mpidr, 3) << 32 | 340 MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 | 341 MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | 342 MPIDR_AFFINITY_LEVEL(mpidr, 0)); 343 344 return aff; 345 } 346 347 static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) 348 { 349 u32 irqnr; 350 351 do { 352 irqnr = gic_read_iar(); 353 354 if (likely(irqnr > 15 && irqnr < 1020) || irqnr >= 8192) { 355 int err; 356 357 if (static_key_true(&supports_deactivate)) 358 gic_write_eoir(irqnr); 359 else 360 isb(); 361 362 err = handle_domain_irq(gic_data.domain, irqnr, regs); 363 if (err) { 364 WARN_ONCE(true, "Unexpected interrupt received!\n"); 365 if (static_key_true(&supports_deactivate)) { 366 if (irqnr < 8192) 367 gic_write_dir(irqnr); 368 } else { 369 gic_write_eoir(irqnr); 370 } 371 } 372 continue; 373 } 374 if (irqnr < 16) { 375 gic_write_eoir(irqnr); 376 if (static_key_true(&supports_deactivate)) 377 gic_write_dir(irqnr); 378 #ifdef CONFIG_SMP 379 /* 380 * Unlike GICv2, we don't need an smp_rmb() here. 381 * The control dependency from gic_read_iar to 382 * the ISB in gic_write_eoir is enough to ensure 383 * that any shared data read by handle_IPI will 384 * be read after the ACK. 385 */ 386 handle_IPI(irqnr, regs); 387 #else 388 WARN_ONCE(true, "Unexpected SGI received!\n"); 389 #endif 390 continue; 391 } 392 } while (irqnr != ICC_IAR1_EL1_SPURIOUS); 393 } 394 395 static void __init gic_dist_init(void) 396 { 397 unsigned int i; 398 u64 affinity; 399 void __iomem *base = gic_data.dist_base; 400 401 /* Disable the distributor */ 402 writel_relaxed(0, base + GICD_CTLR); 403 gic_dist_wait_for_rwp(); 404 405 /* 406 * Configure SPIs as non-secure Group-1. This will only matter 407 * if the GIC only has a single security state. This will not 408 * do the right thing if the kernel is running in secure mode, 409 * but that's not the intended use case anyway. 410 */ 411 for (i = 32; i < gic_data.irq_nr; i += 32) 412 writel_relaxed(~0, base + GICD_IGROUPR + i / 8); 413 414 gic_dist_config(base, gic_data.irq_nr, gic_dist_wait_for_rwp); 415 416 /* Enable distributor with ARE, Group1 */ 417 writel_relaxed(GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G1A | GICD_CTLR_ENABLE_G1, 418 base + GICD_CTLR); 419 420 /* 421 * Set all global interrupts to the boot CPU only. ARE must be 422 * enabled. 423 */ 424 affinity = gic_mpidr_to_affinity(cpu_logical_map(smp_processor_id())); 425 for (i = 32; i < gic_data.irq_nr; i++) 426 gic_write_irouter(affinity, base + GICD_IROUTER + i * 8); 427 } 428 429 static int gic_iterate_rdists(int (*fn)(struct redist_region *, void __iomem *)) 430 { 431 int ret = -ENODEV; 432 int i; 433 434 for (i = 0; i < gic_data.nr_redist_regions; i++) { 435 void __iomem *ptr = gic_data.redist_regions[i].redist_base; 436 u64 typer; 437 u32 reg; 438 439 reg = readl_relaxed(ptr + GICR_PIDR2) & GIC_PIDR2_ARCH_MASK; 440 if (reg != GIC_PIDR2_ARCH_GICv3 && 441 reg != GIC_PIDR2_ARCH_GICv4) { /* We're in trouble... */ 442 pr_warn("No redistributor present @%p\n", ptr); 443 break; 444 } 445 446 do { 447 typer = gic_read_typer(ptr + GICR_TYPER); 448 ret = fn(gic_data.redist_regions + i, ptr); 449 if (!ret) 450 return 0; 451 452 if (gic_data.redist_regions[i].single_redist) 453 break; 454 455 if (gic_data.redist_stride) { 456 ptr += gic_data.redist_stride; 457 } else { 458 ptr += SZ_64K * 2; /* Skip RD_base + SGI_base */ 459 if (typer & GICR_TYPER_VLPIS) 460 ptr += SZ_64K * 2; /* Skip VLPI_base + reserved page */ 461 } 462 } while (!(typer & GICR_TYPER_LAST)); 463 } 464 465 return ret ? -ENODEV : 0; 466 } 467 468 static int __gic_populate_rdist(struct redist_region *region, void __iomem *ptr) 469 { 470 unsigned long mpidr = cpu_logical_map(smp_processor_id()); 471 u64 typer; 472 u32 aff; 473 474 /* 475 * Convert affinity to a 32bit value that can be matched to 476 * GICR_TYPER bits [63:32]. 477 */ 478 aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 24 | 479 MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 | 480 MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | 481 MPIDR_AFFINITY_LEVEL(mpidr, 0)); 482 483 typer = gic_read_typer(ptr + GICR_TYPER); 484 if ((typer >> 32) == aff) { 485 u64 offset = ptr - region->redist_base; 486 gic_data_rdist_rd_base() = ptr; 487 gic_data_rdist()->phys_base = region->phys_base + offset; 488 489 pr_info("CPU%d: found redistributor %lx region %d:%pa\n", 490 smp_processor_id(), mpidr, 491 (int)(region - gic_data.redist_regions), 492 &gic_data_rdist()->phys_base); 493 return 0; 494 } 495 496 /* Try next one */ 497 return 1; 498 } 499 500 static int gic_populate_rdist(void) 501 { 502 if (gic_iterate_rdists(__gic_populate_rdist) == 0) 503 return 0; 504 505 /* We couldn't even deal with ourselves... */ 506 WARN(true, "CPU%d: mpidr %lx has no re-distributor!\n", 507 smp_processor_id(), 508 (unsigned long)cpu_logical_map(smp_processor_id())); 509 return -ENODEV; 510 } 511 512 static int __gic_update_vlpi_properties(struct redist_region *region, 513 void __iomem *ptr) 514 { 515 u64 typer = gic_read_typer(ptr + GICR_TYPER); 516 gic_data.rdists.has_vlpis &= !!(typer & GICR_TYPER_VLPIS); 517 gic_data.rdists.has_direct_lpi &= !!(typer & GICR_TYPER_DirectLPIS); 518 519 return 1; 520 } 521 522 static void gic_update_vlpi_properties(void) 523 { 524 gic_iterate_rdists(__gic_update_vlpi_properties); 525 pr_info("%sVLPI support, %sdirect LPI support\n", 526 !gic_data.rdists.has_vlpis ? "no " : "", 527 !gic_data.rdists.has_direct_lpi ? "no " : ""); 528 } 529 530 static void gic_cpu_sys_reg_init(void) 531 { 532 int i, cpu = smp_processor_id(); 533 u64 mpidr = cpu_logical_map(cpu); 534 u64 need_rss = MPIDR_RS(mpidr); 535 536 /* 537 * Need to check that the SRE bit has actually been set. If 538 * not, it means that SRE is disabled at EL2. We're going to 539 * die painfully, and there is nothing we can do about it. 540 * 541 * Kindly inform the luser. 542 */ 543 if (!gic_enable_sre()) 544 pr_err("GIC: unable to set SRE (disabled at EL2), panic ahead\n"); 545 546 /* Set priority mask register */ 547 gic_write_pmr(DEFAULT_PMR_VALUE); 548 549 /* 550 * Some firmwares hand over to the kernel with the BPR changed from 551 * its reset value (and with a value large enough to prevent 552 * any pre-emptive interrupts from working at all). Writing a zero 553 * to BPR restores is reset value. 554 */ 555 gic_write_bpr1(0); 556 557 if (static_key_true(&supports_deactivate)) { 558 /* EOI drops priority only (mode 1) */ 559 gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop); 560 } else { 561 /* EOI deactivates interrupt too (mode 0) */ 562 gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop_dir); 563 } 564 565 /* ... and let's hit the road... */ 566 gic_write_grpen1(1); 567 568 /* Keep the RSS capability status in per_cpu variable */ 569 per_cpu(has_rss, cpu) = !!(gic_read_ctlr() & ICC_CTLR_EL1_RSS); 570 571 /* Check all the CPUs have capable of sending SGIs to other CPUs */ 572 for_each_online_cpu(i) { 573 bool have_rss = per_cpu(has_rss, i) && per_cpu(has_rss, cpu); 574 575 need_rss |= MPIDR_RS(cpu_logical_map(i)); 576 if (need_rss && (!have_rss)) 577 pr_crit("CPU%d (%lx) can't SGI CPU%d (%lx), no RSS\n", 578 cpu, (unsigned long)mpidr, 579 i, (unsigned long)cpu_logical_map(i)); 580 } 581 582 /** 583 * GIC spec says, when ICC_CTLR_EL1.RSS==1 and GICD_TYPER.RSS==0, 584 * writing ICC_ASGI1R_EL1 register with RS != 0 is a CONSTRAINED 585 * UNPREDICTABLE choice of : 586 * - The write is ignored. 587 * - The RS field is treated as 0. 588 */ 589 if (need_rss && (!gic_data.has_rss)) 590 pr_crit_once("RSS is required but GICD doesn't support it\n"); 591 } 592 593 static int gic_dist_supports_lpis(void) 594 { 595 return !!(readl_relaxed(gic_data.dist_base + GICD_TYPER) & GICD_TYPER_LPIS); 596 } 597 598 static void gic_cpu_init(void) 599 { 600 void __iomem *rbase; 601 602 /* Register ourselves with the rest of the world */ 603 if (gic_populate_rdist()) 604 return; 605 606 gic_enable_redist(true); 607 608 rbase = gic_data_rdist_sgi_base(); 609 610 /* Configure SGIs/PPIs as non-secure Group-1 */ 611 writel_relaxed(~0, rbase + GICR_IGROUPR0); 612 613 gic_cpu_config(rbase, gic_redist_wait_for_rwp); 614 615 /* Give LPIs a spin */ 616 if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis()) 617 its_cpu_init(); 618 619 /* initialise system registers */ 620 gic_cpu_sys_reg_init(); 621 } 622 623 #ifdef CONFIG_SMP 624 625 #define MPIDR_TO_SGI_RS(mpidr) (MPIDR_RS(mpidr) << ICC_SGI1R_RS_SHIFT) 626 #define MPIDR_TO_SGI_CLUSTER_ID(mpidr) ((mpidr) & ~0xFUL) 627 628 static int gic_starting_cpu(unsigned int cpu) 629 { 630 gic_cpu_init(); 631 return 0; 632 } 633 634 static u16 gic_compute_target_list(int *base_cpu, const struct cpumask *mask, 635 unsigned long cluster_id) 636 { 637 int next_cpu, cpu = *base_cpu; 638 unsigned long mpidr = cpu_logical_map(cpu); 639 u16 tlist = 0; 640 641 while (cpu < nr_cpu_ids) { 642 tlist |= 1 << (mpidr & 0xf); 643 644 next_cpu = cpumask_next(cpu, mask); 645 if (next_cpu >= nr_cpu_ids) 646 goto out; 647 cpu = next_cpu; 648 649 mpidr = cpu_logical_map(cpu); 650 651 if (cluster_id != MPIDR_TO_SGI_CLUSTER_ID(mpidr)) { 652 cpu--; 653 goto out; 654 } 655 } 656 out: 657 *base_cpu = cpu; 658 return tlist; 659 } 660 661 #define MPIDR_TO_SGI_AFFINITY(cluster_id, level) \ 662 (MPIDR_AFFINITY_LEVEL(cluster_id, level) \ 663 << ICC_SGI1R_AFFINITY_## level ##_SHIFT) 664 665 static void gic_send_sgi(u64 cluster_id, u16 tlist, unsigned int irq) 666 { 667 u64 val; 668 669 val = (MPIDR_TO_SGI_AFFINITY(cluster_id, 3) | 670 MPIDR_TO_SGI_AFFINITY(cluster_id, 2) | 671 irq << ICC_SGI1R_SGI_ID_SHIFT | 672 MPIDR_TO_SGI_AFFINITY(cluster_id, 1) | 673 MPIDR_TO_SGI_RS(cluster_id) | 674 tlist << ICC_SGI1R_TARGET_LIST_SHIFT); 675 676 pr_debug("CPU%d: ICC_SGI1R_EL1 %llx\n", smp_processor_id(), val); 677 gic_write_sgi1r(val); 678 } 679 680 static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) 681 { 682 int cpu; 683 684 if (WARN_ON(irq >= 16)) 685 return; 686 687 /* 688 * Ensure that stores to Normal memory are visible to the 689 * other CPUs before issuing the IPI. 690 */ 691 smp_wmb(); 692 693 for_each_cpu(cpu, mask) { 694 u64 cluster_id = MPIDR_TO_SGI_CLUSTER_ID(cpu_logical_map(cpu)); 695 u16 tlist; 696 697 tlist = gic_compute_target_list(&cpu, mask, cluster_id); 698 gic_send_sgi(cluster_id, tlist, irq); 699 } 700 701 /* Force the above writes to ICC_SGI1R_EL1 to be executed */ 702 isb(); 703 } 704 705 static void gic_smp_init(void) 706 { 707 set_smp_cross_call(gic_raise_softirq); 708 cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_GIC_STARTING, 709 "irqchip/arm/gicv3:starting", 710 gic_starting_cpu, NULL); 711 } 712 713 static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, 714 bool force) 715 { 716 unsigned int cpu; 717 void __iomem *reg; 718 int enabled; 719 u64 val; 720 721 if (force) 722 cpu = cpumask_first(mask_val); 723 else 724 cpu = cpumask_any_and(mask_val, cpu_online_mask); 725 726 if (cpu >= nr_cpu_ids) 727 return -EINVAL; 728 729 if (gic_irq_in_rdist(d)) 730 return -EINVAL; 731 732 /* If interrupt was enabled, disable it first */ 733 enabled = gic_peek_irq(d, GICD_ISENABLER); 734 if (enabled) 735 gic_mask_irq(d); 736 737 reg = gic_dist_base(d) + GICD_IROUTER + (gic_irq(d) * 8); 738 val = gic_mpidr_to_affinity(cpu_logical_map(cpu)); 739 740 gic_write_irouter(val, reg); 741 742 /* 743 * If the interrupt was enabled, enabled it again. Otherwise, 744 * just wait for the distributor to have digested our changes. 745 */ 746 if (enabled) 747 gic_unmask_irq(d); 748 else 749 gic_dist_wait_for_rwp(); 750 751 irq_data_update_effective_affinity(d, cpumask_of(cpu)); 752 753 return IRQ_SET_MASK_OK_DONE; 754 } 755 #else 756 #define gic_set_affinity NULL 757 #define gic_smp_init() do { } while(0) 758 #endif 759 760 #ifdef CONFIG_CPU_PM 761 /* Check whether it's single security state view */ 762 static bool gic_dist_security_disabled(void) 763 { 764 return readl_relaxed(gic_data.dist_base + GICD_CTLR) & GICD_CTLR_DS; 765 } 766 767 static int gic_cpu_pm_notifier(struct notifier_block *self, 768 unsigned long cmd, void *v) 769 { 770 if (cmd == CPU_PM_EXIT) { 771 if (gic_dist_security_disabled()) 772 gic_enable_redist(true); 773 gic_cpu_sys_reg_init(); 774 } else if (cmd == CPU_PM_ENTER && gic_dist_security_disabled()) { 775 gic_write_grpen1(0); 776 gic_enable_redist(false); 777 } 778 return NOTIFY_OK; 779 } 780 781 static struct notifier_block gic_cpu_pm_notifier_block = { 782 .notifier_call = gic_cpu_pm_notifier, 783 }; 784 785 static void gic_cpu_pm_init(void) 786 { 787 cpu_pm_register_notifier(&gic_cpu_pm_notifier_block); 788 } 789 790 #else 791 static inline void gic_cpu_pm_init(void) { } 792 #endif /* CONFIG_CPU_PM */ 793 794 static struct irq_chip gic_chip = { 795 .name = "GICv3", 796 .irq_mask = gic_mask_irq, 797 .irq_unmask = gic_unmask_irq, 798 .irq_eoi = gic_eoi_irq, 799 .irq_set_type = gic_set_type, 800 .irq_set_affinity = gic_set_affinity, 801 .irq_get_irqchip_state = gic_irq_get_irqchip_state, 802 .irq_set_irqchip_state = gic_irq_set_irqchip_state, 803 .flags = IRQCHIP_SET_TYPE_MASKED, 804 }; 805 806 static struct irq_chip gic_eoimode1_chip = { 807 .name = "GICv3", 808 .irq_mask = gic_eoimode1_mask_irq, 809 .irq_unmask = gic_unmask_irq, 810 .irq_eoi = gic_eoimode1_eoi_irq, 811 .irq_set_type = gic_set_type, 812 .irq_set_affinity = gic_set_affinity, 813 .irq_get_irqchip_state = gic_irq_get_irqchip_state, 814 .irq_set_irqchip_state = gic_irq_set_irqchip_state, 815 .irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity, 816 .flags = IRQCHIP_SET_TYPE_MASKED, 817 }; 818 819 #define GIC_ID_NR (1U << gic_data.rdists.id_bits) 820 821 static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq, 822 irq_hw_number_t hw) 823 { 824 struct irq_chip *chip = &gic_chip; 825 826 if (static_key_true(&supports_deactivate)) 827 chip = &gic_eoimode1_chip; 828 829 /* SGIs are private to the core kernel */ 830 if (hw < 16) 831 return -EPERM; 832 /* Nothing here */ 833 if (hw >= gic_data.irq_nr && hw < 8192) 834 return -EPERM; 835 /* Off limits */ 836 if (hw >= GIC_ID_NR) 837 return -EPERM; 838 839 /* PPIs */ 840 if (hw < 32) { 841 irq_set_percpu_devid(irq); 842 irq_domain_set_info(d, irq, hw, chip, d->host_data, 843 handle_percpu_devid_irq, NULL, NULL); 844 irq_set_status_flags(irq, IRQ_NOAUTOEN); 845 } 846 /* SPIs */ 847 if (hw >= 32 && hw < gic_data.irq_nr) { 848 irq_domain_set_info(d, irq, hw, chip, d->host_data, 849 handle_fasteoi_irq, NULL, NULL); 850 irq_set_probe(irq); 851 irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(irq))); 852 } 853 /* LPIs */ 854 if (hw >= 8192 && hw < GIC_ID_NR) { 855 if (!gic_dist_supports_lpis()) 856 return -EPERM; 857 irq_domain_set_info(d, irq, hw, chip, d->host_data, 858 handle_fasteoi_irq, NULL, NULL); 859 } 860 861 return 0; 862 } 863 864 static int gic_irq_domain_translate(struct irq_domain *d, 865 struct irq_fwspec *fwspec, 866 unsigned long *hwirq, 867 unsigned int *type) 868 { 869 if (is_of_node(fwspec->fwnode)) { 870 if (fwspec->param_count < 3) 871 return -EINVAL; 872 873 switch (fwspec->param[0]) { 874 case 0: /* SPI */ 875 *hwirq = fwspec->param[1] + 32; 876 break; 877 case 1: /* PPI */ 878 *hwirq = fwspec->param[1] + 16; 879 break; 880 case GIC_IRQ_TYPE_LPI: /* LPI */ 881 *hwirq = fwspec->param[1]; 882 break; 883 default: 884 return -EINVAL; 885 } 886 887 *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; 888 return 0; 889 } 890 891 if (is_fwnode_irqchip(fwspec->fwnode)) { 892 if(fwspec->param_count != 2) 893 return -EINVAL; 894 895 *hwirq = fwspec->param[0]; 896 *type = fwspec->param[1]; 897 return 0; 898 } 899 900 return -EINVAL; 901 } 902 903 static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, 904 unsigned int nr_irqs, void *arg) 905 { 906 int i, ret; 907 irq_hw_number_t hwirq; 908 unsigned int type = IRQ_TYPE_NONE; 909 struct irq_fwspec *fwspec = arg; 910 911 ret = gic_irq_domain_translate(domain, fwspec, &hwirq, &type); 912 if (ret) 913 return ret; 914 915 for (i = 0; i < nr_irqs; i++) { 916 ret = gic_irq_domain_map(domain, virq + i, hwirq + i); 917 if (ret) 918 return ret; 919 } 920 921 return 0; 922 } 923 924 static void gic_irq_domain_free(struct irq_domain *domain, unsigned int virq, 925 unsigned int nr_irqs) 926 { 927 int i; 928 929 for (i = 0; i < nr_irqs; i++) { 930 struct irq_data *d = irq_domain_get_irq_data(domain, virq + i); 931 irq_set_handler(virq + i, NULL); 932 irq_domain_reset_irq_data(d); 933 } 934 } 935 936 static int gic_irq_domain_select(struct irq_domain *d, 937 struct irq_fwspec *fwspec, 938 enum irq_domain_bus_token bus_token) 939 { 940 /* Not for us */ 941 if (fwspec->fwnode != d->fwnode) 942 return 0; 943 944 /* If this is not DT, then we have a single domain */ 945 if (!is_of_node(fwspec->fwnode)) 946 return 1; 947 948 /* 949 * If this is a PPI and we have a 4th (non-null) parameter, 950 * then we need to match the partition domain. 951 */ 952 if (fwspec->param_count >= 4 && 953 fwspec->param[0] == 1 && fwspec->param[3] != 0) 954 return d == partition_get_domain(gic_data.ppi_descs[fwspec->param[1]]); 955 956 return d == gic_data.domain; 957 } 958 959 static const struct irq_domain_ops gic_irq_domain_ops = { 960 .translate = gic_irq_domain_translate, 961 .alloc = gic_irq_domain_alloc, 962 .free = gic_irq_domain_free, 963 .select = gic_irq_domain_select, 964 }; 965 966 static int partition_domain_translate(struct irq_domain *d, 967 struct irq_fwspec *fwspec, 968 unsigned long *hwirq, 969 unsigned int *type) 970 { 971 struct device_node *np; 972 int ret; 973 974 np = of_find_node_by_phandle(fwspec->param[3]); 975 if (WARN_ON(!np)) 976 return -EINVAL; 977 978 ret = partition_translate_id(gic_data.ppi_descs[fwspec->param[1]], 979 of_node_to_fwnode(np)); 980 if (ret < 0) 981 return ret; 982 983 *hwirq = ret; 984 *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; 985 986 return 0; 987 } 988 989 static const struct irq_domain_ops partition_domain_ops = { 990 .translate = partition_domain_translate, 991 .select = gic_irq_domain_select, 992 }; 993 994 static int __init gic_init_bases(void __iomem *dist_base, 995 struct redist_region *rdist_regs, 996 u32 nr_redist_regions, 997 u64 redist_stride, 998 struct fwnode_handle *handle) 999 { 1000 u32 typer; 1001 int gic_irqs; 1002 int err; 1003 1004 if (!is_hyp_mode_available()) 1005 static_key_slow_dec(&supports_deactivate); 1006 1007 if (static_key_true(&supports_deactivate)) 1008 pr_info("GIC: Using split EOI/Deactivate mode\n"); 1009 1010 gic_data.fwnode = handle; 1011 gic_data.dist_base = dist_base; 1012 gic_data.redist_regions = rdist_regs; 1013 gic_data.nr_redist_regions = nr_redist_regions; 1014 gic_data.redist_stride = redist_stride; 1015 1016 /* 1017 * Find out how many interrupts are supported. 1018 * The GIC only supports up to 1020 interrupt sources (SGI+PPI+SPI) 1019 */ 1020 typer = readl_relaxed(gic_data.dist_base + GICD_TYPER); 1021 gic_data.rdists.id_bits = GICD_TYPER_ID_BITS(typer); 1022 gic_irqs = GICD_TYPER_IRQS(typer); 1023 if (gic_irqs > 1020) 1024 gic_irqs = 1020; 1025 gic_data.irq_nr = gic_irqs; 1026 1027 gic_data.domain = irq_domain_create_tree(handle, &gic_irq_domain_ops, 1028 &gic_data); 1029 gic_data.rdists.rdist = alloc_percpu(typeof(*gic_data.rdists.rdist)); 1030 gic_data.rdists.has_vlpis = true; 1031 gic_data.rdists.has_direct_lpi = true; 1032 1033 if (WARN_ON(!gic_data.domain) || WARN_ON(!gic_data.rdists.rdist)) { 1034 err = -ENOMEM; 1035 goto out_free; 1036 } 1037 1038 gic_data.has_rss = !!(typer & GICD_TYPER_RSS); 1039 pr_info("Distributor has %sRange Selector support\n", 1040 gic_data.has_rss ? "" : "no "); 1041 1042 set_handle_irq(gic_handle_irq); 1043 1044 gic_update_vlpi_properties(); 1045 1046 if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis()) 1047 its_init(handle, &gic_data.rdists, gic_data.domain); 1048 1049 gic_smp_init(); 1050 gic_dist_init(); 1051 gic_cpu_init(); 1052 gic_cpu_pm_init(); 1053 1054 return 0; 1055 1056 out_free: 1057 if (gic_data.domain) 1058 irq_domain_remove(gic_data.domain); 1059 free_percpu(gic_data.rdists.rdist); 1060 return err; 1061 } 1062 1063 static int __init gic_validate_dist_version(void __iomem *dist_base) 1064 { 1065 u32 reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK; 1066 1067 if (reg != GIC_PIDR2_ARCH_GICv3 && reg != GIC_PIDR2_ARCH_GICv4) 1068 return -ENODEV; 1069 1070 return 0; 1071 } 1072 1073 /* Create all possible partitions at boot time */ 1074 static void __init gic_populate_ppi_partitions(struct device_node *gic_node) 1075 { 1076 struct device_node *parts_node, *child_part; 1077 int part_idx = 0, i; 1078 int nr_parts; 1079 struct partition_affinity *parts; 1080 1081 parts_node = of_get_child_by_name(gic_node, "ppi-partitions"); 1082 if (!parts_node) 1083 return; 1084 1085 nr_parts = of_get_child_count(parts_node); 1086 1087 if (!nr_parts) 1088 goto out_put_node; 1089 1090 parts = kzalloc(sizeof(*parts) * nr_parts, GFP_KERNEL); 1091 if (WARN_ON(!parts)) 1092 goto out_put_node; 1093 1094 for_each_child_of_node(parts_node, child_part) { 1095 struct partition_affinity *part; 1096 int n; 1097 1098 part = &parts[part_idx]; 1099 1100 part->partition_id = of_node_to_fwnode(child_part); 1101 1102 pr_info("GIC: PPI partition %s[%d] { ", 1103 child_part->name, part_idx); 1104 1105 n = of_property_count_elems_of_size(child_part, "affinity", 1106 sizeof(u32)); 1107 WARN_ON(n <= 0); 1108 1109 for (i = 0; i < n; i++) { 1110 int err, cpu; 1111 u32 cpu_phandle; 1112 struct device_node *cpu_node; 1113 1114 err = of_property_read_u32_index(child_part, "affinity", 1115 i, &cpu_phandle); 1116 if (WARN_ON(err)) 1117 continue; 1118 1119 cpu_node = of_find_node_by_phandle(cpu_phandle); 1120 if (WARN_ON(!cpu_node)) 1121 continue; 1122 1123 cpu = of_cpu_node_to_id(cpu_node); 1124 if (WARN_ON(cpu < 0)) 1125 continue; 1126 1127 pr_cont("%pOF[%d] ", cpu_node, cpu); 1128 1129 cpumask_set_cpu(cpu, &part->mask); 1130 } 1131 1132 pr_cont("}\n"); 1133 part_idx++; 1134 } 1135 1136 for (i = 0; i < 16; i++) { 1137 unsigned int irq; 1138 struct partition_desc *desc; 1139 struct irq_fwspec ppi_fwspec = { 1140 .fwnode = gic_data.fwnode, 1141 .param_count = 3, 1142 .param = { 1143 [0] = 1, 1144 [1] = i, 1145 [2] = IRQ_TYPE_NONE, 1146 }, 1147 }; 1148 1149 irq = irq_create_fwspec_mapping(&ppi_fwspec); 1150 if (WARN_ON(!irq)) 1151 continue; 1152 desc = partition_create_desc(gic_data.fwnode, parts, nr_parts, 1153 irq, &partition_domain_ops); 1154 if (WARN_ON(!desc)) 1155 continue; 1156 1157 gic_data.ppi_descs[i] = desc; 1158 } 1159 1160 out_put_node: 1161 of_node_put(parts_node); 1162 } 1163 1164 static void __init gic_of_setup_kvm_info(struct device_node *node) 1165 { 1166 int ret; 1167 struct resource r; 1168 u32 gicv_idx; 1169 1170 gic_v3_kvm_info.type = GIC_V3; 1171 1172 gic_v3_kvm_info.maint_irq = irq_of_parse_and_map(node, 0); 1173 if (!gic_v3_kvm_info.maint_irq) 1174 return; 1175 1176 if (of_property_read_u32(node, "#redistributor-regions", 1177 &gicv_idx)) 1178 gicv_idx = 1; 1179 1180 gicv_idx += 3; /* Also skip GICD, GICC, GICH */ 1181 ret = of_address_to_resource(node, gicv_idx, &r); 1182 if (!ret) 1183 gic_v3_kvm_info.vcpu = r; 1184 1185 gic_v3_kvm_info.has_v4 = gic_data.rdists.has_vlpis; 1186 gic_set_kvm_info(&gic_v3_kvm_info); 1187 } 1188 1189 static int __init gic_of_init(struct device_node *node, struct device_node *parent) 1190 { 1191 void __iomem *dist_base; 1192 struct redist_region *rdist_regs; 1193 u64 redist_stride; 1194 u32 nr_redist_regions; 1195 int err, i; 1196 1197 dist_base = of_iomap(node, 0); 1198 if (!dist_base) { 1199 pr_err("%pOF: unable to map gic dist registers\n", node); 1200 return -ENXIO; 1201 } 1202 1203 err = gic_validate_dist_version(dist_base); 1204 if (err) { 1205 pr_err("%pOF: no distributor detected, giving up\n", node); 1206 goto out_unmap_dist; 1207 } 1208 1209 if (of_property_read_u32(node, "#redistributor-regions", &nr_redist_regions)) 1210 nr_redist_regions = 1; 1211 1212 rdist_regs = kzalloc(sizeof(*rdist_regs) * nr_redist_regions, GFP_KERNEL); 1213 if (!rdist_regs) { 1214 err = -ENOMEM; 1215 goto out_unmap_dist; 1216 } 1217 1218 for (i = 0; i < nr_redist_regions; i++) { 1219 struct resource res; 1220 int ret; 1221 1222 ret = of_address_to_resource(node, 1 + i, &res); 1223 rdist_regs[i].redist_base = of_iomap(node, 1 + i); 1224 if (ret || !rdist_regs[i].redist_base) { 1225 pr_err("%pOF: couldn't map region %d\n", node, i); 1226 err = -ENODEV; 1227 goto out_unmap_rdist; 1228 } 1229 rdist_regs[i].phys_base = res.start; 1230 } 1231 1232 if (of_property_read_u64(node, "redistributor-stride", &redist_stride)) 1233 redist_stride = 0; 1234 1235 err = gic_init_bases(dist_base, rdist_regs, nr_redist_regions, 1236 redist_stride, &node->fwnode); 1237 if (err) 1238 goto out_unmap_rdist; 1239 1240 gic_populate_ppi_partitions(node); 1241 1242 if (static_key_true(&supports_deactivate)) 1243 gic_of_setup_kvm_info(node); 1244 return 0; 1245 1246 out_unmap_rdist: 1247 for (i = 0; i < nr_redist_regions; i++) 1248 if (rdist_regs[i].redist_base) 1249 iounmap(rdist_regs[i].redist_base); 1250 kfree(rdist_regs); 1251 out_unmap_dist: 1252 iounmap(dist_base); 1253 return err; 1254 } 1255 1256 IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init); 1257 1258 #ifdef CONFIG_ACPI 1259 static struct 1260 { 1261 void __iomem *dist_base; 1262 struct redist_region *redist_regs; 1263 u32 nr_redist_regions; 1264 bool single_redist; 1265 u32 maint_irq; 1266 int maint_irq_mode; 1267 phys_addr_t vcpu_base; 1268 } acpi_data __initdata; 1269 1270 static void __init 1271 gic_acpi_register_redist(phys_addr_t phys_base, void __iomem *redist_base) 1272 { 1273 static int count = 0; 1274 1275 acpi_data.redist_regs[count].phys_base = phys_base; 1276 acpi_data.redist_regs[count].redist_base = redist_base; 1277 acpi_data.redist_regs[count].single_redist = acpi_data.single_redist; 1278 count++; 1279 } 1280 1281 static int __init 1282 gic_acpi_parse_madt_redist(struct acpi_subtable_header *header, 1283 const unsigned long end) 1284 { 1285 struct acpi_madt_generic_redistributor *redist = 1286 (struct acpi_madt_generic_redistributor *)header; 1287 void __iomem *redist_base; 1288 1289 redist_base = ioremap(redist->base_address, redist->length); 1290 if (!redist_base) { 1291 pr_err("Couldn't map GICR region @%llx\n", redist->base_address); 1292 return -ENOMEM; 1293 } 1294 1295 gic_acpi_register_redist(redist->base_address, redist_base); 1296 return 0; 1297 } 1298 1299 static int __init 1300 gic_acpi_parse_madt_gicc(struct acpi_subtable_header *header, 1301 const unsigned long end) 1302 { 1303 struct acpi_madt_generic_interrupt *gicc = 1304 (struct acpi_madt_generic_interrupt *)header; 1305 u32 reg = readl_relaxed(acpi_data.dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK; 1306 u32 size = reg == GIC_PIDR2_ARCH_GICv4 ? SZ_64K * 4 : SZ_64K * 2; 1307 void __iomem *redist_base; 1308 1309 /* GICC entry which has !ACPI_MADT_ENABLED is not unusable so skip */ 1310 if (!(gicc->flags & ACPI_MADT_ENABLED)) 1311 return 0; 1312 1313 redist_base = ioremap(gicc->gicr_base_address, size); 1314 if (!redist_base) 1315 return -ENOMEM; 1316 1317 gic_acpi_register_redist(gicc->gicr_base_address, redist_base); 1318 return 0; 1319 } 1320 1321 static int __init gic_acpi_collect_gicr_base(void) 1322 { 1323 acpi_tbl_entry_handler redist_parser; 1324 enum acpi_madt_type type; 1325 1326 if (acpi_data.single_redist) { 1327 type = ACPI_MADT_TYPE_GENERIC_INTERRUPT; 1328 redist_parser = gic_acpi_parse_madt_gicc; 1329 } else { 1330 type = ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR; 1331 redist_parser = gic_acpi_parse_madt_redist; 1332 } 1333 1334 /* Collect redistributor base addresses in GICR entries */ 1335 if (acpi_table_parse_madt(type, redist_parser, 0) > 0) 1336 return 0; 1337 1338 pr_info("No valid GICR entries exist\n"); 1339 return -ENODEV; 1340 } 1341 1342 static int __init gic_acpi_match_gicr(struct acpi_subtable_header *header, 1343 const unsigned long end) 1344 { 1345 /* Subtable presence means that redist exists, that's it */ 1346 return 0; 1347 } 1348 1349 static int __init gic_acpi_match_gicc(struct acpi_subtable_header *header, 1350 const unsigned long end) 1351 { 1352 struct acpi_madt_generic_interrupt *gicc = 1353 (struct acpi_madt_generic_interrupt *)header; 1354 1355 /* 1356 * If GICC is enabled and has valid gicr base address, then it means 1357 * GICR base is presented via GICC 1358 */ 1359 if ((gicc->flags & ACPI_MADT_ENABLED) && gicc->gicr_base_address) 1360 return 0; 1361 1362 /* 1363 * It's perfectly valid firmware can pass disabled GICC entry, driver 1364 * should not treat as errors, skip the entry instead of probe fail. 1365 */ 1366 if (!(gicc->flags & ACPI_MADT_ENABLED)) 1367 return 0; 1368 1369 return -ENODEV; 1370 } 1371 1372 static int __init gic_acpi_count_gicr_regions(void) 1373 { 1374 int count; 1375 1376 /* 1377 * Count how many redistributor regions we have. It is not allowed 1378 * to mix redistributor description, GICR and GICC subtables have to be 1379 * mutually exclusive. 1380 */ 1381 count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR, 1382 gic_acpi_match_gicr, 0); 1383 if (count > 0) { 1384 acpi_data.single_redist = false; 1385 return count; 1386 } 1387 1388 count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT, 1389 gic_acpi_match_gicc, 0); 1390 if (count > 0) 1391 acpi_data.single_redist = true; 1392 1393 return count; 1394 } 1395 1396 static bool __init acpi_validate_gic_table(struct acpi_subtable_header *header, 1397 struct acpi_probe_entry *ape) 1398 { 1399 struct acpi_madt_generic_distributor *dist; 1400 int count; 1401 1402 dist = (struct acpi_madt_generic_distributor *)header; 1403 if (dist->version != ape->driver_data) 1404 return false; 1405 1406 /* We need to do that exercise anyway, the sooner the better */ 1407 count = gic_acpi_count_gicr_regions(); 1408 if (count <= 0) 1409 return false; 1410 1411 acpi_data.nr_redist_regions = count; 1412 return true; 1413 } 1414 1415 static int __init gic_acpi_parse_virt_madt_gicc(struct acpi_subtable_header *header, 1416 const unsigned long end) 1417 { 1418 struct acpi_madt_generic_interrupt *gicc = 1419 (struct acpi_madt_generic_interrupt *)header; 1420 int maint_irq_mode; 1421 static int first_madt = true; 1422 1423 /* Skip unusable CPUs */ 1424 if (!(gicc->flags & ACPI_MADT_ENABLED)) 1425 return 0; 1426 1427 maint_irq_mode = (gicc->flags & ACPI_MADT_VGIC_IRQ_MODE) ? 1428 ACPI_EDGE_SENSITIVE : ACPI_LEVEL_SENSITIVE; 1429 1430 if (first_madt) { 1431 first_madt = false; 1432 1433 acpi_data.maint_irq = gicc->vgic_interrupt; 1434 acpi_data.maint_irq_mode = maint_irq_mode; 1435 acpi_data.vcpu_base = gicc->gicv_base_address; 1436 1437 return 0; 1438 } 1439 1440 /* 1441 * The maintenance interrupt and GICV should be the same for every CPU 1442 */ 1443 if ((acpi_data.maint_irq != gicc->vgic_interrupt) || 1444 (acpi_data.maint_irq_mode != maint_irq_mode) || 1445 (acpi_data.vcpu_base != gicc->gicv_base_address)) 1446 return -EINVAL; 1447 1448 return 0; 1449 } 1450 1451 static bool __init gic_acpi_collect_virt_info(void) 1452 { 1453 int count; 1454 1455 count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT, 1456 gic_acpi_parse_virt_madt_gicc, 0); 1457 1458 return (count > 0); 1459 } 1460 1461 #define ACPI_GICV3_DIST_MEM_SIZE (SZ_64K) 1462 #define ACPI_GICV2_VCTRL_MEM_SIZE (SZ_4K) 1463 #define ACPI_GICV2_VCPU_MEM_SIZE (SZ_8K) 1464 1465 static void __init gic_acpi_setup_kvm_info(void) 1466 { 1467 int irq; 1468 1469 if (!gic_acpi_collect_virt_info()) { 1470 pr_warn("Unable to get hardware information used for virtualization\n"); 1471 return; 1472 } 1473 1474 gic_v3_kvm_info.type = GIC_V3; 1475 1476 irq = acpi_register_gsi(NULL, acpi_data.maint_irq, 1477 acpi_data.maint_irq_mode, 1478 ACPI_ACTIVE_HIGH); 1479 if (irq <= 0) 1480 return; 1481 1482 gic_v3_kvm_info.maint_irq = irq; 1483 1484 if (acpi_data.vcpu_base) { 1485 struct resource *vcpu = &gic_v3_kvm_info.vcpu; 1486 1487 vcpu->flags = IORESOURCE_MEM; 1488 vcpu->start = acpi_data.vcpu_base; 1489 vcpu->end = vcpu->start + ACPI_GICV2_VCPU_MEM_SIZE - 1; 1490 } 1491 1492 gic_v3_kvm_info.has_v4 = gic_data.rdists.has_vlpis; 1493 gic_set_kvm_info(&gic_v3_kvm_info); 1494 } 1495 1496 static int __init 1497 gic_acpi_init(struct acpi_subtable_header *header, const unsigned long end) 1498 { 1499 struct acpi_madt_generic_distributor *dist; 1500 struct fwnode_handle *domain_handle; 1501 size_t size; 1502 int i, err; 1503 1504 /* Get distributor base address */ 1505 dist = (struct acpi_madt_generic_distributor *)header; 1506 acpi_data.dist_base = ioremap(dist->base_address, 1507 ACPI_GICV3_DIST_MEM_SIZE); 1508 if (!acpi_data.dist_base) { 1509 pr_err("Unable to map GICD registers\n"); 1510 return -ENOMEM; 1511 } 1512 1513 err = gic_validate_dist_version(acpi_data.dist_base); 1514 if (err) { 1515 pr_err("No distributor detected at @%p, giving up\n", 1516 acpi_data.dist_base); 1517 goto out_dist_unmap; 1518 } 1519 1520 size = sizeof(*acpi_data.redist_regs) * acpi_data.nr_redist_regions; 1521 acpi_data.redist_regs = kzalloc(size, GFP_KERNEL); 1522 if (!acpi_data.redist_regs) { 1523 err = -ENOMEM; 1524 goto out_dist_unmap; 1525 } 1526 1527 err = gic_acpi_collect_gicr_base(); 1528 if (err) 1529 goto out_redist_unmap; 1530 1531 domain_handle = irq_domain_alloc_fwnode(acpi_data.dist_base); 1532 if (!domain_handle) { 1533 err = -ENOMEM; 1534 goto out_redist_unmap; 1535 } 1536 1537 err = gic_init_bases(acpi_data.dist_base, acpi_data.redist_regs, 1538 acpi_data.nr_redist_regions, 0, domain_handle); 1539 if (err) 1540 goto out_fwhandle_free; 1541 1542 acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, domain_handle); 1543 1544 if (static_key_true(&supports_deactivate)) 1545 gic_acpi_setup_kvm_info(); 1546 1547 return 0; 1548 1549 out_fwhandle_free: 1550 irq_domain_free_fwnode(domain_handle); 1551 out_redist_unmap: 1552 for (i = 0; i < acpi_data.nr_redist_regions; i++) 1553 if (acpi_data.redist_regs[i].redist_base) 1554 iounmap(acpi_data.redist_regs[i].redist_base); 1555 kfree(acpi_data.redist_regs); 1556 out_dist_unmap: 1557 iounmap(acpi_data.dist_base); 1558 return err; 1559 } 1560 IRQCHIP_ACPI_DECLARE(gic_v3, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 1561 acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V3, 1562 gic_acpi_init); 1563 IRQCHIP_ACPI_DECLARE(gic_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 1564 acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V4, 1565 gic_acpi_init); 1566 IRQCHIP_ACPI_DECLARE(gic_v3_or_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 1567 acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_NONE, 1568 gic_acpi_init); 1569 #endif 1570