1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2013-2017 ARM Limited, All Rights Reserved. 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 */ 6 7 #define pr_fmt(fmt) "GICv3: " fmt 8 9 #include <linux/acpi.h> 10 #include <linux/cpu.h> 11 #include <linux/cpu_pm.h> 12 #include <linux/delay.h> 13 #include <linux/interrupt.h> 14 #include <linux/irqdomain.h> 15 #include <linux/of.h> 16 #include <linux/of_address.h> 17 #include <linux/of_irq.h> 18 #include <linux/percpu.h> 19 #include <linux/refcount.h> 20 #include <linux/slab.h> 21 22 #include <linux/irqchip.h> 23 #include <linux/irqchip/arm-gic-common.h> 24 #include <linux/irqchip/arm-gic-v3.h> 25 #include <linux/irqchip/irq-partition-percpu.h> 26 27 #include <asm/cputype.h> 28 #include <asm/exception.h> 29 #include <asm/smp_plat.h> 30 #include <asm/virt.h> 31 32 #include "irq-gic-common.h" 33 34 #define GICD_INT_NMI_PRI (GICD_INT_DEF_PRI & ~0x80) 35 36 #define FLAGS_WORKAROUND_GICR_WAKER_MSM8996 (1ULL << 0) 37 #define FLAGS_WORKAROUND_CAVIUM_ERRATUM_38539 (1ULL << 1) 38 39 #define GIC_IRQ_TYPE_PARTITION (GIC_IRQ_TYPE_LPI + 1) 40 41 struct redist_region { 42 void __iomem *redist_base; 43 phys_addr_t phys_base; 44 bool single_redist; 45 }; 46 47 struct gic_chip_data { 48 struct fwnode_handle *fwnode; 49 void __iomem *dist_base; 50 struct redist_region *redist_regions; 51 struct rdists rdists; 52 struct irq_domain *domain; 53 u64 redist_stride; 54 u32 nr_redist_regions; 55 u64 flags; 56 bool has_rss; 57 unsigned int ppi_nr; 58 struct partition_desc **ppi_descs; 59 }; 60 61 static struct gic_chip_data gic_data __read_mostly; 62 static DEFINE_STATIC_KEY_TRUE(supports_deactivate_key); 63 64 #define GIC_ID_NR (1U << GICD_TYPER_ID_BITS(gic_data.rdists.gicd_typer)) 65 #define GIC_LINE_NR min(GICD_TYPER_SPIS(gic_data.rdists.gicd_typer), 1020U) 66 #define GIC_ESPI_NR GICD_TYPER_ESPIS(gic_data.rdists.gicd_typer) 67 68 /* 69 * The behaviours of RPR and PMR registers differ depending on the value of 70 * SCR_EL3.FIQ, and the behaviour of non-secure priority registers of the 71 * distributor and redistributors depends on whether security is enabled in the 72 * GIC. 73 * 74 * When security is enabled, non-secure priority values from the (re)distributor 75 * are presented to the GIC CPUIF as follow: 76 * (GIC_(R)DIST_PRI[irq] >> 1) | 0x80; 77 * 78 * If SCR_EL3.FIQ == 1, the values writen to/read from PMR and RPR at non-secure 79 * EL1 are subject to a similar operation thus matching the priorities presented 80 * from the (re)distributor when security is enabled. When SCR_EL3.FIQ == 0, 81 * these values are unchanched by the GIC. 82 * 83 * see GICv3/GICv4 Architecture Specification (IHI0069D): 84 * - section 4.8.1 Non-secure accesses to register fields for Secure interrupt 85 * priorities. 86 * - Figure 4-7 Secure read of the priority field for a Non-secure Group 1 87 * interrupt. 88 */ 89 static DEFINE_STATIC_KEY_FALSE(supports_pseudo_nmis); 90 91 /* 92 * Global static key controlling whether an update to PMR allowing more 93 * interrupts requires to be propagated to the redistributor (DSB SY). 94 * And this needs to be exported for modules to be able to enable 95 * interrupts... 96 */ 97 DEFINE_STATIC_KEY_FALSE(gic_pmr_sync); 98 EXPORT_SYMBOL(gic_pmr_sync); 99 100 DEFINE_STATIC_KEY_FALSE(gic_nonsecure_priorities); 101 EXPORT_SYMBOL(gic_nonsecure_priorities); 102 103 /* ppi_nmi_refs[n] == number of cpus having ppi[n + 16] set as NMI */ 104 static refcount_t *ppi_nmi_refs; 105 106 static struct gic_kvm_info gic_v3_kvm_info; 107 static DEFINE_PER_CPU(bool, has_rss); 108 109 #define MPIDR_RS(mpidr) (((mpidr) & 0xF0UL) >> 4) 110 #define gic_data_rdist() (this_cpu_ptr(gic_data.rdists.rdist)) 111 #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base) 112 #define gic_data_rdist_sgi_base() (gic_data_rdist_rd_base() + SZ_64K) 113 114 /* Our default, arbitrary priority value. Linux only uses one anyway. */ 115 #define DEFAULT_PMR_VALUE 0xf0 116 117 enum gic_intid_range { 118 SGI_RANGE, 119 PPI_RANGE, 120 SPI_RANGE, 121 EPPI_RANGE, 122 ESPI_RANGE, 123 LPI_RANGE, 124 __INVALID_RANGE__ 125 }; 126 127 static enum gic_intid_range __get_intid_range(irq_hw_number_t hwirq) 128 { 129 switch (hwirq) { 130 case 0 ... 15: 131 return SGI_RANGE; 132 case 16 ... 31: 133 return PPI_RANGE; 134 case 32 ... 1019: 135 return SPI_RANGE; 136 case EPPI_BASE_INTID ... (EPPI_BASE_INTID + 63): 137 return EPPI_RANGE; 138 case ESPI_BASE_INTID ... (ESPI_BASE_INTID + 1023): 139 return ESPI_RANGE; 140 case 8192 ... GENMASK(23, 0): 141 return LPI_RANGE; 142 default: 143 return __INVALID_RANGE__; 144 } 145 } 146 147 static enum gic_intid_range get_intid_range(struct irq_data *d) 148 { 149 return __get_intid_range(d->hwirq); 150 } 151 152 static inline unsigned int gic_irq(struct irq_data *d) 153 { 154 return d->hwirq; 155 } 156 157 static inline bool gic_irq_in_rdist(struct irq_data *d) 158 { 159 switch (get_intid_range(d)) { 160 case SGI_RANGE: 161 case PPI_RANGE: 162 case EPPI_RANGE: 163 return true; 164 default: 165 return false; 166 } 167 } 168 169 static inline void __iomem *gic_dist_base(struct irq_data *d) 170 { 171 switch (get_intid_range(d)) { 172 case SGI_RANGE: 173 case PPI_RANGE: 174 case EPPI_RANGE: 175 /* SGI+PPI -> SGI_base for this CPU */ 176 return gic_data_rdist_sgi_base(); 177 178 case SPI_RANGE: 179 case ESPI_RANGE: 180 /* SPI -> dist_base */ 181 return gic_data.dist_base; 182 183 default: 184 return NULL; 185 } 186 } 187 188 static void gic_do_wait_for_rwp(void __iomem *base) 189 { 190 u32 count = 1000000; /* 1s! */ 191 192 while (readl_relaxed(base + GICD_CTLR) & GICD_CTLR_RWP) { 193 count--; 194 if (!count) { 195 pr_err_ratelimited("RWP timeout, gone fishing\n"); 196 return; 197 } 198 cpu_relax(); 199 udelay(1); 200 } 201 } 202 203 /* Wait for completion of a distributor change */ 204 static void gic_dist_wait_for_rwp(void) 205 { 206 gic_do_wait_for_rwp(gic_data.dist_base); 207 } 208 209 /* Wait for completion of a redistributor change */ 210 static void gic_redist_wait_for_rwp(void) 211 { 212 gic_do_wait_for_rwp(gic_data_rdist_rd_base()); 213 } 214 215 #ifdef CONFIG_ARM64 216 217 static u64 __maybe_unused gic_read_iar(void) 218 { 219 if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_23154)) 220 return gic_read_iar_cavium_thunderx(); 221 else 222 return gic_read_iar_common(); 223 } 224 #endif 225 226 static void gic_enable_redist(bool enable) 227 { 228 void __iomem *rbase; 229 u32 count = 1000000; /* 1s! */ 230 u32 val; 231 232 if (gic_data.flags & FLAGS_WORKAROUND_GICR_WAKER_MSM8996) 233 return; 234 235 rbase = gic_data_rdist_rd_base(); 236 237 val = readl_relaxed(rbase + GICR_WAKER); 238 if (enable) 239 /* Wake up this CPU redistributor */ 240 val &= ~GICR_WAKER_ProcessorSleep; 241 else 242 val |= GICR_WAKER_ProcessorSleep; 243 writel_relaxed(val, rbase + GICR_WAKER); 244 245 if (!enable) { /* Check that GICR_WAKER is writeable */ 246 val = readl_relaxed(rbase + GICR_WAKER); 247 if (!(val & GICR_WAKER_ProcessorSleep)) 248 return; /* No PM support in this redistributor */ 249 } 250 251 while (--count) { 252 val = readl_relaxed(rbase + GICR_WAKER); 253 if (enable ^ (bool)(val & GICR_WAKER_ChildrenAsleep)) 254 break; 255 cpu_relax(); 256 udelay(1); 257 } 258 if (!count) 259 pr_err_ratelimited("redistributor failed to %s...\n", 260 enable ? "wakeup" : "sleep"); 261 } 262 263 /* 264 * Routines to disable, enable, EOI and route interrupts 265 */ 266 static u32 convert_offset_index(struct irq_data *d, u32 offset, u32 *index) 267 { 268 switch (get_intid_range(d)) { 269 case SGI_RANGE: 270 case PPI_RANGE: 271 case SPI_RANGE: 272 *index = d->hwirq; 273 return offset; 274 case EPPI_RANGE: 275 /* 276 * Contrary to the ESPI range, the EPPI range is contiguous 277 * to the PPI range in the registers, so let's adjust the 278 * displacement accordingly. Consistency is overrated. 279 */ 280 *index = d->hwirq - EPPI_BASE_INTID + 32; 281 return offset; 282 case ESPI_RANGE: 283 *index = d->hwirq - ESPI_BASE_INTID; 284 switch (offset) { 285 case GICD_ISENABLER: 286 return GICD_ISENABLERnE; 287 case GICD_ICENABLER: 288 return GICD_ICENABLERnE; 289 case GICD_ISPENDR: 290 return GICD_ISPENDRnE; 291 case GICD_ICPENDR: 292 return GICD_ICPENDRnE; 293 case GICD_ISACTIVER: 294 return GICD_ISACTIVERnE; 295 case GICD_ICACTIVER: 296 return GICD_ICACTIVERnE; 297 case GICD_IPRIORITYR: 298 return GICD_IPRIORITYRnE; 299 case GICD_ICFGR: 300 return GICD_ICFGRnE; 301 case GICD_IROUTER: 302 return GICD_IROUTERnE; 303 default: 304 break; 305 } 306 break; 307 default: 308 break; 309 } 310 311 WARN_ON(1); 312 *index = d->hwirq; 313 return offset; 314 } 315 316 static int gic_peek_irq(struct irq_data *d, u32 offset) 317 { 318 void __iomem *base; 319 u32 index, mask; 320 321 offset = convert_offset_index(d, offset, &index); 322 mask = 1 << (index % 32); 323 324 if (gic_irq_in_rdist(d)) 325 base = gic_data_rdist_sgi_base(); 326 else 327 base = gic_data.dist_base; 328 329 return !!(readl_relaxed(base + offset + (index / 32) * 4) & mask); 330 } 331 332 static void gic_poke_irq(struct irq_data *d, u32 offset) 333 { 334 void (*rwp_wait)(void); 335 void __iomem *base; 336 u32 index, mask; 337 338 offset = convert_offset_index(d, offset, &index); 339 mask = 1 << (index % 32); 340 341 if (gic_irq_in_rdist(d)) { 342 base = gic_data_rdist_sgi_base(); 343 rwp_wait = gic_redist_wait_for_rwp; 344 } else { 345 base = gic_data.dist_base; 346 rwp_wait = gic_dist_wait_for_rwp; 347 } 348 349 writel_relaxed(mask, base + offset + (index / 32) * 4); 350 rwp_wait(); 351 } 352 353 static void gic_mask_irq(struct irq_data *d) 354 { 355 gic_poke_irq(d, GICD_ICENABLER); 356 } 357 358 static void gic_eoimode1_mask_irq(struct irq_data *d) 359 { 360 gic_mask_irq(d); 361 /* 362 * When masking a forwarded interrupt, make sure it is 363 * deactivated as well. 364 * 365 * This ensures that an interrupt that is getting 366 * disabled/masked will not get "stuck", because there is 367 * noone to deactivate it (guest is being terminated). 368 */ 369 if (irqd_is_forwarded_to_vcpu(d)) 370 gic_poke_irq(d, GICD_ICACTIVER); 371 } 372 373 static void gic_unmask_irq(struct irq_data *d) 374 { 375 gic_poke_irq(d, GICD_ISENABLER); 376 } 377 378 static inline bool gic_supports_nmi(void) 379 { 380 return IS_ENABLED(CONFIG_ARM64_PSEUDO_NMI) && 381 static_branch_likely(&supports_pseudo_nmis); 382 } 383 384 static int gic_irq_set_irqchip_state(struct irq_data *d, 385 enum irqchip_irq_state which, bool val) 386 { 387 u32 reg; 388 389 if (d->hwirq >= 8192) /* SGI/PPI/SPI only */ 390 return -EINVAL; 391 392 switch (which) { 393 case IRQCHIP_STATE_PENDING: 394 reg = val ? GICD_ISPENDR : GICD_ICPENDR; 395 break; 396 397 case IRQCHIP_STATE_ACTIVE: 398 reg = val ? GICD_ISACTIVER : GICD_ICACTIVER; 399 break; 400 401 case IRQCHIP_STATE_MASKED: 402 reg = val ? GICD_ICENABLER : GICD_ISENABLER; 403 break; 404 405 default: 406 return -EINVAL; 407 } 408 409 gic_poke_irq(d, reg); 410 return 0; 411 } 412 413 static int gic_irq_get_irqchip_state(struct irq_data *d, 414 enum irqchip_irq_state which, bool *val) 415 { 416 if (d->hwirq >= 8192) /* PPI/SPI only */ 417 return -EINVAL; 418 419 switch (which) { 420 case IRQCHIP_STATE_PENDING: 421 *val = gic_peek_irq(d, GICD_ISPENDR); 422 break; 423 424 case IRQCHIP_STATE_ACTIVE: 425 *val = gic_peek_irq(d, GICD_ISACTIVER); 426 break; 427 428 case IRQCHIP_STATE_MASKED: 429 *val = !gic_peek_irq(d, GICD_ISENABLER); 430 break; 431 432 default: 433 return -EINVAL; 434 } 435 436 return 0; 437 } 438 439 static void gic_irq_set_prio(struct irq_data *d, u8 prio) 440 { 441 void __iomem *base = gic_dist_base(d); 442 u32 offset, index; 443 444 offset = convert_offset_index(d, GICD_IPRIORITYR, &index); 445 446 writeb_relaxed(prio, base + offset + index); 447 } 448 449 static u32 gic_get_ppi_index(struct irq_data *d) 450 { 451 switch (get_intid_range(d)) { 452 case PPI_RANGE: 453 return d->hwirq - 16; 454 case EPPI_RANGE: 455 return d->hwirq - EPPI_BASE_INTID + 16; 456 default: 457 unreachable(); 458 } 459 } 460 461 static int gic_irq_nmi_setup(struct irq_data *d) 462 { 463 struct irq_desc *desc = irq_to_desc(d->irq); 464 465 if (!gic_supports_nmi()) 466 return -EINVAL; 467 468 if (gic_peek_irq(d, GICD_ISENABLER)) { 469 pr_err("Cannot set NMI property of enabled IRQ %u\n", d->irq); 470 return -EINVAL; 471 } 472 473 /* 474 * A secondary irq_chip should be in charge of LPI request, 475 * it should not be possible to get there 476 */ 477 if (WARN_ON(gic_irq(d) >= 8192)) 478 return -EINVAL; 479 480 /* desc lock should already be held */ 481 if (gic_irq_in_rdist(d)) { 482 u32 idx = gic_get_ppi_index(d); 483 484 /* Setting up PPI as NMI, only switch handler for first NMI */ 485 if (!refcount_inc_not_zero(&ppi_nmi_refs[idx])) { 486 refcount_set(&ppi_nmi_refs[idx], 1); 487 desc->handle_irq = handle_percpu_devid_fasteoi_nmi; 488 } 489 } else { 490 desc->handle_irq = handle_fasteoi_nmi; 491 } 492 493 gic_irq_set_prio(d, GICD_INT_NMI_PRI); 494 495 return 0; 496 } 497 498 static void gic_irq_nmi_teardown(struct irq_data *d) 499 { 500 struct irq_desc *desc = irq_to_desc(d->irq); 501 502 if (WARN_ON(!gic_supports_nmi())) 503 return; 504 505 if (gic_peek_irq(d, GICD_ISENABLER)) { 506 pr_err("Cannot set NMI property of enabled IRQ %u\n", d->irq); 507 return; 508 } 509 510 /* 511 * A secondary irq_chip should be in charge of LPI request, 512 * it should not be possible to get there 513 */ 514 if (WARN_ON(gic_irq(d) >= 8192)) 515 return; 516 517 /* desc lock should already be held */ 518 if (gic_irq_in_rdist(d)) { 519 u32 idx = gic_get_ppi_index(d); 520 521 /* Tearing down NMI, only switch handler for last NMI */ 522 if (refcount_dec_and_test(&ppi_nmi_refs[idx])) 523 desc->handle_irq = handle_percpu_devid_irq; 524 } else { 525 desc->handle_irq = handle_fasteoi_irq; 526 } 527 528 gic_irq_set_prio(d, GICD_INT_DEF_PRI); 529 } 530 531 static void gic_eoi_irq(struct irq_data *d) 532 { 533 gic_write_eoir(gic_irq(d)); 534 } 535 536 static void gic_eoimode1_eoi_irq(struct irq_data *d) 537 { 538 /* 539 * No need to deactivate an LPI, or an interrupt that 540 * is is getting forwarded to a vcpu. 541 */ 542 if (gic_irq(d) >= 8192 || irqd_is_forwarded_to_vcpu(d)) 543 return; 544 gic_write_dir(gic_irq(d)); 545 } 546 547 static int gic_set_type(struct irq_data *d, unsigned int type) 548 { 549 enum gic_intid_range range; 550 unsigned int irq = gic_irq(d); 551 void (*rwp_wait)(void); 552 void __iomem *base; 553 u32 offset, index; 554 int ret; 555 556 range = get_intid_range(d); 557 558 /* Interrupt configuration for SGIs can't be changed */ 559 if (range == SGI_RANGE) 560 return type != IRQ_TYPE_EDGE_RISING ? -EINVAL : 0; 561 562 /* SPIs have restrictions on the supported types */ 563 if ((range == SPI_RANGE || range == ESPI_RANGE) && 564 type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING) 565 return -EINVAL; 566 567 if (gic_irq_in_rdist(d)) { 568 base = gic_data_rdist_sgi_base(); 569 rwp_wait = gic_redist_wait_for_rwp; 570 } else { 571 base = gic_data.dist_base; 572 rwp_wait = gic_dist_wait_for_rwp; 573 } 574 575 offset = convert_offset_index(d, GICD_ICFGR, &index); 576 577 ret = gic_configure_irq(index, type, base + offset, rwp_wait); 578 if (ret && (range == PPI_RANGE || range == EPPI_RANGE)) { 579 /* Misconfigured PPIs are usually not fatal */ 580 pr_warn("GIC: PPI INTID%d is secure or misconfigured\n", irq); 581 ret = 0; 582 } 583 584 return ret; 585 } 586 587 static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu) 588 { 589 if (get_intid_range(d) == SGI_RANGE) 590 return -EINVAL; 591 592 if (vcpu) 593 irqd_set_forwarded_to_vcpu(d); 594 else 595 irqd_clr_forwarded_to_vcpu(d); 596 return 0; 597 } 598 599 static u64 gic_mpidr_to_affinity(unsigned long mpidr) 600 { 601 u64 aff; 602 603 aff = ((u64)MPIDR_AFFINITY_LEVEL(mpidr, 3) << 32 | 604 MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 | 605 MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | 606 MPIDR_AFFINITY_LEVEL(mpidr, 0)); 607 608 return aff; 609 } 610 611 static void gic_deactivate_unhandled(u32 irqnr) 612 { 613 if (static_branch_likely(&supports_deactivate_key)) { 614 if (irqnr < 8192) 615 gic_write_dir(irqnr); 616 } else { 617 gic_write_eoir(irqnr); 618 } 619 } 620 621 static inline void gic_handle_nmi(u32 irqnr, struct pt_regs *regs) 622 { 623 bool irqs_enabled = interrupts_enabled(regs); 624 int err; 625 626 if (irqs_enabled) 627 nmi_enter(); 628 629 if (static_branch_likely(&supports_deactivate_key)) 630 gic_write_eoir(irqnr); 631 /* 632 * Leave the PSR.I bit set to prevent other NMIs to be 633 * received while handling this one. 634 * PSR.I will be restored when we ERET to the 635 * interrupted context. 636 */ 637 err = handle_domain_nmi(gic_data.domain, irqnr, regs); 638 if (err) 639 gic_deactivate_unhandled(irqnr); 640 641 if (irqs_enabled) 642 nmi_exit(); 643 } 644 645 static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) 646 { 647 u32 irqnr; 648 649 irqnr = gic_read_iar(); 650 651 if (gic_supports_nmi() && 652 unlikely(gic_read_rpr() == GICD_INT_NMI_PRI)) { 653 gic_handle_nmi(irqnr, regs); 654 return; 655 } 656 657 if (gic_prio_masking_enabled()) { 658 gic_pmr_mask_irqs(); 659 gic_arch_enable_irqs(); 660 } 661 662 /* Check for special IDs first */ 663 if ((irqnr >= 1020 && irqnr <= 1023)) 664 return; 665 666 if (static_branch_likely(&supports_deactivate_key)) 667 gic_write_eoir(irqnr); 668 else 669 isb(); 670 671 if (handle_domain_irq(gic_data.domain, irqnr, regs)) { 672 WARN_ONCE(true, "Unexpected interrupt received!\n"); 673 gic_deactivate_unhandled(irqnr); 674 } 675 } 676 677 static u32 gic_get_pribits(void) 678 { 679 u32 pribits; 680 681 pribits = gic_read_ctlr(); 682 pribits &= ICC_CTLR_EL1_PRI_BITS_MASK; 683 pribits >>= ICC_CTLR_EL1_PRI_BITS_SHIFT; 684 pribits++; 685 686 return pribits; 687 } 688 689 static bool gic_has_group0(void) 690 { 691 u32 val; 692 u32 old_pmr; 693 694 old_pmr = gic_read_pmr(); 695 696 /* 697 * Let's find out if Group0 is under control of EL3 or not by 698 * setting the highest possible, non-zero priority in PMR. 699 * 700 * If SCR_EL3.FIQ is set, the priority gets shifted down in 701 * order for the CPU interface to set bit 7, and keep the 702 * actual priority in the non-secure range. In the process, it 703 * looses the least significant bit and the actual priority 704 * becomes 0x80. Reading it back returns 0, indicating that 705 * we're don't have access to Group0. 706 */ 707 gic_write_pmr(BIT(8 - gic_get_pribits())); 708 val = gic_read_pmr(); 709 710 gic_write_pmr(old_pmr); 711 712 return val != 0; 713 } 714 715 static void __init gic_dist_init(void) 716 { 717 unsigned int i; 718 u64 affinity; 719 void __iomem *base = gic_data.dist_base; 720 u32 val; 721 722 /* Disable the distributor */ 723 writel_relaxed(0, base + GICD_CTLR); 724 gic_dist_wait_for_rwp(); 725 726 /* 727 * Configure SPIs as non-secure Group-1. This will only matter 728 * if the GIC only has a single security state. This will not 729 * do the right thing if the kernel is running in secure mode, 730 * but that's not the intended use case anyway. 731 */ 732 for (i = 32; i < GIC_LINE_NR; i += 32) 733 writel_relaxed(~0, base + GICD_IGROUPR + i / 8); 734 735 /* Extended SPI range, not handled by the GICv2/GICv3 common code */ 736 for (i = 0; i < GIC_ESPI_NR; i += 32) { 737 writel_relaxed(~0U, base + GICD_ICENABLERnE + i / 8); 738 writel_relaxed(~0U, base + GICD_ICACTIVERnE + i / 8); 739 } 740 741 for (i = 0; i < GIC_ESPI_NR; i += 32) 742 writel_relaxed(~0U, base + GICD_IGROUPRnE + i / 8); 743 744 for (i = 0; i < GIC_ESPI_NR; i += 16) 745 writel_relaxed(0, base + GICD_ICFGRnE + i / 4); 746 747 for (i = 0; i < GIC_ESPI_NR; i += 4) 748 writel_relaxed(GICD_INT_DEF_PRI_X4, base + GICD_IPRIORITYRnE + i); 749 750 /* Now do the common stuff, and wait for the distributor to drain */ 751 gic_dist_config(base, GIC_LINE_NR, gic_dist_wait_for_rwp); 752 753 val = GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G1A | GICD_CTLR_ENABLE_G1; 754 if (gic_data.rdists.gicd_typer2 & GICD_TYPER2_nASSGIcap) { 755 pr_info("Enabling SGIs without active state\n"); 756 val |= GICD_CTLR_nASSGIreq; 757 } 758 759 /* Enable distributor with ARE, Group1 */ 760 writel_relaxed(val, base + GICD_CTLR); 761 762 /* 763 * Set all global interrupts to the boot CPU only. ARE must be 764 * enabled. 765 */ 766 affinity = gic_mpidr_to_affinity(cpu_logical_map(smp_processor_id())); 767 for (i = 32; i < GIC_LINE_NR; i++) 768 gic_write_irouter(affinity, base + GICD_IROUTER + i * 8); 769 770 for (i = 0; i < GIC_ESPI_NR; i++) 771 gic_write_irouter(affinity, base + GICD_IROUTERnE + i * 8); 772 } 773 774 static int gic_iterate_rdists(int (*fn)(struct redist_region *, void __iomem *)) 775 { 776 int ret = -ENODEV; 777 int i; 778 779 for (i = 0; i < gic_data.nr_redist_regions; i++) { 780 void __iomem *ptr = gic_data.redist_regions[i].redist_base; 781 u64 typer; 782 u32 reg; 783 784 reg = readl_relaxed(ptr + GICR_PIDR2) & GIC_PIDR2_ARCH_MASK; 785 if (reg != GIC_PIDR2_ARCH_GICv3 && 786 reg != GIC_PIDR2_ARCH_GICv4) { /* We're in trouble... */ 787 pr_warn("No redistributor present @%p\n", ptr); 788 break; 789 } 790 791 do { 792 typer = gic_read_typer(ptr + GICR_TYPER); 793 ret = fn(gic_data.redist_regions + i, ptr); 794 if (!ret) 795 return 0; 796 797 if (gic_data.redist_regions[i].single_redist) 798 break; 799 800 if (gic_data.redist_stride) { 801 ptr += gic_data.redist_stride; 802 } else { 803 ptr += SZ_64K * 2; /* Skip RD_base + SGI_base */ 804 if (typer & GICR_TYPER_VLPIS) 805 ptr += SZ_64K * 2; /* Skip VLPI_base + reserved page */ 806 } 807 } while (!(typer & GICR_TYPER_LAST)); 808 } 809 810 return ret ? -ENODEV : 0; 811 } 812 813 static int __gic_populate_rdist(struct redist_region *region, void __iomem *ptr) 814 { 815 unsigned long mpidr = cpu_logical_map(smp_processor_id()); 816 u64 typer; 817 u32 aff; 818 819 /* 820 * Convert affinity to a 32bit value that can be matched to 821 * GICR_TYPER bits [63:32]. 822 */ 823 aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 24 | 824 MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 | 825 MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | 826 MPIDR_AFFINITY_LEVEL(mpidr, 0)); 827 828 typer = gic_read_typer(ptr + GICR_TYPER); 829 if ((typer >> 32) == aff) { 830 u64 offset = ptr - region->redist_base; 831 raw_spin_lock_init(&gic_data_rdist()->rd_lock); 832 gic_data_rdist_rd_base() = ptr; 833 gic_data_rdist()->phys_base = region->phys_base + offset; 834 835 pr_info("CPU%d: found redistributor %lx region %d:%pa\n", 836 smp_processor_id(), mpidr, 837 (int)(region - gic_data.redist_regions), 838 &gic_data_rdist()->phys_base); 839 return 0; 840 } 841 842 /* Try next one */ 843 return 1; 844 } 845 846 static int gic_populate_rdist(void) 847 { 848 if (gic_iterate_rdists(__gic_populate_rdist) == 0) 849 return 0; 850 851 /* We couldn't even deal with ourselves... */ 852 WARN(true, "CPU%d: mpidr %lx has no re-distributor!\n", 853 smp_processor_id(), 854 (unsigned long)cpu_logical_map(smp_processor_id())); 855 return -ENODEV; 856 } 857 858 static int __gic_update_rdist_properties(struct redist_region *region, 859 void __iomem *ptr) 860 { 861 u64 typer = gic_read_typer(ptr + GICR_TYPER); 862 863 gic_data.rdists.has_vlpis &= !!(typer & GICR_TYPER_VLPIS); 864 865 /* RVPEID implies some form of DirectLPI, no matter what the doc says... :-/ */ 866 gic_data.rdists.has_rvpeid &= !!(typer & GICR_TYPER_RVPEID); 867 gic_data.rdists.has_direct_lpi &= (!!(typer & GICR_TYPER_DirectLPIS) | 868 gic_data.rdists.has_rvpeid); 869 gic_data.rdists.has_vpend_valid_dirty &= !!(typer & GICR_TYPER_DIRTY); 870 871 /* Detect non-sensical configurations */ 872 if (WARN_ON_ONCE(gic_data.rdists.has_rvpeid && !gic_data.rdists.has_vlpis)) { 873 gic_data.rdists.has_direct_lpi = false; 874 gic_data.rdists.has_vlpis = false; 875 gic_data.rdists.has_rvpeid = false; 876 } 877 878 gic_data.ppi_nr = min(GICR_TYPER_NR_PPIS(typer), gic_data.ppi_nr); 879 880 return 1; 881 } 882 883 static void gic_update_rdist_properties(void) 884 { 885 gic_data.ppi_nr = UINT_MAX; 886 gic_iterate_rdists(__gic_update_rdist_properties); 887 if (WARN_ON(gic_data.ppi_nr == UINT_MAX)) 888 gic_data.ppi_nr = 0; 889 pr_info("%d PPIs implemented\n", gic_data.ppi_nr); 890 if (gic_data.rdists.has_vlpis) 891 pr_info("GICv4 features: %s%s%s\n", 892 gic_data.rdists.has_direct_lpi ? "DirectLPI " : "", 893 gic_data.rdists.has_rvpeid ? "RVPEID " : "", 894 gic_data.rdists.has_vpend_valid_dirty ? "Valid+Dirty " : ""); 895 } 896 897 /* Check whether it's single security state view */ 898 static inline bool gic_dist_security_disabled(void) 899 { 900 return readl_relaxed(gic_data.dist_base + GICD_CTLR) & GICD_CTLR_DS; 901 } 902 903 static void gic_cpu_sys_reg_init(void) 904 { 905 int i, cpu = smp_processor_id(); 906 u64 mpidr = cpu_logical_map(cpu); 907 u64 need_rss = MPIDR_RS(mpidr); 908 bool group0; 909 u32 pribits; 910 911 /* 912 * Need to check that the SRE bit has actually been set. If 913 * not, it means that SRE is disabled at EL2. We're going to 914 * die painfully, and there is nothing we can do about it. 915 * 916 * Kindly inform the luser. 917 */ 918 if (!gic_enable_sre()) 919 pr_err("GIC: unable to set SRE (disabled at EL2), panic ahead\n"); 920 921 pribits = gic_get_pribits(); 922 923 group0 = gic_has_group0(); 924 925 /* Set priority mask register */ 926 if (!gic_prio_masking_enabled()) { 927 write_gicreg(DEFAULT_PMR_VALUE, ICC_PMR_EL1); 928 } else if (gic_supports_nmi()) { 929 /* 930 * Mismatch configuration with boot CPU, the system is likely 931 * to die as interrupt masking will not work properly on all 932 * CPUs 933 * 934 * The boot CPU calls this function before enabling NMI support, 935 * and as a result we'll never see this warning in the boot path 936 * for that CPU. 937 */ 938 if (static_branch_unlikely(&gic_nonsecure_priorities)) 939 WARN_ON(!group0 || gic_dist_security_disabled()); 940 else 941 WARN_ON(group0 && !gic_dist_security_disabled()); 942 } 943 944 /* 945 * Some firmwares hand over to the kernel with the BPR changed from 946 * its reset value (and with a value large enough to prevent 947 * any pre-emptive interrupts from working at all). Writing a zero 948 * to BPR restores is reset value. 949 */ 950 gic_write_bpr1(0); 951 952 if (static_branch_likely(&supports_deactivate_key)) { 953 /* EOI drops priority only (mode 1) */ 954 gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop); 955 } else { 956 /* EOI deactivates interrupt too (mode 0) */ 957 gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop_dir); 958 } 959 960 /* Always whack Group0 before Group1 */ 961 if (group0) { 962 switch(pribits) { 963 case 8: 964 case 7: 965 write_gicreg(0, ICC_AP0R3_EL1); 966 write_gicreg(0, ICC_AP0R2_EL1); 967 fallthrough; 968 case 6: 969 write_gicreg(0, ICC_AP0R1_EL1); 970 fallthrough; 971 case 5: 972 case 4: 973 write_gicreg(0, ICC_AP0R0_EL1); 974 } 975 976 isb(); 977 } 978 979 switch(pribits) { 980 case 8: 981 case 7: 982 write_gicreg(0, ICC_AP1R3_EL1); 983 write_gicreg(0, ICC_AP1R2_EL1); 984 fallthrough; 985 case 6: 986 write_gicreg(0, ICC_AP1R1_EL1); 987 fallthrough; 988 case 5: 989 case 4: 990 write_gicreg(0, ICC_AP1R0_EL1); 991 } 992 993 isb(); 994 995 /* ... and let's hit the road... */ 996 gic_write_grpen1(1); 997 998 /* Keep the RSS capability status in per_cpu variable */ 999 per_cpu(has_rss, cpu) = !!(gic_read_ctlr() & ICC_CTLR_EL1_RSS); 1000 1001 /* Check all the CPUs have capable of sending SGIs to other CPUs */ 1002 for_each_online_cpu(i) { 1003 bool have_rss = per_cpu(has_rss, i) && per_cpu(has_rss, cpu); 1004 1005 need_rss |= MPIDR_RS(cpu_logical_map(i)); 1006 if (need_rss && (!have_rss)) 1007 pr_crit("CPU%d (%lx) can't SGI CPU%d (%lx), no RSS\n", 1008 cpu, (unsigned long)mpidr, 1009 i, (unsigned long)cpu_logical_map(i)); 1010 } 1011 1012 /** 1013 * GIC spec says, when ICC_CTLR_EL1.RSS==1 and GICD_TYPER.RSS==0, 1014 * writing ICC_ASGI1R_EL1 register with RS != 0 is a CONSTRAINED 1015 * UNPREDICTABLE choice of : 1016 * - The write is ignored. 1017 * - The RS field is treated as 0. 1018 */ 1019 if (need_rss && (!gic_data.has_rss)) 1020 pr_crit_once("RSS is required but GICD doesn't support it\n"); 1021 } 1022 1023 static bool gicv3_nolpi; 1024 1025 static int __init gicv3_nolpi_cfg(char *buf) 1026 { 1027 return strtobool(buf, &gicv3_nolpi); 1028 } 1029 early_param("irqchip.gicv3_nolpi", gicv3_nolpi_cfg); 1030 1031 static int gic_dist_supports_lpis(void) 1032 { 1033 return (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && 1034 !!(readl_relaxed(gic_data.dist_base + GICD_TYPER) & GICD_TYPER_LPIS) && 1035 !gicv3_nolpi); 1036 } 1037 1038 static void gic_cpu_init(void) 1039 { 1040 void __iomem *rbase; 1041 int i; 1042 1043 /* Register ourselves with the rest of the world */ 1044 if (gic_populate_rdist()) 1045 return; 1046 1047 gic_enable_redist(true); 1048 1049 WARN((gic_data.ppi_nr > 16 || GIC_ESPI_NR != 0) && 1050 !(gic_read_ctlr() & ICC_CTLR_EL1_ExtRange), 1051 "Distributor has extended ranges, but CPU%d doesn't\n", 1052 smp_processor_id()); 1053 1054 rbase = gic_data_rdist_sgi_base(); 1055 1056 /* Configure SGIs/PPIs as non-secure Group-1 */ 1057 for (i = 0; i < gic_data.ppi_nr + 16; i += 32) 1058 writel_relaxed(~0, rbase + GICR_IGROUPR0 + i / 8); 1059 1060 gic_cpu_config(rbase, gic_data.ppi_nr + 16, gic_redist_wait_for_rwp); 1061 1062 /* initialise system registers */ 1063 gic_cpu_sys_reg_init(); 1064 } 1065 1066 #ifdef CONFIG_SMP 1067 1068 #define MPIDR_TO_SGI_RS(mpidr) (MPIDR_RS(mpidr) << ICC_SGI1R_RS_SHIFT) 1069 #define MPIDR_TO_SGI_CLUSTER_ID(mpidr) ((mpidr) & ~0xFUL) 1070 1071 static int gic_starting_cpu(unsigned int cpu) 1072 { 1073 gic_cpu_init(); 1074 1075 if (gic_dist_supports_lpis()) 1076 its_cpu_init(); 1077 1078 return 0; 1079 } 1080 1081 static u16 gic_compute_target_list(int *base_cpu, const struct cpumask *mask, 1082 unsigned long cluster_id) 1083 { 1084 int next_cpu, cpu = *base_cpu; 1085 unsigned long mpidr = cpu_logical_map(cpu); 1086 u16 tlist = 0; 1087 1088 while (cpu < nr_cpu_ids) { 1089 tlist |= 1 << (mpidr & 0xf); 1090 1091 next_cpu = cpumask_next(cpu, mask); 1092 if (next_cpu >= nr_cpu_ids) 1093 goto out; 1094 cpu = next_cpu; 1095 1096 mpidr = cpu_logical_map(cpu); 1097 1098 if (cluster_id != MPIDR_TO_SGI_CLUSTER_ID(mpidr)) { 1099 cpu--; 1100 goto out; 1101 } 1102 } 1103 out: 1104 *base_cpu = cpu; 1105 return tlist; 1106 } 1107 1108 #define MPIDR_TO_SGI_AFFINITY(cluster_id, level) \ 1109 (MPIDR_AFFINITY_LEVEL(cluster_id, level) \ 1110 << ICC_SGI1R_AFFINITY_## level ##_SHIFT) 1111 1112 static void gic_send_sgi(u64 cluster_id, u16 tlist, unsigned int irq) 1113 { 1114 u64 val; 1115 1116 val = (MPIDR_TO_SGI_AFFINITY(cluster_id, 3) | 1117 MPIDR_TO_SGI_AFFINITY(cluster_id, 2) | 1118 irq << ICC_SGI1R_SGI_ID_SHIFT | 1119 MPIDR_TO_SGI_AFFINITY(cluster_id, 1) | 1120 MPIDR_TO_SGI_RS(cluster_id) | 1121 tlist << ICC_SGI1R_TARGET_LIST_SHIFT); 1122 1123 pr_devel("CPU%d: ICC_SGI1R_EL1 %llx\n", smp_processor_id(), val); 1124 gic_write_sgi1r(val); 1125 } 1126 1127 static void gic_ipi_send_mask(struct irq_data *d, const struct cpumask *mask) 1128 { 1129 int cpu; 1130 1131 if (WARN_ON(d->hwirq >= 16)) 1132 return; 1133 1134 /* 1135 * Ensure that stores to Normal memory are visible to the 1136 * other CPUs before issuing the IPI. 1137 */ 1138 wmb(); 1139 1140 for_each_cpu(cpu, mask) { 1141 u64 cluster_id = MPIDR_TO_SGI_CLUSTER_ID(cpu_logical_map(cpu)); 1142 u16 tlist; 1143 1144 tlist = gic_compute_target_list(&cpu, mask, cluster_id); 1145 gic_send_sgi(cluster_id, tlist, d->hwirq); 1146 } 1147 1148 /* Force the above writes to ICC_SGI1R_EL1 to be executed */ 1149 isb(); 1150 } 1151 1152 static void __init gic_smp_init(void) 1153 { 1154 struct irq_fwspec sgi_fwspec = { 1155 .fwnode = gic_data.fwnode, 1156 .param_count = 1, 1157 }; 1158 int base_sgi; 1159 1160 cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_GIC_STARTING, 1161 "irqchip/arm/gicv3:starting", 1162 gic_starting_cpu, NULL); 1163 1164 /* Register all 8 non-secure SGIs */ 1165 base_sgi = __irq_domain_alloc_irqs(gic_data.domain, -1, 8, 1166 NUMA_NO_NODE, &sgi_fwspec, 1167 false, NULL); 1168 if (WARN_ON(base_sgi <= 0)) 1169 return; 1170 1171 set_smp_ipi_range(base_sgi, 8); 1172 } 1173 1174 static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, 1175 bool force) 1176 { 1177 unsigned int cpu; 1178 u32 offset, index; 1179 void __iomem *reg; 1180 int enabled; 1181 u64 val; 1182 1183 if (force) 1184 cpu = cpumask_first(mask_val); 1185 else 1186 cpu = cpumask_any_and(mask_val, cpu_online_mask); 1187 1188 if (cpu >= nr_cpu_ids) 1189 return -EINVAL; 1190 1191 if (gic_irq_in_rdist(d)) 1192 return -EINVAL; 1193 1194 /* If interrupt was enabled, disable it first */ 1195 enabled = gic_peek_irq(d, GICD_ISENABLER); 1196 if (enabled) 1197 gic_mask_irq(d); 1198 1199 offset = convert_offset_index(d, GICD_IROUTER, &index); 1200 reg = gic_dist_base(d) + offset + (index * 8); 1201 val = gic_mpidr_to_affinity(cpu_logical_map(cpu)); 1202 1203 gic_write_irouter(val, reg); 1204 1205 /* 1206 * If the interrupt was enabled, enabled it again. Otherwise, 1207 * just wait for the distributor to have digested our changes. 1208 */ 1209 if (enabled) 1210 gic_unmask_irq(d); 1211 else 1212 gic_dist_wait_for_rwp(); 1213 1214 irq_data_update_effective_affinity(d, cpumask_of(cpu)); 1215 1216 return IRQ_SET_MASK_OK_DONE; 1217 } 1218 #else 1219 #define gic_set_affinity NULL 1220 #define gic_ipi_send_mask NULL 1221 #define gic_smp_init() do { } while(0) 1222 #endif 1223 1224 static int gic_retrigger(struct irq_data *data) 1225 { 1226 return !gic_irq_set_irqchip_state(data, IRQCHIP_STATE_PENDING, true); 1227 } 1228 1229 #ifdef CONFIG_CPU_PM 1230 static int gic_cpu_pm_notifier(struct notifier_block *self, 1231 unsigned long cmd, void *v) 1232 { 1233 if (cmd == CPU_PM_EXIT) { 1234 if (gic_dist_security_disabled()) 1235 gic_enable_redist(true); 1236 gic_cpu_sys_reg_init(); 1237 } else if (cmd == CPU_PM_ENTER && gic_dist_security_disabled()) { 1238 gic_write_grpen1(0); 1239 gic_enable_redist(false); 1240 } 1241 return NOTIFY_OK; 1242 } 1243 1244 static struct notifier_block gic_cpu_pm_notifier_block = { 1245 .notifier_call = gic_cpu_pm_notifier, 1246 }; 1247 1248 static void gic_cpu_pm_init(void) 1249 { 1250 cpu_pm_register_notifier(&gic_cpu_pm_notifier_block); 1251 } 1252 1253 #else 1254 static inline void gic_cpu_pm_init(void) { } 1255 #endif /* CONFIG_CPU_PM */ 1256 1257 static struct irq_chip gic_chip = { 1258 .name = "GICv3", 1259 .irq_mask = gic_mask_irq, 1260 .irq_unmask = gic_unmask_irq, 1261 .irq_eoi = gic_eoi_irq, 1262 .irq_set_type = gic_set_type, 1263 .irq_set_affinity = gic_set_affinity, 1264 .irq_retrigger = gic_retrigger, 1265 .irq_get_irqchip_state = gic_irq_get_irqchip_state, 1266 .irq_set_irqchip_state = gic_irq_set_irqchip_state, 1267 .irq_nmi_setup = gic_irq_nmi_setup, 1268 .irq_nmi_teardown = gic_irq_nmi_teardown, 1269 .ipi_send_mask = gic_ipi_send_mask, 1270 .flags = IRQCHIP_SET_TYPE_MASKED | 1271 IRQCHIP_SKIP_SET_WAKE | 1272 IRQCHIP_MASK_ON_SUSPEND, 1273 }; 1274 1275 static struct irq_chip gic_eoimode1_chip = { 1276 .name = "GICv3", 1277 .irq_mask = gic_eoimode1_mask_irq, 1278 .irq_unmask = gic_unmask_irq, 1279 .irq_eoi = gic_eoimode1_eoi_irq, 1280 .irq_set_type = gic_set_type, 1281 .irq_set_affinity = gic_set_affinity, 1282 .irq_retrigger = gic_retrigger, 1283 .irq_get_irqchip_state = gic_irq_get_irqchip_state, 1284 .irq_set_irqchip_state = gic_irq_set_irqchip_state, 1285 .irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity, 1286 .irq_nmi_setup = gic_irq_nmi_setup, 1287 .irq_nmi_teardown = gic_irq_nmi_teardown, 1288 .ipi_send_mask = gic_ipi_send_mask, 1289 .flags = IRQCHIP_SET_TYPE_MASKED | 1290 IRQCHIP_SKIP_SET_WAKE | 1291 IRQCHIP_MASK_ON_SUSPEND, 1292 }; 1293 1294 static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq, 1295 irq_hw_number_t hw) 1296 { 1297 struct irq_chip *chip = &gic_chip; 1298 struct irq_data *irqd = irq_desc_get_irq_data(irq_to_desc(irq)); 1299 1300 if (static_branch_likely(&supports_deactivate_key)) 1301 chip = &gic_eoimode1_chip; 1302 1303 switch (__get_intid_range(hw)) { 1304 case SGI_RANGE: 1305 irq_set_percpu_devid(irq); 1306 irq_domain_set_info(d, irq, hw, chip, d->host_data, 1307 handle_percpu_devid_fasteoi_ipi, 1308 NULL, NULL); 1309 break; 1310 1311 case PPI_RANGE: 1312 case EPPI_RANGE: 1313 irq_set_percpu_devid(irq); 1314 irq_domain_set_info(d, irq, hw, chip, d->host_data, 1315 handle_percpu_devid_irq, NULL, NULL); 1316 break; 1317 1318 case SPI_RANGE: 1319 case ESPI_RANGE: 1320 irq_domain_set_info(d, irq, hw, chip, d->host_data, 1321 handle_fasteoi_irq, NULL, NULL); 1322 irq_set_probe(irq); 1323 irqd_set_single_target(irqd); 1324 break; 1325 1326 case LPI_RANGE: 1327 if (!gic_dist_supports_lpis()) 1328 return -EPERM; 1329 irq_domain_set_info(d, irq, hw, chip, d->host_data, 1330 handle_fasteoi_irq, NULL, NULL); 1331 break; 1332 1333 default: 1334 return -EPERM; 1335 } 1336 1337 /* Prevents SW retriggers which mess up the ACK/EOI ordering */ 1338 irqd_set_handle_enforce_irqctx(irqd); 1339 return 0; 1340 } 1341 1342 static int gic_irq_domain_translate(struct irq_domain *d, 1343 struct irq_fwspec *fwspec, 1344 unsigned long *hwirq, 1345 unsigned int *type) 1346 { 1347 if (fwspec->param_count == 1 && fwspec->param[0] < 16) { 1348 *hwirq = fwspec->param[0]; 1349 *type = IRQ_TYPE_EDGE_RISING; 1350 return 0; 1351 } 1352 1353 if (is_of_node(fwspec->fwnode)) { 1354 if (fwspec->param_count < 3) 1355 return -EINVAL; 1356 1357 switch (fwspec->param[0]) { 1358 case 0: /* SPI */ 1359 *hwirq = fwspec->param[1] + 32; 1360 break; 1361 case 1: /* PPI */ 1362 *hwirq = fwspec->param[1] + 16; 1363 break; 1364 case 2: /* ESPI */ 1365 *hwirq = fwspec->param[1] + ESPI_BASE_INTID; 1366 break; 1367 case 3: /* EPPI */ 1368 *hwirq = fwspec->param[1] + EPPI_BASE_INTID; 1369 break; 1370 case GIC_IRQ_TYPE_LPI: /* LPI */ 1371 *hwirq = fwspec->param[1]; 1372 break; 1373 case GIC_IRQ_TYPE_PARTITION: 1374 *hwirq = fwspec->param[1]; 1375 if (fwspec->param[1] >= 16) 1376 *hwirq += EPPI_BASE_INTID - 16; 1377 else 1378 *hwirq += 16; 1379 break; 1380 default: 1381 return -EINVAL; 1382 } 1383 1384 *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; 1385 1386 /* 1387 * Make it clear that broken DTs are... broken. 1388 * Partitionned PPIs are an unfortunate exception. 1389 */ 1390 WARN_ON(*type == IRQ_TYPE_NONE && 1391 fwspec->param[0] != GIC_IRQ_TYPE_PARTITION); 1392 return 0; 1393 } 1394 1395 if (is_fwnode_irqchip(fwspec->fwnode)) { 1396 if(fwspec->param_count != 2) 1397 return -EINVAL; 1398 1399 *hwirq = fwspec->param[0]; 1400 *type = fwspec->param[1]; 1401 1402 WARN_ON(*type == IRQ_TYPE_NONE); 1403 return 0; 1404 } 1405 1406 return -EINVAL; 1407 } 1408 1409 static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, 1410 unsigned int nr_irqs, void *arg) 1411 { 1412 int i, ret; 1413 irq_hw_number_t hwirq; 1414 unsigned int type = IRQ_TYPE_NONE; 1415 struct irq_fwspec *fwspec = arg; 1416 1417 ret = gic_irq_domain_translate(domain, fwspec, &hwirq, &type); 1418 if (ret) 1419 return ret; 1420 1421 for (i = 0; i < nr_irqs; i++) { 1422 ret = gic_irq_domain_map(domain, virq + i, hwirq + i); 1423 if (ret) 1424 return ret; 1425 } 1426 1427 return 0; 1428 } 1429 1430 static void gic_irq_domain_free(struct irq_domain *domain, unsigned int virq, 1431 unsigned int nr_irqs) 1432 { 1433 int i; 1434 1435 for (i = 0; i < nr_irqs; i++) { 1436 struct irq_data *d = irq_domain_get_irq_data(domain, virq + i); 1437 irq_set_handler(virq + i, NULL); 1438 irq_domain_reset_irq_data(d); 1439 } 1440 } 1441 1442 static int gic_irq_domain_select(struct irq_domain *d, 1443 struct irq_fwspec *fwspec, 1444 enum irq_domain_bus_token bus_token) 1445 { 1446 /* Not for us */ 1447 if (fwspec->fwnode != d->fwnode) 1448 return 0; 1449 1450 /* If this is not DT, then we have a single domain */ 1451 if (!is_of_node(fwspec->fwnode)) 1452 return 1; 1453 1454 /* 1455 * If this is a PPI and we have a 4th (non-null) parameter, 1456 * then we need to match the partition domain. 1457 */ 1458 if (fwspec->param_count >= 4 && 1459 fwspec->param[0] == 1 && fwspec->param[3] != 0 && 1460 gic_data.ppi_descs) 1461 return d == partition_get_domain(gic_data.ppi_descs[fwspec->param[1]]); 1462 1463 return d == gic_data.domain; 1464 } 1465 1466 static const struct irq_domain_ops gic_irq_domain_ops = { 1467 .translate = gic_irq_domain_translate, 1468 .alloc = gic_irq_domain_alloc, 1469 .free = gic_irq_domain_free, 1470 .select = gic_irq_domain_select, 1471 }; 1472 1473 static int partition_domain_translate(struct irq_domain *d, 1474 struct irq_fwspec *fwspec, 1475 unsigned long *hwirq, 1476 unsigned int *type) 1477 { 1478 struct device_node *np; 1479 int ret; 1480 1481 if (!gic_data.ppi_descs) 1482 return -ENOMEM; 1483 1484 np = of_find_node_by_phandle(fwspec->param[3]); 1485 if (WARN_ON(!np)) 1486 return -EINVAL; 1487 1488 ret = partition_translate_id(gic_data.ppi_descs[fwspec->param[1]], 1489 of_node_to_fwnode(np)); 1490 if (ret < 0) 1491 return ret; 1492 1493 *hwirq = ret; 1494 *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; 1495 1496 return 0; 1497 } 1498 1499 static const struct irq_domain_ops partition_domain_ops = { 1500 .translate = partition_domain_translate, 1501 .select = gic_irq_domain_select, 1502 }; 1503 1504 static bool gic_enable_quirk_msm8996(void *data) 1505 { 1506 struct gic_chip_data *d = data; 1507 1508 d->flags |= FLAGS_WORKAROUND_GICR_WAKER_MSM8996; 1509 1510 return true; 1511 } 1512 1513 static bool gic_enable_quirk_cavium_38539(void *data) 1514 { 1515 struct gic_chip_data *d = data; 1516 1517 d->flags |= FLAGS_WORKAROUND_CAVIUM_ERRATUM_38539; 1518 1519 return true; 1520 } 1521 1522 static bool gic_enable_quirk_hip06_07(void *data) 1523 { 1524 struct gic_chip_data *d = data; 1525 1526 /* 1527 * HIP06 GICD_IIDR clashes with GIC-600 product number (despite 1528 * not being an actual ARM implementation). The saving grace is 1529 * that GIC-600 doesn't have ESPI, so nothing to do in that case. 1530 * HIP07 doesn't even have a proper IIDR, and still pretends to 1531 * have ESPI. In both cases, put them right. 1532 */ 1533 if (d->rdists.gicd_typer & GICD_TYPER_ESPI) { 1534 /* Zero both ESPI and the RES0 field next to it... */ 1535 d->rdists.gicd_typer &= ~GENMASK(9, 8); 1536 return true; 1537 } 1538 1539 return false; 1540 } 1541 1542 static const struct gic_quirk gic_quirks[] = { 1543 { 1544 .desc = "GICv3: Qualcomm MSM8996 broken firmware", 1545 .compatible = "qcom,msm8996-gic-v3", 1546 .init = gic_enable_quirk_msm8996, 1547 }, 1548 { 1549 .desc = "GICv3: HIP06 erratum 161010803", 1550 .iidr = 0x0204043b, 1551 .mask = 0xffffffff, 1552 .init = gic_enable_quirk_hip06_07, 1553 }, 1554 { 1555 .desc = "GICv3: HIP07 erratum 161010803", 1556 .iidr = 0x00000000, 1557 .mask = 0xffffffff, 1558 .init = gic_enable_quirk_hip06_07, 1559 }, 1560 { 1561 /* 1562 * Reserved register accesses generate a Synchronous 1563 * External Abort. This erratum applies to: 1564 * - ThunderX: CN88xx 1565 * - OCTEON TX: CN83xx, CN81xx 1566 * - OCTEON TX2: CN93xx, CN96xx, CN98xx, CNF95xx* 1567 */ 1568 .desc = "GICv3: Cavium erratum 38539", 1569 .iidr = 0xa000034c, 1570 .mask = 0xe8f00fff, 1571 .init = gic_enable_quirk_cavium_38539, 1572 }, 1573 { 1574 } 1575 }; 1576 1577 static void gic_enable_nmi_support(void) 1578 { 1579 int i; 1580 1581 if (!gic_prio_masking_enabled()) 1582 return; 1583 1584 ppi_nmi_refs = kcalloc(gic_data.ppi_nr, sizeof(*ppi_nmi_refs), GFP_KERNEL); 1585 if (!ppi_nmi_refs) 1586 return; 1587 1588 for (i = 0; i < gic_data.ppi_nr; i++) 1589 refcount_set(&ppi_nmi_refs[i], 0); 1590 1591 /* 1592 * Linux itself doesn't use 1:N distribution, so has no need to 1593 * set PMHE. The only reason to have it set is if EL3 requires it 1594 * (and we can't change it). 1595 */ 1596 if (gic_read_ctlr() & ICC_CTLR_EL1_PMHE_MASK) 1597 static_branch_enable(&gic_pmr_sync); 1598 1599 pr_info("Pseudo-NMIs enabled using %s ICC_PMR_EL1 synchronisation\n", 1600 static_branch_unlikely(&gic_pmr_sync) ? "forced" : "relaxed"); 1601 1602 /* 1603 * How priority values are used by the GIC depends on two things: 1604 * the security state of the GIC (controlled by the GICD_CTRL.DS bit) 1605 * and if Group 0 interrupts can be delivered to Linux in the non-secure 1606 * world as FIQs (controlled by the SCR_EL3.FIQ bit). These affect the 1607 * the ICC_PMR_EL1 register and the priority that software assigns to 1608 * interrupts: 1609 * 1610 * GICD_CTRL.DS | SCR_EL3.FIQ | ICC_PMR_EL1 | Group 1 priority 1611 * ----------------------------------------------------------- 1612 * 1 | - | unchanged | unchanged 1613 * ----------------------------------------------------------- 1614 * 0 | 1 | non-secure | non-secure 1615 * ----------------------------------------------------------- 1616 * 0 | 0 | unchanged | non-secure 1617 * 1618 * where non-secure means that the value is right-shifted by one and the 1619 * MSB bit set, to make it fit in the non-secure priority range. 1620 * 1621 * In the first two cases, where ICC_PMR_EL1 and the interrupt priority 1622 * are both either modified or unchanged, we can use the same set of 1623 * priorities. 1624 * 1625 * In the last case, where only the interrupt priorities are modified to 1626 * be in the non-secure range, we use a different PMR value to mask IRQs 1627 * and the rest of the values that we use remain unchanged. 1628 */ 1629 if (gic_has_group0() && !gic_dist_security_disabled()) 1630 static_branch_enable(&gic_nonsecure_priorities); 1631 1632 static_branch_enable(&supports_pseudo_nmis); 1633 1634 if (static_branch_likely(&supports_deactivate_key)) 1635 gic_eoimode1_chip.flags |= IRQCHIP_SUPPORTS_NMI; 1636 else 1637 gic_chip.flags |= IRQCHIP_SUPPORTS_NMI; 1638 } 1639 1640 static int __init gic_init_bases(void __iomem *dist_base, 1641 struct redist_region *rdist_regs, 1642 u32 nr_redist_regions, 1643 u64 redist_stride, 1644 struct fwnode_handle *handle) 1645 { 1646 u32 typer; 1647 int err; 1648 1649 if (!is_hyp_mode_available()) 1650 static_branch_disable(&supports_deactivate_key); 1651 1652 if (static_branch_likely(&supports_deactivate_key)) 1653 pr_info("GIC: Using split EOI/Deactivate mode\n"); 1654 1655 gic_data.fwnode = handle; 1656 gic_data.dist_base = dist_base; 1657 gic_data.redist_regions = rdist_regs; 1658 gic_data.nr_redist_regions = nr_redist_regions; 1659 gic_data.redist_stride = redist_stride; 1660 1661 /* 1662 * Find out how many interrupts are supported. 1663 */ 1664 typer = readl_relaxed(gic_data.dist_base + GICD_TYPER); 1665 gic_data.rdists.gicd_typer = typer; 1666 1667 gic_enable_quirks(readl_relaxed(gic_data.dist_base + GICD_IIDR), 1668 gic_quirks, &gic_data); 1669 1670 pr_info("%d SPIs implemented\n", GIC_LINE_NR - 32); 1671 pr_info("%d Extended SPIs implemented\n", GIC_ESPI_NR); 1672 1673 /* 1674 * ThunderX1 explodes on reading GICD_TYPER2, in violation of the 1675 * architecture spec (which says that reserved registers are RES0). 1676 */ 1677 if (!(gic_data.flags & FLAGS_WORKAROUND_CAVIUM_ERRATUM_38539)) 1678 gic_data.rdists.gicd_typer2 = readl_relaxed(gic_data.dist_base + GICD_TYPER2); 1679 1680 gic_data.domain = irq_domain_create_tree(handle, &gic_irq_domain_ops, 1681 &gic_data); 1682 gic_data.rdists.rdist = alloc_percpu(typeof(*gic_data.rdists.rdist)); 1683 gic_data.rdists.has_rvpeid = true; 1684 gic_data.rdists.has_vlpis = true; 1685 gic_data.rdists.has_direct_lpi = true; 1686 gic_data.rdists.has_vpend_valid_dirty = true; 1687 1688 if (WARN_ON(!gic_data.domain) || WARN_ON(!gic_data.rdists.rdist)) { 1689 err = -ENOMEM; 1690 goto out_free; 1691 } 1692 1693 irq_domain_update_bus_token(gic_data.domain, DOMAIN_BUS_WIRED); 1694 1695 gic_data.has_rss = !!(typer & GICD_TYPER_RSS); 1696 pr_info("Distributor has %sRange Selector support\n", 1697 gic_data.has_rss ? "" : "no "); 1698 1699 if (typer & GICD_TYPER_MBIS) { 1700 err = mbi_init(handle, gic_data.domain); 1701 if (err) 1702 pr_err("Failed to initialize MBIs\n"); 1703 } 1704 1705 set_handle_irq(gic_handle_irq); 1706 1707 gic_update_rdist_properties(); 1708 1709 gic_dist_init(); 1710 gic_cpu_init(); 1711 gic_smp_init(); 1712 gic_cpu_pm_init(); 1713 1714 if (gic_dist_supports_lpis()) { 1715 its_init(handle, &gic_data.rdists, gic_data.domain); 1716 its_cpu_init(); 1717 } else { 1718 if (IS_ENABLED(CONFIG_ARM_GIC_V2M)) 1719 gicv2m_init(handle, gic_data.domain); 1720 } 1721 1722 gic_enable_nmi_support(); 1723 1724 return 0; 1725 1726 out_free: 1727 if (gic_data.domain) 1728 irq_domain_remove(gic_data.domain); 1729 free_percpu(gic_data.rdists.rdist); 1730 return err; 1731 } 1732 1733 static int __init gic_validate_dist_version(void __iomem *dist_base) 1734 { 1735 u32 reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK; 1736 1737 if (reg != GIC_PIDR2_ARCH_GICv3 && reg != GIC_PIDR2_ARCH_GICv4) 1738 return -ENODEV; 1739 1740 return 0; 1741 } 1742 1743 /* Create all possible partitions at boot time */ 1744 static void __init gic_populate_ppi_partitions(struct device_node *gic_node) 1745 { 1746 struct device_node *parts_node, *child_part; 1747 int part_idx = 0, i; 1748 int nr_parts; 1749 struct partition_affinity *parts; 1750 1751 parts_node = of_get_child_by_name(gic_node, "ppi-partitions"); 1752 if (!parts_node) 1753 return; 1754 1755 gic_data.ppi_descs = kcalloc(gic_data.ppi_nr, sizeof(*gic_data.ppi_descs), GFP_KERNEL); 1756 if (!gic_data.ppi_descs) 1757 return; 1758 1759 nr_parts = of_get_child_count(parts_node); 1760 1761 if (!nr_parts) 1762 goto out_put_node; 1763 1764 parts = kcalloc(nr_parts, sizeof(*parts), GFP_KERNEL); 1765 if (WARN_ON(!parts)) 1766 goto out_put_node; 1767 1768 for_each_child_of_node(parts_node, child_part) { 1769 struct partition_affinity *part; 1770 int n; 1771 1772 part = &parts[part_idx]; 1773 1774 part->partition_id = of_node_to_fwnode(child_part); 1775 1776 pr_info("GIC: PPI partition %pOFn[%d] { ", 1777 child_part, part_idx); 1778 1779 n = of_property_count_elems_of_size(child_part, "affinity", 1780 sizeof(u32)); 1781 WARN_ON(n <= 0); 1782 1783 for (i = 0; i < n; i++) { 1784 int err, cpu; 1785 u32 cpu_phandle; 1786 struct device_node *cpu_node; 1787 1788 err = of_property_read_u32_index(child_part, "affinity", 1789 i, &cpu_phandle); 1790 if (WARN_ON(err)) 1791 continue; 1792 1793 cpu_node = of_find_node_by_phandle(cpu_phandle); 1794 if (WARN_ON(!cpu_node)) 1795 continue; 1796 1797 cpu = of_cpu_node_to_id(cpu_node); 1798 if (WARN_ON(cpu < 0)) 1799 continue; 1800 1801 pr_cont("%pOF[%d] ", cpu_node, cpu); 1802 1803 cpumask_set_cpu(cpu, &part->mask); 1804 } 1805 1806 pr_cont("}\n"); 1807 part_idx++; 1808 } 1809 1810 for (i = 0; i < gic_data.ppi_nr; i++) { 1811 unsigned int irq; 1812 struct partition_desc *desc; 1813 struct irq_fwspec ppi_fwspec = { 1814 .fwnode = gic_data.fwnode, 1815 .param_count = 3, 1816 .param = { 1817 [0] = GIC_IRQ_TYPE_PARTITION, 1818 [1] = i, 1819 [2] = IRQ_TYPE_NONE, 1820 }, 1821 }; 1822 1823 irq = irq_create_fwspec_mapping(&ppi_fwspec); 1824 if (WARN_ON(!irq)) 1825 continue; 1826 desc = partition_create_desc(gic_data.fwnode, parts, nr_parts, 1827 irq, &partition_domain_ops); 1828 if (WARN_ON(!desc)) 1829 continue; 1830 1831 gic_data.ppi_descs[i] = desc; 1832 } 1833 1834 out_put_node: 1835 of_node_put(parts_node); 1836 } 1837 1838 static void __init gic_of_setup_kvm_info(struct device_node *node) 1839 { 1840 int ret; 1841 struct resource r; 1842 u32 gicv_idx; 1843 1844 gic_v3_kvm_info.type = GIC_V3; 1845 1846 gic_v3_kvm_info.maint_irq = irq_of_parse_and_map(node, 0); 1847 if (!gic_v3_kvm_info.maint_irq) 1848 return; 1849 1850 if (of_property_read_u32(node, "#redistributor-regions", 1851 &gicv_idx)) 1852 gicv_idx = 1; 1853 1854 gicv_idx += 3; /* Also skip GICD, GICC, GICH */ 1855 ret = of_address_to_resource(node, gicv_idx, &r); 1856 if (!ret) 1857 gic_v3_kvm_info.vcpu = r; 1858 1859 gic_v3_kvm_info.has_v4 = gic_data.rdists.has_vlpis; 1860 gic_v3_kvm_info.has_v4_1 = gic_data.rdists.has_rvpeid; 1861 gic_set_kvm_info(&gic_v3_kvm_info); 1862 } 1863 1864 static int __init gic_of_init(struct device_node *node, struct device_node *parent) 1865 { 1866 void __iomem *dist_base; 1867 struct redist_region *rdist_regs; 1868 u64 redist_stride; 1869 u32 nr_redist_regions; 1870 int err, i; 1871 1872 dist_base = of_iomap(node, 0); 1873 if (!dist_base) { 1874 pr_err("%pOF: unable to map gic dist registers\n", node); 1875 return -ENXIO; 1876 } 1877 1878 err = gic_validate_dist_version(dist_base); 1879 if (err) { 1880 pr_err("%pOF: no distributor detected, giving up\n", node); 1881 goto out_unmap_dist; 1882 } 1883 1884 if (of_property_read_u32(node, "#redistributor-regions", &nr_redist_regions)) 1885 nr_redist_regions = 1; 1886 1887 rdist_regs = kcalloc(nr_redist_regions, sizeof(*rdist_regs), 1888 GFP_KERNEL); 1889 if (!rdist_regs) { 1890 err = -ENOMEM; 1891 goto out_unmap_dist; 1892 } 1893 1894 for (i = 0; i < nr_redist_regions; i++) { 1895 struct resource res; 1896 int ret; 1897 1898 ret = of_address_to_resource(node, 1 + i, &res); 1899 rdist_regs[i].redist_base = of_iomap(node, 1 + i); 1900 if (ret || !rdist_regs[i].redist_base) { 1901 pr_err("%pOF: couldn't map region %d\n", node, i); 1902 err = -ENODEV; 1903 goto out_unmap_rdist; 1904 } 1905 rdist_regs[i].phys_base = res.start; 1906 } 1907 1908 if (of_property_read_u64(node, "redistributor-stride", &redist_stride)) 1909 redist_stride = 0; 1910 1911 gic_enable_of_quirks(node, gic_quirks, &gic_data); 1912 1913 err = gic_init_bases(dist_base, rdist_regs, nr_redist_regions, 1914 redist_stride, &node->fwnode); 1915 if (err) 1916 goto out_unmap_rdist; 1917 1918 gic_populate_ppi_partitions(node); 1919 1920 if (static_branch_likely(&supports_deactivate_key)) 1921 gic_of_setup_kvm_info(node); 1922 return 0; 1923 1924 out_unmap_rdist: 1925 for (i = 0; i < nr_redist_regions; i++) 1926 if (rdist_regs[i].redist_base) 1927 iounmap(rdist_regs[i].redist_base); 1928 kfree(rdist_regs); 1929 out_unmap_dist: 1930 iounmap(dist_base); 1931 return err; 1932 } 1933 1934 IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init); 1935 1936 #ifdef CONFIG_ACPI 1937 static struct 1938 { 1939 void __iomem *dist_base; 1940 struct redist_region *redist_regs; 1941 u32 nr_redist_regions; 1942 bool single_redist; 1943 int enabled_rdists; 1944 u32 maint_irq; 1945 int maint_irq_mode; 1946 phys_addr_t vcpu_base; 1947 } acpi_data __initdata; 1948 1949 static void __init 1950 gic_acpi_register_redist(phys_addr_t phys_base, void __iomem *redist_base) 1951 { 1952 static int count = 0; 1953 1954 acpi_data.redist_regs[count].phys_base = phys_base; 1955 acpi_data.redist_regs[count].redist_base = redist_base; 1956 acpi_data.redist_regs[count].single_redist = acpi_data.single_redist; 1957 count++; 1958 } 1959 1960 static int __init 1961 gic_acpi_parse_madt_redist(union acpi_subtable_headers *header, 1962 const unsigned long end) 1963 { 1964 struct acpi_madt_generic_redistributor *redist = 1965 (struct acpi_madt_generic_redistributor *)header; 1966 void __iomem *redist_base; 1967 1968 redist_base = ioremap(redist->base_address, redist->length); 1969 if (!redist_base) { 1970 pr_err("Couldn't map GICR region @%llx\n", redist->base_address); 1971 return -ENOMEM; 1972 } 1973 1974 gic_acpi_register_redist(redist->base_address, redist_base); 1975 return 0; 1976 } 1977 1978 static int __init 1979 gic_acpi_parse_madt_gicc(union acpi_subtable_headers *header, 1980 const unsigned long end) 1981 { 1982 struct acpi_madt_generic_interrupt *gicc = 1983 (struct acpi_madt_generic_interrupt *)header; 1984 u32 reg = readl_relaxed(acpi_data.dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK; 1985 u32 size = reg == GIC_PIDR2_ARCH_GICv4 ? SZ_64K * 4 : SZ_64K * 2; 1986 void __iomem *redist_base; 1987 1988 /* GICC entry which has !ACPI_MADT_ENABLED is not unusable so skip */ 1989 if (!(gicc->flags & ACPI_MADT_ENABLED)) 1990 return 0; 1991 1992 redist_base = ioremap(gicc->gicr_base_address, size); 1993 if (!redist_base) 1994 return -ENOMEM; 1995 1996 gic_acpi_register_redist(gicc->gicr_base_address, redist_base); 1997 return 0; 1998 } 1999 2000 static int __init gic_acpi_collect_gicr_base(void) 2001 { 2002 acpi_tbl_entry_handler redist_parser; 2003 enum acpi_madt_type type; 2004 2005 if (acpi_data.single_redist) { 2006 type = ACPI_MADT_TYPE_GENERIC_INTERRUPT; 2007 redist_parser = gic_acpi_parse_madt_gicc; 2008 } else { 2009 type = ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR; 2010 redist_parser = gic_acpi_parse_madt_redist; 2011 } 2012 2013 /* Collect redistributor base addresses in GICR entries */ 2014 if (acpi_table_parse_madt(type, redist_parser, 0) > 0) 2015 return 0; 2016 2017 pr_info("No valid GICR entries exist\n"); 2018 return -ENODEV; 2019 } 2020 2021 static int __init gic_acpi_match_gicr(union acpi_subtable_headers *header, 2022 const unsigned long end) 2023 { 2024 /* Subtable presence means that redist exists, that's it */ 2025 return 0; 2026 } 2027 2028 static int __init gic_acpi_match_gicc(union acpi_subtable_headers *header, 2029 const unsigned long end) 2030 { 2031 struct acpi_madt_generic_interrupt *gicc = 2032 (struct acpi_madt_generic_interrupt *)header; 2033 2034 /* 2035 * If GICC is enabled and has valid gicr base address, then it means 2036 * GICR base is presented via GICC 2037 */ 2038 if ((gicc->flags & ACPI_MADT_ENABLED) && gicc->gicr_base_address) { 2039 acpi_data.enabled_rdists++; 2040 return 0; 2041 } 2042 2043 /* 2044 * It's perfectly valid firmware can pass disabled GICC entry, driver 2045 * should not treat as errors, skip the entry instead of probe fail. 2046 */ 2047 if (!(gicc->flags & ACPI_MADT_ENABLED)) 2048 return 0; 2049 2050 return -ENODEV; 2051 } 2052 2053 static int __init gic_acpi_count_gicr_regions(void) 2054 { 2055 int count; 2056 2057 /* 2058 * Count how many redistributor regions we have. It is not allowed 2059 * to mix redistributor description, GICR and GICC subtables have to be 2060 * mutually exclusive. 2061 */ 2062 count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR, 2063 gic_acpi_match_gicr, 0); 2064 if (count > 0) { 2065 acpi_data.single_redist = false; 2066 return count; 2067 } 2068 2069 count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT, 2070 gic_acpi_match_gicc, 0); 2071 if (count > 0) { 2072 acpi_data.single_redist = true; 2073 count = acpi_data.enabled_rdists; 2074 } 2075 2076 return count; 2077 } 2078 2079 static bool __init acpi_validate_gic_table(struct acpi_subtable_header *header, 2080 struct acpi_probe_entry *ape) 2081 { 2082 struct acpi_madt_generic_distributor *dist; 2083 int count; 2084 2085 dist = (struct acpi_madt_generic_distributor *)header; 2086 if (dist->version != ape->driver_data) 2087 return false; 2088 2089 /* We need to do that exercise anyway, the sooner the better */ 2090 count = gic_acpi_count_gicr_regions(); 2091 if (count <= 0) 2092 return false; 2093 2094 acpi_data.nr_redist_regions = count; 2095 return true; 2096 } 2097 2098 static int __init gic_acpi_parse_virt_madt_gicc(union acpi_subtable_headers *header, 2099 const unsigned long end) 2100 { 2101 struct acpi_madt_generic_interrupt *gicc = 2102 (struct acpi_madt_generic_interrupt *)header; 2103 int maint_irq_mode; 2104 static int first_madt = true; 2105 2106 /* Skip unusable CPUs */ 2107 if (!(gicc->flags & ACPI_MADT_ENABLED)) 2108 return 0; 2109 2110 maint_irq_mode = (gicc->flags & ACPI_MADT_VGIC_IRQ_MODE) ? 2111 ACPI_EDGE_SENSITIVE : ACPI_LEVEL_SENSITIVE; 2112 2113 if (first_madt) { 2114 first_madt = false; 2115 2116 acpi_data.maint_irq = gicc->vgic_interrupt; 2117 acpi_data.maint_irq_mode = maint_irq_mode; 2118 acpi_data.vcpu_base = gicc->gicv_base_address; 2119 2120 return 0; 2121 } 2122 2123 /* 2124 * The maintenance interrupt and GICV should be the same for every CPU 2125 */ 2126 if ((acpi_data.maint_irq != gicc->vgic_interrupt) || 2127 (acpi_data.maint_irq_mode != maint_irq_mode) || 2128 (acpi_data.vcpu_base != gicc->gicv_base_address)) 2129 return -EINVAL; 2130 2131 return 0; 2132 } 2133 2134 static bool __init gic_acpi_collect_virt_info(void) 2135 { 2136 int count; 2137 2138 count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT, 2139 gic_acpi_parse_virt_madt_gicc, 0); 2140 2141 return (count > 0); 2142 } 2143 2144 #define ACPI_GICV3_DIST_MEM_SIZE (SZ_64K) 2145 #define ACPI_GICV2_VCTRL_MEM_SIZE (SZ_4K) 2146 #define ACPI_GICV2_VCPU_MEM_SIZE (SZ_8K) 2147 2148 static void __init gic_acpi_setup_kvm_info(void) 2149 { 2150 int irq; 2151 2152 if (!gic_acpi_collect_virt_info()) { 2153 pr_warn("Unable to get hardware information used for virtualization\n"); 2154 return; 2155 } 2156 2157 gic_v3_kvm_info.type = GIC_V3; 2158 2159 irq = acpi_register_gsi(NULL, acpi_data.maint_irq, 2160 acpi_data.maint_irq_mode, 2161 ACPI_ACTIVE_HIGH); 2162 if (irq <= 0) 2163 return; 2164 2165 gic_v3_kvm_info.maint_irq = irq; 2166 2167 if (acpi_data.vcpu_base) { 2168 struct resource *vcpu = &gic_v3_kvm_info.vcpu; 2169 2170 vcpu->flags = IORESOURCE_MEM; 2171 vcpu->start = acpi_data.vcpu_base; 2172 vcpu->end = vcpu->start + ACPI_GICV2_VCPU_MEM_SIZE - 1; 2173 } 2174 2175 gic_v3_kvm_info.has_v4 = gic_data.rdists.has_vlpis; 2176 gic_v3_kvm_info.has_v4_1 = gic_data.rdists.has_rvpeid; 2177 gic_set_kvm_info(&gic_v3_kvm_info); 2178 } 2179 2180 static int __init 2181 gic_acpi_init(union acpi_subtable_headers *header, const unsigned long end) 2182 { 2183 struct acpi_madt_generic_distributor *dist; 2184 struct fwnode_handle *domain_handle; 2185 size_t size; 2186 int i, err; 2187 2188 /* Get distributor base address */ 2189 dist = (struct acpi_madt_generic_distributor *)header; 2190 acpi_data.dist_base = ioremap(dist->base_address, 2191 ACPI_GICV3_DIST_MEM_SIZE); 2192 if (!acpi_data.dist_base) { 2193 pr_err("Unable to map GICD registers\n"); 2194 return -ENOMEM; 2195 } 2196 2197 err = gic_validate_dist_version(acpi_data.dist_base); 2198 if (err) { 2199 pr_err("No distributor detected at @%p, giving up\n", 2200 acpi_data.dist_base); 2201 goto out_dist_unmap; 2202 } 2203 2204 size = sizeof(*acpi_data.redist_regs) * acpi_data.nr_redist_regions; 2205 acpi_data.redist_regs = kzalloc(size, GFP_KERNEL); 2206 if (!acpi_data.redist_regs) { 2207 err = -ENOMEM; 2208 goto out_dist_unmap; 2209 } 2210 2211 err = gic_acpi_collect_gicr_base(); 2212 if (err) 2213 goto out_redist_unmap; 2214 2215 domain_handle = irq_domain_alloc_fwnode(&dist->base_address); 2216 if (!domain_handle) { 2217 err = -ENOMEM; 2218 goto out_redist_unmap; 2219 } 2220 2221 err = gic_init_bases(acpi_data.dist_base, acpi_data.redist_regs, 2222 acpi_data.nr_redist_regions, 0, domain_handle); 2223 if (err) 2224 goto out_fwhandle_free; 2225 2226 acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, domain_handle); 2227 2228 if (static_branch_likely(&supports_deactivate_key)) 2229 gic_acpi_setup_kvm_info(); 2230 2231 return 0; 2232 2233 out_fwhandle_free: 2234 irq_domain_free_fwnode(domain_handle); 2235 out_redist_unmap: 2236 for (i = 0; i < acpi_data.nr_redist_regions; i++) 2237 if (acpi_data.redist_regs[i].redist_base) 2238 iounmap(acpi_data.redist_regs[i].redist_base); 2239 kfree(acpi_data.redist_regs); 2240 out_dist_unmap: 2241 iounmap(acpi_data.dist_base); 2242 return err; 2243 } 2244 IRQCHIP_ACPI_DECLARE(gic_v3, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 2245 acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V3, 2246 gic_acpi_init); 2247 IRQCHIP_ACPI_DECLARE(gic_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 2248 acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V4, 2249 gic_acpi_init); 2250 IRQCHIP_ACPI_DECLARE(gic_v3_or_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 2251 acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_NONE, 2252 gic_acpi_init); 2253 #endif 2254