1021f6537SMarc Zyngier /* 2021f6537SMarc Zyngier * Copyright (C) 2013, 2014 ARM Limited, All Rights Reserved. 3021f6537SMarc Zyngier * Author: Marc Zyngier <marc.zyngier@arm.com> 4021f6537SMarc Zyngier * 5021f6537SMarc Zyngier * This program is free software; you can redistribute it and/or modify 6021f6537SMarc Zyngier * it under the terms of the GNU General Public License version 2 as 7021f6537SMarc Zyngier * published by the Free Software Foundation. 8021f6537SMarc Zyngier * 9021f6537SMarc Zyngier * This program is distributed in the hope that it will be useful, 10021f6537SMarc Zyngier * but WITHOUT ANY WARRANTY; without even the implied warranty of 11021f6537SMarc Zyngier * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12021f6537SMarc Zyngier * GNU General Public License for more details. 13021f6537SMarc Zyngier * 14021f6537SMarc Zyngier * You should have received a copy of the GNU General Public License 15021f6537SMarc Zyngier * along with this program. If not, see <http://www.gnu.org/licenses/>. 16021f6537SMarc Zyngier */ 17021f6537SMarc Zyngier 18021f6537SMarc Zyngier #include <linux/cpu.h> 193708d52fSSudeep Holla #include <linux/cpu_pm.h> 20021f6537SMarc Zyngier #include <linux/delay.h> 21021f6537SMarc Zyngier #include <linux/interrupt.h> 22021f6537SMarc Zyngier #include <linux/of.h> 23021f6537SMarc Zyngier #include <linux/of_address.h> 24021f6537SMarc Zyngier #include <linux/of_irq.h> 25021f6537SMarc Zyngier #include <linux/percpu.h> 26021f6537SMarc Zyngier #include <linux/slab.h> 27021f6537SMarc Zyngier 2841a83e06SJoel Porquet #include <linux/irqchip.h> 29021f6537SMarc Zyngier #include <linux/irqchip/arm-gic-v3.h> 30021f6537SMarc Zyngier 31021f6537SMarc Zyngier #include <asm/cputype.h> 32021f6537SMarc Zyngier #include <asm/exception.h> 33021f6537SMarc Zyngier #include <asm/smp_plat.h> 340b6a3da9SMarc Zyngier #include <asm/virt.h> 35021f6537SMarc Zyngier 36021f6537SMarc Zyngier #include "irq-gic-common.h" 37021f6537SMarc Zyngier 38f5c1434cSMarc Zyngier struct redist_region { 39f5c1434cSMarc Zyngier void __iomem *redist_base; 40f5c1434cSMarc Zyngier phys_addr_t phys_base; 41f5c1434cSMarc Zyngier }; 42f5c1434cSMarc Zyngier 43021f6537SMarc Zyngier struct gic_chip_data { 44021f6537SMarc Zyngier void __iomem *dist_base; 45f5c1434cSMarc Zyngier struct redist_region *redist_regions; 46f5c1434cSMarc Zyngier struct rdists rdists; 47021f6537SMarc Zyngier struct irq_domain *domain; 48021f6537SMarc Zyngier u64 redist_stride; 49f5c1434cSMarc Zyngier u32 nr_redist_regions; 50021f6537SMarc Zyngier unsigned int irq_nr; 51021f6537SMarc Zyngier }; 52021f6537SMarc Zyngier 53021f6537SMarc Zyngier static struct gic_chip_data gic_data __read_mostly; 540b6a3da9SMarc Zyngier static struct static_key supports_deactivate = STATIC_KEY_INIT_TRUE; 55021f6537SMarc Zyngier 56f5c1434cSMarc Zyngier #define gic_data_rdist() (this_cpu_ptr(gic_data.rdists.rdist)) 57f5c1434cSMarc Zyngier #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base) 58021f6537SMarc Zyngier #define gic_data_rdist_sgi_base() (gic_data_rdist_rd_base() + SZ_64K) 59021f6537SMarc Zyngier 60021f6537SMarc Zyngier /* Our default, arbitrary priority value. Linux only uses one anyway. */ 61021f6537SMarc Zyngier #define DEFAULT_PMR_VALUE 0xf0 62021f6537SMarc Zyngier 63021f6537SMarc Zyngier static inline unsigned int gic_irq(struct irq_data *d) 64021f6537SMarc Zyngier { 65021f6537SMarc Zyngier return d->hwirq; 66021f6537SMarc Zyngier } 67021f6537SMarc Zyngier 68021f6537SMarc Zyngier static inline int gic_irq_in_rdist(struct irq_data *d) 69021f6537SMarc Zyngier { 70021f6537SMarc Zyngier return gic_irq(d) < 32; 71021f6537SMarc Zyngier } 72021f6537SMarc Zyngier 73021f6537SMarc Zyngier static inline void __iomem *gic_dist_base(struct irq_data *d) 74021f6537SMarc Zyngier { 75021f6537SMarc Zyngier if (gic_irq_in_rdist(d)) /* SGI+PPI -> SGI_base for this CPU */ 76021f6537SMarc Zyngier return gic_data_rdist_sgi_base(); 77021f6537SMarc Zyngier 78021f6537SMarc Zyngier if (d->hwirq <= 1023) /* SPI -> dist_base */ 79021f6537SMarc Zyngier return gic_data.dist_base; 80021f6537SMarc Zyngier 81021f6537SMarc Zyngier return NULL; 82021f6537SMarc Zyngier } 83021f6537SMarc Zyngier 84021f6537SMarc Zyngier static void gic_do_wait_for_rwp(void __iomem *base) 85021f6537SMarc Zyngier { 86021f6537SMarc Zyngier u32 count = 1000000; /* 1s! */ 87021f6537SMarc Zyngier 88021f6537SMarc Zyngier while (readl_relaxed(base + GICD_CTLR) & GICD_CTLR_RWP) { 89021f6537SMarc Zyngier count--; 90021f6537SMarc Zyngier if (!count) { 91021f6537SMarc Zyngier pr_err_ratelimited("RWP timeout, gone fishing\n"); 92021f6537SMarc Zyngier return; 93021f6537SMarc Zyngier } 94021f6537SMarc Zyngier cpu_relax(); 95021f6537SMarc Zyngier udelay(1); 96021f6537SMarc Zyngier }; 97021f6537SMarc Zyngier } 98021f6537SMarc Zyngier 99021f6537SMarc Zyngier /* Wait for completion of a distributor change */ 100021f6537SMarc Zyngier static void gic_dist_wait_for_rwp(void) 101021f6537SMarc Zyngier { 102021f6537SMarc Zyngier gic_do_wait_for_rwp(gic_data.dist_base); 103021f6537SMarc Zyngier } 104021f6537SMarc Zyngier 105021f6537SMarc Zyngier /* Wait for completion of a redistributor change */ 106021f6537SMarc Zyngier static void gic_redist_wait_for_rwp(void) 107021f6537SMarc Zyngier { 108021f6537SMarc Zyngier gic_do_wait_for_rwp(gic_data_rdist_rd_base()); 109021f6537SMarc Zyngier } 110021f6537SMarc Zyngier 1117936e914SJean-Philippe Brucker #ifdef CONFIG_ARM64 1128ac2a170SRobert Richter static DEFINE_STATIC_KEY_FALSE(is_cavium_thunderx); 1136d4e11c5SRobert Richter 1146d4e11c5SRobert Richter static u64 __maybe_unused gic_read_iar(void) 1156d4e11c5SRobert Richter { 1168ac2a170SRobert Richter if (static_branch_unlikely(&is_cavium_thunderx)) 1176d4e11c5SRobert Richter return gic_read_iar_cavium_thunderx(); 1186d4e11c5SRobert Richter else 1196d4e11c5SRobert Richter return gic_read_iar_common(); 1206d4e11c5SRobert Richter } 1217936e914SJean-Philippe Brucker #endif 122021f6537SMarc Zyngier 123a2c22510SSudeep Holla static void gic_enable_redist(bool enable) 124021f6537SMarc Zyngier { 125021f6537SMarc Zyngier void __iomem *rbase; 126021f6537SMarc Zyngier u32 count = 1000000; /* 1s! */ 127021f6537SMarc Zyngier u32 val; 128021f6537SMarc Zyngier 129021f6537SMarc Zyngier rbase = gic_data_rdist_rd_base(); 130021f6537SMarc Zyngier 131021f6537SMarc Zyngier val = readl_relaxed(rbase + GICR_WAKER); 132a2c22510SSudeep Holla if (enable) 133a2c22510SSudeep Holla /* Wake up this CPU redistributor */ 134021f6537SMarc Zyngier val &= ~GICR_WAKER_ProcessorSleep; 135a2c22510SSudeep Holla else 136a2c22510SSudeep Holla val |= GICR_WAKER_ProcessorSleep; 137021f6537SMarc Zyngier writel_relaxed(val, rbase + GICR_WAKER); 138021f6537SMarc Zyngier 139a2c22510SSudeep Holla if (!enable) { /* Check that GICR_WAKER is writeable */ 140a2c22510SSudeep Holla val = readl_relaxed(rbase + GICR_WAKER); 141a2c22510SSudeep Holla if (!(val & GICR_WAKER_ProcessorSleep)) 142a2c22510SSudeep Holla return; /* No PM support in this redistributor */ 143021f6537SMarc Zyngier } 144a2c22510SSudeep Holla 145a2c22510SSudeep Holla while (count--) { 146a2c22510SSudeep Holla val = readl_relaxed(rbase + GICR_WAKER); 147a2c22510SSudeep Holla if (enable ^ (val & GICR_WAKER_ChildrenAsleep)) 148a2c22510SSudeep Holla break; 149021f6537SMarc Zyngier cpu_relax(); 150021f6537SMarc Zyngier udelay(1); 151021f6537SMarc Zyngier }; 152a2c22510SSudeep Holla if (!count) 153a2c22510SSudeep Holla pr_err_ratelimited("redistributor failed to %s...\n", 154a2c22510SSudeep Holla enable ? "wakeup" : "sleep"); 155021f6537SMarc Zyngier } 156021f6537SMarc Zyngier 157021f6537SMarc Zyngier /* 158021f6537SMarc Zyngier * Routines to disable, enable, EOI and route interrupts 159021f6537SMarc Zyngier */ 160b594c6e2SMarc Zyngier static int gic_peek_irq(struct irq_data *d, u32 offset) 161b594c6e2SMarc Zyngier { 162b594c6e2SMarc Zyngier u32 mask = 1 << (gic_irq(d) % 32); 163b594c6e2SMarc Zyngier void __iomem *base; 164b594c6e2SMarc Zyngier 165b594c6e2SMarc Zyngier if (gic_irq_in_rdist(d)) 166b594c6e2SMarc Zyngier base = gic_data_rdist_sgi_base(); 167b594c6e2SMarc Zyngier else 168b594c6e2SMarc Zyngier base = gic_data.dist_base; 169b594c6e2SMarc Zyngier 170b594c6e2SMarc Zyngier return !!(readl_relaxed(base + offset + (gic_irq(d) / 32) * 4) & mask); 171b594c6e2SMarc Zyngier } 172b594c6e2SMarc Zyngier 173021f6537SMarc Zyngier static void gic_poke_irq(struct irq_data *d, u32 offset) 174021f6537SMarc Zyngier { 175021f6537SMarc Zyngier u32 mask = 1 << (gic_irq(d) % 32); 176021f6537SMarc Zyngier void (*rwp_wait)(void); 177021f6537SMarc Zyngier void __iomem *base; 178021f6537SMarc Zyngier 179021f6537SMarc Zyngier if (gic_irq_in_rdist(d)) { 180021f6537SMarc Zyngier base = gic_data_rdist_sgi_base(); 181021f6537SMarc Zyngier rwp_wait = gic_redist_wait_for_rwp; 182021f6537SMarc Zyngier } else { 183021f6537SMarc Zyngier base = gic_data.dist_base; 184021f6537SMarc Zyngier rwp_wait = gic_dist_wait_for_rwp; 185021f6537SMarc Zyngier } 186021f6537SMarc Zyngier 187021f6537SMarc Zyngier writel_relaxed(mask, base + offset + (gic_irq(d) / 32) * 4); 188021f6537SMarc Zyngier rwp_wait(); 189021f6537SMarc Zyngier } 190021f6537SMarc Zyngier 191021f6537SMarc Zyngier static void gic_mask_irq(struct irq_data *d) 192021f6537SMarc Zyngier { 193021f6537SMarc Zyngier gic_poke_irq(d, GICD_ICENABLER); 194021f6537SMarc Zyngier } 195021f6537SMarc Zyngier 1960b6a3da9SMarc Zyngier static void gic_eoimode1_mask_irq(struct irq_data *d) 1970b6a3da9SMarc Zyngier { 1980b6a3da9SMarc Zyngier gic_mask_irq(d); 199530bf353SMarc Zyngier /* 200530bf353SMarc Zyngier * When masking a forwarded interrupt, make sure it is 201530bf353SMarc Zyngier * deactivated as well. 202530bf353SMarc Zyngier * 203530bf353SMarc Zyngier * This ensures that an interrupt that is getting 204530bf353SMarc Zyngier * disabled/masked will not get "stuck", because there is 205530bf353SMarc Zyngier * noone to deactivate it (guest is being terminated). 206530bf353SMarc Zyngier */ 2074df7f54dSThomas Gleixner if (irqd_is_forwarded_to_vcpu(d)) 208530bf353SMarc Zyngier gic_poke_irq(d, GICD_ICACTIVER); 2090b6a3da9SMarc Zyngier } 2100b6a3da9SMarc Zyngier 211021f6537SMarc Zyngier static void gic_unmask_irq(struct irq_data *d) 212021f6537SMarc Zyngier { 213021f6537SMarc Zyngier gic_poke_irq(d, GICD_ISENABLER); 214021f6537SMarc Zyngier } 215021f6537SMarc Zyngier 216b594c6e2SMarc Zyngier static int gic_irq_set_irqchip_state(struct irq_data *d, 217b594c6e2SMarc Zyngier enum irqchip_irq_state which, bool val) 218b594c6e2SMarc Zyngier { 219b594c6e2SMarc Zyngier u32 reg; 220b594c6e2SMarc Zyngier 221b594c6e2SMarc Zyngier if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */ 222b594c6e2SMarc Zyngier return -EINVAL; 223b594c6e2SMarc Zyngier 224b594c6e2SMarc Zyngier switch (which) { 225b594c6e2SMarc Zyngier case IRQCHIP_STATE_PENDING: 226b594c6e2SMarc Zyngier reg = val ? GICD_ISPENDR : GICD_ICPENDR; 227b594c6e2SMarc Zyngier break; 228b594c6e2SMarc Zyngier 229b594c6e2SMarc Zyngier case IRQCHIP_STATE_ACTIVE: 230b594c6e2SMarc Zyngier reg = val ? GICD_ISACTIVER : GICD_ICACTIVER; 231b594c6e2SMarc Zyngier break; 232b594c6e2SMarc Zyngier 233b594c6e2SMarc Zyngier case IRQCHIP_STATE_MASKED: 234b594c6e2SMarc Zyngier reg = val ? GICD_ICENABLER : GICD_ISENABLER; 235b594c6e2SMarc Zyngier break; 236b594c6e2SMarc Zyngier 237b594c6e2SMarc Zyngier default: 238b594c6e2SMarc Zyngier return -EINVAL; 239b594c6e2SMarc Zyngier } 240b594c6e2SMarc Zyngier 241b594c6e2SMarc Zyngier gic_poke_irq(d, reg); 242b594c6e2SMarc Zyngier return 0; 243b594c6e2SMarc Zyngier } 244b594c6e2SMarc Zyngier 245b594c6e2SMarc Zyngier static int gic_irq_get_irqchip_state(struct irq_data *d, 246b594c6e2SMarc Zyngier enum irqchip_irq_state which, bool *val) 247b594c6e2SMarc Zyngier { 248b594c6e2SMarc Zyngier if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */ 249b594c6e2SMarc Zyngier return -EINVAL; 250b594c6e2SMarc Zyngier 251b594c6e2SMarc Zyngier switch (which) { 252b594c6e2SMarc Zyngier case IRQCHIP_STATE_PENDING: 253b594c6e2SMarc Zyngier *val = gic_peek_irq(d, GICD_ISPENDR); 254b594c6e2SMarc Zyngier break; 255b594c6e2SMarc Zyngier 256b594c6e2SMarc Zyngier case IRQCHIP_STATE_ACTIVE: 257b594c6e2SMarc Zyngier *val = gic_peek_irq(d, GICD_ISACTIVER); 258b594c6e2SMarc Zyngier break; 259b594c6e2SMarc Zyngier 260b594c6e2SMarc Zyngier case IRQCHIP_STATE_MASKED: 261b594c6e2SMarc Zyngier *val = !gic_peek_irq(d, GICD_ISENABLER); 262b594c6e2SMarc Zyngier break; 263b594c6e2SMarc Zyngier 264b594c6e2SMarc Zyngier default: 265b594c6e2SMarc Zyngier return -EINVAL; 266b594c6e2SMarc Zyngier } 267b594c6e2SMarc Zyngier 268b594c6e2SMarc Zyngier return 0; 269b594c6e2SMarc Zyngier } 270b594c6e2SMarc Zyngier 271021f6537SMarc Zyngier static void gic_eoi_irq(struct irq_data *d) 272021f6537SMarc Zyngier { 273021f6537SMarc Zyngier gic_write_eoir(gic_irq(d)); 274021f6537SMarc Zyngier } 275021f6537SMarc Zyngier 2760b6a3da9SMarc Zyngier static void gic_eoimode1_eoi_irq(struct irq_data *d) 2770b6a3da9SMarc Zyngier { 2780b6a3da9SMarc Zyngier /* 279530bf353SMarc Zyngier * No need to deactivate an LPI, or an interrupt that 280530bf353SMarc Zyngier * is is getting forwarded to a vcpu. 2810b6a3da9SMarc Zyngier */ 2824df7f54dSThomas Gleixner if (gic_irq(d) >= 8192 || irqd_is_forwarded_to_vcpu(d)) 2830b6a3da9SMarc Zyngier return; 2840b6a3da9SMarc Zyngier gic_write_dir(gic_irq(d)); 2850b6a3da9SMarc Zyngier } 2860b6a3da9SMarc Zyngier 287021f6537SMarc Zyngier static int gic_set_type(struct irq_data *d, unsigned int type) 288021f6537SMarc Zyngier { 289021f6537SMarc Zyngier unsigned int irq = gic_irq(d); 290021f6537SMarc Zyngier void (*rwp_wait)(void); 291021f6537SMarc Zyngier void __iomem *base; 292021f6537SMarc Zyngier 293021f6537SMarc Zyngier /* Interrupt configuration for SGIs can't be changed */ 294021f6537SMarc Zyngier if (irq < 16) 295021f6537SMarc Zyngier return -EINVAL; 296021f6537SMarc Zyngier 297fb7e7debSLiviu Dudau /* SPIs have restrictions on the supported types */ 298fb7e7debSLiviu Dudau if (irq >= 32 && type != IRQ_TYPE_LEVEL_HIGH && 299fb7e7debSLiviu Dudau type != IRQ_TYPE_EDGE_RISING) 300021f6537SMarc Zyngier return -EINVAL; 301021f6537SMarc Zyngier 302021f6537SMarc Zyngier if (gic_irq_in_rdist(d)) { 303021f6537SMarc Zyngier base = gic_data_rdist_sgi_base(); 304021f6537SMarc Zyngier rwp_wait = gic_redist_wait_for_rwp; 305021f6537SMarc Zyngier } else { 306021f6537SMarc Zyngier base = gic_data.dist_base; 307021f6537SMarc Zyngier rwp_wait = gic_dist_wait_for_rwp; 308021f6537SMarc Zyngier } 309021f6537SMarc Zyngier 310fb7e7debSLiviu Dudau return gic_configure_irq(irq, type, base, rwp_wait); 311021f6537SMarc Zyngier } 312021f6537SMarc Zyngier 313530bf353SMarc Zyngier static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu) 314530bf353SMarc Zyngier { 3154df7f54dSThomas Gleixner if (vcpu) 3164df7f54dSThomas Gleixner irqd_set_forwarded_to_vcpu(d); 3174df7f54dSThomas Gleixner else 3184df7f54dSThomas Gleixner irqd_clr_forwarded_to_vcpu(d); 319530bf353SMarc Zyngier return 0; 320530bf353SMarc Zyngier } 321530bf353SMarc Zyngier 322f6c86a41SJean-Philippe Brucker static u64 gic_mpidr_to_affinity(unsigned long mpidr) 323021f6537SMarc Zyngier { 324021f6537SMarc Zyngier u64 aff; 325021f6537SMarc Zyngier 326f6c86a41SJean-Philippe Brucker aff = ((u64)MPIDR_AFFINITY_LEVEL(mpidr, 3) << 32 | 327021f6537SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 | 328021f6537SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | 329021f6537SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 0)); 330021f6537SMarc Zyngier 331021f6537SMarc Zyngier return aff; 332021f6537SMarc Zyngier } 333021f6537SMarc Zyngier 334021f6537SMarc Zyngier static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) 335021f6537SMarc Zyngier { 336f6c86a41SJean-Philippe Brucker u32 irqnr; 337021f6537SMarc Zyngier 338021f6537SMarc Zyngier do { 339021f6537SMarc Zyngier irqnr = gic_read_iar(); 340021f6537SMarc Zyngier 341da33f31dSMarc Zyngier if (likely(irqnr > 15 && irqnr < 1020) || irqnr >= 8192) { 342ebc6de00SMarc Zyngier int err; 3430b6a3da9SMarc Zyngier 3440b6a3da9SMarc Zyngier if (static_key_true(&supports_deactivate)) 3450b6a3da9SMarc Zyngier gic_write_eoir(irqnr); 3460b6a3da9SMarc Zyngier 347ebc6de00SMarc Zyngier err = handle_domain_irq(gic_data.domain, irqnr, regs); 348ebc6de00SMarc Zyngier if (err) { 349da33f31dSMarc Zyngier WARN_ONCE(true, "Unexpected interrupt received!\n"); 3500b6a3da9SMarc Zyngier if (static_key_true(&supports_deactivate)) { 3510b6a3da9SMarc Zyngier if (irqnr < 8192) 3520b6a3da9SMarc Zyngier gic_write_dir(irqnr); 3530b6a3da9SMarc Zyngier } else { 354021f6537SMarc Zyngier gic_write_eoir(irqnr); 355021f6537SMarc Zyngier } 3560b6a3da9SMarc Zyngier } 357ebc6de00SMarc Zyngier continue; 358ebc6de00SMarc Zyngier } 359021f6537SMarc Zyngier if (irqnr < 16) { 360021f6537SMarc Zyngier gic_write_eoir(irqnr); 3610b6a3da9SMarc Zyngier if (static_key_true(&supports_deactivate)) 3620b6a3da9SMarc Zyngier gic_write_dir(irqnr); 363021f6537SMarc Zyngier #ifdef CONFIG_SMP 364021f6537SMarc Zyngier handle_IPI(irqnr, regs); 365021f6537SMarc Zyngier #else 366021f6537SMarc Zyngier WARN_ONCE(true, "Unexpected SGI received!\n"); 367021f6537SMarc Zyngier #endif 368021f6537SMarc Zyngier continue; 369021f6537SMarc Zyngier } 370021f6537SMarc Zyngier } while (irqnr != ICC_IAR1_EL1_SPURIOUS); 371021f6537SMarc Zyngier } 372021f6537SMarc Zyngier 373021f6537SMarc Zyngier static void __init gic_dist_init(void) 374021f6537SMarc Zyngier { 375021f6537SMarc Zyngier unsigned int i; 376021f6537SMarc Zyngier u64 affinity; 377021f6537SMarc Zyngier void __iomem *base = gic_data.dist_base; 378021f6537SMarc Zyngier 379021f6537SMarc Zyngier /* Disable the distributor */ 380021f6537SMarc Zyngier writel_relaxed(0, base + GICD_CTLR); 381021f6537SMarc Zyngier gic_dist_wait_for_rwp(); 382021f6537SMarc Zyngier 383021f6537SMarc Zyngier gic_dist_config(base, gic_data.irq_nr, gic_dist_wait_for_rwp); 384021f6537SMarc Zyngier 385021f6537SMarc Zyngier /* Enable distributor with ARE, Group1 */ 386021f6537SMarc Zyngier writel_relaxed(GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G1A | GICD_CTLR_ENABLE_G1, 387021f6537SMarc Zyngier base + GICD_CTLR); 388021f6537SMarc Zyngier 389021f6537SMarc Zyngier /* 390021f6537SMarc Zyngier * Set all global interrupts to the boot CPU only. ARE must be 391021f6537SMarc Zyngier * enabled. 392021f6537SMarc Zyngier */ 393021f6537SMarc Zyngier affinity = gic_mpidr_to_affinity(cpu_logical_map(smp_processor_id())); 394021f6537SMarc Zyngier for (i = 32; i < gic_data.irq_nr; i++) 395021f6537SMarc Zyngier writeq_relaxed(affinity, base + GICD_IROUTER + i * 8); 396021f6537SMarc Zyngier } 397021f6537SMarc Zyngier 398021f6537SMarc Zyngier static int gic_populate_rdist(void) 399021f6537SMarc Zyngier { 400f6c86a41SJean-Philippe Brucker unsigned long mpidr = cpu_logical_map(smp_processor_id()); 401021f6537SMarc Zyngier u64 typer; 402021f6537SMarc Zyngier u32 aff; 403021f6537SMarc Zyngier int i; 404021f6537SMarc Zyngier 405021f6537SMarc Zyngier /* 406021f6537SMarc Zyngier * Convert affinity to a 32bit value that can be matched to 407021f6537SMarc Zyngier * GICR_TYPER bits [63:32]. 408021f6537SMarc Zyngier */ 409021f6537SMarc Zyngier aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 24 | 410021f6537SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 | 411021f6537SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | 412021f6537SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 0)); 413021f6537SMarc Zyngier 414f5c1434cSMarc Zyngier for (i = 0; i < gic_data.nr_redist_regions; i++) { 415f5c1434cSMarc Zyngier void __iomem *ptr = gic_data.redist_regions[i].redist_base; 416021f6537SMarc Zyngier u32 reg; 417021f6537SMarc Zyngier 418021f6537SMarc Zyngier reg = readl_relaxed(ptr + GICR_PIDR2) & GIC_PIDR2_ARCH_MASK; 419021f6537SMarc Zyngier if (reg != GIC_PIDR2_ARCH_GICv3 && 420021f6537SMarc Zyngier reg != GIC_PIDR2_ARCH_GICv4) { /* We're in trouble... */ 421021f6537SMarc Zyngier pr_warn("No redistributor present @%p\n", ptr); 422021f6537SMarc Zyngier break; 423021f6537SMarc Zyngier } 424021f6537SMarc Zyngier 425021f6537SMarc Zyngier do { 426021f6537SMarc Zyngier typer = readq_relaxed(ptr + GICR_TYPER); 427021f6537SMarc Zyngier if ((typer >> 32) == aff) { 428f5c1434cSMarc Zyngier u64 offset = ptr - gic_data.redist_regions[i].redist_base; 429021f6537SMarc Zyngier gic_data_rdist_rd_base() = ptr; 430f5c1434cSMarc Zyngier gic_data_rdist()->phys_base = gic_data.redist_regions[i].phys_base + offset; 431f6c86a41SJean-Philippe Brucker pr_info("CPU%d: found redistributor %lx region %d:%pa\n", 432f6c86a41SJean-Philippe Brucker smp_processor_id(), mpidr, i, 433f6c86a41SJean-Philippe Brucker &gic_data_rdist()->phys_base); 434021f6537SMarc Zyngier return 0; 435021f6537SMarc Zyngier } 436021f6537SMarc Zyngier 437021f6537SMarc Zyngier if (gic_data.redist_stride) { 438021f6537SMarc Zyngier ptr += gic_data.redist_stride; 439021f6537SMarc Zyngier } else { 440021f6537SMarc Zyngier ptr += SZ_64K * 2; /* Skip RD_base + SGI_base */ 441021f6537SMarc Zyngier if (typer & GICR_TYPER_VLPIS) 442021f6537SMarc Zyngier ptr += SZ_64K * 2; /* Skip VLPI_base + reserved page */ 443021f6537SMarc Zyngier } 444021f6537SMarc Zyngier } while (!(typer & GICR_TYPER_LAST)); 445021f6537SMarc Zyngier } 446021f6537SMarc Zyngier 447021f6537SMarc Zyngier /* We couldn't even deal with ourselves... */ 448f6c86a41SJean-Philippe Brucker WARN(true, "CPU%d: mpidr %lx has no re-distributor!\n", 449f6c86a41SJean-Philippe Brucker smp_processor_id(), mpidr); 450021f6537SMarc Zyngier return -ENODEV; 451021f6537SMarc Zyngier } 452021f6537SMarc Zyngier 4533708d52fSSudeep Holla static void gic_cpu_sys_reg_init(void) 454021f6537SMarc Zyngier { 4557cabd008SMarc Zyngier /* 4567cabd008SMarc Zyngier * Need to check that the SRE bit has actually been set. If 4577cabd008SMarc Zyngier * not, it means that SRE is disabled at EL2. We're going to 4587cabd008SMarc Zyngier * die painfully, and there is nothing we can do about it. 4597cabd008SMarc Zyngier * 4607cabd008SMarc Zyngier * Kindly inform the luser. 4617cabd008SMarc Zyngier */ 4627cabd008SMarc Zyngier if (!gic_enable_sre()) 4637cabd008SMarc Zyngier pr_err("GIC: unable to set SRE (disabled at EL2), panic ahead\n"); 464021f6537SMarc Zyngier 465021f6537SMarc Zyngier /* Set priority mask register */ 466021f6537SMarc Zyngier gic_write_pmr(DEFAULT_PMR_VALUE); 467021f6537SMarc Zyngier 4680b6a3da9SMarc Zyngier if (static_key_true(&supports_deactivate)) { 4690b6a3da9SMarc Zyngier /* EOI drops priority only (mode 1) */ 4700b6a3da9SMarc Zyngier gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop); 4710b6a3da9SMarc Zyngier } else { 472021f6537SMarc Zyngier /* EOI deactivates interrupt too (mode 0) */ 473021f6537SMarc Zyngier gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop_dir); 4740b6a3da9SMarc Zyngier } 475021f6537SMarc Zyngier 476021f6537SMarc Zyngier /* ... and let's hit the road... */ 477021f6537SMarc Zyngier gic_write_grpen1(1); 478021f6537SMarc Zyngier } 479021f6537SMarc Zyngier 480da33f31dSMarc Zyngier static int gic_dist_supports_lpis(void) 481da33f31dSMarc Zyngier { 482da33f31dSMarc Zyngier return !!(readl_relaxed(gic_data.dist_base + GICD_TYPER) & GICD_TYPER_LPIS); 483da33f31dSMarc Zyngier } 484da33f31dSMarc Zyngier 485021f6537SMarc Zyngier static void gic_cpu_init(void) 486021f6537SMarc Zyngier { 487021f6537SMarc Zyngier void __iomem *rbase; 488021f6537SMarc Zyngier 489021f6537SMarc Zyngier /* Register ourselves with the rest of the world */ 490021f6537SMarc Zyngier if (gic_populate_rdist()) 491021f6537SMarc Zyngier return; 492021f6537SMarc Zyngier 493a2c22510SSudeep Holla gic_enable_redist(true); 494021f6537SMarc Zyngier 495021f6537SMarc Zyngier rbase = gic_data_rdist_sgi_base(); 496021f6537SMarc Zyngier 497021f6537SMarc Zyngier gic_cpu_config(rbase, gic_redist_wait_for_rwp); 498021f6537SMarc Zyngier 499da33f31dSMarc Zyngier /* Give LPIs a spin */ 500da33f31dSMarc Zyngier if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis()) 501da33f31dSMarc Zyngier its_cpu_init(); 502da33f31dSMarc Zyngier 5033708d52fSSudeep Holla /* initialise system registers */ 5043708d52fSSudeep Holla gic_cpu_sys_reg_init(); 505021f6537SMarc Zyngier } 506021f6537SMarc Zyngier 507021f6537SMarc Zyngier #ifdef CONFIG_SMP 508021f6537SMarc Zyngier static int gic_secondary_init(struct notifier_block *nfb, 509021f6537SMarc Zyngier unsigned long action, void *hcpu) 510021f6537SMarc Zyngier { 511021f6537SMarc Zyngier if (action == CPU_STARTING || action == CPU_STARTING_FROZEN) 512021f6537SMarc Zyngier gic_cpu_init(); 513021f6537SMarc Zyngier return NOTIFY_OK; 514021f6537SMarc Zyngier } 515021f6537SMarc Zyngier 516021f6537SMarc Zyngier /* 517021f6537SMarc Zyngier * Notifier for enabling the GIC CPU interface. Set an arbitrarily high 518021f6537SMarc Zyngier * priority because the GIC needs to be up before the ARM generic timers. 519021f6537SMarc Zyngier */ 520021f6537SMarc Zyngier static struct notifier_block gic_cpu_notifier = { 521021f6537SMarc Zyngier .notifier_call = gic_secondary_init, 522021f6537SMarc Zyngier .priority = 100, 523021f6537SMarc Zyngier }; 524021f6537SMarc Zyngier 525021f6537SMarc Zyngier static u16 gic_compute_target_list(int *base_cpu, const struct cpumask *mask, 526f6c86a41SJean-Philippe Brucker unsigned long cluster_id) 527021f6537SMarc Zyngier { 528021f6537SMarc Zyngier int cpu = *base_cpu; 529f6c86a41SJean-Philippe Brucker unsigned long mpidr = cpu_logical_map(cpu); 530021f6537SMarc Zyngier u16 tlist = 0; 531021f6537SMarc Zyngier 532021f6537SMarc Zyngier while (cpu < nr_cpu_ids) { 533021f6537SMarc Zyngier /* 534021f6537SMarc Zyngier * If we ever get a cluster of more than 16 CPUs, just 535021f6537SMarc Zyngier * scream and skip that CPU. 536021f6537SMarc Zyngier */ 537021f6537SMarc Zyngier if (WARN_ON((mpidr & 0xff) >= 16)) 538021f6537SMarc Zyngier goto out; 539021f6537SMarc Zyngier 540021f6537SMarc Zyngier tlist |= 1 << (mpidr & 0xf); 541021f6537SMarc Zyngier 542021f6537SMarc Zyngier cpu = cpumask_next(cpu, mask); 543614be385SVladimir Murzin if (cpu >= nr_cpu_ids) 544021f6537SMarc Zyngier goto out; 545021f6537SMarc Zyngier 546021f6537SMarc Zyngier mpidr = cpu_logical_map(cpu); 547021f6537SMarc Zyngier 548021f6537SMarc Zyngier if (cluster_id != (mpidr & ~0xffUL)) { 549021f6537SMarc Zyngier cpu--; 550021f6537SMarc Zyngier goto out; 551021f6537SMarc Zyngier } 552021f6537SMarc Zyngier } 553021f6537SMarc Zyngier out: 554021f6537SMarc Zyngier *base_cpu = cpu; 555021f6537SMarc Zyngier return tlist; 556021f6537SMarc Zyngier } 557021f6537SMarc Zyngier 5587e580278SAndre Przywara #define MPIDR_TO_SGI_AFFINITY(cluster_id, level) \ 5597e580278SAndre Przywara (MPIDR_AFFINITY_LEVEL(cluster_id, level) \ 5607e580278SAndre Przywara << ICC_SGI1R_AFFINITY_## level ##_SHIFT) 5617e580278SAndre Przywara 562021f6537SMarc Zyngier static void gic_send_sgi(u64 cluster_id, u16 tlist, unsigned int irq) 563021f6537SMarc Zyngier { 564021f6537SMarc Zyngier u64 val; 565021f6537SMarc Zyngier 5667e580278SAndre Przywara val = (MPIDR_TO_SGI_AFFINITY(cluster_id, 3) | 5677e580278SAndre Przywara MPIDR_TO_SGI_AFFINITY(cluster_id, 2) | 5687e580278SAndre Przywara irq << ICC_SGI1R_SGI_ID_SHIFT | 5697e580278SAndre Przywara MPIDR_TO_SGI_AFFINITY(cluster_id, 1) | 5707e580278SAndre Przywara tlist << ICC_SGI1R_TARGET_LIST_SHIFT); 571021f6537SMarc Zyngier 572021f6537SMarc Zyngier pr_debug("CPU%d: ICC_SGI1R_EL1 %llx\n", smp_processor_id(), val); 573021f6537SMarc Zyngier gic_write_sgi1r(val); 574021f6537SMarc Zyngier } 575021f6537SMarc Zyngier 576021f6537SMarc Zyngier static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) 577021f6537SMarc Zyngier { 578021f6537SMarc Zyngier int cpu; 579021f6537SMarc Zyngier 580021f6537SMarc Zyngier if (WARN_ON(irq >= 16)) 581021f6537SMarc Zyngier return; 582021f6537SMarc Zyngier 583021f6537SMarc Zyngier /* 584021f6537SMarc Zyngier * Ensure that stores to Normal memory are visible to the 585021f6537SMarc Zyngier * other CPUs before issuing the IPI. 586021f6537SMarc Zyngier */ 587021f6537SMarc Zyngier smp_wmb(); 588021f6537SMarc Zyngier 589f9b531feSRusty Russell for_each_cpu(cpu, mask) { 590f6c86a41SJean-Philippe Brucker unsigned long cluster_id = cpu_logical_map(cpu) & ~0xffUL; 591021f6537SMarc Zyngier u16 tlist; 592021f6537SMarc Zyngier 593021f6537SMarc Zyngier tlist = gic_compute_target_list(&cpu, mask, cluster_id); 594021f6537SMarc Zyngier gic_send_sgi(cluster_id, tlist, irq); 595021f6537SMarc Zyngier } 596021f6537SMarc Zyngier 597021f6537SMarc Zyngier /* Force the above writes to ICC_SGI1R_EL1 to be executed */ 598021f6537SMarc Zyngier isb(); 599021f6537SMarc Zyngier } 600021f6537SMarc Zyngier 601021f6537SMarc Zyngier static void gic_smp_init(void) 602021f6537SMarc Zyngier { 603021f6537SMarc Zyngier set_smp_cross_call(gic_raise_softirq); 604021f6537SMarc Zyngier register_cpu_notifier(&gic_cpu_notifier); 605021f6537SMarc Zyngier } 606021f6537SMarc Zyngier 607021f6537SMarc Zyngier static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, 608021f6537SMarc Zyngier bool force) 609021f6537SMarc Zyngier { 610021f6537SMarc Zyngier unsigned int cpu = cpumask_any_and(mask_val, cpu_online_mask); 611021f6537SMarc Zyngier void __iomem *reg; 612021f6537SMarc Zyngier int enabled; 613021f6537SMarc Zyngier u64 val; 614021f6537SMarc Zyngier 615021f6537SMarc Zyngier if (gic_irq_in_rdist(d)) 616021f6537SMarc Zyngier return -EINVAL; 617021f6537SMarc Zyngier 618021f6537SMarc Zyngier /* If interrupt was enabled, disable it first */ 619021f6537SMarc Zyngier enabled = gic_peek_irq(d, GICD_ISENABLER); 620021f6537SMarc Zyngier if (enabled) 621021f6537SMarc Zyngier gic_mask_irq(d); 622021f6537SMarc Zyngier 623021f6537SMarc Zyngier reg = gic_dist_base(d) + GICD_IROUTER + (gic_irq(d) * 8); 624021f6537SMarc Zyngier val = gic_mpidr_to_affinity(cpu_logical_map(cpu)); 625021f6537SMarc Zyngier 626021f6537SMarc Zyngier writeq_relaxed(val, reg); 627021f6537SMarc Zyngier 628021f6537SMarc Zyngier /* 629021f6537SMarc Zyngier * If the interrupt was enabled, enabled it again. Otherwise, 630021f6537SMarc Zyngier * just wait for the distributor to have digested our changes. 631021f6537SMarc Zyngier */ 632021f6537SMarc Zyngier if (enabled) 633021f6537SMarc Zyngier gic_unmask_irq(d); 634021f6537SMarc Zyngier else 635021f6537SMarc Zyngier gic_dist_wait_for_rwp(); 636021f6537SMarc Zyngier 637021f6537SMarc Zyngier return IRQ_SET_MASK_OK; 638021f6537SMarc Zyngier } 639021f6537SMarc Zyngier #else 640021f6537SMarc Zyngier #define gic_set_affinity NULL 641021f6537SMarc Zyngier #define gic_smp_init() do { } while(0) 642021f6537SMarc Zyngier #endif 643021f6537SMarc Zyngier 6443708d52fSSudeep Holla #ifdef CONFIG_CPU_PM 6453708d52fSSudeep Holla static int gic_cpu_pm_notifier(struct notifier_block *self, 6463708d52fSSudeep Holla unsigned long cmd, void *v) 6473708d52fSSudeep Holla { 6483708d52fSSudeep Holla if (cmd == CPU_PM_EXIT) { 6493708d52fSSudeep Holla gic_enable_redist(true); 6503708d52fSSudeep Holla gic_cpu_sys_reg_init(); 6513708d52fSSudeep Holla } else if (cmd == CPU_PM_ENTER) { 6523708d52fSSudeep Holla gic_write_grpen1(0); 6533708d52fSSudeep Holla gic_enable_redist(false); 6543708d52fSSudeep Holla } 6553708d52fSSudeep Holla return NOTIFY_OK; 6563708d52fSSudeep Holla } 6573708d52fSSudeep Holla 6583708d52fSSudeep Holla static struct notifier_block gic_cpu_pm_notifier_block = { 6593708d52fSSudeep Holla .notifier_call = gic_cpu_pm_notifier, 6603708d52fSSudeep Holla }; 6613708d52fSSudeep Holla 6623708d52fSSudeep Holla static void gic_cpu_pm_init(void) 6633708d52fSSudeep Holla { 6643708d52fSSudeep Holla cpu_pm_register_notifier(&gic_cpu_pm_notifier_block); 6653708d52fSSudeep Holla } 6663708d52fSSudeep Holla 6673708d52fSSudeep Holla #else 6683708d52fSSudeep Holla static inline void gic_cpu_pm_init(void) { } 6693708d52fSSudeep Holla #endif /* CONFIG_CPU_PM */ 6703708d52fSSudeep Holla 671021f6537SMarc Zyngier static struct irq_chip gic_chip = { 672021f6537SMarc Zyngier .name = "GICv3", 673021f6537SMarc Zyngier .irq_mask = gic_mask_irq, 674021f6537SMarc Zyngier .irq_unmask = gic_unmask_irq, 675021f6537SMarc Zyngier .irq_eoi = gic_eoi_irq, 676021f6537SMarc Zyngier .irq_set_type = gic_set_type, 677021f6537SMarc Zyngier .irq_set_affinity = gic_set_affinity, 678b594c6e2SMarc Zyngier .irq_get_irqchip_state = gic_irq_get_irqchip_state, 679b594c6e2SMarc Zyngier .irq_set_irqchip_state = gic_irq_set_irqchip_state, 68055963c9fSSudeep Holla .flags = IRQCHIP_SET_TYPE_MASKED, 681021f6537SMarc Zyngier }; 682021f6537SMarc Zyngier 6830b6a3da9SMarc Zyngier static struct irq_chip gic_eoimode1_chip = { 6840b6a3da9SMarc Zyngier .name = "GICv3", 6850b6a3da9SMarc Zyngier .irq_mask = gic_eoimode1_mask_irq, 6860b6a3da9SMarc Zyngier .irq_unmask = gic_unmask_irq, 6870b6a3da9SMarc Zyngier .irq_eoi = gic_eoimode1_eoi_irq, 6880b6a3da9SMarc Zyngier .irq_set_type = gic_set_type, 6890b6a3da9SMarc Zyngier .irq_set_affinity = gic_set_affinity, 6900b6a3da9SMarc Zyngier .irq_get_irqchip_state = gic_irq_get_irqchip_state, 6910b6a3da9SMarc Zyngier .irq_set_irqchip_state = gic_irq_set_irqchip_state, 692530bf353SMarc Zyngier .irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity, 6930b6a3da9SMarc Zyngier .flags = IRQCHIP_SET_TYPE_MASKED, 6940b6a3da9SMarc Zyngier }; 6950b6a3da9SMarc Zyngier 696da33f31dSMarc Zyngier #define GIC_ID_NR (1U << gic_data.rdists.id_bits) 697da33f31dSMarc Zyngier 698021f6537SMarc Zyngier static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq, 699021f6537SMarc Zyngier irq_hw_number_t hw) 700021f6537SMarc Zyngier { 7010b6a3da9SMarc Zyngier struct irq_chip *chip = &gic_chip; 7020b6a3da9SMarc Zyngier 7030b6a3da9SMarc Zyngier if (static_key_true(&supports_deactivate)) 7040b6a3da9SMarc Zyngier chip = &gic_eoimode1_chip; 7050b6a3da9SMarc Zyngier 706021f6537SMarc Zyngier /* SGIs are private to the core kernel */ 707021f6537SMarc Zyngier if (hw < 16) 708021f6537SMarc Zyngier return -EPERM; 709da33f31dSMarc Zyngier /* Nothing here */ 710da33f31dSMarc Zyngier if (hw >= gic_data.irq_nr && hw < 8192) 711da33f31dSMarc Zyngier return -EPERM; 712da33f31dSMarc Zyngier /* Off limits */ 713da33f31dSMarc Zyngier if (hw >= GIC_ID_NR) 714da33f31dSMarc Zyngier return -EPERM; 715da33f31dSMarc Zyngier 716021f6537SMarc Zyngier /* PPIs */ 717021f6537SMarc Zyngier if (hw < 32) { 718021f6537SMarc Zyngier irq_set_percpu_devid(irq); 7190b6a3da9SMarc Zyngier irq_domain_set_info(d, irq, hw, chip, d->host_data, 720443acc4fSMarc Zyngier handle_percpu_devid_irq, NULL, NULL); 721d17cab44SRob Herring irq_set_status_flags(irq, IRQ_NOAUTOEN); 722021f6537SMarc Zyngier } 723021f6537SMarc Zyngier /* SPIs */ 724021f6537SMarc Zyngier if (hw >= 32 && hw < gic_data.irq_nr) { 7250b6a3da9SMarc Zyngier irq_domain_set_info(d, irq, hw, chip, d->host_data, 726443acc4fSMarc Zyngier handle_fasteoi_irq, NULL, NULL); 727d17cab44SRob Herring irq_set_probe(irq); 728021f6537SMarc Zyngier } 729da33f31dSMarc Zyngier /* LPIs */ 730da33f31dSMarc Zyngier if (hw >= 8192 && hw < GIC_ID_NR) { 731da33f31dSMarc Zyngier if (!gic_dist_supports_lpis()) 732da33f31dSMarc Zyngier return -EPERM; 7330b6a3da9SMarc Zyngier irq_domain_set_info(d, irq, hw, chip, d->host_data, 734da33f31dSMarc Zyngier handle_fasteoi_irq, NULL, NULL); 735da33f31dSMarc Zyngier } 736da33f31dSMarc Zyngier 737021f6537SMarc Zyngier return 0; 738021f6537SMarc Zyngier } 739021f6537SMarc Zyngier 740021f6537SMarc Zyngier static int gic_irq_domain_xlate(struct irq_domain *d, 741021f6537SMarc Zyngier struct device_node *controller, 742021f6537SMarc Zyngier const u32 *intspec, unsigned int intsize, 743021f6537SMarc Zyngier unsigned long *out_hwirq, unsigned int *out_type) 744021f6537SMarc Zyngier { 745021f6537SMarc Zyngier if (d->of_node != controller) 746021f6537SMarc Zyngier return -EINVAL; 747021f6537SMarc Zyngier if (intsize < 3) 748021f6537SMarc Zyngier return -EINVAL; 749021f6537SMarc Zyngier 750021f6537SMarc Zyngier switch(intspec[0]) { 751021f6537SMarc Zyngier case 0: /* SPI */ 752021f6537SMarc Zyngier *out_hwirq = intspec[1] + 32; 753021f6537SMarc Zyngier break; 754021f6537SMarc Zyngier case 1: /* PPI */ 755021f6537SMarc Zyngier *out_hwirq = intspec[1] + 16; 756021f6537SMarc Zyngier break; 757da33f31dSMarc Zyngier case GIC_IRQ_TYPE_LPI: /* LPI */ 758da33f31dSMarc Zyngier *out_hwirq = intspec[1]; 759da33f31dSMarc Zyngier break; 760021f6537SMarc Zyngier default: 761021f6537SMarc Zyngier return -EINVAL; 762021f6537SMarc Zyngier } 763021f6537SMarc Zyngier 764021f6537SMarc Zyngier *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK; 765021f6537SMarc Zyngier return 0; 766021f6537SMarc Zyngier } 767021f6537SMarc Zyngier 768443acc4fSMarc Zyngier static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, 769443acc4fSMarc Zyngier unsigned int nr_irqs, void *arg) 770443acc4fSMarc Zyngier { 771443acc4fSMarc Zyngier int i, ret; 772443acc4fSMarc Zyngier irq_hw_number_t hwirq; 773443acc4fSMarc Zyngier unsigned int type = IRQ_TYPE_NONE; 774443acc4fSMarc Zyngier struct of_phandle_args *irq_data = arg; 775443acc4fSMarc Zyngier 776443acc4fSMarc Zyngier ret = gic_irq_domain_xlate(domain, irq_data->np, irq_data->args, 777443acc4fSMarc Zyngier irq_data->args_count, &hwirq, &type); 778443acc4fSMarc Zyngier if (ret) 779443acc4fSMarc Zyngier return ret; 780443acc4fSMarc Zyngier 781443acc4fSMarc Zyngier for (i = 0; i < nr_irqs; i++) 782443acc4fSMarc Zyngier gic_irq_domain_map(domain, virq + i, hwirq + i); 783443acc4fSMarc Zyngier 784443acc4fSMarc Zyngier return 0; 785443acc4fSMarc Zyngier } 786443acc4fSMarc Zyngier 787443acc4fSMarc Zyngier static void gic_irq_domain_free(struct irq_domain *domain, unsigned int virq, 788443acc4fSMarc Zyngier unsigned int nr_irqs) 789443acc4fSMarc Zyngier { 790443acc4fSMarc Zyngier int i; 791443acc4fSMarc Zyngier 792443acc4fSMarc Zyngier for (i = 0; i < nr_irqs; i++) { 793443acc4fSMarc Zyngier struct irq_data *d = irq_domain_get_irq_data(domain, virq + i); 794443acc4fSMarc Zyngier irq_set_handler(virq + i, NULL); 795443acc4fSMarc Zyngier irq_domain_reset_irq_data(d); 796443acc4fSMarc Zyngier } 797443acc4fSMarc Zyngier } 798443acc4fSMarc Zyngier 799021f6537SMarc Zyngier static const struct irq_domain_ops gic_irq_domain_ops = { 800021f6537SMarc Zyngier .xlate = gic_irq_domain_xlate, 801443acc4fSMarc Zyngier .alloc = gic_irq_domain_alloc, 802443acc4fSMarc Zyngier .free = gic_irq_domain_free, 803021f6537SMarc Zyngier }; 804021f6537SMarc Zyngier 8056d4e11c5SRobert Richter static void gicv3_enable_quirks(void) 8066d4e11c5SRobert Richter { 8077936e914SJean-Philippe Brucker #ifdef CONFIG_ARM64 8086d4e11c5SRobert Richter if (cpus_have_cap(ARM64_WORKAROUND_CAVIUM_23154)) 8098ac2a170SRobert Richter static_branch_enable(&is_cavium_thunderx); 8107936e914SJean-Philippe Brucker #endif 8116d4e11c5SRobert Richter } 8126d4e11c5SRobert Richter 813021f6537SMarc Zyngier static int __init gic_of_init(struct device_node *node, struct device_node *parent) 814021f6537SMarc Zyngier { 815021f6537SMarc Zyngier void __iomem *dist_base; 816f5c1434cSMarc Zyngier struct redist_region *rdist_regs; 817021f6537SMarc Zyngier u64 redist_stride; 818f5c1434cSMarc Zyngier u32 nr_redist_regions; 819f5c1434cSMarc Zyngier u32 typer; 820021f6537SMarc Zyngier u32 reg; 821021f6537SMarc Zyngier int gic_irqs; 822021f6537SMarc Zyngier int err; 823021f6537SMarc Zyngier int i; 824021f6537SMarc Zyngier 825021f6537SMarc Zyngier dist_base = of_iomap(node, 0); 826021f6537SMarc Zyngier if (!dist_base) { 827021f6537SMarc Zyngier pr_err("%s: unable to map gic dist registers\n", 828021f6537SMarc Zyngier node->full_name); 829021f6537SMarc Zyngier return -ENXIO; 830021f6537SMarc Zyngier } 831021f6537SMarc Zyngier 832021f6537SMarc Zyngier reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK; 833021f6537SMarc Zyngier if (reg != GIC_PIDR2_ARCH_GICv3 && reg != GIC_PIDR2_ARCH_GICv4) { 834021f6537SMarc Zyngier pr_err("%s: no distributor detected, giving up\n", 835021f6537SMarc Zyngier node->full_name); 836021f6537SMarc Zyngier err = -ENODEV; 837021f6537SMarc Zyngier goto out_unmap_dist; 838021f6537SMarc Zyngier } 839021f6537SMarc Zyngier 840f5c1434cSMarc Zyngier if (of_property_read_u32(node, "#redistributor-regions", &nr_redist_regions)) 841f5c1434cSMarc Zyngier nr_redist_regions = 1; 842021f6537SMarc Zyngier 843f5c1434cSMarc Zyngier rdist_regs = kzalloc(sizeof(*rdist_regs) * nr_redist_regions, GFP_KERNEL); 844f5c1434cSMarc Zyngier if (!rdist_regs) { 845021f6537SMarc Zyngier err = -ENOMEM; 846021f6537SMarc Zyngier goto out_unmap_dist; 847021f6537SMarc Zyngier } 848021f6537SMarc Zyngier 849f5c1434cSMarc Zyngier for (i = 0; i < nr_redist_regions; i++) { 850f5c1434cSMarc Zyngier struct resource res; 851f5c1434cSMarc Zyngier int ret; 852f5c1434cSMarc Zyngier 853f5c1434cSMarc Zyngier ret = of_address_to_resource(node, 1 + i, &res); 854f5c1434cSMarc Zyngier rdist_regs[i].redist_base = of_iomap(node, 1 + i); 855f5c1434cSMarc Zyngier if (ret || !rdist_regs[i].redist_base) { 856021f6537SMarc Zyngier pr_err("%s: couldn't map region %d\n", 857021f6537SMarc Zyngier node->full_name, i); 858021f6537SMarc Zyngier err = -ENODEV; 859021f6537SMarc Zyngier goto out_unmap_rdist; 860021f6537SMarc Zyngier } 861f5c1434cSMarc Zyngier rdist_regs[i].phys_base = res.start; 862021f6537SMarc Zyngier } 863021f6537SMarc Zyngier 864021f6537SMarc Zyngier if (of_property_read_u64(node, "redistributor-stride", &redist_stride)) 865021f6537SMarc Zyngier redist_stride = 0; 866021f6537SMarc Zyngier 8670b6a3da9SMarc Zyngier if (!is_hyp_mode_available()) 8680b6a3da9SMarc Zyngier static_key_slow_dec(&supports_deactivate); 8690b6a3da9SMarc Zyngier 8700b6a3da9SMarc Zyngier if (static_key_true(&supports_deactivate)) 8710b6a3da9SMarc Zyngier pr_info("GIC: Using split EOI/Deactivate mode\n"); 8720b6a3da9SMarc Zyngier 873021f6537SMarc Zyngier gic_data.dist_base = dist_base; 874f5c1434cSMarc Zyngier gic_data.redist_regions = rdist_regs; 875f5c1434cSMarc Zyngier gic_data.nr_redist_regions = nr_redist_regions; 876021f6537SMarc Zyngier gic_data.redist_stride = redist_stride; 877021f6537SMarc Zyngier 8786d4e11c5SRobert Richter gicv3_enable_quirks(); 8796d4e11c5SRobert Richter 880021f6537SMarc Zyngier /* 881021f6537SMarc Zyngier * Find out how many interrupts are supported. 882021f6537SMarc Zyngier * The GIC only supports up to 1020 interrupt sources (SGI+PPI+SPI) 883021f6537SMarc Zyngier */ 884f5c1434cSMarc Zyngier typer = readl_relaxed(gic_data.dist_base + GICD_TYPER); 885f5c1434cSMarc Zyngier gic_data.rdists.id_bits = GICD_TYPER_ID_BITS(typer); 886f5c1434cSMarc Zyngier gic_irqs = GICD_TYPER_IRQS(typer); 887021f6537SMarc Zyngier if (gic_irqs > 1020) 888021f6537SMarc Zyngier gic_irqs = 1020; 889021f6537SMarc Zyngier gic_data.irq_nr = gic_irqs; 890021f6537SMarc Zyngier 891021f6537SMarc Zyngier gic_data.domain = irq_domain_add_tree(node, &gic_irq_domain_ops, 892021f6537SMarc Zyngier &gic_data); 893f5c1434cSMarc Zyngier gic_data.rdists.rdist = alloc_percpu(typeof(*gic_data.rdists.rdist)); 894021f6537SMarc Zyngier 895f5c1434cSMarc Zyngier if (WARN_ON(!gic_data.domain) || WARN_ON(!gic_data.rdists.rdist)) { 896021f6537SMarc Zyngier err = -ENOMEM; 897021f6537SMarc Zyngier goto out_free; 898021f6537SMarc Zyngier } 899021f6537SMarc Zyngier 900021f6537SMarc Zyngier set_handle_irq(gic_handle_irq); 901021f6537SMarc Zyngier 902da33f31dSMarc Zyngier if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis()) 903da33f31dSMarc Zyngier its_init(node, &gic_data.rdists, gic_data.domain); 904da33f31dSMarc Zyngier 905021f6537SMarc Zyngier gic_smp_init(); 906021f6537SMarc Zyngier gic_dist_init(); 907021f6537SMarc Zyngier gic_cpu_init(); 9083708d52fSSudeep Holla gic_cpu_pm_init(); 909021f6537SMarc Zyngier 910021f6537SMarc Zyngier return 0; 911021f6537SMarc Zyngier 912021f6537SMarc Zyngier out_free: 913021f6537SMarc Zyngier if (gic_data.domain) 914021f6537SMarc Zyngier irq_domain_remove(gic_data.domain); 915f5c1434cSMarc Zyngier free_percpu(gic_data.rdists.rdist); 916021f6537SMarc Zyngier out_unmap_rdist: 917f5c1434cSMarc Zyngier for (i = 0; i < nr_redist_regions; i++) 918f5c1434cSMarc Zyngier if (rdist_regs[i].redist_base) 919f5c1434cSMarc Zyngier iounmap(rdist_regs[i].redist_base); 920f5c1434cSMarc Zyngier kfree(rdist_regs); 921021f6537SMarc Zyngier out_unmap_dist: 922021f6537SMarc Zyngier iounmap(dist_base); 923021f6537SMarc Zyngier return err; 924021f6537SMarc Zyngier } 925021f6537SMarc Zyngier 926021f6537SMarc Zyngier IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init); 927