1021f6537SMarc Zyngier /* 20edc23eaSMarc Zyngier * Copyright (C) 2013-2017 ARM Limited, All Rights Reserved. 3021f6537SMarc Zyngier * Author: Marc Zyngier <marc.zyngier@arm.com> 4021f6537SMarc Zyngier * 5021f6537SMarc Zyngier * This program is free software; you can redistribute it and/or modify 6021f6537SMarc Zyngier * it under the terms of the GNU General Public License version 2 as 7021f6537SMarc Zyngier * published by the Free Software Foundation. 8021f6537SMarc Zyngier * 9021f6537SMarc Zyngier * This program is distributed in the hope that it will be useful, 10021f6537SMarc Zyngier * but WITHOUT ANY WARRANTY; without even the implied warranty of 11021f6537SMarc Zyngier * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12021f6537SMarc Zyngier * GNU General Public License for more details. 13021f6537SMarc Zyngier * 14021f6537SMarc Zyngier * You should have received a copy of the GNU General Public License 15021f6537SMarc Zyngier * along with this program. If not, see <http://www.gnu.org/licenses/>. 16021f6537SMarc Zyngier */ 17021f6537SMarc Zyngier 1868628bb8SJulien Grall #define pr_fmt(fmt) "GICv3: " fmt 1968628bb8SJulien Grall 20ffa7d616STomasz Nowicki #include <linux/acpi.h> 21021f6537SMarc Zyngier #include <linux/cpu.h> 223708d52fSSudeep Holla #include <linux/cpu_pm.h> 23021f6537SMarc Zyngier #include <linux/delay.h> 24021f6537SMarc Zyngier #include <linux/interrupt.h> 25ffa7d616STomasz Nowicki #include <linux/irqdomain.h> 26021f6537SMarc Zyngier #include <linux/of.h> 27021f6537SMarc Zyngier #include <linux/of_address.h> 28021f6537SMarc Zyngier #include <linux/of_irq.h> 29021f6537SMarc Zyngier #include <linux/percpu.h> 30021f6537SMarc Zyngier #include <linux/slab.h> 31021f6537SMarc Zyngier 3241a83e06SJoel Porquet #include <linux/irqchip.h> 331839e576SJulien Grall #include <linux/irqchip/arm-gic-common.h> 34021f6537SMarc Zyngier #include <linux/irqchip/arm-gic-v3.h> 35e3825ba1SMarc Zyngier #include <linux/irqchip/irq-partition-percpu.h> 36021f6537SMarc Zyngier 37021f6537SMarc Zyngier #include <asm/cputype.h> 38021f6537SMarc Zyngier #include <asm/exception.h> 39021f6537SMarc Zyngier #include <asm/smp_plat.h> 400b6a3da9SMarc Zyngier #include <asm/virt.h> 41021f6537SMarc Zyngier 42021f6537SMarc Zyngier #include "irq-gic-common.h" 43021f6537SMarc Zyngier 449c8114c2SSrinivas Kandagatla #define FLAGS_WORKAROUND_GICR_WAKER_MSM8996 (1ULL << 0) 459c8114c2SSrinivas Kandagatla 46f5c1434cSMarc Zyngier struct redist_region { 47f5c1434cSMarc Zyngier void __iomem *redist_base; 48f5c1434cSMarc Zyngier phys_addr_t phys_base; 49b70fb7afSTomasz Nowicki bool single_redist; 50f5c1434cSMarc Zyngier }; 51f5c1434cSMarc Zyngier 52021f6537SMarc Zyngier struct gic_chip_data { 53e3825ba1SMarc Zyngier struct fwnode_handle *fwnode; 54021f6537SMarc Zyngier void __iomem *dist_base; 55f5c1434cSMarc Zyngier struct redist_region *redist_regions; 56f5c1434cSMarc Zyngier struct rdists rdists; 57021f6537SMarc Zyngier struct irq_domain *domain; 58021f6537SMarc Zyngier u64 redist_stride; 59f5c1434cSMarc Zyngier u32 nr_redist_regions; 609c8114c2SSrinivas Kandagatla u64 flags; 61eda0d04aSShanker Donthineni bool has_rss; 62021f6537SMarc Zyngier unsigned int irq_nr; 63e3825ba1SMarc Zyngier struct partition_desc *ppi_descs[16]; 64021f6537SMarc Zyngier }; 65021f6537SMarc Zyngier 66021f6537SMarc Zyngier static struct gic_chip_data gic_data __read_mostly; 67d01d3274SDavidlohr Bueso static DEFINE_STATIC_KEY_TRUE(supports_deactivate_key); 68021f6537SMarc Zyngier 691839e576SJulien Grall static struct gic_kvm_info gic_v3_kvm_info; 70eda0d04aSShanker Donthineni static DEFINE_PER_CPU(bool, has_rss); 711839e576SJulien Grall 72eda0d04aSShanker Donthineni #define MPIDR_RS(mpidr) (((mpidr) & 0xF0UL) >> 4) 73f5c1434cSMarc Zyngier #define gic_data_rdist() (this_cpu_ptr(gic_data.rdists.rdist)) 74f5c1434cSMarc Zyngier #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base) 75021f6537SMarc Zyngier #define gic_data_rdist_sgi_base() (gic_data_rdist_rd_base() + SZ_64K) 76021f6537SMarc Zyngier 77021f6537SMarc Zyngier /* Our default, arbitrary priority value. Linux only uses one anyway. */ 78021f6537SMarc Zyngier #define DEFAULT_PMR_VALUE 0xf0 79021f6537SMarc Zyngier 80021f6537SMarc Zyngier static inline unsigned int gic_irq(struct irq_data *d) 81021f6537SMarc Zyngier { 82021f6537SMarc Zyngier return d->hwirq; 83021f6537SMarc Zyngier } 84021f6537SMarc Zyngier 85021f6537SMarc Zyngier static inline int gic_irq_in_rdist(struct irq_data *d) 86021f6537SMarc Zyngier { 87021f6537SMarc Zyngier return gic_irq(d) < 32; 88021f6537SMarc Zyngier } 89021f6537SMarc Zyngier 90021f6537SMarc Zyngier static inline void __iomem *gic_dist_base(struct irq_data *d) 91021f6537SMarc Zyngier { 92021f6537SMarc Zyngier if (gic_irq_in_rdist(d)) /* SGI+PPI -> SGI_base for this CPU */ 93021f6537SMarc Zyngier return gic_data_rdist_sgi_base(); 94021f6537SMarc Zyngier 95021f6537SMarc Zyngier if (d->hwirq <= 1023) /* SPI -> dist_base */ 96021f6537SMarc Zyngier return gic_data.dist_base; 97021f6537SMarc Zyngier 98021f6537SMarc Zyngier return NULL; 99021f6537SMarc Zyngier } 100021f6537SMarc Zyngier 101021f6537SMarc Zyngier static void gic_do_wait_for_rwp(void __iomem *base) 102021f6537SMarc Zyngier { 103021f6537SMarc Zyngier u32 count = 1000000; /* 1s! */ 104021f6537SMarc Zyngier 105021f6537SMarc Zyngier while (readl_relaxed(base + GICD_CTLR) & GICD_CTLR_RWP) { 106021f6537SMarc Zyngier count--; 107021f6537SMarc Zyngier if (!count) { 108021f6537SMarc Zyngier pr_err_ratelimited("RWP timeout, gone fishing\n"); 109021f6537SMarc Zyngier return; 110021f6537SMarc Zyngier } 111021f6537SMarc Zyngier cpu_relax(); 112021f6537SMarc Zyngier udelay(1); 113021f6537SMarc Zyngier }; 114021f6537SMarc Zyngier } 115021f6537SMarc Zyngier 116021f6537SMarc Zyngier /* Wait for completion of a distributor change */ 117021f6537SMarc Zyngier static void gic_dist_wait_for_rwp(void) 118021f6537SMarc Zyngier { 119021f6537SMarc Zyngier gic_do_wait_for_rwp(gic_data.dist_base); 120021f6537SMarc Zyngier } 121021f6537SMarc Zyngier 122021f6537SMarc Zyngier /* Wait for completion of a redistributor change */ 123021f6537SMarc Zyngier static void gic_redist_wait_for_rwp(void) 124021f6537SMarc Zyngier { 125021f6537SMarc Zyngier gic_do_wait_for_rwp(gic_data_rdist_rd_base()); 126021f6537SMarc Zyngier } 127021f6537SMarc Zyngier 1287936e914SJean-Philippe Brucker #ifdef CONFIG_ARM64 1296d4e11c5SRobert Richter 1306d4e11c5SRobert Richter static u64 __maybe_unused gic_read_iar(void) 1316d4e11c5SRobert Richter { 132a4023f68SSuzuki K Poulose if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_23154)) 1336d4e11c5SRobert Richter return gic_read_iar_cavium_thunderx(); 1346d4e11c5SRobert Richter else 1356d4e11c5SRobert Richter return gic_read_iar_common(); 1366d4e11c5SRobert Richter } 1377936e914SJean-Philippe Brucker #endif 138021f6537SMarc Zyngier 139a2c22510SSudeep Holla static void gic_enable_redist(bool enable) 140021f6537SMarc Zyngier { 141021f6537SMarc Zyngier void __iomem *rbase; 142021f6537SMarc Zyngier u32 count = 1000000; /* 1s! */ 143021f6537SMarc Zyngier u32 val; 144021f6537SMarc Zyngier 1459c8114c2SSrinivas Kandagatla if (gic_data.flags & FLAGS_WORKAROUND_GICR_WAKER_MSM8996) 1469c8114c2SSrinivas Kandagatla return; 1479c8114c2SSrinivas Kandagatla 148021f6537SMarc Zyngier rbase = gic_data_rdist_rd_base(); 149021f6537SMarc Zyngier 150021f6537SMarc Zyngier val = readl_relaxed(rbase + GICR_WAKER); 151a2c22510SSudeep Holla if (enable) 152a2c22510SSudeep Holla /* Wake up this CPU redistributor */ 153021f6537SMarc Zyngier val &= ~GICR_WAKER_ProcessorSleep; 154a2c22510SSudeep Holla else 155a2c22510SSudeep Holla val |= GICR_WAKER_ProcessorSleep; 156021f6537SMarc Zyngier writel_relaxed(val, rbase + GICR_WAKER); 157021f6537SMarc Zyngier 158a2c22510SSudeep Holla if (!enable) { /* Check that GICR_WAKER is writeable */ 159a2c22510SSudeep Holla val = readl_relaxed(rbase + GICR_WAKER); 160a2c22510SSudeep Holla if (!(val & GICR_WAKER_ProcessorSleep)) 161a2c22510SSudeep Holla return; /* No PM support in this redistributor */ 162021f6537SMarc Zyngier } 163a2c22510SSudeep Holla 164d102eb5cSDan Carpenter while (--count) { 165a2c22510SSudeep Holla val = readl_relaxed(rbase + GICR_WAKER); 166cf1d9d11SAndrew Jones if (enable ^ (bool)(val & GICR_WAKER_ChildrenAsleep)) 167a2c22510SSudeep Holla break; 168021f6537SMarc Zyngier cpu_relax(); 169021f6537SMarc Zyngier udelay(1); 170021f6537SMarc Zyngier }; 171a2c22510SSudeep Holla if (!count) 172a2c22510SSudeep Holla pr_err_ratelimited("redistributor failed to %s...\n", 173a2c22510SSudeep Holla enable ? "wakeup" : "sleep"); 174021f6537SMarc Zyngier } 175021f6537SMarc Zyngier 176021f6537SMarc Zyngier /* 177021f6537SMarc Zyngier * Routines to disable, enable, EOI and route interrupts 178021f6537SMarc Zyngier */ 179b594c6e2SMarc Zyngier static int gic_peek_irq(struct irq_data *d, u32 offset) 180b594c6e2SMarc Zyngier { 181b594c6e2SMarc Zyngier u32 mask = 1 << (gic_irq(d) % 32); 182b594c6e2SMarc Zyngier void __iomem *base; 183b594c6e2SMarc Zyngier 184b594c6e2SMarc Zyngier if (gic_irq_in_rdist(d)) 185b594c6e2SMarc Zyngier base = gic_data_rdist_sgi_base(); 186b594c6e2SMarc Zyngier else 187b594c6e2SMarc Zyngier base = gic_data.dist_base; 188b594c6e2SMarc Zyngier 189b594c6e2SMarc Zyngier return !!(readl_relaxed(base + offset + (gic_irq(d) / 32) * 4) & mask); 190b594c6e2SMarc Zyngier } 191b594c6e2SMarc Zyngier 192021f6537SMarc Zyngier static void gic_poke_irq(struct irq_data *d, u32 offset) 193021f6537SMarc Zyngier { 194021f6537SMarc Zyngier u32 mask = 1 << (gic_irq(d) % 32); 195021f6537SMarc Zyngier void (*rwp_wait)(void); 196021f6537SMarc Zyngier void __iomem *base; 197021f6537SMarc Zyngier 198021f6537SMarc Zyngier if (gic_irq_in_rdist(d)) { 199021f6537SMarc Zyngier base = gic_data_rdist_sgi_base(); 200021f6537SMarc Zyngier rwp_wait = gic_redist_wait_for_rwp; 201021f6537SMarc Zyngier } else { 202021f6537SMarc Zyngier base = gic_data.dist_base; 203021f6537SMarc Zyngier rwp_wait = gic_dist_wait_for_rwp; 204021f6537SMarc Zyngier } 205021f6537SMarc Zyngier 206021f6537SMarc Zyngier writel_relaxed(mask, base + offset + (gic_irq(d) / 32) * 4); 207021f6537SMarc Zyngier rwp_wait(); 208021f6537SMarc Zyngier } 209021f6537SMarc Zyngier 210021f6537SMarc Zyngier static void gic_mask_irq(struct irq_data *d) 211021f6537SMarc Zyngier { 212021f6537SMarc Zyngier gic_poke_irq(d, GICD_ICENABLER); 213021f6537SMarc Zyngier } 214021f6537SMarc Zyngier 2150b6a3da9SMarc Zyngier static void gic_eoimode1_mask_irq(struct irq_data *d) 2160b6a3da9SMarc Zyngier { 2170b6a3da9SMarc Zyngier gic_mask_irq(d); 218530bf353SMarc Zyngier /* 219530bf353SMarc Zyngier * When masking a forwarded interrupt, make sure it is 220530bf353SMarc Zyngier * deactivated as well. 221530bf353SMarc Zyngier * 222530bf353SMarc Zyngier * This ensures that an interrupt that is getting 223530bf353SMarc Zyngier * disabled/masked will not get "stuck", because there is 224530bf353SMarc Zyngier * noone to deactivate it (guest is being terminated). 225530bf353SMarc Zyngier */ 2264df7f54dSThomas Gleixner if (irqd_is_forwarded_to_vcpu(d)) 227530bf353SMarc Zyngier gic_poke_irq(d, GICD_ICACTIVER); 2280b6a3da9SMarc Zyngier } 2290b6a3da9SMarc Zyngier 230021f6537SMarc Zyngier static void gic_unmask_irq(struct irq_data *d) 231021f6537SMarc Zyngier { 232021f6537SMarc Zyngier gic_poke_irq(d, GICD_ISENABLER); 233021f6537SMarc Zyngier } 234021f6537SMarc Zyngier 235b594c6e2SMarc Zyngier static int gic_irq_set_irqchip_state(struct irq_data *d, 236b594c6e2SMarc Zyngier enum irqchip_irq_state which, bool val) 237b594c6e2SMarc Zyngier { 238b594c6e2SMarc Zyngier u32 reg; 239b594c6e2SMarc Zyngier 240b594c6e2SMarc Zyngier if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */ 241b594c6e2SMarc Zyngier return -EINVAL; 242b594c6e2SMarc Zyngier 243b594c6e2SMarc Zyngier switch (which) { 244b594c6e2SMarc Zyngier case IRQCHIP_STATE_PENDING: 245b594c6e2SMarc Zyngier reg = val ? GICD_ISPENDR : GICD_ICPENDR; 246b594c6e2SMarc Zyngier break; 247b594c6e2SMarc Zyngier 248b594c6e2SMarc Zyngier case IRQCHIP_STATE_ACTIVE: 249b594c6e2SMarc Zyngier reg = val ? GICD_ISACTIVER : GICD_ICACTIVER; 250b594c6e2SMarc Zyngier break; 251b594c6e2SMarc Zyngier 252b594c6e2SMarc Zyngier case IRQCHIP_STATE_MASKED: 253b594c6e2SMarc Zyngier reg = val ? GICD_ICENABLER : GICD_ISENABLER; 254b594c6e2SMarc Zyngier break; 255b594c6e2SMarc Zyngier 256b594c6e2SMarc Zyngier default: 257b594c6e2SMarc Zyngier return -EINVAL; 258b594c6e2SMarc Zyngier } 259b594c6e2SMarc Zyngier 260b594c6e2SMarc Zyngier gic_poke_irq(d, reg); 261b594c6e2SMarc Zyngier return 0; 262b594c6e2SMarc Zyngier } 263b594c6e2SMarc Zyngier 264b594c6e2SMarc Zyngier static int gic_irq_get_irqchip_state(struct irq_data *d, 265b594c6e2SMarc Zyngier enum irqchip_irq_state which, bool *val) 266b594c6e2SMarc Zyngier { 267b594c6e2SMarc Zyngier if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */ 268b594c6e2SMarc Zyngier return -EINVAL; 269b594c6e2SMarc Zyngier 270b594c6e2SMarc Zyngier switch (which) { 271b594c6e2SMarc Zyngier case IRQCHIP_STATE_PENDING: 272b594c6e2SMarc Zyngier *val = gic_peek_irq(d, GICD_ISPENDR); 273b594c6e2SMarc Zyngier break; 274b594c6e2SMarc Zyngier 275b594c6e2SMarc Zyngier case IRQCHIP_STATE_ACTIVE: 276b594c6e2SMarc Zyngier *val = gic_peek_irq(d, GICD_ISACTIVER); 277b594c6e2SMarc Zyngier break; 278b594c6e2SMarc Zyngier 279b594c6e2SMarc Zyngier case IRQCHIP_STATE_MASKED: 280b594c6e2SMarc Zyngier *val = !gic_peek_irq(d, GICD_ISENABLER); 281b594c6e2SMarc Zyngier break; 282b594c6e2SMarc Zyngier 283b594c6e2SMarc Zyngier default: 284b594c6e2SMarc Zyngier return -EINVAL; 285b594c6e2SMarc Zyngier } 286b594c6e2SMarc Zyngier 287b594c6e2SMarc Zyngier return 0; 288b594c6e2SMarc Zyngier } 289b594c6e2SMarc Zyngier 290021f6537SMarc Zyngier static void gic_eoi_irq(struct irq_data *d) 291021f6537SMarc Zyngier { 292021f6537SMarc Zyngier gic_write_eoir(gic_irq(d)); 293021f6537SMarc Zyngier } 294021f6537SMarc Zyngier 2950b6a3da9SMarc Zyngier static void gic_eoimode1_eoi_irq(struct irq_data *d) 2960b6a3da9SMarc Zyngier { 2970b6a3da9SMarc Zyngier /* 298530bf353SMarc Zyngier * No need to deactivate an LPI, or an interrupt that 299530bf353SMarc Zyngier * is is getting forwarded to a vcpu. 3000b6a3da9SMarc Zyngier */ 3014df7f54dSThomas Gleixner if (gic_irq(d) >= 8192 || irqd_is_forwarded_to_vcpu(d)) 3020b6a3da9SMarc Zyngier return; 3030b6a3da9SMarc Zyngier gic_write_dir(gic_irq(d)); 3040b6a3da9SMarc Zyngier } 3050b6a3da9SMarc Zyngier 306021f6537SMarc Zyngier static int gic_set_type(struct irq_data *d, unsigned int type) 307021f6537SMarc Zyngier { 308021f6537SMarc Zyngier unsigned int irq = gic_irq(d); 309021f6537SMarc Zyngier void (*rwp_wait)(void); 310021f6537SMarc Zyngier void __iomem *base; 311021f6537SMarc Zyngier 312021f6537SMarc Zyngier /* Interrupt configuration for SGIs can't be changed */ 313021f6537SMarc Zyngier if (irq < 16) 314021f6537SMarc Zyngier return -EINVAL; 315021f6537SMarc Zyngier 316fb7e7debSLiviu Dudau /* SPIs have restrictions on the supported types */ 317fb7e7debSLiviu Dudau if (irq >= 32 && type != IRQ_TYPE_LEVEL_HIGH && 318fb7e7debSLiviu Dudau type != IRQ_TYPE_EDGE_RISING) 319021f6537SMarc Zyngier return -EINVAL; 320021f6537SMarc Zyngier 321021f6537SMarc Zyngier if (gic_irq_in_rdist(d)) { 322021f6537SMarc Zyngier base = gic_data_rdist_sgi_base(); 323021f6537SMarc Zyngier rwp_wait = gic_redist_wait_for_rwp; 324021f6537SMarc Zyngier } else { 325021f6537SMarc Zyngier base = gic_data.dist_base; 326021f6537SMarc Zyngier rwp_wait = gic_dist_wait_for_rwp; 327021f6537SMarc Zyngier } 328021f6537SMarc Zyngier 329fb7e7debSLiviu Dudau return gic_configure_irq(irq, type, base, rwp_wait); 330021f6537SMarc Zyngier } 331021f6537SMarc Zyngier 332530bf353SMarc Zyngier static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu) 333530bf353SMarc Zyngier { 3344df7f54dSThomas Gleixner if (vcpu) 3354df7f54dSThomas Gleixner irqd_set_forwarded_to_vcpu(d); 3364df7f54dSThomas Gleixner else 3374df7f54dSThomas Gleixner irqd_clr_forwarded_to_vcpu(d); 338530bf353SMarc Zyngier return 0; 339530bf353SMarc Zyngier } 340530bf353SMarc Zyngier 341f6c86a41SJean-Philippe Brucker static u64 gic_mpidr_to_affinity(unsigned long mpidr) 342021f6537SMarc Zyngier { 343021f6537SMarc Zyngier u64 aff; 344021f6537SMarc Zyngier 345f6c86a41SJean-Philippe Brucker aff = ((u64)MPIDR_AFFINITY_LEVEL(mpidr, 3) << 32 | 346021f6537SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 | 347021f6537SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | 348021f6537SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 0)); 349021f6537SMarc Zyngier 350021f6537SMarc Zyngier return aff; 351021f6537SMarc Zyngier } 352021f6537SMarc Zyngier 353021f6537SMarc Zyngier static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) 354021f6537SMarc Zyngier { 355f6c86a41SJean-Philippe Brucker u32 irqnr; 356021f6537SMarc Zyngier 357021f6537SMarc Zyngier irqnr = gic_read_iar(); 358021f6537SMarc Zyngier 3593f1f3234SJulien Thierry if (gic_prio_masking_enabled()) { 3603f1f3234SJulien Thierry gic_pmr_mask_irqs(); 3613f1f3234SJulien Thierry gic_arch_enable_irqs(); 3623f1f3234SJulien Thierry } 3633f1f3234SJulien Thierry 364da33f31dSMarc Zyngier if (likely(irqnr > 15 && irqnr < 1020) || irqnr >= 8192) { 365ebc6de00SMarc Zyngier int err; 3660b6a3da9SMarc Zyngier 367d01d3274SDavidlohr Bueso if (static_branch_likely(&supports_deactivate_key)) 3680b6a3da9SMarc Zyngier gic_write_eoir(irqnr); 36939a06b67SWill Deacon else 37039a06b67SWill Deacon isb(); 3710b6a3da9SMarc Zyngier 372ebc6de00SMarc Zyngier err = handle_domain_irq(gic_data.domain, irqnr, regs); 373ebc6de00SMarc Zyngier if (err) { 374da33f31dSMarc Zyngier WARN_ONCE(true, "Unexpected interrupt received!\n"); 375d01d3274SDavidlohr Bueso if (static_branch_likely(&supports_deactivate_key)) { 3760b6a3da9SMarc Zyngier if (irqnr < 8192) 3770b6a3da9SMarc Zyngier gic_write_dir(irqnr); 3780b6a3da9SMarc Zyngier } else { 379021f6537SMarc Zyngier gic_write_eoir(irqnr); 380021f6537SMarc Zyngier } 3810b6a3da9SMarc Zyngier } 382342677d7SJulien Thierry return; 383ebc6de00SMarc Zyngier } 384021f6537SMarc Zyngier if (irqnr < 16) { 385021f6537SMarc Zyngier gic_write_eoir(irqnr); 386d01d3274SDavidlohr Bueso if (static_branch_likely(&supports_deactivate_key)) 3870b6a3da9SMarc Zyngier gic_write_dir(irqnr); 388021f6537SMarc Zyngier #ifdef CONFIG_SMP 389f86c4fbdSWill Deacon /* 390f86c4fbdSWill Deacon * Unlike GICv2, we don't need an smp_rmb() here. 391f86c4fbdSWill Deacon * The control dependency from gic_read_iar to 392f86c4fbdSWill Deacon * the ISB in gic_write_eoir is enough to ensure 393f86c4fbdSWill Deacon * that any shared data read by handle_IPI will 394f86c4fbdSWill Deacon * be read after the ACK. 395f86c4fbdSWill Deacon */ 396021f6537SMarc Zyngier handle_IPI(irqnr, regs); 397021f6537SMarc Zyngier #else 398021f6537SMarc Zyngier WARN_ONCE(true, "Unexpected SGI received!\n"); 399021f6537SMarc Zyngier #endif 400021f6537SMarc Zyngier } 401021f6537SMarc Zyngier } 402021f6537SMarc Zyngier 403b5cf6073SJulien Thierry static u32 gic_get_pribits(void) 404b5cf6073SJulien Thierry { 405b5cf6073SJulien Thierry u32 pribits; 406b5cf6073SJulien Thierry 407b5cf6073SJulien Thierry pribits = gic_read_ctlr(); 408b5cf6073SJulien Thierry pribits &= ICC_CTLR_EL1_PRI_BITS_MASK; 409b5cf6073SJulien Thierry pribits >>= ICC_CTLR_EL1_PRI_BITS_SHIFT; 410b5cf6073SJulien Thierry pribits++; 411b5cf6073SJulien Thierry 412b5cf6073SJulien Thierry return pribits; 413b5cf6073SJulien Thierry } 414b5cf6073SJulien Thierry 415b5cf6073SJulien Thierry static bool gic_has_group0(void) 416b5cf6073SJulien Thierry { 417b5cf6073SJulien Thierry u32 val; 418e7932188SJulien Thierry u32 old_pmr; 419e7932188SJulien Thierry 420e7932188SJulien Thierry old_pmr = gic_read_pmr(); 421b5cf6073SJulien Thierry 422b5cf6073SJulien Thierry /* 423b5cf6073SJulien Thierry * Let's find out if Group0 is under control of EL3 or not by 424b5cf6073SJulien Thierry * setting the highest possible, non-zero priority in PMR. 425b5cf6073SJulien Thierry * 426b5cf6073SJulien Thierry * If SCR_EL3.FIQ is set, the priority gets shifted down in 427b5cf6073SJulien Thierry * order for the CPU interface to set bit 7, and keep the 428b5cf6073SJulien Thierry * actual priority in the non-secure range. In the process, it 429b5cf6073SJulien Thierry * looses the least significant bit and the actual priority 430b5cf6073SJulien Thierry * becomes 0x80. Reading it back returns 0, indicating that 431b5cf6073SJulien Thierry * we're don't have access to Group0. 432b5cf6073SJulien Thierry */ 433b5cf6073SJulien Thierry gic_write_pmr(BIT(8 - gic_get_pribits())); 434b5cf6073SJulien Thierry val = gic_read_pmr(); 435b5cf6073SJulien Thierry 436e7932188SJulien Thierry gic_write_pmr(old_pmr); 437e7932188SJulien Thierry 438b5cf6073SJulien Thierry return val != 0; 439b5cf6073SJulien Thierry } 440b5cf6073SJulien Thierry 441021f6537SMarc Zyngier static void __init gic_dist_init(void) 442021f6537SMarc Zyngier { 443021f6537SMarc Zyngier unsigned int i; 444021f6537SMarc Zyngier u64 affinity; 445021f6537SMarc Zyngier void __iomem *base = gic_data.dist_base; 446021f6537SMarc Zyngier 447021f6537SMarc Zyngier /* Disable the distributor */ 448021f6537SMarc Zyngier writel_relaxed(0, base + GICD_CTLR); 449021f6537SMarc Zyngier gic_dist_wait_for_rwp(); 450021f6537SMarc Zyngier 4517c9b9730SMarc Zyngier /* 4527c9b9730SMarc Zyngier * Configure SPIs as non-secure Group-1. This will only matter 4537c9b9730SMarc Zyngier * if the GIC only has a single security state. This will not 4547c9b9730SMarc Zyngier * do the right thing if the kernel is running in secure mode, 4557c9b9730SMarc Zyngier * but that's not the intended use case anyway. 4567c9b9730SMarc Zyngier */ 4577c9b9730SMarc Zyngier for (i = 32; i < gic_data.irq_nr; i += 32) 4587c9b9730SMarc Zyngier writel_relaxed(~0, base + GICD_IGROUPR + i / 8); 4597c9b9730SMarc Zyngier 460021f6537SMarc Zyngier gic_dist_config(base, gic_data.irq_nr, gic_dist_wait_for_rwp); 461021f6537SMarc Zyngier 462021f6537SMarc Zyngier /* Enable distributor with ARE, Group1 */ 463021f6537SMarc Zyngier writel_relaxed(GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G1A | GICD_CTLR_ENABLE_G1, 464021f6537SMarc Zyngier base + GICD_CTLR); 465021f6537SMarc Zyngier 466021f6537SMarc Zyngier /* 467021f6537SMarc Zyngier * Set all global interrupts to the boot CPU only. ARE must be 468021f6537SMarc Zyngier * enabled. 469021f6537SMarc Zyngier */ 470021f6537SMarc Zyngier affinity = gic_mpidr_to_affinity(cpu_logical_map(smp_processor_id())); 471021f6537SMarc Zyngier for (i = 32; i < gic_data.irq_nr; i++) 47272c97126SJean-Philippe Brucker gic_write_irouter(affinity, base + GICD_IROUTER + i * 8); 473021f6537SMarc Zyngier } 474021f6537SMarc Zyngier 4750d94ded2SMarc Zyngier static int gic_iterate_rdists(int (*fn)(struct redist_region *, void __iomem *)) 476021f6537SMarc Zyngier { 4770d94ded2SMarc Zyngier int ret = -ENODEV; 478021f6537SMarc Zyngier int i; 479021f6537SMarc Zyngier 480f5c1434cSMarc Zyngier for (i = 0; i < gic_data.nr_redist_regions; i++) { 481f5c1434cSMarc Zyngier void __iomem *ptr = gic_data.redist_regions[i].redist_base; 4820d94ded2SMarc Zyngier u64 typer; 483021f6537SMarc Zyngier u32 reg; 484021f6537SMarc Zyngier 485021f6537SMarc Zyngier reg = readl_relaxed(ptr + GICR_PIDR2) & GIC_PIDR2_ARCH_MASK; 486021f6537SMarc Zyngier if (reg != GIC_PIDR2_ARCH_GICv3 && 487021f6537SMarc Zyngier reg != GIC_PIDR2_ARCH_GICv4) { /* We're in trouble... */ 488021f6537SMarc Zyngier pr_warn("No redistributor present @%p\n", ptr); 489021f6537SMarc Zyngier break; 490021f6537SMarc Zyngier } 491021f6537SMarc Zyngier 492021f6537SMarc Zyngier do { 49372c97126SJean-Philippe Brucker typer = gic_read_typer(ptr + GICR_TYPER); 4940d94ded2SMarc Zyngier ret = fn(gic_data.redist_regions + i, ptr); 4950d94ded2SMarc Zyngier if (!ret) 496021f6537SMarc Zyngier return 0; 497021f6537SMarc Zyngier 498b70fb7afSTomasz Nowicki if (gic_data.redist_regions[i].single_redist) 499b70fb7afSTomasz Nowicki break; 500b70fb7afSTomasz Nowicki 501021f6537SMarc Zyngier if (gic_data.redist_stride) { 502021f6537SMarc Zyngier ptr += gic_data.redist_stride; 503021f6537SMarc Zyngier } else { 504021f6537SMarc Zyngier ptr += SZ_64K * 2; /* Skip RD_base + SGI_base */ 505021f6537SMarc Zyngier if (typer & GICR_TYPER_VLPIS) 506021f6537SMarc Zyngier ptr += SZ_64K * 2; /* Skip VLPI_base + reserved page */ 507021f6537SMarc Zyngier } 508021f6537SMarc Zyngier } while (!(typer & GICR_TYPER_LAST)); 509021f6537SMarc Zyngier } 510021f6537SMarc Zyngier 5110d94ded2SMarc Zyngier return ret ? -ENODEV : 0; 5120d94ded2SMarc Zyngier } 5130d94ded2SMarc Zyngier 5140d94ded2SMarc Zyngier static int __gic_populate_rdist(struct redist_region *region, void __iomem *ptr) 5150d94ded2SMarc Zyngier { 5160d94ded2SMarc Zyngier unsigned long mpidr = cpu_logical_map(smp_processor_id()); 5170d94ded2SMarc Zyngier u64 typer; 5180d94ded2SMarc Zyngier u32 aff; 5190d94ded2SMarc Zyngier 5200d94ded2SMarc Zyngier /* 5210d94ded2SMarc Zyngier * Convert affinity to a 32bit value that can be matched to 5220d94ded2SMarc Zyngier * GICR_TYPER bits [63:32]. 5230d94ded2SMarc Zyngier */ 5240d94ded2SMarc Zyngier aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 24 | 5250d94ded2SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 | 5260d94ded2SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | 5270d94ded2SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 0)); 5280d94ded2SMarc Zyngier 5290d94ded2SMarc Zyngier typer = gic_read_typer(ptr + GICR_TYPER); 5300d94ded2SMarc Zyngier if ((typer >> 32) == aff) { 5310d94ded2SMarc Zyngier u64 offset = ptr - region->redist_base; 5320d94ded2SMarc Zyngier gic_data_rdist_rd_base() = ptr; 5330d94ded2SMarc Zyngier gic_data_rdist()->phys_base = region->phys_base + offset; 5340d94ded2SMarc Zyngier 5350d94ded2SMarc Zyngier pr_info("CPU%d: found redistributor %lx region %d:%pa\n", 5360d94ded2SMarc Zyngier smp_processor_id(), mpidr, 5370d94ded2SMarc Zyngier (int)(region - gic_data.redist_regions), 5380d94ded2SMarc Zyngier &gic_data_rdist()->phys_base); 5390d94ded2SMarc Zyngier return 0; 5400d94ded2SMarc Zyngier } 5410d94ded2SMarc Zyngier 5420d94ded2SMarc Zyngier /* Try next one */ 5430d94ded2SMarc Zyngier return 1; 5440d94ded2SMarc Zyngier } 5450d94ded2SMarc Zyngier 5460d94ded2SMarc Zyngier static int gic_populate_rdist(void) 5470d94ded2SMarc Zyngier { 5480d94ded2SMarc Zyngier if (gic_iterate_rdists(__gic_populate_rdist) == 0) 5490d94ded2SMarc Zyngier return 0; 5500d94ded2SMarc Zyngier 551021f6537SMarc Zyngier /* We couldn't even deal with ourselves... */ 552f6c86a41SJean-Philippe Brucker WARN(true, "CPU%d: mpidr %lx has no re-distributor!\n", 5530d94ded2SMarc Zyngier smp_processor_id(), 5540d94ded2SMarc Zyngier (unsigned long)cpu_logical_map(smp_processor_id())); 555021f6537SMarc Zyngier return -ENODEV; 556021f6537SMarc Zyngier } 557021f6537SMarc Zyngier 5580edc23eaSMarc Zyngier static int __gic_update_vlpi_properties(struct redist_region *region, 5590edc23eaSMarc Zyngier void __iomem *ptr) 5600edc23eaSMarc Zyngier { 5610edc23eaSMarc Zyngier u64 typer = gic_read_typer(ptr + GICR_TYPER); 5620edc23eaSMarc Zyngier gic_data.rdists.has_vlpis &= !!(typer & GICR_TYPER_VLPIS); 5630edc23eaSMarc Zyngier gic_data.rdists.has_direct_lpi &= !!(typer & GICR_TYPER_DirectLPIS); 5640edc23eaSMarc Zyngier 5650edc23eaSMarc Zyngier return 1; 5660edc23eaSMarc Zyngier } 5670edc23eaSMarc Zyngier 5680edc23eaSMarc Zyngier static void gic_update_vlpi_properties(void) 5690edc23eaSMarc Zyngier { 5700edc23eaSMarc Zyngier gic_iterate_rdists(__gic_update_vlpi_properties); 5710edc23eaSMarc Zyngier pr_info("%sVLPI support, %sdirect LPI support\n", 5720edc23eaSMarc Zyngier !gic_data.rdists.has_vlpis ? "no " : "", 5730edc23eaSMarc Zyngier !gic_data.rdists.has_direct_lpi ? "no " : ""); 5740edc23eaSMarc Zyngier } 5750edc23eaSMarc Zyngier 5763708d52fSSudeep Holla static void gic_cpu_sys_reg_init(void) 577021f6537SMarc Zyngier { 578eda0d04aSShanker Donthineni int i, cpu = smp_processor_id(); 579eda0d04aSShanker Donthineni u64 mpidr = cpu_logical_map(cpu); 580eda0d04aSShanker Donthineni u64 need_rss = MPIDR_RS(mpidr); 58133625282SMarc Zyngier bool group0; 582b5cf6073SJulien Thierry u32 pribits; 583eda0d04aSShanker Donthineni 5847cabd008SMarc Zyngier /* 5857cabd008SMarc Zyngier * Need to check that the SRE bit has actually been set. If 5867cabd008SMarc Zyngier * not, it means that SRE is disabled at EL2. We're going to 5877cabd008SMarc Zyngier * die painfully, and there is nothing we can do about it. 5887cabd008SMarc Zyngier * 5897cabd008SMarc Zyngier * Kindly inform the luser. 5907cabd008SMarc Zyngier */ 5917cabd008SMarc Zyngier if (!gic_enable_sre()) 5927cabd008SMarc Zyngier pr_err("GIC: unable to set SRE (disabled at EL2), panic ahead\n"); 593021f6537SMarc Zyngier 594b5cf6073SJulien Thierry pribits = gic_get_pribits(); 59533625282SMarc Zyngier 596b5cf6073SJulien Thierry group0 = gic_has_group0(); 59733625282SMarc Zyngier 598021f6537SMarc Zyngier /* Set priority mask register */ 599e7932188SJulien Thierry if (!gic_prio_masking_enabled()) 60033625282SMarc Zyngier write_gicreg(DEFAULT_PMR_VALUE, ICC_PMR_EL1); 601021f6537SMarc Zyngier 60291ef8442SDaniel Thompson /* 60391ef8442SDaniel Thompson * Some firmwares hand over to the kernel with the BPR changed from 60491ef8442SDaniel Thompson * its reset value (and with a value large enough to prevent 60591ef8442SDaniel Thompson * any pre-emptive interrupts from working at all). Writing a zero 60691ef8442SDaniel Thompson * to BPR restores is reset value. 60791ef8442SDaniel Thompson */ 60891ef8442SDaniel Thompson gic_write_bpr1(0); 60991ef8442SDaniel Thompson 610d01d3274SDavidlohr Bueso if (static_branch_likely(&supports_deactivate_key)) { 6110b6a3da9SMarc Zyngier /* EOI drops priority only (mode 1) */ 6120b6a3da9SMarc Zyngier gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop); 6130b6a3da9SMarc Zyngier } else { 614021f6537SMarc Zyngier /* EOI deactivates interrupt too (mode 0) */ 615021f6537SMarc Zyngier gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop_dir); 6160b6a3da9SMarc Zyngier } 617021f6537SMarc Zyngier 61833625282SMarc Zyngier /* Always whack Group0 before Group1 */ 61933625282SMarc Zyngier if (group0) { 62033625282SMarc Zyngier switch(pribits) { 62133625282SMarc Zyngier case 8: 62233625282SMarc Zyngier case 7: 62333625282SMarc Zyngier write_gicreg(0, ICC_AP0R3_EL1); 62433625282SMarc Zyngier write_gicreg(0, ICC_AP0R2_EL1); 62533625282SMarc Zyngier case 6: 62633625282SMarc Zyngier write_gicreg(0, ICC_AP0R1_EL1); 62733625282SMarc Zyngier case 5: 62833625282SMarc Zyngier case 4: 62933625282SMarc Zyngier write_gicreg(0, ICC_AP0R0_EL1); 63033625282SMarc Zyngier } 631d6062a6dSMarc Zyngier 63233625282SMarc Zyngier isb(); 63333625282SMarc Zyngier } 63433625282SMarc Zyngier 63533625282SMarc Zyngier switch(pribits) { 636d6062a6dSMarc Zyngier case 8: 637d6062a6dSMarc Zyngier case 7: 638d6062a6dSMarc Zyngier write_gicreg(0, ICC_AP1R3_EL1); 639d6062a6dSMarc Zyngier write_gicreg(0, ICC_AP1R2_EL1); 640d6062a6dSMarc Zyngier case 6: 641d6062a6dSMarc Zyngier write_gicreg(0, ICC_AP1R1_EL1); 642d6062a6dSMarc Zyngier case 5: 643d6062a6dSMarc Zyngier case 4: 644d6062a6dSMarc Zyngier write_gicreg(0, ICC_AP1R0_EL1); 645d6062a6dSMarc Zyngier } 646d6062a6dSMarc Zyngier 647d6062a6dSMarc Zyngier isb(); 648d6062a6dSMarc Zyngier 649021f6537SMarc Zyngier /* ... and let's hit the road... */ 650021f6537SMarc Zyngier gic_write_grpen1(1); 651eda0d04aSShanker Donthineni 652eda0d04aSShanker Donthineni /* Keep the RSS capability status in per_cpu variable */ 653eda0d04aSShanker Donthineni per_cpu(has_rss, cpu) = !!(gic_read_ctlr() & ICC_CTLR_EL1_RSS); 654eda0d04aSShanker Donthineni 655eda0d04aSShanker Donthineni /* Check all the CPUs have capable of sending SGIs to other CPUs */ 656eda0d04aSShanker Donthineni for_each_online_cpu(i) { 657eda0d04aSShanker Donthineni bool have_rss = per_cpu(has_rss, i) && per_cpu(has_rss, cpu); 658eda0d04aSShanker Donthineni 659eda0d04aSShanker Donthineni need_rss |= MPIDR_RS(cpu_logical_map(i)); 660eda0d04aSShanker Donthineni if (need_rss && (!have_rss)) 661eda0d04aSShanker Donthineni pr_crit("CPU%d (%lx) can't SGI CPU%d (%lx), no RSS\n", 662eda0d04aSShanker Donthineni cpu, (unsigned long)mpidr, 663eda0d04aSShanker Donthineni i, (unsigned long)cpu_logical_map(i)); 664eda0d04aSShanker Donthineni } 665eda0d04aSShanker Donthineni 666eda0d04aSShanker Donthineni /** 667eda0d04aSShanker Donthineni * GIC spec says, when ICC_CTLR_EL1.RSS==1 and GICD_TYPER.RSS==0, 668eda0d04aSShanker Donthineni * writing ICC_ASGI1R_EL1 register with RS != 0 is a CONSTRAINED 669eda0d04aSShanker Donthineni * UNPREDICTABLE choice of : 670eda0d04aSShanker Donthineni * - The write is ignored. 671eda0d04aSShanker Donthineni * - The RS field is treated as 0. 672eda0d04aSShanker Donthineni */ 673eda0d04aSShanker Donthineni if (need_rss && (!gic_data.has_rss)) 674eda0d04aSShanker Donthineni pr_crit_once("RSS is required but GICD doesn't support it\n"); 675021f6537SMarc Zyngier } 676021f6537SMarc Zyngier 677f736d65dSMarc Zyngier static bool gicv3_nolpi; 678f736d65dSMarc Zyngier 679f736d65dSMarc Zyngier static int __init gicv3_nolpi_cfg(char *buf) 680f736d65dSMarc Zyngier { 681f736d65dSMarc Zyngier return strtobool(buf, &gicv3_nolpi); 682f736d65dSMarc Zyngier } 683f736d65dSMarc Zyngier early_param("irqchip.gicv3_nolpi", gicv3_nolpi_cfg); 684f736d65dSMarc Zyngier 685da33f31dSMarc Zyngier static int gic_dist_supports_lpis(void) 686da33f31dSMarc Zyngier { 687d38a71c5SMarc Zyngier return (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && 688d38a71c5SMarc Zyngier !!(readl_relaxed(gic_data.dist_base + GICD_TYPER) & GICD_TYPER_LPIS) && 689d38a71c5SMarc Zyngier !gicv3_nolpi); 690da33f31dSMarc Zyngier } 691da33f31dSMarc Zyngier 692021f6537SMarc Zyngier static void gic_cpu_init(void) 693021f6537SMarc Zyngier { 694021f6537SMarc Zyngier void __iomem *rbase; 695021f6537SMarc Zyngier 696021f6537SMarc Zyngier /* Register ourselves with the rest of the world */ 697021f6537SMarc Zyngier if (gic_populate_rdist()) 698021f6537SMarc Zyngier return; 699021f6537SMarc Zyngier 700a2c22510SSudeep Holla gic_enable_redist(true); 701021f6537SMarc Zyngier 702021f6537SMarc Zyngier rbase = gic_data_rdist_sgi_base(); 703021f6537SMarc Zyngier 7047c9b9730SMarc Zyngier /* Configure SGIs/PPIs as non-secure Group-1 */ 7057c9b9730SMarc Zyngier writel_relaxed(~0, rbase + GICR_IGROUPR0); 7067c9b9730SMarc Zyngier 707021f6537SMarc Zyngier gic_cpu_config(rbase, gic_redist_wait_for_rwp); 708021f6537SMarc Zyngier 7093708d52fSSudeep Holla /* initialise system registers */ 7103708d52fSSudeep Holla gic_cpu_sys_reg_init(); 711021f6537SMarc Zyngier } 712021f6537SMarc Zyngier 713021f6537SMarc Zyngier #ifdef CONFIG_SMP 714021f6537SMarc Zyngier 715eda0d04aSShanker Donthineni #define MPIDR_TO_SGI_RS(mpidr) (MPIDR_RS(mpidr) << ICC_SGI1R_RS_SHIFT) 716eda0d04aSShanker Donthineni #define MPIDR_TO_SGI_CLUSTER_ID(mpidr) ((mpidr) & ~0xFUL) 717eda0d04aSShanker Donthineni 7186670a6d8SRichard Cochran static int gic_starting_cpu(unsigned int cpu) 7196670a6d8SRichard Cochran { 7206670a6d8SRichard Cochran gic_cpu_init(); 721d38a71c5SMarc Zyngier 722d38a71c5SMarc Zyngier if (gic_dist_supports_lpis()) 723d38a71c5SMarc Zyngier its_cpu_init(); 724d38a71c5SMarc Zyngier 7256670a6d8SRichard Cochran return 0; 7266670a6d8SRichard Cochran } 727021f6537SMarc Zyngier 728021f6537SMarc Zyngier static u16 gic_compute_target_list(int *base_cpu, const struct cpumask *mask, 729f6c86a41SJean-Philippe Brucker unsigned long cluster_id) 730021f6537SMarc Zyngier { 731727653d6SJames Morse int next_cpu, cpu = *base_cpu; 732f6c86a41SJean-Philippe Brucker unsigned long mpidr = cpu_logical_map(cpu); 733021f6537SMarc Zyngier u16 tlist = 0; 734021f6537SMarc Zyngier 735021f6537SMarc Zyngier while (cpu < nr_cpu_ids) { 736021f6537SMarc Zyngier tlist |= 1 << (mpidr & 0xf); 737021f6537SMarc Zyngier 738727653d6SJames Morse next_cpu = cpumask_next(cpu, mask); 739727653d6SJames Morse if (next_cpu >= nr_cpu_ids) 740021f6537SMarc Zyngier goto out; 741727653d6SJames Morse cpu = next_cpu; 742021f6537SMarc Zyngier 743021f6537SMarc Zyngier mpidr = cpu_logical_map(cpu); 744021f6537SMarc Zyngier 745eda0d04aSShanker Donthineni if (cluster_id != MPIDR_TO_SGI_CLUSTER_ID(mpidr)) { 746021f6537SMarc Zyngier cpu--; 747021f6537SMarc Zyngier goto out; 748021f6537SMarc Zyngier } 749021f6537SMarc Zyngier } 750021f6537SMarc Zyngier out: 751021f6537SMarc Zyngier *base_cpu = cpu; 752021f6537SMarc Zyngier return tlist; 753021f6537SMarc Zyngier } 754021f6537SMarc Zyngier 7557e580278SAndre Przywara #define MPIDR_TO_SGI_AFFINITY(cluster_id, level) \ 7567e580278SAndre Przywara (MPIDR_AFFINITY_LEVEL(cluster_id, level) \ 7577e580278SAndre Przywara << ICC_SGI1R_AFFINITY_## level ##_SHIFT) 7587e580278SAndre Przywara 759021f6537SMarc Zyngier static void gic_send_sgi(u64 cluster_id, u16 tlist, unsigned int irq) 760021f6537SMarc Zyngier { 761021f6537SMarc Zyngier u64 val; 762021f6537SMarc Zyngier 7637e580278SAndre Przywara val = (MPIDR_TO_SGI_AFFINITY(cluster_id, 3) | 7647e580278SAndre Przywara MPIDR_TO_SGI_AFFINITY(cluster_id, 2) | 7657e580278SAndre Przywara irq << ICC_SGI1R_SGI_ID_SHIFT | 7667e580278SAndre Przywara MPIDR_TO_SGI_AFFINITY(cluster_id, 1) | 767eda0d04aSShanker Donthineni MPIDR_TO_SGI_RS(cluster_id) | 7687e580278SAndre Przywara tlist << ICC_SGI1R_TARGET_LIST_SHIFT); 769021f6537SMarc Zyngier 770b6dd4d83SMark Salter pr_devel("CPU%d: ICC_SGI1R_EL1 %llx\n", smp_processor_id(), val); 771021f6537SMarc Zyngier gic_write_sgi1r(val); 772021f6537SMarc Zyngier } 773021f6537SMarc Zyngier 774021f6537SMarc Zyngier static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) 775021f6537SMarc Zyngier { 776021f6537SMarc Zyngier int cpu; 777021f6537SMarc Zyngier 778021f6537SMarc Zyngier if (WARN_ON(irq >= 16)) 779021f6537SMarc Zyngier return; 780021f6537SMarc Zyngier 781021f6537SMarc Zyngier /* 782021f6537SMarc Zyngier * Ensure that stores to Normal memory are visible to the 783021f6537SMarc Zyngier * other CPUs before issuing the IPI. 784021f6537SMarc Zyngier */ 78521ec30c0SShanker Donthineni wmb(); 786021f6537SMarc Zyngier 787f9b531feSRusty Russell for_each_cpu(cpu, mask) { 788eda0d04aSShanker Donthineni u64 cluster_id = MPIDR_TO_SGI_CLUSTER_ID(cpu_logical_map(cpu)); 789021f6537SMarc Zyngier u16 tlist; 790021f6537SMarc Zyngier 791021f6537SMarc Zyngier tlist = gic_compute_target_list(&cpu, mask, cluster_id); 792021f6537SMarc Zyngier gic_send_sgi(cluster_id, tlist, irq); 793021f6537SMarc Zyngier } 794021f6537SMarc Zyngier 795021f6537SMarc Zyngier /* Force the above writes to ICC_SGI1R_EL1 to be executed */ 796021f6537SMarc Zyngier isb(); 797021f6537SMarc Zyngier } 798021f6537SMarc Zyngier 799021f6537SMarc Zyngier static void gic_smp_init(void) 800021f6537SMarc Zyngier { 801021f6537SMarc Zyngier set_smp_cross_call(gic_raise_softirq); 8026896bcd1SThomas Gleixner cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_GIC_STARTING, 80373c1b41eSThomas Gleixner "irqchip/arm/gicv3:starting", 80473c1b41eSThomas Gleixner gic_starting_cpu, NULL); 805021f6537SMarc Zyngier } 806021f6537SMarc Zyngier 807021f6537SMarc Zyngier static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, 808021f6537SMarc Zyngier bool force) 809021f6537SMarc Zyngier { 81065a30f8bSSuzuki K Poulose unsigned int cpu; 811021f6537SMarc Zyngier void __iomem *reg; 812021f6537SMarc Zyngier int enabled; 813021f6537SMarc Zyngier u64 val; 814021f6537SMarc Zyngier 81565a30f8bSSuzuki K Poulose if (force) 81665a30f8bSSuzuki K Poulose cpu = cpumask_first(mask_val); 81765a30f8bSSuzuki K Poulose else 81865a30f8bSSuzuki K Poulose cpu = cpumask_any_and(mask_val, cpu_online_mask); 81965a30f8bSSuzuki K Poulose 820866d7c1bSSuzuki K Poulose if (cpu >= nr_cpu_ids) 821866d7c1bSSuzuki K Poulose return -EINVAL; 822866d7c1bSSuzuki K Poulose 823021f6537SMarc Zyngier if (gic_irq_in_rdist(d)) 824021f6537SMarc Zyngier return -EINVAL; 825021f6537SMarc Zyngier 826021f6537SMarc Zyngier /* If interrupt was enabled, disable it first */ 827021f6537SMarc Zyngier enabled = gic_peek_irq(d, GICD_ISENABLER); 828021f6537SMarc Zyngier if (enabled) 829021f6537SMarc Zyngier gic_mask_irq(d); 830021f6537SMarc Zyngier 831021f6537SMarc Zyngier reg = gic_dist_base(d) + GICD_IROUTER + (gic_irq(d) * 8); 832021f6537SMarc Zyngier val = gic_mpidr_to_affinity(cpu_logical_map(cpu)); 833021f6537SMarc Zyngier 83472c97126SJean-Philippe Brucker gic_write_irouter(val, reg); 835021f6537SMarc Zyngier 836021f6537SMarc Zyngier /* 837021f6537SMarc Zyngier * If the interrupt was enabled, enabled it again. Otherwise, 838021f6537SMarc Zyngier * just wait for the distributor to have digested our changes. 839021f6537SMarc Zyngier */ 840021f6537SMarc Zyngier if (enabled) 841021f6537SMarc Zyngier gic_unmask_irq(d); 842021f6537SMarc Zyngier else 843021f6537SMarc Zyngier gic_dist_wait_for_rwp(); 844021f6537SMarc Zyngier 845956ae91aSMarc Zyngier irq_data_update_effective_affinity(d, cpumask_of(cpu)); 846956ae91aSMarc Zyngier 8470fc6fa29SAntoine Tenart return IRQ_SET_MASK_OK_DONE; 848021f6537SMarc Zyngier } 849021f6537SMarc Zyngier #else 850021f6537SMarc Zyngier #define gic_set_affinity NULL 851021f6537SMarc Zyngier #define gic_smp_init() do { } while(0) 852021f6537SMarc Zyngier #endif 853021f6537SMarc Zyngier 8543708d52fSSudeep Holla #ifdef CONFIG_CPU_PM 855ccd9432aSSudeep Holla /* Check whether it's single security state view */ 856ccd9432aSSudeep Holla static bool gic_dist_security_disabled(void) 857ccd9432aSSudeep Holla { 858ccd9432aSSudeep Holla return readl_relaxed(gic_data.dist_base + GICD_CTLR) & GICD_CTLR_DS; 859ccd9432aSSudeep Holla } 860ccd9432aSSudeep Holla 8613708d52fSSudeep Holla static int gic_cpu_pm_notifier(struct notifier_block *self, 8623708d52fSSudeep Holla unsigned long cmd, void *v) 8633708d52fSSudeep Holla { 8643708d52fSSudeep Holla if (cmd == CPU_PM_EXIT) { 865ccd9432aSSudeep Holla if (gic_dist_security_disabled()) 8663708d52fSSudeep Holla gic_enable_redist(true); 8673708d52fSSudeep Holla gic_cpu_sys_reg_init(); 868ccd9432aSSudeep Holla } else if (cmd == CPU_PM_ENTER && gic_dist_security_disabled()) { 8693708d52fSSudeep Holla gic_write_grpen1(0); 8703708d52fSSudeep Holla gic_enable_redist(false); 8713708d52fSSudeep Holla } 8723708d52fSSudeep Holla return NOTIFY_OK; 8733708d52fSSudeep Holla } 8743708d52fSSudeep Holla 8753708d52fSSudeep Holla static struct notifier_block gic_cpu_pm_notifier_block = { 8763708d52fSSudeep Holla .notifier_call = gic_cpu_pm_notifier, 8773708d52fSSudeep Holla }; 8783708d52fSSudeep Holla 8793708d52fSSudeep Holla static void gic_cpu_pm_init(void) 8803708d52fSSudeep Holla { 8813708d52fSSudeep Holla cpu_pm_register_notifier(&gic_cpu_pm_notifier_block); 8823708d52fSSudeep Holla } 8833708d52fSSudeep Holla 8843708d52fSSudeep Holla #else 8853708d52fSSudeep Holla static inline void gic_cpu_pm_init(void) { } 8863708d52fSSudeep Holla #endif /* CONFIG_CPU_PM */ 8873708d52fSSudeep Holla 888021f6537SMarc Zyngier static struct irq_chip gic_chip = { 889021f6537SMarc Zyngier .name = "GICv3", 890021f6537SMarc Zyngier .irq_mask = gic_mask_irq, 891021f6537SMarc Zyngier .irq_unmask = gic_unmask_irq, 892021f6537SMarc Zyngier .irq_eoi = gic_eoi_irq, 893021f6537SMarc Zyngier .irq_set_type = gic_set_type, 894021f6537SMarc Zyngier .irq_set_affinity = gic_set_affinity, 895b594c6e2SMarc Zyngier .irq_get_irqchip_state = gic_irq_get_irqchip_state, 896b594c6e2SMarc Zyngier .irq_set_irqchip_state = gic_irq_set_irqchip_state, 8974110b5cbSMarc Zyngier .flags = IRQCHIP_SET_TYPE_MASKED | 8984110b5cbSMarc Zyngier IRQCHIP_SKIP_SET_WAKE | 8994110b5cbSMarc Zyngier IRQCHIP_MASK_ON_SUSPEND, 900021f6537SMarc Zyngier }; 901021f6537SMarc Zyngier 9020b6a3da9SMarc Zyngier static struct irq_chip gic_eoimode1_chip = { 9030b6a3da9SMarc Zyngier .name = "GICv3", 9040b6a3da9SMarc Zyngier .irq_mask = gic_eoimode1_mask_irq, 9050b6a3da9SMarc Zyngier .irq_unmask = gic_unmask_irq, 9060b6a3da9SMarc Zyngier .irq_eoi = gic_eoimode1_eoi_irq, 9070b6a3da9SMarc Zyngier .irq_set_type = gic_set_type, 9080b6a3da9SMarc Zyngier .irq_set_affinity = gic_set_affinity, 9090b6a3da9SMarc Zyngier .irq_get_irqchip_state = gic_irq_get_irqchip_state, 9100b6a3da9SMarc Zyngier .irq_set_irqchip_state = gic_irq_set_irqchip_state, 911530bf353SMarc Zyngier .irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity, 9124110b5cbSMarc Zyngier .flags = IRQCHIP_SET_TYPE_MASKED | 9134110b5cbSMarc Zyngier IRQCHIP_SKIP_SET_WAKE | 9144110b5cbSMarc Zyngier IRQCHIP_MASK_ON_SUSPEND, 9150b6a3da9SMarc Zyngier }; 9160b6a3da9SMarc Zyngier 917a4f9edb2SMarc Zyngier #define GIC_ID_NR (1U << GICD_TYPER_ID_BITS(gic_data.rdists.gicd_typer)) 918da33f31dSMarc Zyngier 919021f6537SMarc Zyngier static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq, 920021f6537SMarc Zyngier irq_hw_number_t hw) 921021f6537SMarc Zyngier { 9220b6a3da9SMarc Zyngier struct irq_chip *chip = &gic_chip; 9230b6a3da9SMarc Zyngier 924d01d3274SDavidlohr Bueso if (static_branch_likely(&supports_deactivate_key)) 9250b6a3da9SMarc Zyngier chip = &gic_eoimode1_chip; 9260b6a3da9SMarc Zyngier 927021f6537SMarc Zyngier /* SGIs are private to the core kernel */ 928021f6537SMarc Zyngier if (hw < 16) 929021f6537SMarc Zyngier return -EPERM; 930da33f31dSMarc Zyngier /* Nothing here */ 931da33f31dSMarc Zyngier if (hw >= gic_data.irq_nr && hw < 8192) 932da33f31dSMarc Zyngier return -EPERM; 933da33f31dSMarc Zyngier /* Off limits */ 934da33f31dSMarc Zyngier if (hw >= GIC_ID_NR) 935da33f31dSMarc Zyngier return -EPERM; 936da33f31dSMarc Zyngier 937021f6537SMarc Zyngier /* PPIs */ 938021f6537SMarc Zyngier if (hw < 32) { 939021f6537SMarc Zyngier irq_set_percpu_devid(irq); 9400b6a3da9SMarc Zyngier irq_domain_set_info(d, irq, hw, chip, d->host_data, 941443acc4fSMarc Zyngier handle_percpu_devid_irq, NULL, NULL); 942d17cab44SRob Herring irq_set_status_flags(irq, IRQ_NOAUTOEN); 943021f6537SMarc Zyngier } 944021f6537SMarc Zyngier /* SPIs */ 945021f6537SMarc Zyngier if (hw >= 32 && hw < gic_data.irq_nr) { 9460b6a3da9SMarc Zyngier irq_domain_set_info(d, irq, hw, chip, d->host_data, 947443acc4fSMarc Zyngier handle_fasteoi_irq, NULL, NULL); 948d17cab44SRob Herring irq_set_probe(irq); 949956ae91aSMarc Zyngier irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(irq))); 950021f6537SMarc Zyngier } 951da33f31dSMarc Zyngier /* LPIs */ 952da33f31dSMarc Zyngier if (hw >= 8192 && hw < GIC_ID_NR) { 953da33f31dSMarc Zyngier if (!gic_dist_supports_lpis()) 954da33f31dSMarc Zyngier return -EPERM; 9550b6a3da9SMarc Zyngier irq_domain_set_info(d, irq, hw, chip, d->host_data, 956da33f31dSMarc Zyngier handle_fasteoi_irq, NULL, NULL); 957da33f31dSMarc Zyngier } 958da33f31dSMarc Zyngier 959021f6537SMarc Zyngier return 0; 960021f6537SMarc Zyngier } 961021f6537SMarc Zyngier 96265da7d19SMarc Zyngier #define GIC_IRQ_TYPE_PARTITION (GIC_IRQ_TYPE_LPI + 1) 96365da7d19SMarc Zyngier 964f833f57fSMarc Zyngier static int gic_irq_domain_translate(struct irq_domain *d, 965f833f57fSMarc Zyngier struct irq_fwspec *fwspec, 966f833f57fSMarc Zyngier unsigned long *hwirq, 967f833f57fSMarc Zyngier unsigned int *type) 968021f6537SMarc Zyngier { 969f833f57fSMarc Zyngier if (is_of_node(fwspec->fwnode)) { 970f833f57fSMarc Zyngier if (fwspec->param_count < 3) 971021f6537SMarc Zyngier return -EINVAL; 972021f6537SMarc Zyngier 973db8c70ecSMarc Zyngier switch (fwspec->param[0]) { 974db8c70ecSMarc Zyngier case 0: /* SPI */ 975db8c70ecSMarc Zyngier *hwirq = fwspec->param[1] + 32; 976db8c70ecSMarc Zyngier break; 977db8c70ecSMarc Zyngier case 1: /* PPI */ 97865da7d19SMarc Zyngier case GIC_IRQ_TYPE_PARTITION: 979f833f57fSMarc Zyngier *hwirq = fwspec->param[1] + 16; 980db8c70ecSMarc Zyngier break; 981db8c70ecSMarc Zyngier case GIC_IRQ_TYPE_LPI: /* LPI */ 982db8c70ecSMarc Zyngier *hwirq = fwspec->param[1]; 983db8c70ecSMarc Zyngier break; 984db8c70ecSMarc Zyngier default: 985db8c70ecSMarc Zyngier return -EINVAL; 986db8c70ecSMarc Zyngier } 987f833f57fSMarc Zyngier 988f833f57fSMarc Zyngier *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; 9896ef6386eSMarc Zyngier 99065da7d19SMarc Zyngier /* 99165da7d19SMarc Zyngier * Make it clear that broken DTs are... broken. 99265da7d19SMarc Zyngier * Partitionned PPIs are an unfortunate exception. 99365da7d19SMarc Zyngier */ 99465da7d19SMarc Zyngier WARN_ON(*type == IRQ_TYPE_NONE && 99565da7d19SMarc Zyngier fwspec->param[0] != GIC_IRQ_TYPE_PARTITION); 996f833f57fSMarc Zyngier return 0; 997021f6537SMarc Zyngier } 998021f6537SMarc Zyngier 999ffa7d616STomasz Nowicki if (is_fwnode_irqchip(fwspec->fwnode)) { 1000ffa7d616STomasz Nowicki if(fwspec->param_count != 2) 1001ffa7d616STomasz Nowicki return -EINVAL; 1002ffa7d616STomasz Nowicki 1003ffa7d616STomasz Nowicki *hwirq = fwspec->param[0]; 1004ffa7d616STomasz Nowicki *type = fwspec->param[1]; 10056ef6386eSMarc Zyngier 10066ef6386eSMarc Zyngier WARN_ON(*type == IRQ_TYPE_NONE); 1007ffa7d616STomasz Nowicki return 0; 1008ffa7d616STomasz Nowicki } 1009ffa7d616STomasz Nowicki 1010f833f57fSMarc Zyngier return -EINVAL; 1011021f6537SMarc Zyngier } 1012021f6537SMarc Zyngier 1013443acc4fSMarc Zyngier static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, 1014443acc4fSMarc Zyngier unsigned int nr_irqs, void *arg) 1015443acc4fSMarc Zyngier { 1016443acc4fSMarc Zyngier int i, ret; 1017443acc4fSMarc Zyngier irq_hw_number_t hwirq; 1018443acc4fSMarc Zyngier unsigned int type = IRQ_TYPE_NONE; 1019f833f57fSMarc Zyngier struct irq_fwspec *fwspec = arg; 1020443acc4fSMarc Zyngier 1021f833f57fSMarc Zyngier ret = gic_irq_domain_translate(domain, fwspec, &hwirq, &type); 1022443acc4fSMarc Zyngier if (ret) 1023443acc4fSMarc Zyngier return ret; 1024443acc4fSMarc Zyngier 102563c16c6eSSuzuki K Poulose for (i = 0; i < nr_irqs; i++) { 102663c16c6eSSuzuki K Poulose ret = gic_irq_domain_map(domain, virq + i, hwirq + i); 102763c16c6eSSuzuki K Poulose if (ret) 102863c16c6eSSuzuki K Poulose return ret; 102963c16c6eSSuzuki K Poulose } 1030443acc4fSMarc Zyngier 1031443acc4fSMarc Zyngier return 0; 1032443acc4fSMarc Zyngier } 1033443acc4fSMarc Zyngier 1034443acc4fSMarc Zyngier static void gic_irq_domain_free(struct irq_domain *domain, unsigned int virq, 1035443acc4fSMarc Zyngier unsigned int nr_irqs) 1036443acc4fSMarc Zyngier { 1037443acc4fSMarc Zyngier int i; 1038443acc4fSMarc Zyngier 1039443acc4fSMarc Zyngier for (i = 0; i < nr_irqs; i++) { 1040443acc4fSMarc Zyngier struct irq_data *d = irq_domain_get_irq_data(domain, virq + i); 1041443acc4fSMarc Zyngier irq_set_handler(virq + i, NULL); 1042443acc4fSMarc Zyngier irq_domain_reset_irq_data(d); 1043443acc4fSMarc Zyngier } 1044443acc4fSMarc Zyngier } 1045443acc4fSMarc Zyngier 1046e3825ba1SMarc Zyngier static int gic_irq_domain_select(struct irq_domain *d, 1047e3825ba1SMarc Zyngier struct irq_fwspec *fwspec, 1048e3825ba1SMarc Zyngier enum irq_domain_bus_token bus_token) 1049e3825ba1SMarc Zyngier { 1050e3825ba1SMarc Zyngier /* Not for us */ 1051e3825ba1SMarc Zyngier if (fwspec->fwnode != d->fwnode) 1052e3825ba1SMarc Zyngier return 0; 1053e3825ba1SMarc Zyngier 1054e3825ba1SMarc Zyngier /* If this is not DT, then we have a single domain */ 1055e3825ba1SMarc Zyngier if (!is_of_node(fwspec->fwnode)) 1056e3825ba1SMarc Zyngier return 1; 1057e3825ba1SMarc Zyngier 1058e3825ba1SMarc Zyngier /* 1059e3825ba1SMarc Zyngier * If this is a PPI and we have a 4th (non-null) parameter, 1060e3825ba1SMarc Zyngier * then we need to match the partition domain. 1061e3825ba1SMarc Zyngier */ 1062e3825ba1SMarc Zyngier if (fwspec->param_count >= 4 && 1063e3825ba1SMarc Zyngier fwspec->param[0] == 1 && fwspec->param[3] != 0) 1064e3825ba1SMarc Zyngier return d == partition_get_domain(gic_data.ppi_descs[fwspec->param[1]]); 1065e3825ba1SMarc Zyngier 1066e3825ba1SMarc Zyngier return d == gic_data.domain; 1067e3825ba1SMarc Zyngier } 1068e3825ba1SMarc Zyngier 1069021f6537SMarc Zyngier static const struct irq_domain_ops gic_irq_domain_ops = { 1070f833f57fSMarc Zyngier .translate = gic_irq_domain_translate, 1071443acc4fSMarc Zyngier .alloc = gic_irq_domain_alloc, 1072443acc4fSMarc Zyngier .free = gic_irq_domain_free, 1073e3825ba1SMarc Zyngier .select = gic_irq_domain_select, 1074e3825ba1SMarc Zyngier }; 1075e3825ba1SMarc Zyngier 1076e3825ba1SMarc Zyngier static int partition_domain_translate(struct irq_domain *d, 1077e3825ba1SMarc Zyngier struct irq_fwspec *fwspec, 1078e3825ba1SMarc Zyngier unsigned long *hwirq, 1079e3825ba1SMarc Zyngier unsigned int *type) 1080e3825ba1SMarc Zyngier { 1081e3825ba1SMarc Zyngier struct device_node *np; 1082e3825ba1SMarc Zyngier int ret; 1083e3825ba1SMarc Zyngier 1084e3825ba1SMarc Zyngier np = of_find_node_by_phandle(fwspec->param[3]); 1085e3825ba1SMarc Zyngier if (WARN_ON(!np)) 1086e3825ba1SMarc Zyngier return -EINVAL; 1087e3825ba1SMarc Zyngier 1088e3825ba1SMarc Zyngier ret = partition_translate_id(gic_data.ppi_descs[fwspec->param[1]], 1089e3825ba1SMarc Zyngier of_node_to_fwnode(np)); 1090e3825ba1SMarc Zyngier if (ret < 0) 1091e3825ba1SMarc Zyngier return ret; 1092e3825ba1SMarc Zyngier 1093e3825ba1SMarc Zyngier *hwirq = ret; 1094e3825ba1SMarc Zyngier *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; 1095e3825ba1SMarc Zyngier 1096e3825ba1SMarc Zyngier return 0; 1097e3825ba1SMarc Zyngier } 1098e3825ba1SMarc Zyngier 1099e3825ba1SMarc Zyngier static const struct irq_domain_ops partition_domain_ops = { 1100e3825ba1SMarc Zyngier .translate = partition_domain_translate, 1101e3825ba1SMarc Zyngier .select = gic_irq_domain_select, 1102021f6537SMarc Zyngier }; 1103021f6537SMarc Zyngier 11049c8114c2SSrinivas Kandagatla static bool gic_enable_quirk_msm8996(void *data) 11059c8114c2SSrinivas Kandagatla { 11069c8114c2SSrinivas Kandagatla struct gic_chip_data *d = data; 11079c8114c2SSrinivas Kandagatla 11089c8114c2SSrinivas Kandagatla d->flags |= FLAGS_WORKAROUND_GICR_WAKER_MSM8996; 11099c8114c2SSrinivas Kandagatla 11109c8114c2SSrinivas Kandagatla return true; 11119c8114c2SSrinivas Kandagatla } 11129c8114c2SSrinivas Kandagatla 1113db57d746STomasz Nowicki static int __init gic_init_bases(void __iomem *dist_base, 1114db57d746STomasz Nowicki struct redist_region *rdist_regs, 1115db57d746STomasz Nowicki u32 nr_redist_regions, 1116db57d746STomasz Nowicki u64 redist_stride, 1117db57d746STomasz Nowicki struct fwnode_handle *handle) 1118db57d746STomasz Nowicki { 1119db57d746STomasz Nowicki u32 typer; 1120db57d746STomasz Nowicki int gic_irqs; 1121db57d746STomasz Nowicki int err; 1122db57d746STomasz Nowicki 1123db57d746STomasz Nowicki if (!is_hyp_mode_available()) 1124d01d3274SDavidlohr Bueso static_branch_disable(&supports_deactivate_key); 1125db57d746STomasz Nowicki 1126d01d3274SDavidlohr Bueso if (static_branch_likely(&supports_deactivate_key)) 1127db57d746STomasz Nowicki pr_info("GIC: Using split EOI/Deactivate mode\n"); 1128db57d746STomasz Nowicki 1129e3825ba1SMarc Zyngier gic_data.fwnode = handle; 1130db57d746STomasz Nowicki gic_data.dist_base = dist_base; 1131db57d746STomasz Nowicki gic_data.redist_regions = rdist_regs; 1132db57d746STomasz Nowicki gic_data.nr_redist_regions = nr_redist_regions; 1133db57d746STomasz Nowicki gic_data.redist_stride = redist_stride; 1134db57d746STomasz Nowicki 1135db57d746STomasz Nowicki /* 1136db57d746STomasz Nowicki * Find out how many interrupts are supported. 1137db57d746STomasz Nowicki * The GIC only supports up to 1020 interrupt sources (SGI+PPI+SPI) 1138db57d746STomasz Nowicki */ 1139db57d746STomasz Nowicki typer = readl_relaxed(gic_data.dist_base + GICD_TYPER); 1140a4f9edb2SMarc Zyngier gic_data.rdists.gicd_typer = typer; 1141db57d746STomasz Nowicki gic_irqs = GICD_TYPER_IRQS(typer); 1142db57d746STomasz Nowicki if (gic_irqs > 1020) 1143db57d746STomasz Nowicki gic_irqs = 1020; 1144db57d746STomasz Nowicki gic_data.irq_nr = gic_irqs; 1145db57d746STomasz Nowicki 1146db57d746STomasz Nowicki gic_data.domain = irq_domain_create_tree(handle, &gic_irq_domain_ops, 1147db57d746STomasz Nowicki &gic_data); 1148b2425b51SMarc Zyngier irq_domain_update_bus_token(gic_data.domain, DOMAIN_BUS_WIRED); 1149db57d746STomasz Nowicki gic_data.rdists.rdist = alloc_percpu(typeof(*gic_data.rdists.rdist)); 11500edc23eaSMarc Zyngier gic_data.rdists.has_vlpis = true; 11510edc23eaSMarc Zyngier gic_data.rdists.has_direct_lpi = true; 1152db57d746STomasz Nowicki 1153db57d746STomasz Nowicki if (WARN_ON(!gic_data.domain) || WARN_ON(!gic_data.rdists.rdist)) { 1154db57d746STomasz Nowicki err = -ENOMEM; 1155db57d746STomasz Nowicki goto out_free; 1156db57d746STomasz Nowicki } 1157db57d746STomasz Nowicki 1158eda0d04aSShanker Donthineni gic_data.has_rss = !!(typer & GICD_TYPER_RSS); 1159eda0d04aSShanker Donthineni pr_info("Distributor has %sRange Selector support\n", 1160eda0d04aSShanker Donthineni gic_data.has_rss ? "" : "no "); 1161eda0d04aSShanker Donthineni 116250528752SMarc Zyngier if (typer & GICD_TYPER_MBIS) { 116350528752SMarc Zyngier err = mbi_init(handle, gic_data.domain); 116450528752SMarc Zyngier if (err) 116550528752SMarc Zyngier pr_err("Failed to initialize MBIs\n"); 116650528752SMarc Zyngier } 116750528752SMarc Zyngier 1168db57d746STomasz Nowicki set_handle_irq(gic_handle_irq); 1169db57d746STomasz Nowicki 11700edc23eaSMarc Zyngier gic_update_vlpi_properties(); 11710edc23eaSMarc Zyngier 1172db57d746STomasz Nowicki gic_smp_init(); 1173db57d746STomasz Nowicki gic_dist_init(); 1174db57d746STomasz Nowicki gic_cpu_init(); 1175db57d746STomasz Nowicki gic_cpu_pm_init(); 1176db57d746STomasz Nowicki 1177d38a71c5SMarc Zyngier if (gic_dist_supports_lpis()) { 1178d38a71c5SMarc Zyngier its_init(handle, &gic_data.rdists, gic_data.domain); 1179d38a71c5SMarc Zyngier its_cpu_init(); 1180d38a71c5SMarc Zyngier } 1181d38a71c5SMarc Zyngier 1182db57d746STomasz Nowicki return 0; 1183db57d746STomasz Nowicki 1184db57d746STomasz Nowicki out_free: 1185db57d746STomasz Nowicki if (gic_data.domain) 1186db57d746STomasz Nowicki irq_domain_remove(gic_data.domain); 1187db57d746STomasz Nowicki free_percpu(gic_data.rdists.rdist); 1188db57d746STomasz Nowicki return err; 1189db57d746STomasz Nowicki } 1190db57d746STomasz Nowicki 1191db57d746STomasz Nowicki static int __init gic_validate_dist_version(void __iomem *dist_base) 1192db57d746STomasz Nowicki { 1193db57d746STomasz Nowicki u32 reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK; 1194db57d746STomasz Nowicki 1195db57d746STomasz Nowicki if (reg != GIC_PIDR2_ARCH_GICv3 && reg != GIC_PIDR2_ARCH_GICv4) 1196db57d746STomasz Nowicki return -ENODEV; 1197db57d746STomasz Nowicki 1198db57d746STomasz Nowicki return 0; 1199db57d746STomasz Nowicki } 1200db57d746STomasz Nowicki 1201e3825ba1SMarc Zyngier /* Create all possible partitions at boot time */ 12027beaa24bSLinus Torvalds static void __init gic_populate_ppi_partitions(struct device_node *gic_node) 1203e3825ba1SMarc Zyngier { 1204e3825ba1SMarc Zyngier struct device_node *parts_node, *child_part; 1205e3825ba1SMarc Zyngier int part_idx = 0, i; 1206e3825ba1SMarc Zyngier int nr_parts; 1207e3825ba1SMarc Zyngier struct partition_affinity *parts; 1208e3825ba1SMarc Zyngier 120900ee9a1cSJohan Hovold parts_node = of_get_child_by_name(gic_node, "ppi-partitions"); 1210e3825ba1SMarc Zyngier if (!parts_node) 1211e3825ba1SMarc Zyngier return; 1212e3825ba1SMarc Zyngier 1213e3825ba1SMarc Zyngier nr_parts = of_get_child_count(parts_node); 1214e3825ba1SMarc Zyngier 1215e3825ba1SMarc Zyngier if (!nr_parts) 121600ee9a1cSJohan Hovold goto out_put_node; 1217e3825ba1SMarc Zyngier 12186396bb22SKees Cook parts = kcalloc(nr_parts, sizeof(*parts), GFP_KERNEL); 1219e3825ba1SMarc Zyngier if (WARN_ON(!parts)) 122000ee9a1cSJohan Hovold goto out_put_node; 1221e3825ba1SMarc Zyngier 1222e3825ba1SMarc Zyngier for_each_child_of_node(parts_node, child_part) { 1223e3825ba1SMarc Zyngier struct partition_affinity *part; 1224e3825ba1SMarc Zyngier int n; 1225e3825ba1SMarc Zyngier 1226e3825ba1SMarc Zyngier part = &parts[part_idx]; 1227e3825ba1SMarc Zyngier 1228e3825ba1SMarc Zyngier part->partition_id = of_node_to_fwnode(child_part); 1229e3825ba1SMarc Zyngier 12302ef790dcSRob Herring pr_info("GIC: PPI partition %pOFn[%d] { ", 12312ef790dcSRob Herring child_part, part_idx); 1232e3825ba1SMarc Zyngier 1233e3825ba1SMarc Zyngier n = of_property_count_elems_of_size(child_part, "affinity", 1234e3825ba1SMarc Zyngier sizeof(u32)); 1235e3825ba1SMarc Zyngier WARN_ON(n <= 0); 1236e3825ba1SMarc Zyngier 1237e3825ba1SMarc Zyngier for (i = 0; i < n; i++) { 1238e3825ba1SMarc Zyngier int err, cpu; 1239e3825ba1SMarc Zyngier u32 cpu_phandle; 1240e3825ba1SMarc Zyngier struct device_node *cpu_node; 1241e3825ba1SMarc Zyngier 1242e3825ba1SMarc Zyngier err = of_property_read_u32_index(child_part, "affinity", 1243e3825ba1SMarc Zyngier i, &cpu_phandle); 1244e3825ba1SMarc Zyngier if (WARN_ON(err)) 1245e3825ba1SMarc Zyngier continue; 1246e3825ba1SMarc Zyngier 1247e3825ba1SMarc Zyngier cpu_node = of_find_node_by_phandle(cpu_phandle); 1248e3825ba1SMarc Zyngier if (WARN_ON(!cpu_node)) 1249e3825ba1SMarc Zyngier continue; 1250e3825ba1SMarc Zyngier 1251c08ec7daSSuzuki K Poulose cpu = of_cpu_node_to_id(cpu_node); 1252c08ec7daSSuzuki K Poulose if (WARN_ON(cpu < 0)) 1253e3825ba1SMarc Zyngier continue; 1254e3825ba1SMarc Zyngier 1255e81f54c6SRob Herring pr_cont("%pOF[%d] ", cpu_node, cpu); 1256e3825ba1SMarc Zyngier 1257e3825ba1SMarc Zyngier cpumask_set_cpu(cpu, &part->mask); 1258e3825ba1SMarc Zyngier } 1259e3825ba1SMarc Zyngier 1260e3825ba1SMarc Zyngier pr_cont("}\n"); 1261e3825ba1SMarc Zyngier part_idx++; 1262e3825ba1SMarc Zyngier } 1263e3825ba1SMarc Zyngier 1264e3825ba1SMarc Zyngier for (i = 0; i < 16; i++) { 1265e3825ba1SMarc Zyngier unsigned int irq; 1266e3825ba1SMarc Zyngier struct partition_desc *desc; 1267e3825ba1SMarc Zyngier struct irq_fwspec ppi_fwspec = { 1268e3825ba1SMarc Zyngier .fwnode = gic_data.fwnode, 1269e3825ba1SMarc Zyngier .param_count = 3, 1270e3825ba1SMarc Zyngier .param = { 127165da7d19SMarc Zyngier [0] = GIC_IRQ_TYPE_PARTITION, 1272e3825ba1SMarc Zyngier [1] = i, 1273e3825ba1SMarc Zyngier [2] = IRQ_TYPE_NONE, 1274e3825ba1SMarc Zyngier }, 1275e3825ba1SMarc Zyngier }; 1276e3825ba1SMarc Zyngier 1277e3825ba1SMarc Zyngier irq = irq_create_fwspec_mapping(&ppi_fwspec); 1278e3825ba1SMarc Zyngier if (WARN_ON(!irq)) 1279e3825ba1SMarc Zyngier continue; 1280e3825ba1SMarc Zyngier desc = partition_create_desc(gic_data.fwnode, parts, nr_parts, 1281e3825ba1SMarc Zyngier irq, &partition_domain_ops); 1282e3825ba1SMarc Zyngier if (WARN_ON(!desc)) 1283e3825ba1SMarc Zyngier continue; 1284e3825ba1SMarc Zyngier 1285e3825ba1SMarc Zyngier gic_data.ppi_descs[i] = desc; 1286e3825ba1SMarc Zyngier } 128700ee9a1cSJohan Hovold 128800ee9a1cSJohan Hovold out_put_node: 128900ee9a1cSJohan Hovold of_node_put(parts_node); 1290e3825ba1SMarc Zyngier } 1291e3825ba1SMarc Zyngier 12921839e576SJulien Grall static void __init gic_of_setup_kvm_info(struct device_node *node) 12931839e576SJulien Grall { 12941839e576SJulien Grall int ret; 12951839e576SJulien Grall struct resource r; 12961839e576SJulien Grall u32 gicv_idx; 12971839e576SJulien Grall 12981839e576SJulien Grall gic_v3_kvm_info.type = GIC_V3; 12991839e576SJulien Grall 13001839e576SJulien Grall gic_v3_kvm_info.maint_irq = irq_of_parse_and_map(node, 0); 13011839e576SJulien Grall if (!gic_v3_kvm_info.maint_irq) 13021839e576SJulien Grall return; 13031839e576SJulien Grall 13041839e576SJulien Grall if (of_property_read_u32(node, "#redistributor-regions", 13051839e576SJulien Grall &gicv_idx)) 13061839e576SJulien Grall gicv_idx = 1; 13071839e576SJulien Grall 13081839e576SJulien Grall gicv_idx += 3; /* Also skip GICD, GICC, GICH */ 13091839e576SJulien Grall ret = of_address_to_resource(node, gicv_idx, &r); 13101839e576SJulien Grall if (!ret) 13111839e576SJulien Grall gic_v3_kvm_info.vcpu = r; 13121839e576SJulien Grall 13134bdf5025SMarc Zyngier gic_v3_kvm_info.has_v4 = gic_data.rdists.has_vlpis; 13141839e576SJulien Grall gic_set_kvm_info(&gic_v3_kvm_info); 13151839e576SJulien Grall } 13161839e576SJulien Grall 1317f70fdb42SSrinivas Kandagatla static const struct gic_quirk gic_quirks[] = { 1318f70fdb42SSrinivas Kandagatla { 13199c8114c2SSrinivas Kandagatla .desc = "GICv3: Qualcomm MSM8996 broken firmware", 13209c8114c2SSrinivas Kandagatla .compatible = "qcom,msm8996-gic-v3", 13219c8114c2SSrinivas Kandagatla .init = gic_enable_quirk_msm8996, 13229c8114c2SSrinivas Kandagatla }, 13239c8114c2SSrinivas Kandagatla { 1324f70fdb42SSrinivas Kandagatla } 1325f70fdb42SSrinivas Kandagatla }; 1326f70fdb42SSrinivas Kandagatla 1327021f6537SMarc Zyngier static int __init gic_of_init(struct device_node *node, struct device_node *parent) 1328021f6537SMarc Zyngier { 1329021f6537SMarc Zyngier void __iomem *dist_base; 1330f5c1434cSMarc Zyngier struct redist_region *rdist_regs; 1331021f6537SMarc Zyngier u64 redist_stride; 1332f5c1434cSMarc Zyngier u32 nr_redist_regions; 1333db57d746STomasz Nowicki int err, i; 1334021f6537SMarc Zyngier 1335021f6537SMarc Zyngier dist_base = of_iomap(node, 0); 1336021f6537SMarc Zyngier if (!dist_base) { 1337e81f54c6SRob Herring pr_err("%pOF: unable to map gic dist registers\n", node); 1338021f6537SMarc Zyngier return -ENXIO; 1339021f6537SMarc Zyngier } 1340021f6537SMarc Zyngier 1341db57d746STomasz Nowicki err = gic_validate_dist_version(dist_base); 1342db57d746STomasz Nowicki if (err) { 1343e81f54c6SRob Herring pr_err("%pOF: no distributor detected, giving up\n", node); 1344021f6537SMarc Zyngier goto out_unmap_dist; 1345021f6537SMarc Zyngier } 1346021f6537SMarc Zyngier 1347f5c1434cSMarc Zyngier if (of_property_read_u32(node, "#redistributor-regions", &nr_redist_regions)) 1348f5c1434cSMarc Zyngier nr_redist_regions = 1; 1349021f6537SMarc Zyngier 13506396bb22SKees Cook rdist_regs = kcalloc(nr_redist_regions, sizeof(*rdist_regs), 13516396bb22SKees Cook GFP_KERNEL); 1352f5c1434cSMarc Zyngier if (!rdist_regs) { 1353021f6537SMarc Zyngier err = -ENOMEM; 1354021f6537SMarc Zyngier goto out_unmap_dist; 1355021f6537SMarc Zyngier } 1356021f6537SMarc Zyngier 1357f5c1434cSMarc Zyngier for (i = 0; i < nr_redist_regions; i++) { 1358f5c1434cSMarc Zyngier struct resource res; 1359f5c1434cSMarc Zyngier int ret; 1360f5c1434cSMarc Zyngier 1361f5c1434cSMarc Zyngier ret = of_address_to_resource(node, 1 + i, &res); 1362f5c1434cSMarc Zyngier rdist_regs[i].redist_base = of_iomap(node, 1 + i); 1363f5c1434cSMarc Zyngier if (ret || !rdist_regs[i].redist_base) { 1364e81f54c6SRob Herring pr_err("%pOF: couldn't map region %d\n", node, i); 1365021f6537SMarc Zyngier err = -ENODEV; 1366021f6537SMarc Zyngier goto out_unmap_rdist; 1367021f6537SMarc Zyngier } 1368f5c1434cSMarc Zyngier rdist_regs[i].phys_base = res.start; 1369021f6537SMarc Zyngier } 1370021f6537SMarc Zyngier 1371021f6537SMarc Zyngier if (of_property_read_u64(node, "redistributor-stride", &redist_stride)) 1372021f6537SMarc Zyngier redist_stride = 0; 1373021f6537SMarc Zyngier 1374f70fdb42SSrinivas Kandagatla gic_enable_of_quirks(node, gic_quirks, &gic_data); 1375f70fdb42SSrinivas Kandagatla 1376db57d746STomasz Nowicki err = gic_init_bases(dist_base, rdist_regs, nr_redist_regions, 1377db57d746STomasz Nowicki redist_stride, &node->fwnode); 1378e3825ba1SMarc Zyngier if (err) 1379e3825ba1SMarc Zyngier goto out_unmap_rdist; 1380e3825ba1SMarc Zyngier 1381e3825ba1SMarc Zyngier gic_populate_ppi_partitions(node); 1382d33a3c8cSChristoffer Dall 1383d01d3274SDavidlohr Bueso if (static_branch_likely(&supports_deactivate_key)) 13841839e576SJulien Grall gic_of_setup_kvm_info(node); 1385021f6537SMarc Zyngier return 0; 1386021f6537SMarc Zyngier 1387021f6537SMarc Zyngier out_unmap_rdist: 1388f5c1434cSMarc Zyngier for (i = 0; i < nr_redist_regions; i++) 1389f5c1434cSMarc Zyngier if (rdist_regs[i].redist_base) 1390f5c1434cSMarc Zyngier iounmap(rdist_regs[i].redist_base); 1391f5c1434cSMarc Zyngier kfree(rdist_regs); 1392021f6537SMarc Zyngier out_unmap_dist: 1393021f6537SMarc Zyngier iounmap(dist_base); 1394021f6537SMarc Zyngier return err; 1395021f6537SMarc Zyngier } 1396021f6537SMarc Zyngier 1397021f6537SMarc Zyngier IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init); 1398ffa7d616STomasz Nowicki 1399ffa7d616STomasz Nowicki #ifdef CONFIG_ACPI 1400611f039fSJulien Grall static struct 1401611f039fSJulien Grall { 1402611f039fSJulien Grall void __iomem *dist_base; 1403611f039fSJulien Grall struct redist_region *redist_regs; 1404611f039fSJulien Grall u32 nr_redist_regions; 1405611f039fSJulien Grall bool single_redist; 14061839e576SJulien Grall u32 maint_irq; 14071839e576SJulien Grall int maint_irq_mode; 14081839e576SJulien Grall phys_addr_t vcpu_base; 1409611f039fSJulien Grall } acpi_data __initdata; 1410b70fb7afSTomasz Nowicki 1411b70fb7afSTomasz Nowicki static void __init 1412b70fb7afSTomasz Nowicki gic_acpi_register_redist(phys_addr_t phys_base, void __iomem *redist_base) 1413b70fb7afSTomasz Nowicki { 1414b70fb7afSTomasz Nowicki static int count = 0; 1415b70fb7afSTomasz Nowicki 1416611f039fSJulien Grall acpi_data.redist_regs[count].phys_base = phys_base; 1417611f039fSJulien Grall acpi_data.redist_regs[count].redist_base = redist_base; 1418611f039fSJulien Grall acpi_data.redist_regs[count].single_redist = acpi_data.single_redist; 1419b70fb7afSTomasz Nowicki count++; 1420b70fb7afSTomasz Nowicki } 1421ffa7d616STomasz Nowicki 1422ffa7d616STomasz Nowicki static int __init 1423ffa7d616STomasz Nowicki gic_acpi_parse_madt_redist(struct acpi_subtable_header *header, 1424ffa7d616STomasz Nowicki const unsigned long end) 1425ffa7d616STomasz Nowicki { 1426ffa7d616STomasz Nowicki struct acpi_madt_generic_redistributor *redist = 1427ffa7d616STomasz Nowicki (struct acpi_madt_generic_redistributor *)header; 1428ffa7d616STomasz Nowicki void __iomem *redist_base; 1429ffa7d616STomasz Nowicki 1430ffa7d616STomasz Nowicki redist_base = ioremap(redist->base_address, redist->length); 1431ffa7d616STomasz Nowicki if (!redist_base) { 1432ffa7d616STomasz Nowicki pr_err("Couldn't map GICR region @%llx\n", redist->base_address); 1433ffa7d616STomasz Nowicki return -ENOMEM; 1434ffa7d616STomasz Nowicki } 1435ffa7d616STomasz Nowicki 1436b70fb7afSTomasz Nowicki gic_acpi_register_redist(redist->base_address, redist_base); 1437ffa7d616STomasz Nowicki return 0; 1438ffa7d616STomasz Nowicki } 1439ffa7d616STomasz Nowicki 1440b70fb7afSTomasz Nowicki static int __init 1441b70fb7afSTomasz Nowicki gic_acpi_parse_madt_gicc(struct acpi_subtable_header *header, 1442b70fb7afSTomasz Nowicki const unsigned long end) 1443b70fb7afSTomasz Nowicki { 1444b70fb7afSTomasz Nowicki struct acpi_madt_generic_interrupt *gicc = 1445b70fb7afSTomasz Nowicki (struct acpi_madt_generic_interrupt *)header; 1446611f039fSJulien Grall u32 reg = readl_relaxed(acpi_data.dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK; 1447b70fb7afSTomasz Nowicki u32 size = reg == GIC_PIDR2_ARCH_GICv4 ? SZ_64K * 4 : SZ_64K * 2; 1448b70fb7afSTomasz Nowicki void __iomem *redist_base; 1449b70fb7afSTomasz Nowicki 1450ebe2f871SShanker Donthineni /* GICC entry which has !ACPI_MADT_ENABLED is not unusable so skip */ 1451ebe2f871SShanker Donthineni if (!(gicc->flags & ACPI_MADT_ENABLED)) 1452ebe2f871SShanker Donthineni return 0; 1453ebe2f871SShanker Donthineni 1454b70fb7afSTomasz Nowicki redist_base = ioremap(gicc->gicr_base_address, size); 1455b70fb7afSTomasz Nowicki if (!redist_base) 1456b70fb7afSTomasz Nowicki return -ENOMEM; 1457b70fb7afSTomasz Nowicki 1458b70fb7afSTomasz Nowicki gic_acpi_register_redist(gicc->gicr_base_address, redist_base); 1459b70fb7afSTomasz Nowicki return 0; 1460b70fb7afSTomasz Nowicki } 1461b70fb7afSTomasz Nowicki 1462b70fb7afSTomasz Nowicki static int __init gic_acpi_collect_gicr_base(void) 1463b70fb7afSTomasz Nowicki { 1464b70fb7afSTomasz Nowicki acpi_tbl_entry_handler redist_parser; 1465b70fb7afSTomasz Nowicki enum acpi_madt_type type; 1466b70fb7afSTomasz Nowicki 1467611f039fSJulien Grall if (acpi_data.single_redist) { 1468b70fb7afSTomasz Nowicki type = ACPI_MADT_TYPE_GENERIC_INTERRUPT; 1469b70fb7afSTomasz Nowicki redist_parser = gic_acpi_parse_madt_gicc; 1470b70fb7afSTomasz Nowicki } else { 1471b70fb7afSTomasz Nowicki type = ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR; 1472b70fb7afSTomasz Nowicki redist_parser = gic_acpi_parse_madt_redist; 1473b70fb7afSTomasz Nowicki } 1474b70fb7afSTomasz Nowicki 1475b70fb7afSTomasz Nowicki /* Collect redistributor base addresses in GICR entries */ 1476b70fb7afSTomasz Nowicki if (acpi_table_parse_madt(type, redist_parser, 0) > 0) 1477b70fb7afSTomasz Nowicki return 0; 1478b70fb7afSTomasz Nowicki 1479b70fb7afSTomasz Nowicki pr_info("No valid GICR entries exist\n"); 1480b70fb7afSTomasz Nowicki return -ENODEV; 1481b70fb7afSTomasz Nowicki } 1482b70fb7afSTomasz Nowicki 1483ffa7d616STomasz Nowicki static int __init gic_acpi_match_gicr(struct acpi_subtable_header *header, 1484ffa7d616STomasz Nowicki const unsigned long end) 1485ffa7d616STomasz Nowicki { 1486ffa7d616STomasz Nowicki /* Subtable presence means that redist exists, that's it */ 1487ffa7d616STomasz Nowicki return 0; 1488ffa7d616STomasz Nowicki } 1489ffa7d616STomasz Nowicki 1490b70fb7afSTomasz Nowicki static int __init gic_acpi_match_gicc(struct acpi_subtable_header *header, 1491b70fb7afSTomasz Nowicki const unsigned long end) 1492b70fb7afSTomasz Nowicki { 1493b70fb7afSTomasz Nowicki struct acpi_madt_generic_interrupt *gicc = 1494b70fb7afSTomasz Nowicki (struct acpi_madt_generic_interrupt *)header; 1495b70fb7afSTomasz Nowicki 1496b70fb7afSTomasz Nowicki /* 1497b70fb7afSTomasz Nowicki * If GICC is enabled and has valid gicr base address, then it means 1498b70fb7afSTomasz Nowicki * GICR base is presented via GICC 1499b70fb7afSTomasz Nowicki */ 1500b70fb7afSTomasz Nowicki if ((gicc->flags & ACPI_MADT_ENABLED) && gicc->gicr_base_address) 1501b70fb7afSTomasz Nowicki return 0; 1502b70fb7afSTomasz Nowicki 1503ebe2f871SShanker Donthineni /* 1504ebe2f871SShanker Donthineni * It's perfectly valid firmware can pass disabled GICC entry, driver 1505ebe2f871SShanker Donthineni * should not treat as errors, skip the entry instead of probe fail. 1506ebe2f871SShanker Donthineni */ 1507ebe2f871SShanker Donthineni if (!(gicc->flags & ACPI_MADT_ENABLED)) 1508ebe2f871SShanker Donthineni return 0; 1509ebe2f871SShanker Donthineni 1510b70fb7afSTomasz Nowicki return -ENODEV; 1511b70fb7afSTomasz Nowicki } 1512b70fb7afSTomasz Nowicki 1513b70fb7afSTomasz Nowicki static int __init gic_acpi_count_gicr_regions(void) 1514b70fb7afSTomasz Nowicki { 1515b70fb7afSTomasz Nowicki int count; 1516b70fb7afSTomasz Nowicki 1517b70fb7afSTomasz Nowicki /* 1518b70fb7afSTomasz Nowicki * Count how many redistributor regions we have. It is not allowed 1519b70fb7afSTomasz Nowicki * to mix redistributor description, GICR and GICC subtables have to be 1520b70fb7afSTomasz Nowicki * mutually exclusive. 1521b70fb7afSTomasz Nowicki */ 1522b70fb7afSTomasz Nowicki count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR, 1523b70fb7afSTomasz Nowicki gic_acpi_match_gicr, 0); 1524b70fb7afSTomasz Nowicki if (count > 0) { 1525611f039fSJulien Grall acpi_data.single_redist = false; 1526b70fb7afSTomasz Nowicki return count; 1527b70fb7afSTomasz Nowicki } 1528b70fb7afSTomasz Nowicki 1529b70fb7afSTomasz Nowicki count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT, 1530b70fb7afSTomasz Nowicki gic_acpi_match_gicc, 0); 1531b70fb7afSTomasz Nowicki if (count > 0) 1532611f039fSJulien Grall acpi_data.single_redist = true; 1533b70fb7afSTomasz Nowicki 1534b70fb7afSTomasz Nowicki return count; 1535b70fb7afSTomasz Nowicki } 1536b70fb7afSTomasz Nowicki 1537ffa7d616STomasz Nowicki static bool __init acpi_validate_gic_table(struct acpi_subtable_header *header, 1538ffa7d616STomasz Nowicki struct acpi_probe_entry *ape) 1539ffa7d616STomasz Nowicki { 1540ffa7d616STomasz Nowicki struct acpi_madt_generic_distributor *dist; 1541ffa7d616STomasz Nowicki int count; 1542ffa7d616STomasz Nowicki 1543ffa7d616STomasz Nowicki dist = (struct acpi_madt_generic_distributor *)header; 1544ffa7d616STomasz Nowicki if (dist->version != ape->driver_data) 1545ffa7d616STomasz Nowicki return false; 1546ffa7d616STomasz Nowicki 1547ffa7d616STomasz Nowicki /* We need to do that exercise anyway, the sooner the better */ 1548b70fb7afSTomasz Nowicki count = gic_acpi_count_gicr_regions(); 1549ffa7d616STomasz Nowicki if (count <= 0) 1550ffa7d616STomasz Nowicki return false; 1551ffa7d616STomasz Nowicki 1552611f039fSJulien Grall acpi_data.nr_redist_regions = count; 1553ffa7d616STomasz Nowicki return true; 1554ffa7d616STomasz Nowicki } 1555ffa7d616STomasz Nowicki 15561839e576SJulien Grall static int __init gic_acpi_parse_virt_madt_gicc(struct acpi_subtable_header *header, 15571839e576SJulien Grall const unsigned long end) 15581839e576SJulien Grall { 15591839e576SJulien Grall struct acpi_madt_generic_interrupt *gicc = 15601839e576SJulien Grall (struct acpi_madt_generic_interrupt *)header; 15611839e576SJulien Grall int maint_irq_mode; 15621839e576SJulien Grall static int first_madt = true; 15631839e576SJulien Grall 15641839e576SJulien Grall /* Skip unusable CPUs */ 15651839e576SJulien Grall if (!(gicc->flags & ACPI_MADT_ENABLED)) 15661839e576SJulien Grall return 0; 15671839e576SJulien Grall 15681839e576SJulien Grall maint_irq_mode = (gicc->flags & ACPI_MADT_VGIC_IRQ_MODE) ? 15691839e576SJulien Grall ACPI_EDGE_SENSITIVE : ACPI_LEVEL_SENSITIVE; 15701839e576SJulien Grall 15711839e576SJulien Grall if (first_madt) { 15721839e576SJulien Grall first_madt = false; 15731839e576SJulien Grall 15741839e576SJulien Grall acpi_data.maint_irq = gicc->vgic_interrupt; 15751839e576SJulien Grall acpi_data.maint_irq_mode = maint_irq_mode; 15761839e576SJulien Grall acpi_data.vcpu_base = gicc->gicv_base_address; 15771839e576SJulien Grall 15781839e576SJulien Grall return 0; 15791839e576SJulien Grall } 15801839e576SJulien Grall 15811839e576SJulien Grall /* 15821839e576SJulien Grall * The maintenance interrupt and GICV should be the same for every CPU 15831839e576SJulien Grall */ 15841839e576SJulien Grall if ((acpi_data.maint_irq != gicc->vgic_interrupt) || 15851839e576SJulien Grall (acpi_data.maint_irq_mode != maint_irq_mode) || 15861839e576SJulien Grall (acpi_data.vcpu_base != gicc->gicv_base_address)) 15871839e576SJulien Grall return -EINVAL; 15881839e576SJulien Grall 15891839e576SJulien Grall return 0; 15901839e576SJulien Grall } 15911839e576SJulien Grall 15921839e576SJulien Grall static bool __init gic_acpi_collect_virt_info(void) 15931839e576SJulien Grall { 15941839e576SJulien Grall int count; 15951839e576SJulien Grall 15961839e576SJulien Grall count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT, 15971839e576SJulien Grall gic_acpi_parse_virt_madt_gicc, 0); 15981839e576SJulien Grall 15991839e576SJulien Grall return (count > 0); 16001839e576SJulien Grall } 16011839e576SJulien Grall 1602ffa7d616STomasz Nowicki #define ACPI_GICV3_DIST_MEM_SIZE (SZ_64K) 16031839e576SJulien Grall #define ACPI_GICV2_VCTRL_MEM_SIZE (SZ_4K) 16041839e576SJulien Grall #define ACPI_GICV2_VCPU_MEM_SIZE (SZ_8K) 16051839e576SJulien Grall 16061839e576SJulien Grall static void __init gic_acpi_setup_kvm_info(void) 16071839e576SJulien Grall { 16081839e576SJulien Grall int irq; 16091839e576SJulien Grall 16101839e576SJulien Grall if (!gic_acpi_collect_virt_info()) { 16111839e576SJulien Grall pr_warn("Unable to get hardware information used for virtualization\n"); 16121839e576SJulien Grall return; 16131839e576SJulien Grall } 16141839e576SJulien Grall 16151839e576SJulien Grall gic_v3_kvm_info.type = GIC_V3; 16161839e576SJulien Grall 16171839e576SJulien Grall irq = acpi_register_gsi(NULL, acpi_data.maint_irq, 16181839e576SJulien Grall acpi_data.maint_irq_mode, 16191839e576SJulien Grall ACPI_ACTIVE_HIGH); 16201839e576SJulien Grall if (irq <= 0) 16211839e576SJulien Grall return; 16221839e576SJulien Grall 16231839e576SJulien Grall gic_v3_kvm_info.maint_irq = irq; 16241839e576SJulien Grall 16251839e576SJulien Grall if (acpi_data.vcpu_base) { 16261839e576SJulien Grall struct resource *vcpu = &gic_v3_kvm_info.vcpu; 16271839e576SJulien Grall 16281839e576SJulien Grall vcpu->flags = IORESOURCE_MEM; 16291839e576SJulien Grall vcpu->start = acpi_data.vcpu_base; 16301839e576SJulien Grall vcpu->end = vcpu->start + ACPI_GICV2_VCPU_MEM_SIZE - 1; 16311839e576SJulien Grall } 16321839e576SJulien Grall 16334bdf5025SMarc Zyngier gic_v3_kvm_info.has_v4 = gic_data.rdists.has_vlpis; 16341839e576SJulien Grall gic_set_kvm_info(&gic_v3_kvm_info); 16351839e576SJulien Grall } 1636ffa7d616STomasz Nowicki 1637ffa7d616STomasz Nowicki static int __init 1638ffa7d616STomasz Nowicki gic_acpi_init(struct acpi_subtable_header *header, const unsigned long end) 1639ffa7d616STomasz Nowicki { 1640ffa7d616STomasz Nowicki struct acpi_madt_generic_distributor *dist; 1641ffa7d616STomasz Nowicki struct fwnode_handle *domain_handle; 1642611f039fSJulien Grall size_t size; 1643b70fb7afSTomasz Nowicki int i, err; 1644ffa7d616STomasz Nowicki 1645ffa7d616STomasz Nowicki /* Get distributor base address */ 1646ffa7d616STomasz Nowicki dist = (struct acpi_madt_generic_distributor *)header; 1647611f039fSJulien Grall acpi_data.dist_base = ioremap(dist->base_address, 1648611f039fSJulien Grall ACPI_GICV3_DIST_MEM_SIZE); 1649611f039fSJulien Grall if (!acpi_data.dist_base) { 1650ffa7d616STomasz Nowicki pr_err("Unable to map GICD registers\n"); 1651ffa7d616STomasz Nowicki return -ENOMEM; 1652ffa7d616STomasz Nowicki } 1653ffa7d616STomasz Nowicki 1654611f039fSJulien Grall err = gic_validate_dist_version(acpi_data.dist_base); 1655ffa7d616STomasz Nowicki if (err) { 165671192a68SArvind Yadav pr_err("No distributor detected at @%p, giving up\n", 1657611f039fSJulien Grall acpi_data.dist_base); 1658ffa7d616STomasz Nowicki goto out_dist_unmap; 1659ffa7d616STomasz Nowicki } 1660ffa7d616STomasz Nowicki 1661611f039fSJulien Grall size = sizeof(*acpi_data.redist_regs) * acpi_data.nr_redist_regions; 1662611f039fSJulien Grall acpi_data.redist_regs = kzalloc(size, GFP_KERNEL); 1663611f039fSJulien Grall if (!acpi_data.redist_regs) { 1664ffa7d616STomasz Nowicki err = -ENOMEM; 1665ffa7d616STomasz Nowicki goto out_dist_unmap; 1666ffa7d616STomasz Nowicki } 1667ffa7d616STomasz Nowicki 1668b70fb7afSTomasz Nowicki err = gic_acpi_collect_gicr_base(); 1669b70fb7afSTomasz Nowicki if (err) 1670ffa7d616STomasz Nowicki goto out_redist_unmap; 1671ffa7d616STomasz Nowicki 1672611f039fSJulien Grall domain_handle = irq_domain_alloc_fwnode(acpi_data.dist_base); 1673ffa7d616STomasz Nowicki if (!domain_handle) { 1674ffa7d616STomasz Nowicki err = -ENOMEM; 1675ffa7d616STomasz Nowicki goto out_redist_unmap; 1676ffa7d616STomasz Nowicki } 1677ffa7d616STomasz Nowicki 1678611f039fSJulien Grall err = gic_init_bases(acpi_data.dist_base, acpi_data.redist_regs, 1679611f039fSJulien Grall acpi_data.nr_redist_regions, 0, domain_handle); 1680ffa7d616STomasz Nowicki if (err) 1681ffa7d616STomasz Nowicki goto out_fwhandle_free; 1682ffa7d616STomasz Nowicki 1683ffa7d616STomasz Nowicki acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, domain_handle); 1684d33a3c8cSChristoffer Dall 1685d01d3274SDavidlohr Bueso if (static_branch_likely(&supports_deactivate_key)) 16861839e576SJulien Grall gic_acpi_setup_kvm_info(); 16871839e576SJulien Grall 1688ffa7d616STomasz Nowicki return 0; 1689ffa7d616STomasz Nowicki 1690ffa7d616STomasz Nowicki out_fwhandle_free: 1691ffa7d616STomasz Nowicki irq_domain_free_fwnode(domain_handle); 1692ffa7d616STomasz Nowicki out_redist_unmap: 1693611f039fSJulien Grall for (i = 0; i < acpi_data.nr_redist_regions; i++) 1694611f039fSJulien Grall if (acpi_data.redist_regs[i].redist_base) 1695611f039fSJulien Grall iounmap(acpi_data.redist_regs[i].redist_base); 1696611f039fSJulien Grall kfree(acpi_data.redist_regs); 1697ffa7d616STomasz Nowicki out_dist_unmap: 1698611f039fSJulien Grall iounmap(acpi_data.dist_base); 1699ffa7d616STomasz Nowicki return err; 1700ffa7d616STomasz Nowicki } 1701ffa7d616STomasz Nowicki IRQCHIP_ACPI_DECLARE(gic_v3, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 1702ffa7d616STomasz Nowicki acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V3, 1703ffa7d616STomasz Nowicki gic_acpi_init); 1704ffa7d616STomasz Nowicki IRQCHIP_ACPI_DECLARE(gic_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 1705ffa7d616STomasz Nowicki acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V4, 1706ffa7d616STomasz Nowicki gic_acpi_init); 1707ffa7d616STomasz Nowicki IRQCHIP_ACPI_DECLARE(gic_v3_or_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 1708ffa7d616STomasz Nowicki acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_NONE, 1709ffa7d616STomasz Nowicki gic_acpi_init); 1710ffa7d616STomasz Nowicki #endif 1711