1021f6537SMarc Zyngier /* 2021f6537SMarc Zyngier * Copyright (C) 2013, 2014 ARM Limited, All Rights Reserved. 3021f6537SMarc Zyngier * Author: Marc Zyngier <marc.zyngier@arm.com> 4021f6537SMarc Zyngier * 5021f6537SMarc Zyngier * This program is free software; you can redistribute it and/or modify 6021f6537SMarc Zyngier * it under the terms of the GNU General Public License version 2 as 7021f6537SMarc Zyngier * published by the Free Software Foundation. 8021f6537SMarc Zyngier * 9021f6537SMarc Zyngier * This program is distributed in the hope that it will be useful, 10021f6537SMarc Zyngier * but WITHOUT ANY WARRANTY; without even the implied warranty of 11021f6537SMarc Zyngier * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12021f6537SMarc Zyngier * GNU General Public License for more details. 13021f6537SMarc Zyngier * 14021f6537SMarc Zyngier * You should have received a copy of the GNU General Public License 15021f6537SMarc Zyngier * along with this program. If not, see <http://www.gnu.org/licenses/>. 16021f6537SMarc Zyngier */ 17021f6537SMarc Zyngier 18ffa7d616STomasz Nowicki #include <linux/acpi.h> 19021f6537SMarc Zyngier #include <linux/cpu.h> 203708d52fSSudeep Holla #include <linux/cpu_pm.h> 21021f6537SMarc Zyngier #include <linux/delay.h> 22021f6537SMarc Zyngier #include <linux/interrupt.h> 23ffa7d616STomasz Nowicki #include <linux/irqdomain.h> 24021f6537SMarc Zyngier #include <linux/of.h> 25021f6537SMarc Zyngier #include <linux/of_address.h> 26021f6537SMarc Zyngier #include <linux/of_irq.h> 27021f6537SMarc Zyngier #include <linux/percpu.h> 28021f6537SMarc Zyngier #include <linux/slab.h> 29021f6537SMarc Zyngier 3041a83e06SJoel Porquet #include <linux/irqchip.h> 31021f6537SMarc Zyngier #include <linux/irqchip/arm-gic-v3.h> 32e3825ba1SMarc Zyngier #include <linux/irqchip/irq-partition-percpu.h> 33021f6537SMarc Zyngier 34021f6537SMarc Zyngier #include <asm/cputype.h> 35021f6537SMarc Zyngier #include <asm/exception.h> 36021f6537SMarc Zyngier #include <asm/smp_plat.h> 370b6a3da9SMarc Zyngier #include <asm/virt.h> 38021f6537SMarc Zyngier 39021f6537SMarc Zyngier #include "irq-gic-common.h" 40021f6537SMarc Zyngier 41f5c1434cSMarc Zyngier struct redist_region { 42f5c1434cSMarc Zyngier void __iomem *redist_base; 43f5c1434cSMarc Zyngier phys_addr_t phys_base; 44b70fb7afSTomasz Nowicki bool single_redist; 45f5c1434cSMarc Zyngier }; 46f5c1434cSMarc Zyngier 47021f6537SMarc Zyngier struct gic_chip_data { 48e3825ba1SMarc Zyngier struct fwnode_handle *fwnode; 49021f6537SMarc Zyngier void __iomem *dist_base; 50f5c1434cSMarc Zyngier struct redist_region *redist_regions; 51f5c1434cSMarc Zyngier struct rdists rdists; 52021f6537SMarc Zyngier struct irq_domain *domain; 53021f6537SMarc Zyngier u64 redist_stride; 54f5c1434cSMarc Zyngier u32 nr_redist_regions; 55021f6537SMarc Zyngier unsigned int irq_nr; 56e3825ba1SMarc Zyngier struct partition_desc *ppi_descs[16]; 57021f6537SMarc Zyngier }; 58021f6537SMarc Zyngier 59021f6537SMarc Zyngier static struct gic_chip_data gic_data __read_mostly; 600b6a3da9SMarc Zyngier static struct static_key supports_deactivate = STATIC_KEY_INIT_TRUE; 61021f6537SMarc Zyngier 62f5c1434cSMarc Zyngier #define gic_data_rdist() (this_cpu_ptr(gic_data.rdists.rdist)) 63f5c1434cSMarc Zyngier #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base) 64021f6537SMarc Zyngier #define gic_data_rdist_sgi_base() (gic_data_rdist_rd_base() + SZ_64K) 65021f6537SMarc Zyngier 66021f6537SMarc Zyngier /* Our default, arbitrary priority value. Linux only uses one anyway. */ 67021f6537SMarc Zyngier #define DEFAULT_PMR_VALUE 0xf0 68021f6537SMarc Zyngier 69021f6537SMarc Zyngier static inline unsigned int gic_irq(struct irq_data *d) 70021f6537SMarc Zyngier { 71021f6537SMarc Zyngier return d->hwirq; 72021f6537SMarc Zyngier } 73021f6537SMarc Zyngier 74021f6537SMarc Zyngier static inline int gic_irq_in_rdist(struct irq_data *d) 75021f6537SMarc Zyngier { 76021f6537SMarc Zyngier return gic_irq(d) < 32; 77021f6537SMarc Zyngier } 78021f6537SMarc Zyngier 79021f6537SMarc Zyngier static inline void __iomem *gic_dist_base(struct irq_data *d) 80021f6537SMarc Zyngier { 81021f6537SMarc Zyngier if (gic_irq_in_rdist(d)) /* SGI+PPI -> SGI_base for this CPU */ 82021f6537SMarc Zyngier return gic_data_rdist_sgi_base(); 83021f6537SMarc Zyngier 84021f6537SMarc Zyngier if (d->hwirq <= 1023) /* SPI -> dist_base */ 85021f6537SMarc Zyngier return gic_data.dist_base; 86021f6537SMarc Zyngier 87021f6537SMarc Zyngier return NULL; 88021f6537SMarc Zyngier } 89021f6537SMarc Zyngier 90021f6537SMarc Zyngier static void gic_do_wait_for_rwp(void __iomem *base) 91021f6537SMarc Zyngier { 92021f6537SMarc Zyngier u32 count = 1000000; /* 1s! */ 93021f6537SMarc Zyngier 94021f6537SMarc Zyngier while (readl_relaxed(base + GICD_CTLR) & GICD_CTLR_RWP) { 95021f6537SMarc Zyngier count--; 96021f6537SMarc Zyngier if (!count) { 97021f6537SMarc Zyngier pr_err_ratelimited("RWP timeout, gone fishing\n"); 98021f6537SMarc Zyngier return; 99021f6537SMarc Zyngier } 100021f6537SMarc Zyngier cpu_relax(); 101021f6537SMarc Zyngier udelay(1); 102021f6537SMarc Zyngier }; 103021f6537SMarc Zyngier } 104021f6537SMarc Zyngier 105021f6537SMarc Zyngier /* Wait for completion of a distributor change */ 106021f6537SMarc Zyngier static void gic_dist_wait_for_rwp(void) 107021f6537SMarc Zyngier { 108021f6537SMarc Zyngier gic_do_wait_for_rwp(gic_data.dist_base); 109021f6537SMarc Zyngier } 110021f6537SMarc Zyngier 111021f6537SMarc Zyngier /* Wait for completion of a redistributor change */ 112021f6537SMarc Zyngier static void gic_redist_wait_for_rwp(void) 113021f6537SMarc Zyngier { 114021f6537SMarc Zyngier gic_do_wait_for_rwp(gic_data_rdist_rd_base()); 115021f6537SMarc Zyngier } 116021f6537SMarc Zyngier 1177936e914SJean-Philippe Brucker #ifdef CONFIG_ARM64 1188ac2a170SRobert Richter static DEFINE_STATIC_KEY_FALSE(is_cavium_thunderx); 1196d4e11c5SRobert Richter 1206d4e11c5SRobert Richter static u64 __maybe_unused gic_read_iar(void) 1216d4e11c5SRobert Richter { 1228ac2a170SRobert Richter if (static_branch_unlikely(&is_cavium_thunderx)) 1236d4e11c5SRobert Richter return gic_read_iar_cavium_thunderx(); 1246d4e11c5SRobert Richter else 1256d4e11c5SRobert Richter return gic_read_iar_common(); 1266d4e11c5SRobert Richter } 1277936e914SJean-Philippe Brucker #endif 128021f6537SMarc Zyngier 129a2c22510SSudeep Holla static void gic_enable_redist(bool enable) 130021f6537SMarc Zyngier { 131021f6537SMarc Zyngier void __iomem *rbase; 132021f6537SMarc Zyngier u32 count = 1000000; /* 1s! */ 133021f6537SMarc Zyngier u32 val; 134021f6537SMarc Zyngier 135021f6537SMarc Zyngier rbase = gic_data_rdist_rd_base(); 136021f6537SMarc Zyngier 137021f6537SMarc Zyngier val = readl_relaxed(rbase + GICR_WAKER); 138a2c22510SSudeep Holla if (enable) 139a2c22510SSudeep Holla /* Wake up this CPU redistributor */ 140021f6537SMarc Zyngier val &= ~GICR_WAKER_ProcessorSleep; 141a2c22510SSudeep Holla else 142a2c22510SSudeep Holla val |= GICR_WAKER_ProcessorSleep; 143021f6537SMarc Zyngier writel_relaxed(val, rbase + GICR_WAKER); 144021f6537SMarc Zyngier 145a2c22510SSudeep Holla if (!enable) { /* Check that GICR_WAKER is writeable */ 146a2c22510SSudeep Holla val = readl_relaxed(rbase + GICR_WAKER); 147a2c22510SSudeep Holla if (!(val & GICR_WAKER_ProcessorSleep)) 148a2c22510SSudeep Holla return; /* No PM support in this redistributor */ 149021f6537SMarc Zyngier } 150a2c22510SSudeep Holla 151a2c22510SSudeep Holla while (count--) { 152a2c22510SSudeep Holla val = readl_relaxed(rbase + GICR_WAKER); 153a2c22510SSudeep Holla if (enable ^ (val & GICR_WAKER_ChildrenAsleep)) 154a2c22510SSudeep Holla break; 155021f6537SMarc Zyngier cpu_relax(); 156021f6537SMarc Zyngier udelay(1); 157021f6537SMarc Zyngier }; 158a2c22510SSudeep Holla if (!count) 159a2c22510SSudeep Holla pr_err_ratelimited("redistributor failed to %s...\n", 160a2c22510SSudeep Holla enable ? "wakeup" : "sleep"); 161021f6537SMarc Zyngier } 162021f6537SMarc Zyngier 163021f6537SMarc Zyngier /* 164021f6537SMarc Zyngier * Routines to disable, enable, EOI and route interrupts 165021f6537SMarc Zyngier */ 166b594c6e2SMarc Zyngier static int gic_peek_irq(struct irq_data *d, u32 offset) 167b594c6e2SMarc Zyngier { 168b594c6e2SMarc Zyngier u32 mask = 1 << (gic_irq(d) % 32); 169b594c6e2SMarc Zyngier void __iomem *base; 170b594c6e2SMarc Zyngier 171b594c6e2SMarc Zyngier if (gic_irq_in_rdist(d)) 172b594c6e2SMarc Zyngier base = gic_data_rdist_sgi_base(); 173b594c6e2SMarc Zyngier else 174b594c6e2SMarc Zyngier base = gic_data.dist_base; 175b594c6e2SMarc Zyngier 176b594c6e2SMarc Zyngier return !!(readl_relaxed(base + offset + (gic_irq(d) / 32) * 4) & mask); 177b594c6e2SMarc Zyngier } 178b594c6e2SMarc Zyngier 179021f6537SMarc Zyngier static void gic_poke_irq(struct irq_data *d, u32 offset) 180021f6537SMarc Zyngier { 181021f6537SMarc Zyngier u32 mask = 1 << (gic_irq(d) % 32); 182021f6537SMarc Zyngier void (*rwp_wait)(void); 183021f6537SMarc Zyngier void __iomem *base; 184021f6537SMarc Zyngier 185021f6537SMarc Zyngier if (gic_irq_in_rdist(d)) { 186021f6537SMarc Zyngier base = gic_data_rdist_sgi_base(); 187021f6537SMarc Zyngier rwp_wait = gic_redist_wait_for_rwp; 188021f6537SMarc Zyngier } else { 189021f6537SMarc Zyngier base = gic_data.dist_base; 190021f6537SMarc Zyngier rwp_wait = gic_dist_wait_for_rwp; 191021f6537SMarc Zyngier } 192021f6537SMarc Zyngier 193021f6537SMarc Zyngier writel_relaxed(mask, base + offset + (gic_irq(d) / 32) * 4); 194021f6537SMarc Zyngier rwp_wait(); 195021f6537SMarc Zyngier } 196021f6537SMarc Zyngier 197021f6537SMarc Zyngier static void gic_mask_irq(struct irq_data *d) 198021f6537SMarc Zyngier { 199021f6537SMarc Zyngier gic_poke_irq(d, GICD_ICENABLER); 200021f6537SMarc Zyngier } 201021f6537SMarc Zyngier 2020b6a3da9SMarc Zyngier static void gic_eoimode1_mask_irq(struct irq_data *d) 2030b6a3da9SMarc Zyngier { 2040b6a3da9SMarc Zyngier gic_mask_irq(d); 205530bf353SMarc Zyngier /* 206530bf353SMarc Zyngier * When masking a forwarded interrupt, make sure it is 207530bf353SMarc Zyngier * deactivated as well. 208530bf353SMarc Zyngier * 209530bf353SMarc Zyngier * This ensures that an interrupt that is getting 210530bf353SMarc Zyngier * disabled/masked will not get "stuck", because there is 211530bf353SMarc Zyngier * noone to deactivate it (guest is being terminated). 212530bf353SMarc Zyngier */ 2134df7f54dSThomas Gleixner if (irqd_is_forwarded_to_vcpu(d)) 214530bf353SMarc Zyngier gic_poke_irq(d, GICD_ICACTIVER); 2150b6a3da9SMarc Zyngier } 2160b6a3da9SMarc Zyngier 217021f6537SMarc Zyngier static void gic_unmask_irq(struct irq_data *d) 218021f6537SMarc Zyngier { 219021f6537SMarc Zyngier gic_poke_irq(d, GICD_ISENABLER); 220021f6537SMarc Zyngier } 221021f6537SMarc Zyngier 222b594c6e2SMarc Zyngier static int gic_irq_set_irqchip_state(struct irq_data *d, 223b594c6e2SMarc Zyngier enum irqchip_irq_state which, bool val) 224b594c6e2SMarc Zyngier { 225b594c6e2SMarc Zyngier u32 reg; 226b594c6e2SMarc Zyngier 227b594c6e2SMarc Zyngier if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */ 228b594c6e2SMarc Zyngier return -EINVAL; 229b594c6e2SMarc Zyngier 230b594c6e2SMarc Zyngier switch (which) { 231b594c6e2SMarc Zyngier case IRQCHIP_STATE_PENDING: 232b594c6e2SMarc Zyngier reg = val ? GICD_ISPENDR : GICD_ICPENDR; 233b594c6e2SMarc Zyngier break; 234b594c6e2SMarc Zyngier 235b594c6e2SMarc Zyngier case IRQCHIP_STATE_ACTIVE: 236b594c6e2SMarc Zyngier reg = val ? GICD_ISACTIVER : GICD_ICACTIVER; 237b594c6e2SMarc Zyngier break; 238b594c6e2SMarc Zyngier 239b594c6e2SMarc Zyngier case IRQCHIP_STATE_MASKED: 240b594c6e2SMarc Zyngier reg = val ? GICD_ICENABLER : GICD_ISENABLER; 241b594c6e2SMarc Zyngier break; 242b594c6e2SMarc Zyngier 243b594c6e2SMarc Zyngier default: 244b594c6e2SMarc Zyngier return -EINVAL; 245b594c6e2SMarc Zyngier } 246b594c6e2SMarc Zyngier 247b594c6e2SMarc Zyngier gic_poke_irq(d, reg); 248b594c6e2SMarc Zyngier return 0; 249b594c6e2SMarc Zyngier } 250b594c6e2SMarc Zyngier 251b594c6e2SMarc Zyngier static int gic_irq_get_irqchip_state(struct irq_data *d, 252b594c6e2SMarc Zyngier enum irqchip_irq_state which, bool *val) 253b594c6e2SMarc Zyngier { 254b594c6e2SMarc Zyngier if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */ 255b594c6e2SMarc Zyngier return -EINVAL; 256b594c6e2SMarc Zyngier 257b594c6e2SMarc Zyngier switch (which) { 258b594c6e2SMarc Zyngier case IRQCHIP_STATE_PENDING: 259b594c6e2SMarc Zyngier *val = gic_peek_irq(d, GICD_ISPENDR); 260b594c6e2SMarc Zyngier break; 261b594c6e2SMarc Zyngier 262b594c6e2SMarc Zyngier case IRQCHIP_STATE_ACTIVE: 263b594c6e2SMarc Zyngier *val = gic_peek_irq(d, GICD_ISACTIVER); 264b594c6e2SMarc Zyngier break; 265b594c6e2SMarc Zyngier 266b594c6e2SMarc Zyngier case IRQCHIP_STATE_MASKED: 267b594c6e2SMarc Zyngier *val = !gic_peek_irq(d, GICD_ISENABLER); 268b594c6e2SMarc Zyngier break; 269b594c6e2SMarc Zyngier 270b594c6e2SMarc Zyngier default: 271b594c6e2SMarc Zyngier return -EINVAL; 272b594c6e2SMarc Zyngier } 273b594c6e2SMarc Zyngier 274b594c6e2SMarc Zyngier return 0; 275b594c6e2SMarc Zyngier } 276b594c6e2SMarc Zyngier 277021f6537SMarc Zyngier static void gic_eoi_irq(struct irq_data *d) 278021f6537SMarc Zyngier { 279021f6537SMarc Zyngier gic_write_eoir(gic_irq(d)); 280021f6537SMarc Zyngier } 281021f6537SMarc Zyngier 2820b6a3da9SMarc Zyngier static void gic_eoimode1_eoi_irq(struct irq_data *d) 2830b6a3da9SMarc Zyngier { 2840b6a3da9SMarc Zyngier /* 285530bf353SMarc Zyngier * No need to deactivate an LPI, or an interrupt that 286530bf353SMarc Zyngier * is is getting forwarded to a vcpu. 2870b6a3da9SMarc Zyngier */ 2884df7f54dSThomas Gleixner if (gic_irq(d) >= 8192 || irqd_is_forwarded_to_vcpu(d)) 2890b6a3da9SMarc Zyngier return; 2900b6a3da9SMarc Zyngier gic_write_dir(gic_irq(d)); 2910b6a3da9SMarc Zyngier } 2920b6a3da9SMarc Zyngier 293021f6537SMarc Zyngier static int gic_set_type(struct irq_data *d, unsigned int type) 294021f6537SMarc Zyngier { 295021f6537SMarc Zyngier unsigned int irq = gic_irq(d); 296021f6537SMarc Zyngier void (*rwp_wait)(void); 297021f6537SMarc Zyngier void __iomem *base; 298021f6537SMarc Zyngier 299021f6537SMarc Zyngier /* Interrupt configuration for SGIs can't be changed */ 300021f6537SMarc Zyngier if (irq < 16) 301021f6537SMarc Zyngier return -EINVAL; 302021f6537SMarc Zyngier 303fb7e7debSLiviu Dudau /* SPIs have restrictions on the supported types */ 304fb7e7debSLiviu Dudau if (irq >= 32 && type != IRQ_TYPE_LEVEL_HIGH && 305fb7e7debSLiviu Dudau type != IRQ_TYPE_EDGE_RISING) 306021f6537SMarc Zyngier return -EINVAL; 307021f6537SMarc Zyngier 308021f6537SMarc Zyngier if (gic_irq_in_rdist(d)) { 309021f6537SMarc Zyngier base = gic_data_rdist_sgi_base(); 310021f6537SMarc Zyngier rwp_wait = gic_redist_wait_for_rwp; 311021f6537SMarc Zyngier } else { 312021f6537SMarc Zyngier base = gic_data.dist_base; 313021f6537SMarc Zyngier rwp_wait = gic_dist_wait_for_rwp; 314021f6537SMarc Zyngier } 315021f6537SMarc Zyngier 316fb7e7debSLiviu Dudau return gic_configure_irq(irq, type, base, rwp_wait); 317021f6537SMarc Zyngier } 318021f6537SMarc Zyngier 319530bf353SMarc Zyngier static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu) 320530bf353SMarc Zyngier { 3214df7f54dSThomas Gleixner if (vcpu) 3224df7f54dSThomas Gleixner irqd_set_forwarded_to_vcpu(d); 3234df7f54dSThomas Gleixner else 3244df7f54dSThomas Gleixner irqd_clr_forwarded_to_vcpu(d); 325530bf353SMarc Zyngier return 0; 326530bf353SMarc Zyngier } 327530bf353SMarc Zyngier 328f6c86a41SJean-Philippe Brucker static u64 gic_mpidr_to_affinity(unsigned long mpidr) 329021f6537SMarc Zyngier { 330021f6537SMarc Zyngier u64 aff; 331021f6537SMarc Zyngier 332f6c86a41SJean-Philippe Brucker aff = ((u64)MPIDR_AFFINITY_LEVEL(mpidr, 3) << 32 | 333021f6537SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 | 334021f6537SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | 335021f6537SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 0)); 336021f6537SMarc Zyngier 337021f6537SMarc Zyngier return aff; 338021f6537SMarc Zyngier } 339021f6537SMarc Zyngier 340021f6537SMarc Zyngier static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) 341021f6537SMarc Zyngier { 342f6c86a41SJean-Philippe Brucker u32 irqnr; 343021f6537SMarc Zyngier 344021f6537SMarc Zyngier do { 345021f6537SMarc Zyngier irqnr = gic_read_iar(); 346021f6537SMarc Zyngier 347da33f31dSMarc Zyngier if (likely(irqnr > 15 && irqnr < 1020) || irqnr >= 8192) { 348ebc6de00SMarc Zyngier int err; 3490b6a3da9SMarc Zyngier 3500b6a3da9SMarc Zyngier if (static_key_true(&supports_deactivate)) 3510b6a3da9SMarc Zyngier gic_write_eoir(irqnr); 3520b6a3da9SMarc Zyngier 353ebc6de00SMarc Zyngier err = handle_domain_irq(gic_data.domain, irqnr, regs); 354ebc6de00SMarc Zyngier if (err) { 355da33f31dSMarc Zyngier WARN_ONCE(true, "Unexpected interrupt received!\n"); 3560b6a3da9SMarc Zyngier if (static_key_true(&supports_deactivate)) { 3570b6a3da9SMarc Zyngier if (irqnr < 8192) 3580b6a3da9SMarc Zyngier gic_write_dir(irqnr); 3590b6a3da9SMarc Zyngier } else { 360021f6537SMarc Zyngier gic_write_eoir(irqnr); 361021f6537SMarc Zyngier } 3620b6a3da9SMarc Zyngier } 363ebc6de00SMarc Zyngier continue; 364ebc6de00SMarc Zyngier } 365021f6537SMarc Zyngier if (irqnr < 16) { 366021f6537SMarc Zyngier gic_write_eoir(irqnr); 3670b6a3da9SMarc Zyngier if (static_key_true(&supports_deactivate)) 3680b6a3da9SMarc Zyngier gic_write_dir(irqnr); 369021f6537SMarc Zyngier #ifdef CONFIG_SMP 370021f6537SMarc Zyngier handle_IPI(irqnr, regs); 371021f6537SMarc Zyngier #else 372021f6537SMarc Zyngier WARN_ONCE(true, "Unexpected SGI received!\n"); 373021f6537SMarc Zyngier #endif 374021f6537SMarc Zyngier continue; 375021f6537SMarc Zyngier } 376021f6537SMarc Zyngier } while (irqnr != ICC_IAR1_EL1_SPURIOUS); 377021f6537SMarc Zyngier } 378021f6537SMarc Zyngier 379021f6537SMarc Zyngier static void __init gic_dist_init(void) 380021f6537SMarc Zyngier { 381021f6537SMarc Zyngier unsigned int i; 382021f6537SMarc Zyngier u64 affinity; 383021f6537SMarc Zyngier void __iomem *base = gic_data.dist_base; 384021f6537SMarc Zyngier 385021f6537SMarc Zyngier /* Disable the distributor */ 386021f6537SMarc Zyngier writel_relaxed(0, base + GICD_CTLR); 387021f6537SMarc Zyngier gic_dist_wait_for_rwp(); 388021f6537SMarc Zyngier 389021f6537SMarc Zyngier gic_dist_config(base, gic_data.irq_nr, gic_dist_wait_for_rwp); 390021f6537SMarc Zyngier 391021f6537SMarc Zyngier /* Enable distributor with ARE, Group1 */ 392021f6537SMarc Zyngier writel_relaxed(GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G1A | GICD_CTLR_ENABLE_G1, 393021f6537SMarc Zyngier base + GICD_CTLR); 394021f6537SMarc Zyngier 395021f6537SMarc Zyngier /* 396021f6537SMarc Zyngier * Set all global interrupts to the boot CPU only. ARE must be 397021f6537SMarc Zyngier * enabled. 398021f6537SMarc Zyngier */ 399021f6537SMarc Zyngier affinity = gic_mpidr_to_affinity(cpu_logical_map(smp_processor_id())); 400021f6537SMarc Zyngier for (i = 32; i < gic_data.irq_nr; i++) 40172c97126SJean-Philippe Brucker gic_write_irouter(affinity, base + GICD_IROUTER + i * 8); 402021f6537SMarc Zyngier } 403021f6537SMarc Zyngier 404021f6537SMarc Zyngier static int gic_populate_rdist(void) 405021f6537SMarc Zyngier { 406f6c86a41SJean-Philippe Brucker unsigned long mpidr = cpu_logical_map(smp_processor_id()); 407021f6537SMarc Zyngier u64 typer; 408021f6537SMarc Zyngier u32 aff; 409021f6537SMarc Zyngier int i; 410021f6537SMarc Zyngier 411021f6537SMarc Zyngier /* 412021f6537SMarc Zyngier * Convert affinity to a 32bit value that can be matched to 413021f6537SMarc Zyngier * GICR_TYPER bits [63:32]. 414021f6537SMarc Zyngier */ 415021f6537SMarc Zyngier aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 24 | 416021f6537SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 | 417021f6537SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | 418021f6537SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 0)); 419021f6537SMarc Zyngier 420f5c1434cSMarc Zyngier for (i = 0; i < gic_data.nr_redist_regions; i++) { 421f5c1434cSMarc Zyngier void __iomem *ptr = gic_data.redist_regions[i].redist_base; 422021f6537SMarc Zyngier u32 reg; 423021f6537SMarc Zyngier 424021f6537SMarc Zyngier reg = readl_relaxed(ptr + GICR_PIDR2) & GIC_PIDR2_ARCH_MASK; 425021f6537SMarc Zyngier if (reg != GIC_PIDR2_ARCH_GICv3 && 426021f6537SMarc Zyngier reg != GIC_PIDR2_ARCH_GICv4) { /* We're in trouble... */ 427021f6537SMarc Zyngier pr_warn("No redistributor present @%p\n", ptr); 428021f6537SMarc Zyngier break; 429021f6537SMarc Zyngier } 430021f6537SMarc Zyngier 431021f6537SMarc Zyngier do { 43272c97126SJean-Philippe Brucker typer = gic_read_typer(ptr + GICR_TYPER); 433021f6537SMarc Zyngier if ((typer >> 32) == aff) { 434f5c1434cSMarc Zyngier u64 offset = ptr - gic_data.redist_regions[i].redist_base; 435021f6537SMarc Zyngier gic_data_rdist_rd_base() = ptr; 436f5c1434cSMarc Zyngier gic_data_rdist()->phys_base = gic_data.redist_regions[i].phys_base + offset; 437f6c86a41SJean-Philippe Brucker pr_info("CPU%d: found redistributor %lx region %d:%pa\n", 438f6c86a41SJean-Philippe Brucker smp_processor_id(), mpidr, i, 439f6c86a41SJean-Philippe Brucker &gic_data_rdist()->phys_base); 440021f6537SMarc Zyngier return 0; 441021f6537SMarc Zyngier } 442021f6537SMarc Zyngier 443b70fb7afSTomasz Nowicki if (gic_data.redist_regions[i].single_redist) 444b70fb7afSTomasz Nowicki break; 445b70fb7afSTomasz Nowicki 446021f6537SMarc Zyngier if (gic_data.redist_stride) { 447021f6537SMarc Zyngier ptr += gic_data.redist_stride; 448021f6537SMarc Zyngier } else { 449021f6537SMarc Zyngier ptr += SZ_64K * 2; /* Skip RD_base + SGI_base */ 450021f6537SMarc Zyngier if (typer & GICR_TYPER_VLPIS) 451021f6537SMarc Zyngier ptr += SZ_64K * 2; /* Skip VLPI_base + reserved page */ 452021f6537SMarc Zyngier } 453021f6537SMarc Zyngier } while (!(typer & GICR_TYPER_LAST)); 454021f6537SMarc Zyngier } 455021f6537SMarc Zyngier 456021f6537SMarc Zyngier /* We couldn't even deal with ourselves... */ 457f6c86a41SJean-Philippe Brucker WARN(true, "CPU%d: mpidr %lx has no re-distributor!\n", 458f6c86a41SJean-Philippe Brucker smp_processor_id(), mpidr); 459021f6537SMarc Zyngier return -ENODEV; 460021f6537SMarc Zyngier } 461021f6537SMarc Zyngier 4623708d52fSSudeep Holla static void gic_cpu_sys_reg_init(void) 463021f6537SMarc Zyngier { 4647cabd008SMarc Zyngier /* 4657cabd008SMarc Zyngier * Need to check that the SRE bit has actually been set. If 4667cabd008SMarc Zyngier * not, it means that SRE is disabled at EL2. We're going to 4677cabd008SMarc Zyngier * die painfully, and there is nothing we can do about it. 4687cabd008SMarc Zyngier * 4697cabd008SMarc Zyngier * Kindly inform the luser. 4707cabd008SMarc Zyngier */ 4717cabd008SMarc Zyngier if (!gic_enable_sre()) 4727cabd008SMarc Zyngier pr_err("GIC: unable to set SRE (disabled at EL2), panic ahead\n"); 473021f6537SMarc Zyngier 474021f6537SMarc Zyngier /* Set priority mask register */ 475021f6537SMarc Zyngier gic_write_pmr(DEFAULT_PMR_VALUE); 476021f6537SMarc Zyngier 4770b6a3da9SMarc Zyngier if (static_key_true(&supports_deactivate)) { 4780b6a3da9SMarc Zyngier /* EOI drops priority only (mode 1) */ 4790b6a3da9SMarc Zyngier gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop); 4800b6a3da9SMarc Zyngier } else { 481021f6537SMarc Zyngier /* EOI deactivates interrupt too (mode 0) */ 482021f6537SMarc Zyngier gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop_dir); 4830b6a3da9SMarc Zyngier } 484021f6537SMarc Zyngier 485021f6537SMarc Zyngier /* ... and let's hit the road... */ 486021f6537SMarc Zyngier gic_write_grpen1(1); 487021f6537SMarc Zyngier } 488021f6537SMarc Zyngier 489da33f31dSMarc Zyngier static int gic_dist_supports_lpis(void) 490da33f31dSMarc Zyngier { 491da33f31dSMarc Zyngier return !!(readl_relaxed(gic_data.dist_base + GICD_TYPER) & GICD_TYPER_LPIS); 492da33f31dSMarc Zyngier } 493da33f31dSMarc Zyngier 494021f6537SMarc Zyngier static void gic_cpu_init(void) 495021f6537SMarc Zyngier { 496021f6537SMarc Zyngier void __iomem *rbase; 497021f6537SMarc Zyngier 498021f6537SMarc Zyngier /* Register ourselves with the rest of the world */ 499021f6537SMarc Zyngier if (gic_populate_rdist()) 500021f6537SMarc Zyngier return; 501021f6537SMarc Zyngier 502a2c22510SSudeep Holla gic_enable_redist(true); 503021f6537SMarc Zyngier 504021f6537SMarc Zyngier rbase = gic_data_rdist_sgi_base(); 505021f6537SMarc Zyngier 506021f6537SMarc Zyngier gic_cpu_config(rbase, gic_redist_wait_for_rwp); 507021f6537SMarc Zyngier 508da33f31dSMarc Zyngier /* Give LPIs a spin */ 509da33f31dSMarc Zyngier if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis()) 510da33f31dSMarc Zyngier its_cpu_init(); 511da33f31dSMarc Zyngier 5123708d52fSSudeep Holla /* initialise system registers */ 5133708d52fSSudeep Holla gic_cpu_sys_reg_init(); 514021f6537SMarc Zyngier } 515021f6537SMarc Zyngier 516021f6537SMarc Zyngier #ifdef CONFIG_SMP 517021f6537SMarc Zyngier static int gic_secondary_init(struct notifier_block *nfb, 518021f6537SMarc Zyngier unsigned long action, void *hcpu) 519021f6537SMarc Zyngier { 520021f6537SMarc Zyngier if (action == CPU_STARTING || action == CPU_STARTING_FROZEN) 521021f6537SMarc Zyngier gic_cpu_init(); 522021f6537SMarc Zyngier return NOTIFY_OK; 523021f6537SMarc Zyngier } 524021f6537SMarc Zyngier 525021f6537SMarc Zyngier /* 526021f6537SMarc Zyngier * Notifier for enabling the GIC CPU interface. Set an arbitrarily high 527021f6537SMarc Zyngier * priority because the GIC needs to be up before the ARM generic timers. 528021f6537SMarc Zyngier */ 529021f6537SMarc Zyngier static struct notifier_block gic_cpu_notifier = { 530021f6537SMarc Zyngier .notifier_call = gic_secondary_init, 531021f6537SMarc Zyngier .priority = 100, 532021f6537SMarc Zyngier }; 533021f6537SMarc Zyngier 534021f6537SMarc Zyngier static u16 gic_compute_target_list(int *base_cpu, const struct cpumask *mask, 535f6c86a41SJean-Philippe Brucker unsigned long cluster_id) 536021f6537SMarc Zyngier { 537021f6537SMarc Zyngier int cpu = *base_cpu; 538f6c86a41SJean-Philippe Brucker unsigned long mpidr = cpu_logical_map(cpu); 539021f6537SMarc Zyngier u16 tlist = 0; 540021f6537SMarc Zyngier 541021f6537SMarc Zyngier while (cpu < nr_cpu_ids) { 542021f6537SMarc Zyngier /* 543021f6537SMarc Zyngier * If we ever get a cluster of more than 16 CPUs, just 544021f6537SMarc Zyngier * scream and skip that CPU. 545021f6537SMarc Zyngier */ 546021f6537SMarc Zyngier if (WARN_ON((mpidr & 0xff) >= 16)) 547021f6537SMarc Zyngier goto out; 548021f6537SMarc Zyngier 549021f6537SMarc Zyngier tlist |= 1 << (mpidr & 0xf); 550021f6537SMarc Zyngier 551021f6537SMarc Zyngier cpu = cpumask_next(cpu, mask); 552614be385SVladimir Murzin if (cpu >= nr_cpu_ids) 553021f6537SMarc Zyngier goto out; 554021f6537SMarc Zyngier 555021f6537SMarc Zyngier mpidr = cpu_logical_map(cpu); 556021f6537SMarc Zyngier 557021f6537SMarc Zyngier if (cluster_id != (mpidr & ~0xffUL)) { 558021f6537SMarc Zyngier cpu--; 559021f6537SMarc Zyngier goto out; 560021f6537SMarc Zyngier } 561021f6537SMarc Zyngier } 562021f6537SMarc Zyngier out: 563021f6537SMarc Zyngier *base_cpu = cpu; 564021f6537SMarc Zyngier return tlist; 565021f6537SMarc Zyngier } 566021f6537SMarc Zyngier 5677e580278SAndre Przywara #define MPIDR_TO_SGI_AFFINITY(cluster_id, level) \ 5687e580278SAndre Przywara (MPIDR_AFFINITY_LEVEL(cluster_id, level) \ 5697e580278SAndre Przywara << ICC_SGI1R_AFFINITY_## level ##_SHIFT) 5707e580278SAndre Przywara 571021f6537SMarc Zyngier static void gic_send_sgi(u64 cluster_id, u16 tlist, unsigned int irq) 572021f6537SMarc Zyngier { 573021f6537SMarc Zyngier u64 val; 574021f6537SMarc Zyngier 5757e580278SAndre Przywara val = (MPIDR_TO_SGI_AFFINITY(cluster_id, 3) | 5767e580278SAndre Przywara MPIDR_TO_SGI_AFFINITY(cluster_id, 2) | 5777e580278SAndre Przywara irq << ICC_SGI1R_SGI_ID_SHIFT | 5787e580278SAndre Przywara MPIDR_TO_SGI_AFFINITY(cluster_id, 1) | 5797e580278SAndre Przywara tlist << ICC_SGI1R_TARGET_LIST_SHIFT); 580021f6537SMarc Zyngier 581021f6537SMarc Zyngier pr_debug("CPU%d: ICC_SGI1R_EL1 %llx\n", smp_processor_id(), val); 582021f6537SMarc Zyngier gic_write_sgi1r(val); 583021f6537SMarc Zyngier } 584021f6537SMarc Zyngier 585021f6537SMarc Zyngier static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) 586021f6537SMarc Zyngier { 587021f6537SMarc Zyngier int cpu; 588021f6537SMarc Zyngier 589021f6537SMarc Zyngier if (WARN_ON(irq >= 16)) 590021f6537SMarc Zyngier return; 591021f6537SMarc Zyngier 592021f6537SMarc Zyngier /* 593021f6537SMarc Zyngier * Ensure that stores to Normal memory are visible to the 594021f6537SMarc Zyngier * other CPUs before issuing the IPI. 595021f6537SMarc Zyngier */ 596021f6537SMarc Zyngier smp_wmb(); 597021f6537SMarc Zyngier 598f9b531feSRusty Russell for_each_cpu(cpu, mask) { 599f6c86a41SJean-Philippe Brucker unsigned long cluster_id = cpu_logical_map(cpu) & ~0xffUL; 600021f6537SMarc Zyngier u16 tlist; 601021f6537SMarc Zyngier 602021f6537SMarc Zyngier tlist = gic_compute_target_list(&cpu, mask, cluster_id); 603021f6537SMarc Zyngier gic_send_sgi(cluster_id, tlist, irq); 604021f6537SMarc Zyngier } 605021f6537SMarc Zyngier 606021f6537SMarc Zyngier /* Force the above writes to ICC_SGI1R_EL1 to be executed */ 607021f6537SMarc Zyngier isb(); 608021f6537SMarc Zyngier } 609021f6537SMarc Zyngier 610021f6537SMarc Zyngier static void gic_smp_init(void) 611021f6537SMarc Zyngier { 612021f6537SMarc Zyngier set_smp_cross_call(gic_raise_softirq); 613021f6537SMarc Zyngier register_cpu_notifier(&gic_cpu_notifier); 614021f6537SMarc Zyngier } 615021f6537SMarc Zyngier 616021f6537SMarc Zyngier static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, 617021f6537SMarc Zyngier bool force) 618021f6537SMarc Zyngier { 619021f6537SMarc Zyngier unsigned int cpu = cpumask_any_and(mask_val, cpu_online_mask); 620021f6537SMarc Zyngier void __iomem *reg; 621021f6537SMarc Zyngier int enabled; 622021f6537SMarc Zyngier u64 val; 623021f6537SMarc Zyngier 624021f6537SMarc Zyngier if (gic_irq_in_rdist(d)) 625021f6537SMarc Zyngier return -EINVAL; 626021f6537SMarc Zyngier 627021f6537SMarc Zyngier /* If interrupt was enabled, disable it first */ 628021f6537SMarc Zyngier enabled = gic_peek_irq(d, GICD_ISENABLER); 629021f6537SMarc Zyngier if (enabled) 630021f6537SMarc Zyngier gic_mask_irq(d); 631021f6537SMarc Zyngier 632021f6537SMarc Zyngier reg = gic_dist_base(d) + GICD_IROUTER + (gic_irq(d) * 8); 633021f6537SMarc Zyngier val = gic_mpidr_to_affinity(cpu_logical_map(cpu)); 634021f6537SMarc Zyngier 63572c97126SJean-Philippe Brucker gic_write_irouter(val, reg); 636021f6537SMarc Zyngier 637021f6537SMarc Zyngier /* 638021f6537SMarc Zyngier * If the interrupt was enabled, enabled it again. Otherwise, 639021f6537SMarc Zyngier * just wait for the distributor to have digested our changes. 640021f6537SMarc Zyngier */ 641021f6537SMarc Zyngier if (enabled) 642021f6537SMarc Zyngier gic_unmask_irq(d); 643021f6537SMarc Zyngier else 644021f6537SMarc Zyngier gic_dist_wait_for_rwp(); 645021f6537SMarc Zyngier 6460fc6fa29SAntoine Tenart return IRQ_SET_MASK_OK_DONE; 647021f6537SMarc Zyngier } 648021f6537SMarc Zyngier #else 649021f6537SMarc Zyngier #define gic_set_affinity NULL 650021f6537SMarc Zyngier #define gic_smp_init() do { } while(0) 651021f6537SMarc Zyngier #endif 652021f6537SMarc Zyngier 6533708d52fSSudeep Holla #ifdef CONFIG_CPU_PM 6543708d52fSSudeep Holla static int gic_cpu_pm_notifier(struct notifier_block *self, 6553708d52fSSudeep Holla unsigned long cmd, void *v) 6563708d52fSSudeep Holla { 6573708d52fSSudeep Holla if (cmd == CPU_PM_EXIT) { 6583708d52fSSudeep Holla gic_enable_redist(true); 6593708d52fSSudeep Holla gic_cpu_sys_reg_init(); 6603708d52fSSudeep Holla } else if (cmd == CPU_PM_ENTER) { 6613708d52fSSudeep Holla gic_write_grpen1(0); 6623708d52fSSudeep Holla gic_enable_redist(false); 6633708d52fSSudeep Holla } 6643708d52fSSudeep Holla return NOTIFY_OK; 6653708d52fSSudeep Holla } 6663708d52fSSudeep Holla 6673708d52fSSudeep Holla static struct notifier_block gic_cpu_pm_notifier_block = { 6683708d52fSSudeep Holla .notifier_call = gic_cpu_pm_notifier, 6693708d52fSSudeep Holla }; 6703708d52fSSudeep Holla 6713708d52fSSudeep Holla static void gic_cpu_pm_init(void) 6723708d52fSSudeep Holla { 6733708d52fSSudeep Holla cpu_pm_register_notifier(&gic_cpu_pm_notifier_block); 6743708d52fSSudeep Holla } 6753708d52fSSudeep Holla 6763708d52fSSudeep Holla #else 6773708d52fSSudeep Holla static inline void gic_cpu_pm_init(void) { } 6783708d52fSSudeep Holla #endif /* CONFIG_CPU_PM */ 6793708d52fSSudeep Holla 680021f6537SMarc Zyngier static struct irq_chip gic_chip = { 681021f6537SMarc Zyngier .name = "GICv3", 682021f6537SMarc Zyngier .irq_mask = gic_mask_irq, 683021f6537SMarc Zyngier .irq_unmask = gic_unmask_irq, 684021f6537SMarc Zyngier .irq_eoi = gic_eoi_irq, 685021f6537SMarc Zyngier .irq_set_type = gic_set_type, 686021f6537SMarc Zyngier .irq_set_affinity = gic_set_affinity, 687b594c6e2SMarc Zyngier .irq_get_irqchip_state = gic_irq_get_irqchip_state, 688b594c6e2SMarc Zyngier .irq_set_irqchip_state = gic_irq_set_irqchip_state, 68955963c9fSSudeep Holla .flags = IRQCHIP_SET_TYPE_MASKED, 690021f6537SMarc Zyngier }; 691021f6537SMarc Zyngier 6920b6a3da9SMarc Zyngier static struct irq_chip gic_eoimode1_chip = { 6930b6a3da9SMarc Zyngier .name = "GICv3", 6940b6a3da9SMarc Zyngier .irq_mask = gic_eoimode1_mask_irq, 6950b6a3da9SMarc Zyngier .irq_unmask = gic_unmask_irq, 6960b6a3da9SMarc Zyngier .irq_eoi = gic_eoimode1_eoi_irq, 6970b6a3da9SMarc Zyngier .irq_set_type = gic_set_type, 6980b6a3da9SMarc Zyngier .irq_set_affinity = gic_set_affinity, 6990b6a3da9SMarc Zyngier .irq_get_irqchip_state = gic_irq_get_irqchip_state, 7000b6a3da9SMarc Zyngier .irq_set_irqchip_state = gic_irq_set_irqchip_state, 701530bf353SMarc Zyngier .irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity, 7020b6a3da9SMarc Zyngier .flags = IRQCHIP_SET_TYPE_MASKED, 7030b6a3da9SMarc Zyngier }; 7040b6a3da9SMarc Zyngier 705da33f31dSMarc Zyngier #define GIC_ID_NR (1U << gic_data.rdists.id_bits) 706da33f31dSMarc Zyngier 707021f6537SMarc Zyngier static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq, 708021f6537SMarc Zyngier irq_hw_number_t hw) 709021f6537SMarc Zyngier { 7100b6a3da9SMarc Zyngier struct irq_chip *chip = &gic_chip; 7110b6a3da9SMarc Zyngier 7120b6a3da9SMarc Zyngier if (static_key_true(&supports_deactivate)) 7130b6a3da9SMarc Zyngier chip = &gic_eoimode1_chip; 7140b6a3da9SMarc Zyngier 715021f6537SMarc Zyngier /* SGIs are private to the core kernel */ 716021f6537SMarc Zyngier if (hw < 16) 717021f6537SMarc Zyngier return -EPERM; 718da33f31dSMarc Zyngier /* Nothing here */ 719da33f31dSMarc Zyngier if (hw >= gic_data.irq_nr && hw < 8192) 720da33f31dSMarc Zyngier return -EPERM; 721da33f31dSMarc Zyngier /* Off limits */ 722da33f31dSMarc Zyngier if (hw >= GIC_ID_NR) 723da33f31dSMarc Zyngier return -EPERM; 724da33f31dSMarc Zyngier 725021f6537SMarc Zyngier /* PPIs */ 726021f6537SMarc Zyngier if (hw < 32) { 727021f6537SMarc Zyngier irq_set_percpu_devid(irq); 7280b6a3da9SMarc Zyngier irq_domain_set_info(d, irq, hw, chip, d->host_data, 729443acc4fSMarc Zyngier handle_percpu_devid_irq, NULL, NULL); 730d17cab44SRob Herring irq_set_status_flags(irq, IRQ_NOAUTOEN); 731021f6537SMarc Zyngier } 732021f6537SMarc Zyngier /* SPIs */ 733021f6537SMarc Zyngier if (hw >= 32 && hw < gic_data.irq_nr) { 7340b6a3da9SMarc Zyngier irq_domain_set_info(d, irq, hw, chip, d->host_data, 735443acc4fSMarc Zyngier handle_fasteoi_irq, NULL, NULL); 736d17cab44SRob Herring irq_set_probe(irq); 737021f6537SMarc Zyngier } 738da33f31dSMarc Zyngier /* LPIs */ 739da33f31dSMarc Zyngier if (hw >= 8192 && hw < GIC_ID_NR) { 740da33f31dSMarc Zyngier if (!gic_dist_supports_lpis()) 741da33f31dSMarc Zyngier return -EPERM; 7420b6a3da9SMarc Zyngier irq_domain_set_info(d, irq, hw, chip, d->host_data, 743da33f31dSMarc Zyngier handle_fasteoi_irq, NULL, NULL); 744da33f31dSMarc Zyngier } 745da33f31dSMarc Zyngier 746021f6537SMarc Zyngier return 0; 747021f6537SMarc Zyngier } 748021f6537SMarc Zyngier 749f833f57fSMarc Zyngier static int gic_irq_domain_translate(struct irq_domain *d, 750f833f57fSMarc Zyngier struct irq_fwspec *fwspec, 751f833f57fSMarc Zyngier unsigned long *hwirq, 752f833f57fSMarc Zyngier unsigned int *type) 753021f6537SMarc Zyngier { 754f833f57fSMarc Zyngier if (is_of_node(fwspec->fwnode)) { 755f833f57fSMarc Zyngier if (fwspec->param_count < 3) 756021f6537SMarc Zyngier return -EINVAL; 757021f6537SMarc Zyngier 758db8c70ecSMarc Zyngier switch (fwspec->param[0]) { 759db8c70ecSMarc Zyngier case 0: /* SPI */ 760db8c70ecSMarc Zyngier *hwirq = fwspec->param[1] + 32; 761db8c70ecSMarc Zyngier break; 762db8c70ecSMarc Zyngier case 1: /* PPI */ 763f833f57fSMarc Zyngier *hwirq = fwspec->param[1] + 16; 764db8c70ecSMarc Zyngier break; 765db8c70ecSMarc Zyngier case GIC_IRQ_TYPE_LPI: /* LPI */ 766db8c70ecSMarc Zyngier *hwirq = fwspec->param[1]; 767db8c70ecSMarc Zyngier break; 768db8c70ecSMarc Zyngier default: 769db8c70ecSMarc Zyngier return -EINVAL; 770db8c70ecSMarc Zyngier } 771f833f57fSMarc Zyngier 772f833f57fSMarc Zyngier *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; 773f833f57fSMarc Zyngier return 0; 774021f6537SMarc Zyngier } 775021f6537SMarc Zyngier 776ffa7d616STomasz Nowicki if (is_fwnode_irqchip(fwspec->fwnode)) { 777ffa7d616STomasz Nowicki if(fwspec->param_count != 2) 778ffa7d616STomasz Nowicki return -EINVAL; 779ffa7d616STomasz Nowicki 780ffa7d616STomasz Nowicki *hwirq = fwspec->param[0]; 781ffa7d616STomasz Nowicki *type = fwspec->param[1]; 782ffa7d616STomasz Nowicki return 0; 783ffa7d616STomasz Nowicki } 784ffa7d616STomasz Nowicki 785f833f57fSMarc Zyngier return -EINVAL; 786021f6537SMarc Zyngier } 787021f6537SMarc Zyngier 788443acc4fSMarc Zyngier static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, 789443acc4fSMarc Zyngier unsigned int nr_irqs, void *arg) 790443acc4fSMarc Zyngier { 791443acc4fSMarc Zyngier int i, ret; 792443acc4fSMarc Zyngier irq_hw_number_t hwirq; 793443acc4fSMarc Zyngier unsigned int type = IRQ_TYPE_NONE; 794f833f57fSMarc Zyngier struct irq_fwspec *fwspec = arg; 795443acc4fSMarc Zyngier 796f833f57fSMarc Zyngier ret = gic_irq_domain_translate(domain, fwspec, &hwirq, &type); 797443acc4fSMarc Zyngier if (ret) 798443acc4fSMarc Zyngier return ret; 799443acc4fSMarc Zyngier 800443acc4fSMarc Zyngier for (i = 0; i < nr_irqs; i++) 801443acc4fSMarc Zyngier gic_irq_domain_map(domain, virq + i, hwirq + i); 802443acc4fSMarc Zyngier 803443acc4fSMarc Zyngier return 0; 804443acc4fSMarc Zyngier } 805443acc4fSMarc Zyngier 806443acc4fSMarc Zyngier static void gic_irq_domain_free(struct irq_domain *domain, unsigned int virq, 807443acc4fSMarc Zyngier unsigned int nr_irqs) 808443acc4fSMarc Zyngier { 809443acc4fSMarc Zyngier int i; 810443acc4fSMarc Zyngier 811443acc4fSMarc Zyngier for (i = 0; i < nr_irqs; i++) { 812443acc4fSMarc Zyngier struct irq_data *d = irq_domain_get_irq_data(domain, virq + i); 813443acc4fSMarc Zyngier irq_set_handler(virq + i, NULL); 814443acc4fSMarc Zyngier irq_domain_reset_irq_data(d); 815443acc4fSMarc Zyngier } 816443acc4fSMarc Zyngier } 817443acc4fSMarc Zyngier 818e3825ba1SMarc Zyngier static int gic_irq_domain_select(struct irq_domain *d, 819e3825ba1SMarc Zyngier struct irq_fwspec *fwspec, 820e3825ba1SMarc Zyngier enum irq_domain_bus_token bus_token) 821e3825ba1SMarc Zyngier { 822e3825ba1SMarc Zyngier /* Not for us */ 823e3825ba1SMarc Zyngier if (fwspec->fwnode != d->fwnode) 824e3825ba1SMarc Zyngier return 0; 825e3825ba1SMarc Zyngier 826e3825ba1SMarc Zyngier /* If this is not DT, then we have a single domain */ 827e3825ba1SMarc Zyngier if (!is_of_node(fwspec->fwnode)) 828e3825ba1SMarc Zyngier return 1; 829e3825ba1SMarc Zyngier 830e3825ba1SMarc Zyngier /* 831e3825ba1SMarc Zyngier * If this is a PPI and we have a 4th (non-null) parameter, 832e3825ba1SMarc Zyngier * then we need to match the partition domain. 833e3825ba1SMarc Zyngier */ 834e3825ba1SMarc Zyngier if (fwspec->param_count >= 4 && 835e3825ba1SMarc Zyngier fwspec->param[0] == 1 && fwspec->param[3] != 0) 836e3825ba1SMarc Zyngier return d == partition_get_domain(gic_data.ppi_descs[fwspec->param[1]]); 837e3825ba1SMarc Zyngier 838e3825ba1SMarc Zyngier return d == gic_data.domain; 839e3825ba1SMarc Zyngier } 840e3825ba1SMarc Zyngier 841021f6537SMarc Zyngier static const struct irq_domain_ops gic_irq_domain_ops = { 842f833f57fSMarc Zyngier .translate = gic_irq_domain_translate, 843443acc4fSMarc Zyngier .alloc = gic_irq_domain_alloc, 844443acc4fSMarc Zyngier .free = gic_irq_domain_free, 845e3825ba1SMarc Zyngier .select = gic_irq_domain_select, 846e3825ba1SMarc Zyngier }; 847e3825ba1SMarc Zyngier 848e3825ba1SMarc Zyngier static int partition_domain_translate(struct irq_domain *d, 849e3825ba1SMarc Zyngier struct irq_fwspec *fwspec, 850e3825ba1SMarc Zyngier unsigned long *hwirq, 851e3825ba1SMarc Zyngier unsigned int *type) 852e3825ba1SMarc Zyngier { 853e3825ba1SMarc Zyngier struct device_node *np; 854e3825ba1SMarc Zyngier int ret; 855e3825ba1SMarc Zyngier 856e3825ba1SMarc Zyngier np = of_find_node_by_phandle(fwspec->param[3]); 857e3825ba1SMarc Zyngier if (WARN_ON(!np)) 858e3825ba1SMarc Zyngier return -EINVAL; 859e3825ba1SMarc Zyngier 860e3825ba1SMarc Zyngier ret = partition_translate_id(gic_data.ppi_descs[fwspec->param[1]], 861e3825ba1SMarc Zyngier of_node_to_fwnode(np)); 862e3825ba1SMarc Zyngier if (ret < 0) 863e3825ba1SMarc Zyngier return ret; 864e3825ba1SMarc Zyngier 865e3825ba1SMarc Zyngier *hwirq = ret; 866e3825ba1SMarc Zyngier *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; 867e3825ba1SMarc Zyngier 868e3825ba1SMarc Zyngier return 0; 869e3825ba1SMarc Zyngier } 870e3825ba1SMarc Zyngier 871e3825ba1SMarc Zyngier static const struct irq_domain_ops partition_domain_ops = { 872e3825ba1SMarc Zyngier .translate = partition_domain_translate, 873e3825ba1SMarc Zyngier .select = gic_irq_domain_select, 874021f6537SMarc Zyngier }; 875021f6537SMarc Zyngier 8766d4e11c5SRobert Richter static void gicv3_enable_quirks(void) 8776d4e11c5SRobert Richter { 8787936e914SJean-Philippe Brucker #ifdef CONFIG_ARM64 8796d4e11c5SRobert Richter if (cpus_have_cap(ARM64_WORKAROUND_CAVIUM_23154)) 8808ac2a170SRobert Richter static_branch_enable(&is_cavium_thunderx); 8817936e914SJean-Philippe Brucker #endif 8826d4e11c5SRobert Richter } 8836d4e11c5SRobert Richter 884db57d746STomasz Nowicki static int __init gic_init_bases(void __iomem *dist_base, 885db57d746STomasz Nowicki struct redist_region *rdist_regs, 886db57d746STomasz Nowicki u32 nr_redist_regions, 887db57d746STomasz Nowicki u64 redist_stride, 888db57d746STomasz Nowicki struct fwnode_handle *handle) 889db57d746STomasz Nowicki { 890db57d746STomasz Nowicki struct device_node *node; 891db57d746STomasz Nowicki u32 typer; 892db57d746STomasz Nowicki int gic_irqs; 893db57d746STomasz Nowicki int err; 894db57d746STomasz Nowicki 895db57d746STomasz Nowicki if (!is_hyp_mode_available()) 896db57d746STomasz Nowicki static_key_slow_dec(&supports_deactivate); 897db57d746STomasz Nowicki 898db57d746STomasz Nowicki if (static_key_true(&supports_deactivate)) 899db57d746STomasz Nowicki pr_info("GIC: Using split EOI/Deactivate mode\n"); 900db57d746STomasz Nowicki 901e3825ba1SMarc Zyngier gic_data.fwnode = handle; 902db57d746STomasz Nowicki gic_data.dist_base = dist_base; 903db57d746STomasz Nowicki gic_data.redist_regions = rdist_regs; 904db57d746STomasz Nowicki gic_data.nr_redist_regions = nr_redist_regions; 905db57d746STomasz Nowicki gic_data.redist_stride = redist_stride; 906db57d746STomasz Nowicki 907db57d746STomasz Nowicki gicv3_enable_quirks(); 908db57d746STomasz Nowicki 909db57d746STomasz Nowicki /* 910db57d746STomasz Nowicki * Find out how many interrupts are supported. 911db57d746STomasz Nowicki * The GIC only supports up to 1020 interrupt sources (SGI+PPI+SPI) 912db57d746STomasz Nowicki */ 913db57d746STomasz Nowicki typer = readl_relaxed(gic_data.dist_base + GICD_TYPER); 914db57d746STomasz Nowicki gic_data.rdists.id_bits = GICD_TYPER_ID_BITS(typer); 915db57d746STomasz Nowicki gic_irqs = GICD_TYPER_IRQS(typer); 916db57d746STomasz Nowicki if (gic_irqs > 1020) 917db57d746STomasz Nowicki gic_irqs = 1020; 918db57d746STomasz Nowicki gic_data.irq_nr = gic_irqs; 919db57d746STomasz Nowicki 920db57d746STomasz Nowicki gic_data.domain = irq_domain_create_tree(handle, &gic_irq_domain_ops, 921db57d746STomasz Nowicki &gic_data); 922db57d746STomasz Nowicki gic_data.rdists.rdist = alloc_percpu(typeof(*gic_data.rdists.rdist)); 923db57d746STomasz Nowicki 924db57d746STomasz Nowicki if (WARN_ON(!gic_data.domain) || WARN_ON(!gic_data.rdists.rdist)) { 925db57d746STomasz Nowicki err = -ENOMEM; 926db57d746STomasz Nowicki goto out_free; 927db57d746STomasz Nowicki } 928db57d746STomasz Nowicki 929db57d746STomasz Nowicki set_handle_irq(gic_handle_irq); 930db57d746STomasz Nowicki 931db57d746STomasz Nowicki node = to_of_node(handle); 932db57d746STomasz Nowicki if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis() && 933db57d746STomasz Nowicki node) /* Temp hack to prevent ITS init for ACPI */ 934db57d746STomasz Nowicki its_init(node, &gic_data.rdists, gic_data.domain); 935db57d746STomasz Nowicki 936db57d746STomasz Nowicki gic_smp_init(); 937db57d746STomasz Nowicki gic_dist_init(); 938db57d746STomasz Nowicki gic_cpu_init(); 939db57d746STomasz Nowicki gic_cpu_pm_init(); 940db57d746STomasz Nowicki 941db57d746STomasz Nowicki return 0; 942db57d746STomasz Nowicki 943db57d746STomasz Nowicki out_free: 944db57d746STomasz Nowicki if (gic_data.domain) 945db57d746STomasz Nowicki irq_domain_remove(gic_data.domain); 946db57d746STomasz Nowicki free_percpu(gic_data.rdists.rdist); 947db57d746STomasz Nowicki return err; 948db57d746STomasz Nowicki } 949db57d746STomasz Nowicki 950db57d746STomasz Nowicki static int __init gic_validate_dist_version(void __iomem *dist_base) 951db57d746STomasz Nowicki { 952db57d746STomasz Nowicki u32 reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK; 953db57d746STomasz Nowicki 954db57d746STomasz Nowicki if (reg != GIC_PIDR2_ARCH_GICv3 && reg != GIC_PIDR2_ARCH_GICv4) 955db57d746STomasz Nowicki return -ENODEV; 956db57d746STomasz Nowicki 957db57d746STomasz Nowicki return 0; 958db57d746STomasz Nowicki } 959db57d746STomasz Nowicki 960e3825ba1SMarc Zyngier static int get_cpu_number(struct device_node *dn) 961e3825ba1SMarc Zyngier { 962e3825ba1SMarc Zyngier const __be32 *cell; 963e3825ba1SMarc Zyngier u64 hwid; 964e3825ba1SMarc Zyngier int i; 965e3825ba1SMarc Zyngier 966e3825ba1SMarc Zyngier cell = of_get_property(dn, "reg", NULL); 967e3825ba1SMarc Zyngier if (!cell) 968e3825ba1SMarc Zyngier return -1; 969e3825ba1SMarc Zyngier 970e3825ba1SMarc Zyngier hwid = of_read_number(cell, of_n_addr_cells(dn)); 971e3825ba1SMarc Zyngier 972e3825ba1SMarc Zyngier /* 973e3825ba1SMarc Zyngier * Non affinity bits must be set to 0 in the DT 974e3825ba1SMarc Zyngier */ 975e3825ba1SMarc Zyngier if (hwid & ~MPIDR_HWID_BITMASK) 976e3825ba1SMarc Zyngier return -1; 977e3825ba1SMarc Zyngier 978e3825ba1SMarc Zyngier for (i = 0; i < num_possible_cpus(); i++) 979e3825ba1SMarc Zyngier if (cpu_logical_map(i) == hwid) 980e3825ba1SMarc Zyngier return i; 981e3825ba1SMarc Zyngier 982e3825ba1SMarc Zyngier return -1; 983e3825ba1SMarc Zyngier } 984e3825ba1SMarc Zyngier 985e3825ba1SMarc Zyngier /* Create all possible partitions at boot time */ 986e3825ba1SMarc Zyngier static void gic_populate_ppi_partitions(struct device_node *gic_node) 987e3825ba1SMarc Zyngier { 988e3825ba1SMarc Zyngier struct device_node *parts_node, *child_part; 989e3825ba1SMarc Zyngier int part_idx = 0, i; 990e3825ba1SMarc Zyngier int nr_parts; 991e3825ba1SMarc Zyngier struct partition_affinity *parts; 992e3825ba1SMarc Zyngier 993e3825ba1SMarc Zyngier parts_node = of_find_node_by_name(gic_node, "ppi-partitions"); 994e3825ba1SMarc Zyngier if (!parts_node) 995e3825ba1SMarc Zyngier return; 996e3825ba1SMarc Zyngier 997e3825ba1SMarc Zyngier nr_parts = of_get_child_count(parts_node); 998e3825ba1SMarc Zyngier 999e3825ba1SMarc Zyngier if (!nr_parts) 1000e3825ba1SMarc Zyngier return; 1001e3825ba1SMarc Zyngier 1002e3825ba1SMarc Zyngier parts = kzalloc(sizeof(*parts) * nr_parts, GFP_KERNEL); 1003e3825ba1SMarc Zyngier if (WARN_ON(!parts)) 1004e3825ba1SMarc Zyngier return; 1005e3825ba1SMarc Zyngier 1006e3825ba1SMarc Zyngier for_each_child_of_node(parts_node, child_part) { 1007e3825ba1SMarc Zyngier struct partition_affinity *part; 1008e3825ba1SMarc Zyngier int n; 1009e3825ba1SMarc Zyngier 1010e3825ba1SMarc Zyngier part = &parts[part_idx]; 1011e3825ba1SMarc Zyngier 1012e3825ba1SMarc Zyngier part->partition_id = of_node_to_fwnode(child_part); 1013e3825ba1SMarc Zyngier 1014e3825ba1SMarc Zyngier pr_info("GIC: PPI partition %s[%d] { ", 1015e3825ba1SMarc Zyngier child_part->name, part_idx); 1016e3825ba1SMarc Zyngier 1017e3825ba1SMarc Zyngier n = of_property_count_elems_of_size(child_part, "affinity", 1018e3825ba1SMarc Zyngier sizeof(u32)); 1019e3825ba1SMarc Zyngier WARN_ON(n <= 0); 1020e3825ba1SMarc Zyngier 1021e3825ba1SMarc Zyngier for (i = 0; i < n; i++) { 1022e3825ba1SMarc Zyngier int err, cpu; 1023e3825ba1SMarc Zyngier u32 cpu_phandle; 1024e3825ba1SMarc Zyngier struct device_node *cpu_node; 1025e3825ba1SMarc Zyngier 1026e3825ba1SMarc Zyngier err = of_property_read_u32_index(child_part, "affinity", 1027e3825ba1SMarc Zyngier i, &cpu_phandle); 1028e3825ba1SMarc Zyngier if (WARN_ON(err)) 1029e3825ba1SMarc Zyngier continue; 1030e3825ba1SMarc Zyngier 1031e3825ba1SMarc Zyngier cpu_node = of_find_node_by_phandle(cpu_phandle); 1032e3825ba1SMarc Zyngier if (WARN_ON(!cpu_node)) 1033e3825ba1SMarc Zyngier continue; 1034e3825ba1SMarc Zyngier 1035e3825ba1SMarc Zyngier cpu = get_cpu_number(cpu_node); 1036e3825ba1SMarc Zyngier if (WARN_ON(cpu == -1)) 1037e3825ba1SMarc Zyngier continue; 1038e3825ba1SMarc Zyngier 1039e3825ba1SMarc Zyngier pr_cont("%s[%d] ", cpu_node->full_name, cpu); 1040e3825ba1SMarc Zyngier 1041e3825ba1SMarc Zyngier cpumask_set_cpu(cpu, &part->mask); 1042e3825ba1SMarc Zyngier } 1043e3825ba1SMarc Zyngier 1044e3825ba1SMarc Zyngier pr_cont("}\n"); 1045e3825ba1SMarc Zyngier part_idx++; 1046e3825ba1SMarc Zyngier } 1047e3825ba1SMarc Zyngier 1048e3825ba1SMarc Zyngier for (i = 0; i < 16; i++) { 1049e3825ba1SMarc Zyngier unsigned int irq; 1050e3825ba1SMarc Zyngier struct partition_desc *desc; 1051e3825ba1SMarc Zyngier struct irq_fwspec ppi_fwspec = { 1052e3825ba1SMarc Zyngier .fwnode = gic_data.fwnode, 1053e3825ba1SMarc Zyngier .param_count = 3, 1054e3825ba1SMarc Zyngier .param = { 1055e3825ba1SMarc Zyngier [0] = 1, 1056e3825ba1SMarc Zyngier [1] = i, 1057e3825ba1SMarc Zyngier [2] = IRQ_TYPE_NONE, 1058e3825ba1SMarc Zyngier }, 1059e3825ba1SMarc Zyngier }; 1060e3825ba1SMarc Zyngier 1061e3825ba1SMarc Zyngier irq = irq_create_fwspec_mapping(&ppi_fwspec); 1062e3825ba1SMarc Zyngier if (WARN_ON(!irq)) 1063e3825ba1SMarc Zyngier continue; 1064e3825ba1SMarc Zyngier desc = partition_create_desc(gic_data.fwnode, parts, nr_parts, 1065e3825ba1SMarc Zyngier irq, &partition_domain_ops); 1066e3825ba1SMarc Zyngier if (WARN_ON(!desc)) 1067e3825ba1SMarc Zyngier continue; 1068e3825ba1SMarc Zyngier 1069e3825ba1SMarc Zyngier gic_data.ppi_descs[i] = desc; 1070e3825ba1SMarc Zyngier } 1071e3825ba1SMarc Zyngier } 1072e3825ba1SMarc Zyngier 1073021f6537SMarc Zyngier static int __init gic_of_init(struct device_node *node, struct device_node *parent) 1074021f6537SMarc Zyngier { 1075021f6537SMarc Zyngier void __iomem *dist_base; 1076f5c1434cSMarc Zyngier struct redist_region *rdist_regs; 1077021f6537SMarc Zyngier u64 redist_stride; 1078f5c1434cSMarc Zyngier u32 nr_redist_regions; 1079db57d746STomasz Nowicki int err, i; 1080021f6537SMarc Zyngier 1081021f6537SMarc Zyngier dist_base = of_iomap(node, 0); 1082021f6537SMarc Zyngier if (!dist_base) { 1083021f6537SMarc Zyngier pr_err("%s: unable to map gic dist registers\n", 1084021f6537SMarc Zyngier node->full_name); 1085021f6537SMarc Zyngier return -ENXIO; 1086021f6537SMarc Zyngier } 1087021f6537SMarc Zyngier 1088db57d746STomasz Nowicki err = gic_validate_dist_version(dist_base); 1089db57d746STomasz Nowicki if (err) { 1090021f6537SMarc Zyngier pr_err("%s: no distributor detected, giving up\n", 1091021f6537SMarc Zyngier node->full_name); 1092021f6537SMarc Zyngier goto out_unmap_dist; 1093021f6537SMarc Zyngier } 1094021f6537SMarc Zyngier 1095f5c1434cSMarc Zyngier if (of_property_read_u32(node, "#redistributor-regions", &nr_redist_regions)) 1096f5c1434cSMarc Zyngier nr_redist_regions = 1; 1097021f6537SMarc Zyngier 1098f5c1434cSMarc Zyngier rdist_regs = kzalloc(sizeof(*rdist_regs) * nr_redist_regions, GFP_KERNEL); 1099f5c1434cSMarc Zyngier if (!rdist_regs) { 1100021f6537SMarc Zyngier err = -ENOMEM; 1101021f6537SMarc Zyngier goto out_unmap_dist; 1102021f6537SMarc Zyngier } 1103021f6537SMarc Zyngier 1104f5c1434cSMarc Zyngier for (i = 0; i < nr_redist_regions; i++) { 1105f5c1434cSMarc Zyngier struct resource res; 1106f5c1434cSMarc Zyngier int ret; 1107f5c1434cSMarc Zyngier 1108f5c1434cSMarc Zyngier ret = of_address_to_resource(node, 1 + i, &res); 1109f5c1434cSMarc Zyngier rdist_regs[i].redist_base = of_iomap(node, 1 + i); 1110f5c1434cSMarc Zyngier if (ret || !rdist_regs[i].redist_base) { 1111021f6537SMarc Zyngier pr_err("%s: couldn't map region %d\n", 1112021f6537SMarc Zyngier node->full_name, i); 1113021f6537SMarc Zyngier err = -ENODEV; 1114021f6537SMarc Zyngier goto out_unmap_rdist; 1115021f6537SMarc Zyngier } 1116f5c1434cSMarc Zyngier rdist_regs[i].phys_base = res.start; 1117021f6537SMarc Zyngier } 1118021f6537SMarc Zyngier 1119021f6537SMarc Zyngier if (of_property_read_u64(node, "redistributor-stride", &redist_stride)) 1120021f6537SMarc Zyngier redist_stride = 0; 1121021f6537SMarc Zyngier 1122db57d746STomasz Nowicki err = gic_init_bases(dist_base, rdist_regs, nr_redist_regions, 1123db57d746STomasz Nowicki redist_stride, &node->fwnode); 1124e3825ba1SMarc Zyngier if (err) 1125e3825ba1SMarc Zyngier goto out_unmap_rdist; 1126e3825ba1SMarc Zyngier 1127e3825ba1SMarc Zyngier gic_populate_ppi_partitions(node); 1128021f6537SMarc Zyngier return 0; 1129021f6537SMarc Zyngier 1130021f6537SMarc Zyngier out_unmap_rdist: 1131f5c1434cSMarc Zyngier for (i = 0; i < nr_redist_regions; i++) 1132f5c1434cSMarc Zyngier if (rdist_regs[i].redist_base) 1133f5c1434cSMarc Zyngier iounmap(rdist_regs[i].redist_base); 1134f5c1434cSMarc Zyngier kfree(rdist_regs); 1135021f6537SMarc Zyngier out_unmap_dist: 1136021f6537SMarc Zyngier iounmap(dist_base); 1137021f6537SMarc Zyngier return err; 1138021f6537SMarc Zyngier } 1139021f6537SMarc Zyngier 1140021f6537SMarc Zyngier IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init); 1141ffa7d616STomasz Nowicki 1142ffa7d616STomasz Nowicki #ifdef CONFIG_ACPI 1143b70fb7afSTomasz Nowicki static void __iomem *dist_base; 1144ffa7d616STomasz Nowicki static struct redist_region *redist_regs __initdata; 1145ffa7d616STomasz Nowicki static u32 nr_redist_regions __initdata; 1146b70fb7afSTomasz Nowicki static bool single_redist; 1147b70fb7afSTomasz Nowicki 1148b70fb7afSTomasz Nowicki static void __init 1149b70fb7afSTomasz Nowicki gic_acpi_register_redist(phys_addr_t phys_base, void __iomem *redist_base) 1150b70fb7afSTomasz Nowicki { 1151b70fb7afSTomasz Nowicki static int count = 0; 1152b70fb7afSTomasz Nowicki 1153b70fb7afSTomasz Nowicki redist_regs[count].phys_base = phys_base; 1154b70fb7afSTomasz Nowicki redist_regs[count].redist_base = redist_base; 1155b70fb7afSTomasz Nowicki redist_regs[count].single_redist = single_redist; 1156b70fb7afSTomasz Nowicki count++; 1157b70fb7afSTomasz Nowicki } 1158ffa7d616STomasz Nowicki 1159ffa7d616STomasz Nowicki static int __init 1160ffa7d616STomasz Nowicki gic_acpi_parse_madt_redist(struct acpi_subtable_header *header, 1161ffa7d616STomasz Nowicki const unsigned long end) 1162ffa7d616STomasz Nowicki { 1163ffa7d616STomasz Nowicki struct acpi_madt_generic_redistributor *redist = 1164ffa7d616STomasz Nowicki (struct acpi_madt_generic_redistributor *)header; 1165ffa7d616STomasz Nowicki void __iomem *redist_base; 1166ffa7d616STomasz Nowicki 1167ffa7d616STomasz Nowicki redist_base = ioremap(redist->base_address, redist->length); 1168ffa7d616STomasz Nowicki if (!redist_base) { 1169ffa7d616STomasz Nowicki pr_err("Couldn't map GICR region @%llx\n", redist->base_address); 1170ffa7d616STomasz Nowicki return -ENOMEM; 1171ffa7d616STomasz Nowicki } 1172ffa7d616STomasz Nowicki 1173b70fb7afSTomasz Nowicki gic_acpi_register_redist(redist->base_address, redist_base); 1174ffa7d616STomasz Nowicki return 0; 1175ffa7d616STomasz Nowicki } 1176ffa7d616STomasz Nowicki 1177b70fb7afSTomasz Nowicki static int __init 1178b70fb7afSTomasz Nowicki gic_acpi_parse_madt_gicc(struct acpi_subtable_header *header, 1179b70fb7afSTomasz Nowicki const unsigned long end) 1180b70fb7afSTomasz Nowicki { 1181b70fb7afSTomasz Nowicki struct acpi_madt_generic_interrupt *gicc = 1182b70fb7afSTomasz Nowicki (struct acpi_madt_generic_interrupt *)header; 1183b70fb7afSTomasz Nowicki u32 reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK; 1184b70fb7afSTomasz Nowicki u32 size = reg == GIC_PIDR2_ARCH_GICv4 ? SZ_64K * 4 : SZ_64K * 2; 1185b70fb7afSTomasz Nowicki void __iomem *redist_base; 1186b70fb7afSTomasz Nowicki 1187b70fb7afSTomasz Nowicki redist_base = ioremap(gicc->gicr_base_address, size); 1188b70fb7afSTomasz Nowicki if (!redist_base) 1189b70fb7afSTomasz Nowicki return -ENOMEM; 1190b70fb7afSTomasz Nowicki 1191b70fb7afSTomasz Nowicki gic_acpi_register_redist(gicc->gicr_base_address, redist_base); 1192b70fb7afSTomasz Nowicki return 0; 1193b70fb7afSTomasz Nowicki } 1194b70fb7afSTomasz Nowicki 1195b70fb7afSTomasz Nowicki static int __init gic_acpi_collect_gicr_base(void) 1196b70fb7afSTomasz Nowicki { 1197b70fb7afSTomasz Nowicki acpi_tbl_entry_handler redist_parser; 1198b70fb7afSTomasz Nowicki enum acpi_madt_type type; 1199b70fb7afSTomasz Nowicki 1200b70fb7afSTomasz Nowicki if (single_redist) { 1201b70fb7afSTomasz Nowicki type = ACPI_MADT_TYPE_GENERIC_INTERRUPT; 1202b70fb7afSTomasz Nowicki redist_parser = gic_acpi_parse_madt_gicc; 1203b70fb7afSTomasz Nowicki } else { 1204b70fb7afSTomasz Nowicki type = ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR; 1205b70fb7afSTomasz Nowicki redist_parser = gic_acpi_parse_madt_redist; 1206b70fb7afSTomasz Nowicki } 1207b70fb7afSTomasz Nowicki 1208b70fb7afSTomasz Nowicki /* Collect redistributor base addresses in GICR entries */ 1209b70fb7afSTomasz Nowicki if (acpi_table_parse_madt(type, redist_parser, 0) > 0) 1210b70fb7afSTomasz Nowicki return 0; 1211b70fb7afSTomasz Nowicki 1212b70fb7afSTomasz Nowicki pr_info("No valid GICR entries exist\n"); 1213b70fb7afSTomasz Nowicki return -ENODEV; 1214b70fb7afSTomasz Nowicki } 1215b70fb7afSTomasz Nowicki 1216ffa7d616STomasz Nowicki static int __init gic_acpi_match_gicr(struct acpi_subtable_header *header, 1217ffa7d616STomasz Nowicki const unsigned long end) 1218ffa7d616STomasz Nowicki { 1219ffa7d616STomasz Nowicki /* Subtable presence means that redist exists, that's it */ 1220ffa7d616STomasz Nowicki return 0; 1221ffa7d616STomasz Nowicki } 1222ffa7d616STomasz Nowicki 1223b70fb7afSTomasz Nowicki static int __init gic_acpi_match_gicc(struct acpi_subtable_header *header, 1224b70fb7afSTomasz Nowicki const unsigned long end) 1225b70fb7afSTomasz Nowicki { 1226b70fb7afSTomasz Nowicki struct acpi_madt_generic_interrupt *gicc = 1227b70fb7afSTomasz Nowicki (struct acpi_madt_generic_interrupt *)header; 1228b70fb7afSTomasz Nowicki 1229b70fb7afSTomasz Nowicki /* 1230b70fb7afSTomasz Nowicki * If GICC is enabled and has valid gicr base address, then it means 1231b70fb7afSTomasz Nowicki * GICR base is presented via GICC 1232b70fb7afSTomasz Nowicki */ 1233b70fb7afSTomasz Nowicki if ((gicc->flags & ACPI_MADT_ENABLED) && gicc->gicr_base_address) 1234b70fb7afSTomasz Nowicki return 0; 1235b70fb7afSTomasz Nowicki 1236b70fb7afSTomasz Nowicki return -ENODEV; 1237b70fb7afSTomasz Nowicki } 1238b70fb7afSTomasz Nowicki 1239b70fb7afSTomasz Nowicki static int __init gic_acpi_count_gicr_regions(void) 1240b70fb7afSTomasz Nowicki { 1241b70fb7afSTomasz Nowicki int count; 1242b70fb7afSTomasz Nowicki 1243b70fb7afSTomasz Nowicki /* 1244b70fb7afSTomasz Nowicki * Count how many redistributor regions we have. It is not allowed 1245b70fb7afSTomasz Nowicki * to mix redistributor description, GICR and GICC subtables have to be 1246b70fb7afSTomasz Nowicki * mutually exclusive. 1247b70fb7afSTomasz Nowicki */ 1248b70fb7afSTomasz Nowicki count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR, 1249b70fb7afSTomasz Nowicki gic_acpi_match_gicr, 0); 1250b70fb7afSTomasz Nowicki if (count > 0) { 1251b70fb7afSTomasz Nowicki single_redist = false; 1252b70fb7afSTomasz Nowicki return count; 1253b70fb7afSTomasz Nowicki } 1254b70fb7afSTomasz Nowicki 1255b70fb7afSTomasz Nowicki count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT, 1256b70fb7afSTomasz Nowicki gic_acpi_match_gicc, 0); 1257b70fb7afSTomasz Nowicki if (count > 0) 1258b70fb7afSTomasz Nowicki single_redist = true; 1259b70fb7afSTomasz Nowicki 1260b70fb7afSTomasz Nowicki return count; 1261b70fb7afSTomasz Nowicki } 1262b70fb7afSTomasz Nowicki 1263ffa7d616STomasz Nowicki static bool __init acpi_validate_gic_table(struct acpi_subtable_header *header, 1264ffa7d616STomasz Nowicki struct acpi_probe_entry *ape) 1265ffa7d616STomasz Nowicki { 1266ffa7d616STomasz Nowicki struct acpi_madt_generic_distributor *dist; 1267ffa7d616STomasz Nowicki int count; 1268ffa7d616STomasz Nowicki 1269ffa7d616STomasz Nowicki dist = (struct acpi_madt_generic_distributor *)header; 1270ffa7d616STomasz Nowicki if (dist->version != ape->driver_data) 1271ffa7d616STomasz Nowicki return false; 1272ffa7d616STomasz Nowicki 1273ffa7d616STomasz Nowicki /* We need to do that exercise anyway, the sooner the better */ 1274b70fb7afSTomasz Nowicki count = gic_acpi_count_gicr_regions(); 1275ffa7d616STomasz Nowicki if (count <= 0) 1276ffa7d616STomasz Nowicki return false; 1277ffa7d616STomasz Nowicki 1278ffa7d616STomasz Nowicki nr_redist_regions = count; 1279ffa7d616STomasz Nowicki return true; 1280ffa7d616STomasz Nowicki } 1281ffa7d616STomasz Nowicki 1282ffa7d616STomasz Nowicki #define ACPI_GICV3_DIST_MEM_SIZE (SZ_64K) 1283ffa7d616STomasz Nowicki 1284ffa7d616STomasz Nowicki static int __init 1285ffa7d616STomasz Nowicki gic_acpi_init(struct acpi_subtable_header *header, const unsigned long end) 1286ffa7d616STomasz Nowicki { 1287ffa7d616STomasz Nowicki struct acpi_madt_generic_distributor *dist; 1288ffa7d616STomasz Nowicki struct fwnode_handle *domain_handle; 1289b70fb7afSTomasz Nowicki int i, err; 1290ffa7d616STomasz Nowicki 1291ffa7d616STomasz Nowicki /* Get distributor base address */ 1292ffa7d616STomasz Nowicki dist = (struct acpi_madt_generic_distributor *)header; 1293ffa7d616STomasz Nowicki dist_base = ioremap(dist->base_address, ACPI_GICV3_DIST_MEM_SIZE); 1294ffa7d616STomasz Nowicki if (!dist_base) { 1295ffa7d616STomasz Nowicki pr_err("Unable to map GICD registers\n"); 1296ffa7d616STomasz Nowicki return -ENOMEM; 1297ffa7d616STomasz Nowicki } 1298ffa7d616STomasz Nowicki 1299ffa7d616STomasz Nowicki err = gic_validate_dist_version(dist_base); 1300ffa7d616STomasz Nowicki if (err) { 1301ffa7d616STomasz Nowicki pr_err("No distributor detected at @%p, giving up", dist_base); 1302ffa7d616STomasz Nowicki goto out_dist_unmap; 1303ffa7d616STomasz Nowicki } 1304ffa7d616STomasz Nowicki 1305ffa7d616STomasz Nowicki redist_regs = kzalloc(sizeof(*redist_regs) * nr_redist_regions, 1306ffa7d616STomasz Nowicki GFP_KERNEL); 1307ffa7d616STomasz Nowicki if (!redist_regs) { 1308ffa7d616STomasz Nowicki err = -ENOMEM; 1309ffa7d616STomasz Nowicki goto out_dist_unmap; 1310ffa7d616STomasz Nowicki } 1311ffa7d616STomasz Nowicki 1312b70fb7afSTomasz Nowicki err = gic_acpi_collect_gicr_base(); 1313b70fb7afSTomasz Nowicki if (err) 1314ffa7d616STomasz Nowicki goto out_redist_unmap; 1315ffa7d616STomasz Nowicki 1316ffa7d616STomasz Nowicki domain_handle = irq_domain_alloc_fwnode(dist_base); 1317ffa7d616STomasz Nowicki if (!domain_handle) { 1318ffa7d616STomasz Nowicki err = -ENOMEM; 1319ffa7d616STomasz Nowicki goto out_redist_unmap; 1320ffa7d616STomasz Nowicki } 1321ffa7d616STomasz Nowicki 1322ffa7d616STomasz Nowicki err = gic_init_bases(dist_base, redist_regs, nr_redist_regions, 0, 1323ffa7d616STomasz Nowicki domain_handle); 1324ffa7d616STomasz Nowicki if (err) 1325ffa7d616STomasz Nowicki goto out_fwhandle_free; 1326ffa7d616STomasz Nowicki 1327ffa7d616STomasz Nowicki acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, domain_handle); 1328ffa7d616STomasz Nowicki return 0; 1329ffa7d616STomasz Nowicki 1330ffa7d616STomasz Nowicki out_fwhandle_free: 1331ffa7d616STomasz Nowicki irq_domain_free_fwnode(domain_handle); 1332ffa7d616STomasz Nowicki out_redist_unmap: 1333ffa7d616STomasz Nowicki for (i = 0; i < nr_redist_regions; i++) 1334ffa7d616STomasz Nowicki if (redist_regs[i].redist_base) 1335ffa7d616STomasz Nowicki iounmap(redist_regs[i].redist_base); 1336ffa7d616STomasz Nowicki kfree(redist_regs); 1337ffa7d616STomasz Nowicki out_dist_unmap: 1338ffa7d616STomasz Nowicki iounmap(dist_base); 1339ffa7d616STomasz Nowicki return err; 1340ffa7d616STomasz Nowicki } 1341ffa7d616STomasz Nowicki IRQCHIP_ACPI_DECLARE(gic_v3, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 1342ffa7d616STomasz Nowicki acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V3, 1343ffa7d616STomasz Nowicki gic_acpi_init); 1344ffa7d616STomasz Nowicki IRQCHIP_ACPI_DECLARE(gic_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 1345ffa7d616STomasz Nowicki acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V4, 1346ffa7d616STomasz Nowicki gic_acpi_init); 1347ffa7d616STomasz Nowicki IRQCHIP_ACPI_DECLARE(gic_v3_or_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 1348ffa7d616STomasz Nowicki acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_NONE, 1349ffa7d616STomasz Nowicki gic_acpi_init); 1350ffa7d616STomasz Nowicki #endif 1351