1021f6537SMarc Zyngier /* 20edc23eaSMarc Zyngier * Copyright (C) 2013-2017 ARM Limited, All Rights Reserved. 3021f6537SMarc Zyngier * Author: Marc Zyngier <marc.zyngier@arm.com> 4021f6537SMarc Zyngier * 5021f6537SMarc Zyngier * This program is free software; you can redistribute it and/or modify 6021f6537SMarc Zyngier * it under the terms of the GNU General Public License version 2 as 7021f6537SMarc Zyngier * published by the Free Software Foundation. 8021f6537SMarc Zyngier * 9021f6537SMarc Zyngier * This program is distributed in the hope that it will be useful, 10021f6537SMarc Zyngier * but WITHOUT ANY WARRANTY; without even the implied warranty of 11021f6537SMarc Zyngier * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12021f6537SMarc Zyngier * GNU General Public License for more details. 13021f6537SMarc Zyngier * 14021f6537SMarc Zyngier * You should have received a copy of the GNU General Public License 15021f6537SMarc Zyngier * along with this program. If not, see <http://www.gnu.org/licenses/>. 16021f6537SMarc Zyngier */ 17021f6537SMarc Zyngier 1868628bb8SJulien Grall #define pr_fmt(fmt) "GICv3: " fmt 1968628bb8SJulien Grall 20ffa7d616STomasz Nowicki #include <linux/acpi.h> 21021f6537SMarc Zyngier #include <linux/cpu.h> 223708d52fSSudeep Holla #include <linux/cpu_pm.h> 23021f6537SMarc Zyngier #include <linux/delay.h> 24021f6537SMarc Zyngier #include <linux/interrupt.h> 25ffa7d616STomasz Nowicki #include <linux/irqdomain.h> 26021f6537SMarc Zyngier #include <linux/of.h> 27021f6537SMarc Zyngier #include <linux/of_address.h> 28021f6537SMarc Zyngier #include <linux/of_irq.h> 29021f6537SMarc Zyngier #include <linux/percpu.h> 30021f6537SMarc Zyngier #include <linux/slab.h> 31021f6537SMarc Zyngier 3241a83e06SJoel Porquet #include <linux/irqchip.h> 331839e576SJulien Grall #include <linux/irqchip/arm-gic-common.h> 34021f6537SMarc Zyngier #include <linux/irqchip/arm-gic-v3.h> 35e3825ba1SMarc Zyngier #include <linux/irqchip/irq-partition-percpu.h> 36021f6537SMarc Zyngier 37021f6537SMarc Zyngier #include <asm/cputype.h> 38021f6537SMarc Zyngier #include <asm/exception.h> 39021f6537SMarc Zyngier #include <asm/smp_plat.h> 400b6a3da9SMarc Zyngier #include <asm/virt.h> 41021f6537SMarc Zyngier 42021f6537SMarc Zyngier #include "irq-gic-common.h" 43021f6537SMarc Zyngier 449c8114c2SSrinivas Kandagatla #define FLAGS_WORKAROUND_GICR_WAKER_MSM8996 (1ULL << 0) 459c8114c2SSrinivas Kandagatla 46f5c1434cSMarc Zyngier struct redist_region { 47f5c1434cSMarc Zyngier void __iomem *redist_base; 48f5c1434cSMarc Zyngier phys_addr_t phys_base; 49b70fb7afSTomasz Nowicki bool single_redist; 50f5c1434cSMarc Zyngier }; 51f5c1434cSMarc Zyngier 52021f6537SMarc Zyngier struct gic_chip_data { 53e3825ba1SMarc Zyngier struct fwnode_handle *fwnode; 54021f6537SMarc Zyngier void __iomem *dist_base; 55f5c1434cSMarc Zyngier struct redist_region *redist_regions; 56f5c1434cSMarc Zyngier struct rdists rdists; 57021f6537SMarc Zyngier struct irq_domain *domain; 58021f6537SMarc Zyngier u64 redist_stride; 59f5c1434cSMarc Zyngier u32 nr_redist_regions; 609c8114c2SSrinivas Kandagatla u64 flags; 61eda0d04aSShanker Donthineni bool has_rss; 62021f6537SMarc Zyngier unsigned int irq_nr; 63e3825ba1SMarc Zyngier struct partition_desc *ppi_descs[16]; 64021f6537SMarc Zyngier }; 65021f6537SMarc Zyngier 66021f6537SMarc Zyngier static struct gic_chip_data gic_data __read_mostly; 67d01d3274SDavidlohr Bueso static DEFINE_STATIC_KEY_TRUE(supports_deactivate_key); 68021f6537SMarc Zyngier 69d98d0a99SJulien Thierry /* 70d98d0a99SJulien Thierry * The behaviours of RPR and PMR registers differ depending on the value of 71d98d0a99SJulien Thierry * SCR_EL3.FIQ, and the behaviour of non-secure priority registers of the 72d98d0a99SJulien Thierry * distributor and redistributors depends on whether security is enabled in the 73d98d0a99SJulien Thierry * GIC. 74d98d0a99SJulien Thierry * 75d98d0a99SJulien Thierry * When security is enabled, non-secure priority values from the (re)distributor 76d98d0a99SJulien Thierry * are presented to the GIC CPUIF as follow: 77d98d0a99SJulien Thierry * (GIC_(R)DIST_PRI[irq] >> 1) | 0x80; 78d98d0a99SJulien Thierry * 79d98d0a99SJulien Thierry * If SCR_EL3.FIQ == 1, the values writen to/read from PMR and RPR at non-secure 80d98d0a99SJulien Thierry * EL1 are subject to a similar operation thus matching the priorities presented 81d98d0a99SJulien Thierry * from the (re)distributor when security is enabled. 82d98d0a99SJulien Thierry * 83d98d0a99SJulien Thierry * see GICv3/GICv4 Architecture Specification (IHI0069D): 84d98d0a99SJulien Thierry * - section 4.8.1 Non-secure accesses to register fields for Secure interrupt 85d98d0a99SJulien Thierry * priorities. 86d98d0a99SJulien Thierry * - Figure 4-7 Secure read of the priority field for a Non-secure Group 1 87d98d0a99SJulien Thierry * interrupt. 88d98d0a99SJulien Thierry * 89d98d0a99SJulien Thierry * For now, we only support pseudo-NMIs if we have non-secure view of 90d98d0a99SJulien Thierry * priorities. 91d98d0a99SJulien Thierry */ 92d98d0a99SJulien Thierry static DEFINE_STATIC_KEY_FALSE(supports_pseudo_nmis); 93d98d0a99SJulien Thierry 941839e576SJulien Grall static struct gic_kvm_info gic_v3_kvm_info; 95eda0d04aSShanker Donthineni static DEFINE_PER_CPU(bool, has_rss); 961839e576SJulien Grall 97eda0d04aSShanker Donthineni #define MPIDR_RS(mpidr) (((mpidr) & 0xF0UL) >> 4) 98f5c1434cSMarc Zyngier #define gic_data_rdist() (this_cpu_ptr(gic_data.rdists.rdist)) 99f5c1434cSMarc Zyngier #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base) 100021f6537SMarc Zyngier #define gic_data_rdist_sgi_base() (gic_data_rdist_rd_base() + SZ_64K) 101021f6537SMarc Zyngier 102021f6537SMarc Zyngier /* Our default, arbitrary priority value. Linux only uses one anyway. */ 103021f6537SMarc Zyngier #define DEFAULT_PMR_VALUE 0xf0 104021f6537SMarc Zyngier 105021f6537SMarc Zyngier static inline unsigned int gic_irq(struct irq_data *d) 106021f6537SMarc Zyngier { 107021f6537SMarc Zyngier return d->hwirq; 108021f6537SMarc Zyngier } 109021f6537SMarc Zyngier 110021f6537SMarc Zyngier static inline int gic_irq_in_rdist(struct irq_data *d) 111021f6537SMarc Zyngier { 112021f6537SMarc Zyngier return gic_irq(d) < 32; 113021f6537SMarc Zyngier } 114021f6537SMarc Zyngier 115021f6537SMarc Zyngier static inline void __iomem *gic_dist_base(struct irq_data *d) 116021f6537SMarc Zyngier { 117021f6537SMarc Zyngier if (gic_irq_in_rdist(d)) /* SGI+PPI -> SGI_base for this CPU */ 118021f6537SMarc Zyngier return gic_data_rdist_sgi_base(); 119021f6537SMarc Zyngier 120021f6537SMarc Zyngier if (d->hwirq <= 1023) /* SPI -> dist_base */ 121021f6537SMarc Zyngier return gic_data.dist_base; 122021f6537SMarc Zyngier 123021f6537SMarc Zyngier return NULL; 124021f6537SMarc Zyngier } 125021f6537SMarc Zyngier 126021f6537SMarc Zyngier static void gic_do_wait_for_rwp(void __iomem *base) 127021f6537SMarc Zyngier { 128021f6537SMarc Zyngier u32 count = 1000000; /* 1s! */ 129021f6537SMarc Zyngier 130021f6537SMarc Zyngier while (readl_relaxed(base + GICD_CTLR) & GICD_CTLR_RWP) { 131021f6537SMarc Zyngier count--; 132021f6537SMarc Zyngier if (!count) { 133021f6537SMarc Zyngier pr_err_ratelimited("RWP timeout, gone fishing\n"); 134021f6537SMarc Zyngier return; 135021f6537SMarc Zyngier } 136021f6537SMarc Zyngier cpu_relax(); 137021f6537SMarc Zyngier udelay(1); 138021f6537SMarc Zyngier }; 139021f6537SMarc Zyngier } 140021f6537SMarc Zyngier 141021f6537SMarc Zyngier /* Wait for completion of a distributor change */ 142021f6537SMarc Zyngier static void gic_dist_wait_for_rwp(void) 143021f6537SMarc Zyngier { 144021f6537SMarc Zyngier gic_do_wait_for_rwp(gic_data.dist_base); 145021f6537SMarc Zyngier } 146021f6537SMarc Zyngier 147021f6537SMarc Zyngier /* Wait for completion of a redistributor change */ 148021f6537SMarc Zyngier static void gic_redist_wait_for_rwp(void) 149021f6537SMarc Zyngier { 150021f6537SMarc Zyngier gic_do_wait_for_rwp(gic_data_rdist_rd_base()); 151021f6537SMarc Zyngier } 152021f6537SMarc Zyngier 1537936e914SJean-Philippe Brucker #ifdef CONFIG_ARM64 1546d4e11c5SRobert Richter 1556d4e11c5SRobert Richter static u64 __maybe_unused gic_read_iar(void) 1566d4e11c5SRobert Richter { 157a4023f68SSuzuki K Poulose if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_23154)) 1586d4e11c5SRobert Richter return gic_read_iar_cavium_thunderx(); 1596d4e11c5SRobert Richter else 1606d4e11c5SRobert Richter return gic_read_iar_common(); 1616d4e11c5SRobert Richter } 1627936e914SJean-Philippe Brucker #endif 163021f6537SMarc Zyngier 164a2c22510SSudeep Holla static void gic_enable_redist(bool enable) 165021f6537SMarc Zyngier { 166021f6537SMarc Zyngier void __iomem *rbase; 167021f6537SMarc Zyngier u32 count = 1000000; /* 1s! */ 168021f6537SMarc Zyngier u32 val; 169021f6537SMarc Zyngier 1709c8114c2SSrinivas Kandagatla if (gic_data.flags & FLAGS_WORKAROUND_GICR_WAKER_MSM8996) 1719c8114c2SSrinivas Kandagatla return; 1729c8114c2SSrinivas Kandagatla 173021f6537SMarc Zyngier rbase = gic_data_rdist_rd_base(); 174021f6537SMarc Zyngier 175021f6537SMarc Zyngier val = readl_relaxed(rbase + GICR_WAKER); 176a2c22510SSudeep Holla if (enable) 177a2c22510SSudeep Holla /* Wake up this CPU redistributor */ 178021f6537SMarc Zyngier val &= ~GICR_WAKER_ProcessorSleep; 179a2c22510SSudeep Holla else 180a2c22510SSudeep Holla val |= GICR_WAKER_ProcessorSleep; 181021f6537SMarc Zyngier writel_relaxed(val, rbase + GICR_WAKER); 182021f6537SMarc Zyngier 183a2c22510SSudeep Holla if (!enable) { /* Check that GICR_WAKER is writeable */ 184a2c22510SSudeep Holla val = readl_relaxed(rbase + GICR_WAKER); 185a2c22510SSudeep Holla if (!(val & GICR_WAKER_ProcessorSleep)) 186a2c22510SSudeep Holla return; /* No PM support in this redistributor */ 187021f6537SMarc Zyngier } 188a2c22510SSudeep Holla 189d102eb5cSDan Carpenter while (--count) { 190a2c22510SSudeep Holla val = readl_relaxed(rbase + GICR_WAKER); 191cf1d9d11SAndrew Jones if (enable ^ (bool)(val & GICR_WAKER_ChildrenAsleep)) 192a2c22510SSudeep Holla break; 193021f6537SMarc Zyngier cpu_relax(); 194021f6537SMarc Zyngier udelay(1); 195021f6537SMarc Zyngier }; 196a2c22510SSudeep Holla if (!count) 197a2c22510SSudeep Holla pr_err_ratelimited("redistributor failed to %s...\n", 198a2c22510SSudeep Holla enable ? "wakeup" : "sleep"); 199021f6537SMarc Zyngier } 200021f6537SMarc Zyngier 201021f6537SMarc Zyngier /* 202021f6537SMarc Zyngier * Routines to disable, enable, EOI and route interrupts 203021f6537SMarc Zyngier */ 204b594c6e2SMarc Zyngier static int gic_peek_irq(struct irq_data *d, u32 offset) 205b594c6e2SMarc Zyngier { 206b594c6e2SMarc Zyngier u32 mask = 1 << (gic_irq(d) % 32); 207b594c6e2SMarc Zyngier void __iomem *base; 208b594c6e2SMarc Zyngier 209b594c6e2SMarc Zyngier if (gic_irq_in_rdist(d)) 210b594c6e2SMarc Zyngier base = gic_data_rdist_sgi_base(); 211b594c6e2SMarc Zyngier else 212b594c6e2SMarc Zyngier base = gic_data.dist_base; 213b594c6e2SMarc Zyngier 214b594c6e2SMarc Zyngier return !!(readl_relaxed(base + offset + (gic_irq(d) / 32) * 4) & mask); 215b594c6e2SMarc Zyngier } 216b594c6e2SMarc Zyngier 217021f6537SMarc Zyngier static void gic_poke_irq(struct irq_data *d, u32 offset) 218021f6537SMarc Zyngier { 219021f6537SMarc Zyngier u32 mask = 1 << (gic_irq(d) % 32); 220021f6537SMarc Zyngier void (*rwp_wait)(void); 221021f6537SMarc Zyngier void __iomem *base; 222021f6537SMarc Zyngier 223021f6537SMarc Zyngier if (gic_irq_in_rdist(d)) { 224021f6537SMarc Zyngier base = gic_data_rdist_sgi_base(); 225021f6537SMarc Zyngier rwp_wait = gic_redist_wait_for_rwp; 226021f6537SMarc Zyngier } else { 227021f6537SMarc Zyngier base = gic_data.dist_base; 228021f6537SMarc Zyngier rwp_wait = gic_dist_wait_for_rwp; 229021f6537SMarc Zyngier } 230021f6537SMarc Zyngier 231021f6537SMarc Zyngier writel_relaxed(mask, base + offset + (gic_irq(d) / 32) * 4); 232021f6537SMarc Zyngier rwp_wait(); 233021f6537SMarc Zyngier } 234021f6537SMarc Zyngier 235021f6537SMarc Zyngier static void gic_mask_irq(struct irq_data *d) 236021f6537SMarc Zyngier { 237021f6537SMarc Zyngier gic_poke_irq(d, GICD_ICENABLER); 238021f6537SMarc Zyngier } 239021f6537SMarc Zyngier 2400b6a3da9SMarc Zyngier static void gic_eoimode1_mask_irq(struct irq_data *d) 2410b6a3da9SMarc Zyngier { 2420b6a3da9SMarc Zyngier gic_mask_irq(d); 243530bf353SMarc Zyngier /* 244530bf353SMarc Zyngier * When masking a forwarded interrupt, make sure it is 245530bf353SMarc Zyngier * deactivated as well. 246530bf353SMarc Zyngier * 247530bf353SMarc Zyngier * This ensures that an interrupt that is getting 248530bf353SMarc Zyngier * disabled/masked will not get "stuck", because there is 249530bf353SMarc Zyngier * noone to deactivate it (guest is being terminated). 250530bf353SMarc Zyngier */ 2514df7f54dSThomas Gleixner if (irqd_is_forwarded_to_vcpu(d)) 252530bf353SMarc Zyngier gic_poke_irq(d, GICD_ICACTIVER); 2530b6a3da9SMarc Zyngier } 2540b6a3da9SMarc Zyngier 255021f6537SMarc Zyngier static void gic_unmask_irq(struct irq_data *d) 256021f6537SMarc Zyngier { 257021f6537SMarc Zyngier gic_poke_irq(d, GICD_ISENABLER); 258021f6537SMarc Zyngier } 259021f6537SMarc Zyngier 260d98d0a99SJulien Thierry static inline bool gic_supports_nmi(void) 261d98d0a99SJulien Thierry { 262d98d0a99SJulien Thierry return IS_ENABLED(CONFIG_ARM64_PSEUDO_NMI) && 263d98d0a99SJulien Thierry static_branch_likely(&supports_pseudo_nmis); 264d98d0a99SJulien Thierry } 265d98d0a99SJulien Thierry 266b594c6e2SMarc Zyngier static int gic_irq_set_irqchip_state(struct irq_data *d, 267b594c6e2SMarc Zyngier enum irqchip_irq_state which, bool val) 268b594c6e2SMarc Zyngier { 269b594c6e2SMarc Zyngier u32 reg; 270b594c6e2SMarc Zyngier 271b594c6e2SMarc Zyngier if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */ 272b594c6e2SMarc Zyngier return -EINVAL; 273b594c6e2SMarc Zyngier 274b594c6e2SMarc Zyngier switch (which) { 275b594c6e2SMarc Zyngier case IRQCHIP_STATE_PENDING: 276b594c6e2SMarc Zyngier reg = val ? GICD_ISPENDR : GICD_ICPENDR; 277b594c6e2SMarc Zyngier break; 278b594c6e2SMarc Zyngier 279b594c6e2SMarc Zyngier case IRQCHIP_STATE_ACTIVE: 280b594c6e2SMarc Zyngier reg = val ? GICD_ISACTIVER : GICD_ICACTIVER; 281b594c6e2SMarc Zyngier break; 282b594c6e2SMarc Zyngier 283b594c6e2SMarc Zyngier case IRQCHIP_STATE_MASKED: 284b594c6e2SMarc Zyngier reg = val ? GICD_ICENABLER : GICD_ISENABLER; 285b594c6e2SMarc Zyngier break; 286b594c6e2SMarc Zyngier 287b594c6e2SMarc Zyngier default: 288b594c6e2SMarc Zyngier return -EINVAL; 289b594c6e2SMarc Zyngier } 290b594c6e2SMarc Zyngier 291b594c6e2SMarc Zyngier gic_poke_irq(d, reg); 292b594c6e2SMarc Zyngier return 0; 293b594c6e2SMarc Zyngier } 294b594c6e2SMarc Zyngier 295b594c6e2SMarc Zyngier static int gic_irq_get_irqchip_state(struct irq_data *d, 296b594c6e2SMarc Zyngier enum irqchip_irq_state which, bool *val) 297b594c6e2SMarc Zyngier { 298b594c6e2SMarc Zyngier if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */ 299b594c6e2SMarc Zyngier return -EINVAL; 300b594c6e2SMarc Zyngier 301b594c6e2SMarc Zyngier switch (which) { 302b594c6e2SMarc Zyngier case IRQCHIP_STATE_PENDING: 303b594c6e2SMarc Zyngier *val = gic_peek_irq(d, GICD_ISPENDR); 304b594c6e2SMarc Zyngier break; 305b594c6e2SMarc Zyngier 306b594c6e2SMarc Zyngier case IRQCHIP_STATE_ACTIVE: 307b594c6e2SMarc Zyngier *val = gic_peek_irq(d, GICD_ISACTIVER); 308b594c6e2SMarc Zyngier break; 309b594c6e2SMarc Zyngier 310b594c6e2SMarc Zyngier case IRQCHIP_STATE_MASKED: 311b594c6e2SMarc Zyngier *val = !gic_peek_irq(d, GICD_ISENABLER); 312b594c6e2SMarc Zyngier break; 313b594c6e2SMarc Zyngier 314b594c6e2SMarc Zyngier default: 315b594c6e2SMarc Zyngier return -EINVAL; 316b594c6e2SMarc Zyngier } 317b594c6e2SMarc Zyngier 318b594c6e2SMarc Zyngier return 0; 319b594c6e2SMarc Zyngier } 320b594c6e2SMarc Zyngier 321021f6537SMarc Zyngier static void gic_eoi_irq(struct irq_data *d) 322021f6537SMarc Zyngier { 323021f6537SMarc Zyngier gic_write_eoir(gic_irq(d)); 324021f6537SMarc Zyngier } 325021f6537SMarc Zyngier 3260b6a3da9SMarc Zyngier static void gic_eoimode1_eoi_irq(struct irq_data *d) 3270b6a3da9SMarc Zyngier { 3280b6a3da9SMarc Zyngier /* 329530bf353SMarc Zyngier * No need to deactivate an LPI, or an interrupt that 330530bf353SMarc Zyngier * is is getting forwarded to a vcpu. 3310b6a3da9SMarc Zyngier */ 3324df7f54dSThomas Gleixner if (gic_irq(d) >= 8192 || irqd_is_forwarded_to_vcpu(d)) 3330b6a3da9SMarc Zyngier return; 3340b6a3da9SMarc Zyngier gic_write_dir(gic_irq(d)); 3350b6a3da9SMarc Zyngier } 3360b6a3da9SMarc Zyngier 337021f6537SMarc Zyngier static int gic_set_type(struct irq_data *d, unsigned int type) 338021f6537SMarc Zyngier { 339021f6537SMarc Zyngier unsigned int irq = gic_irq(d); 340021f6537SMarc Zyngier void (*rwp_wait)(void); 341021f6537SMarc Zyngier void __iomem *base; 342021f6537SMarc Zyngier 343021f6537SMarc Zyngier /* Interrupt configuration for SGIs can't be changed */ 344021f6537SMarc Zyngier if (irq < 16) 345021f6537SMarc Zyngier return -EINVAL; 346021f6537SMarc Zyngier 347fb7e7debSLiviu Dudau /* SPIs have restrictions on the supported types */ 348fb7e7debSLiviu Dudau if (irq >= 32 && type != IRQ_TYPE_LEVEL_HIGH && 349fb7e7debSLiviu Dudau type != IRQ_TYPE_EDGE_RISING) 350021f6537SMarc Zyngier return -EINVAL; 351021f6537SMarc Zyngier 352021f6537SMarc Zyngier if (gic_irq_in_rdist(d)) { 353021f6537SMarc Zyngier base = gic_data_rdist_sgi_base(); 354021f6537SMarc Zyngier rwp_wait = gic_redist_wait_for_rwp; 355021f6537SMarc Zyngier } else { 356021f6537SMarc Zyngier base = gic_data.dist_base; 357021f6537SMarc Zyngier rwp_wait = gic_dist_wait_for_rwp; 358021f6537SMarc Zyngier } 359021f6537SMarc Zyngier 360fb7e7debSLiviu Dudau return gic_configure_irq(irq, type, base, rwp_wait); 361021f6537SMarc Zyngier } 362021f6537SMarc Zyngier 363530bf353SMarc Zyngier static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu) 364530bf353SMarc Zyngier { 3654df7f54dSThomas Gleixner if (vcpu) 3664df7f54dSThomas Gleixner irqd_set_forwarded_to_vcpu(d); 3674df7f54dSThomas Gleixner else 3684df7f54dSThomas Gleixner irqd_clr_forwarded_to_vcpu(d); 369530bf353SMarc Zyngier return 0; 370530bf353SMarc Zyngier } 371530bf353SMarc Zyngier 372f6c86a41SJean-Philippe Brucker static u64 gic_mpidr_to_affinity(unsigned long mpidr) 373021f6537SMarc Zyngier { 374021f6537SMarc Zyngier u64 aff; 375021f6537SMarc Zyngier 376f6c86a41SJean-Philippe Brucker aff = ((u64)MPIDR_AFFINITY_LEVEL(mpidr, 3) << 32 | 377021f6537SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 | 378021f6537SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | 379021f6537SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 0)); 380021f6537SMarc Zyngier 381021f6537SMarc Zyngier return aff; 382021f6537SMarc Zyngier } 383021f6537SMarc Zyngier 384021f6537SMarc Zyngier static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) 385021f6537SMarc Zyngier { 386f6c86a41SJean-Philippe Brucker u32 irqnr; 387021f6537SMarc Zyngier 388021f6537SMarc Zyngier irqnr = gic_read_iar(); 389021f6537SMarc Zyngier 3903f1f3234SJulien Thierry if (gic_prio_masking_enabled()) { 3913f1f3234SJulien Thierry gic_pmr_mask_irqs(); 3923f1f3234SJulien Thierry gic_arch_enable_irqs(); 3933f1f3234SJulien Thierry } 3943f1f3234SJulien Thierry 395da33f31dSMarc Zyngier if (likely(irqnr > 15 && irqnr < 1020) || irqnr >= 8192) { 396ebc6de00SMarc Zyngier int err; 3970b6a3da9SMarc Zyngier 398d01d3274SDavidlohr Bueso if (static_branch_likely(&supports_deactivate_key)) 3990b6a3da9SMarc Zyngier gic_write_eoir(irqnr); 40039a06b67SWill Deacon else 40139a06b67SWill Deacon isb(); 4020b6a3da9SMarc Zyngier 403ebc6de00SMarc Zyngier err = handle_domain_irq(gic_data.domain, irqnr, regs); 404ebc6de00SMarc Zyngier if (err) { 405da33f31dSMarc Zyngier WARN_ONCE(true, "Unexpected interrupt received!\n"); 406d01d3274SDavidlohr Bueso if (static_branch_likely(&supports_deactivate_key)) { 4070b6a3da9SMarc Zyngier if (irqnr < 8192) 4080b6a3da9SMarc Zyngier gic_write_dir(irqnr); 4090b6a3da9SMarc Zyngier } else { 410021f6537SMarc Zyngier gic_write_eoir(irqnr); 411021f6537SMarc Zyngier } 4120b6a3da9SMarc Zyngier } 413342677d7SJulien Thierry return; 414ebc6de00SMarc Zyngier } 415021f6537SMarc Zyngier if (irqnr < 16) { 416021f6537SMarc Zyngier gic_write_eoir(irqnr); 417d01d3274SDavidlohr Bueso if (static_branch_likely(&supports_deactivate_key)) 4180b6a3da9SMarc Zyngier gic_write_dir(irqnr); 419021f6537SMarc Zyngier #ifdef CONFIG_SMP 420f86c4fbdSWill Deacon /* 421f86c4fbdSWill Deacon * Unlike GICv2, we don't need an smp_rmb() here. 422f86c4fbdSWill Deacon * The control dependency from gic_read_iar to 423f86c4fbdSWill Deacon * the ISB in gic_write_eoir is enough to ensure 424f86c4fbdSWill Deacon * that any shared data read by handle_IPI will 425f86c4fbdSWill Deacon * be read after the ACK. 426f86c4fbdSWill Deacon */ 427021f6537SMarc Zyngier handle_IPI(irqnr, regs); 428021f6537SMarc Zyngier #else 429021f6537SMarc Zyngier WARN_ONCE(true, "Unexpected SGI received!\n"); 430021f6537SMarc Zyngier #endif 431021f6537SMarc Zyngier } 432021f6537SMarc Zyngier } 433021f6537SMarc Zyngier 434b5cf6073SJulien Thierry static u32 gic_get_pribits(void) 435b5cf6073SJulien Thierry { 436b5cf6073SJulien Thierry u32 pribits; 437b5cf6073SJulien Thierry 438b5cf6073SJulien Thierry pribits = gic_read_ctlr(); 439b5cf6073SJulien Thierry pribits &= ICC_CTLR_EL1_PRI_BITS_MASK; 440b5cf6073SJulien Thierry pribits >>= ICC_CTLR_EL1_PRI_BITS_SHIFT; 441b5cf6073SJulien Thierry pribits++; 442b5cf6073SJulien Thierry 443b5cf6073SJulien Thierry return pribits; 444b5cf6073SJulien Thierry } 445b5cf6073SJulien Thierry 446b5cf6073SJulien Thierry static bool gic_has_group0(void) 447b5cf6073SJulien Thierry { 448b5cf6073SJulien Thierry u32 val; 449e7932188SJulien Thierry u32 old_pmr; 450e7932188SJulien Thierry 451e7932188SJulien Thierry old_pmr = gic_read_pmr(); 452b5cf6073SJulien Thierry 453b5cf6073SJulien Thierry /* 454b5cf6073SJulien Thierry * Let's find out if Group0 is under control of EL3 or not by 455b5cf6073SJulien Thierry * setting the highest possible, non-zero priority in PMR. 456b5cf6073SJulien Thierry * 457b5cf6073SJulien Thierry * If SCR_EL3.FIQ is set, the priority gets shifted down in 458b5cf6073SJulien Thierry * order for the CPU interface to set bit 7, and keep the 459b5cf6073SJulien Thierry * actual priority in the non-secure range. In the process, it 460b5cf6073SJulien Thierry * looses the least significant bit and the actual priority 461b5cf6073SJulien Thierry * becomes 0x80. Reading it back returns 0, indicating that 462b5cf6073SJulien Thierry * we're don't have access to Group0. 463b5cf6073SJulien Thierry */ 464b5cf6073SJulien Thierry gic_write_pmr(BIT(8 - gic_get_pribits())); 465b5cf6073SJulien Thierry val = gic_read_pmr(); 466b5cf6073SJulien Thierry 467e7932188SJulien Thierry gic_write_pmr(old_pmr); 468e7932188SJulien Thierry 469b5cf6073SJulien Thierry return val != 0; 470b5cf6073SJulien Thierry } 471b5cf6073SJulien Thierry 472021f6537SMarc Zyngier static void __init gic_dist_init(void) 473021f6537SMarc Zyngier { 474021f6537SMarc Zyngier unsigned int i; 475021f6537SMarc Zyngier u64 affinity; 476021f6537SMarc Zyngier void __iomem *base = gic_data.dist_base; 477021f6537SMarc Zyngier 478021f6537SMarc Zyngier /* Disable the distributor */ 479021f6537SMarc Zyngier writel_relaxed(0, base + GICD_CTLR); 480021f6537SMarc Zyngier gic_dist_wait_for_rwp(); 481021f6537SMarc Zyngier 4827c9b9730SMarc Zyngier /* 4837c9b9730SMarc Zyngier * Configure SPIs as non-secure Group-1. This will only matter 4847c9b9730SMarc Zyngier * if the GIC only has a single security state. This will not 4857c9b9730SMarc Zyngier * do the right thing if the kernel is running in secure mode, 4867c9b9730SMarc Zyngier * but that's not the intended use case anyway. 4877c9b9730SMarc Zyngier */ 4887c9b9730SMarc Zyngier for (i = 32; i < gic_data.irq_nr; i += 32) 4897c9b9730SMarc Zyngier writel_relaxed(~0, base + GICD_IGROUPR + i / 8); 4907c9b9730SMarc Zyngier 491021f6537SMarc Zyngier gic_dist_config(base, gic_data.irq_nr, gic_dist_wait_for_rwp); 492021f6537SMarc Zyngier 493021f6537SMarc Zyngier /* Enable distributor with ARE, Group1 */ 494021f6537SMarc Zyngier writel_relaxed(GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G1A | GICD_CTLR_ENABLE_G1, 495021f6537SMarc Zyngier base + GICD_CTLR); 496021f6537SMarc Zyngier 497021f6537SMarc Zyngier /* 498021f6537SMarc Zyngier * Set all global interrupts to the boot CPU only. ARE must be 499021f6537SMarc Zyngier * enabled. 500021f6537SMarc Zyngier */ 501021f6537SMarc Zyngier affinity = gic_mpidr_to_affinity(cpu_logical_map(smp_processor_id())); 502021f6537SMarc Zyngier for (i = 32; i < gic_data.irq_nr; i++) 50372c97126SJean-Philippe Brucker gic_write_irouter(affinity, base + GICD_IROUTER + i * 8); 504021f6537SMarc Zyngier } 505021f6537SMarc Zyngier 5060d94ded2SMarc Zyngier static int gic_iterate_rdists(int (*fn)(struct redist_region *, void __iomem *)) 507021f6537SMarc Zyngier { 5080d94ded2SMarc Zyngier int ret = -ENODEV; 509021f6537SMarc Zyngier int i; 510021f6537SMarc Zyngier 511f5c1434cSMarc Zyngier for (i = 0; i < gic_data.nr_redist_regions; i++) { 512f5c1434cSMarc Zyngier void __iomem *ptr = gic_data.redist_regions[i].redist_base; 5130d94ded2SMarc Zyngier u64 typer; 514021f6537SMarc Zyngier u32 reg; 515021f6537SMarc Zyngier 516021f6537SMarc Zyngier reg = readl_relaxed(ptr + GICR_PIDR2) & GIC_PIDR2_ARCH_MASK; 517021f6537SMarc Zyngier if (reg != GIC_PIDR2_ARCH_GICv3 && 518021f6537SMarc Zyngier reg != GIC_PIDR2_ARCH_GICv4) { /* We're in trouble... */ 519021f6537SMarc Zyngier pr_warn("No redistributor present @%p\n", ptr); 520021f6537SMarc Zyngier break; 521021f6537SMarc Zyngier } 522021f6537SMarc Zyngier 523021f6537SMarc Zyngier do { 52472c97126SJean-Philippe Brucker typer = gic_read_typer(ptr + GICR_TYPER); 5250d94ded2SMarc Zyngier ret = fn(gic_data.redist_regions + i, ptr); 5260d94ded2SMarc Zyngier if (!ret) 527021f6537SMarc Zyngier return 0; 528021f6537SMarc Zyngier 529b70fb7afSTomasz Nowicki if (gic_data.redist_regions[i].single_redist) 530b70fb7afSTomasz Nowicki break; 531b70fb7afSTomasz Nowicki 532021f6537SMarc Zyngier if (gic_data.redist_stride) { 533021f6537SMarc Zyngier ptr += gic_data.redist_stride; 534021f6537SMarc Zyngier } else { 535021f6537SMarc Zyngier ptr += SZ_64K * 2; /* Skip RD_base + SGI_base */ 536021f6537SMarc Zyngier if (typer & GICR_TYPER_VLPIS) 537021f6537SMarc Zyngier ptr += SZ_64K * 2; /* Skip VLPI_base + reserved page */ 538021f6537SMarc Zyngier } 539021f6537SMarc Zyngier } while (!(typer & GICR_TYPER_LAST)); 540021f6537SMarc Zyngier } 541021f6537SMarc Zyngier 5420d94ded2SMarc Zyngier return ret ? -ENODEV : 0; 5430d94ded2SMarc Zyngier } 5440d94ded2SMarc Zyngier 5450d94ded2SMarc Zyngier static int __gic_populate_rdist(struct redist_region *region, void __iomem *ptr) 5460d94ded2SMarc Zyngier { 5470d94ded2SMarc Zyngier unsigned long mpidr = cpu_logical_map(smp_processor_id()); 5480d94ded2SMarc Zyngier u64 typer; 5490d94ded2SMarc Zyngier u32 aff; 5500d94ded2SMarc Zyngier 5510d94ded2SMarc Zyngier /* 5520d94ded2SMarc Zyngier * Convert affinity to a 32bit value that can be matched to 5530d94ded2SMarc Zyngier * GICR_TYPER bits [63:32]. 5540d94ded2SMarc Zyngier */ 5550d94ded2SMarc Zyngier aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 24 | 5560d94ded2SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 | 5570d94ded2SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | 5580d94ded2SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 0)); 5590d94ded2SMarc Zyngier 5600d94ded2SMarc Zyngier typer = gic_read_typer(ptr + GICR_TYPER); 5610d94ded2SMarc Zyngier if ((typer >> 32) == aff) { 5620d94ded2SMarc Zyngier u64 offset = ptr - region->redist_base; 5630d94ded2SMarc Zyngier gic_data_rdist_rd_base() = ptr; 5640d94ded2SMarc Zyngier gic_data_rdist()->phys_base = region->phys_base + offset; 5650d94ded2SMarc Zyngier 5660d94ded2SMarc Zyngier pr_info("CPU%d: found redistributor %lx region %d:%pa\n", 5670d94ded2SMarc Zyngier smp_processor_id(), mpidr, 5680d94ded2SMarc Zyngier (int)(region - gic_data.redist_regions), 5690d94ded2SMarc Zyngier &gic_data_rdist()->phys_base); 5700d94ded2SMarc Zyngier return 0; 5710d94ded2SMarc Zyngier } 5720d94ded2SMarc Zyngier 5730d94ded2SMarc Zyngier /* Try next one */ 5740d94ded2SMarc Zyngier return 1; 5750d94ded2SMarc Zyngier } 5760d94ded2SMarc Zyngier 5770d94ded2SMarc Zyngier static int gic_populate_rdist(void) 5780d94ded2SMarc Zyngier { 5790d94ded2SMarc Zyngier if (gic_iterate_rdists(__gic_populate_rdist) == 0) 5800d94ded2SMarc Zyngier return 0; 5810d94ded2SMarc Zyngier 582021f6537SMarc Zyngier /* We couldn't even deal with ourselves... */ 583f6c86a41SJean-Philippe Brucker WARN(true, "CPU%d: mpidr %lx has no re-distributor!\n", 5840d94ded2SMarc Zyngier smp_processor_id(), 5850d94ded2SMarc Zyngier (unsigned long)cpu_logical_map(smp_processor_id())); 586021f6537SMarc Zyngier return -ENODEV; 587021f6537SMarc Zyngier } 588021f6537SMarc Zyngier 5890edc23eaSMarc Zyngier static int __gic_update_vlpi_properties(struct redist_region *region, 5900edc23eaSMarc Zyngier void __iomem *ptr) 5910edc23eaSMarc Zyngier { 5920edc23eaSMarc Zyngier u64 typer = gic_read_typer(ptr + GICR_TYPER); 5930edc23eaSMarc Zyngier gic_data.rdists.has_vlpis &= !!(typer & GICR_TYPER_VLPIS); 5940edc23eaSMarc Zyngier gic_data.rdists.has_direct_lpi &= !!(typer & GICR_TYPER_DirectLPIS); 5950edc23eaSMarc Zyngier 5960edc23eaSMarc Zyngier return 1; 5970edc23eaSMarc Zyngier } 5980edc23eaSMarc Zyngier 5990edc23eaSMarc Zyngier static void gic_update_vlpi_properties(void) 6000edc23eaSMarc Zyngier { 6010edc23eaSMarc Zyngier gic_iterate_rdists(__gic_update_vlpi_properties); 6020edc23eaSMarc Zyngier pr_info("%sVLPI support, %sdirect LPI support\n", 6030edc23eaSMarc Zyngier !gic_data.rdists.has_vlpis ? "no " : "", 6040edc23eaSMarc Zyngier !gic_data.rdists.has_direct_lpi ? "no " : ""); 6050edc23eaSMarc Zyngier } 6060edc23eaSMarc Zyngier 607d98d0a99SJulien Thierry /* Check whether it's single security state view */ 608d98d0a99SJulien Thierry static inline bool gic_dist_security_disabled(void) 609d98d0a99SJulien Thierry { 610d98d0a99SJulien Thierry return readl_relaxed(gic_data.dist_base + GICD_CTLR) & GICD_CTLR_DS; 611d98d0a99SJulien Thierry } 612d98d0a99SJulien Thierry 6133708d52fSSudeep Holla static void gic_cpu_sys_reg_init(void) 614021f6537SMarc Zyngier { 615eda0d04aSShanker Donthineni int i, cpu = smp_processor_id(); 616eda0d04aSShanker Donthineni u64 mpidr = cpu_logical_map(cpu); 617eda0d04aSShanker Donthineni u64 need_rss = MPIDR_RS(mpidr); 61833625282SMarc Zyngier bool group0; 619b5cf6073SJulien Thierry u32 pribits; 620eda0d04aSShanker Donthineni 6217cabd008SMarc Zyngier /* 6227cabd008SMarc Zyngier * Need to check that the SRE bit has actually been set. If 6237cabd008SMarc Zyngier * not, it means that SRE is disabled at EL2. We're going to 6247cabd008SMarc Zyngier * die painfully, and there is nothing we can do about it. 6257cabd008SMarc Zyngier * 6267cabd008SMarc Zyngier * Kindly inform the luser. 6277cabd008SMarc Zyngier */ 6287cabd008SMarc Zyngier if (!gic_enable_sre()) 6297cabd008SMarc Zyngier pr_err("GIC: unable to set SRE (disabled at EL2), panic ahead\n"); 630021f6537SMarc Zyngier 631b5cf6073SJulien Thierry pribits = gic_get_pribits(); 63233625282SMarc Zyngier 633b5cf6073SJulien Thierry group0 = gic_has_group0(); 63433625282SMarc Zyngier 635021f6537SMarc Zyngier /* Set priority mask register */ 636d98d0a99SJulien Thierry if (!gic_prio_masking_enabled()) { 63733625282SMarc Zyngier write_gicreg(DEFAULT_PMR_VALUE, ICC_PMR_EL1); 638d98d0a99SJulien Thierry } else { 639d98d0a99SJulien Thierry /* 640d98d0a99SJulien Thierry * Mismatch configuration with boot CPU, the system is likely 641d98d0a99SJulien Thierry * to die as interrupt masking will not work properly on all 642d98d0a99SJulien Thierry * CPUs 643d98d0a99SJulien Thierry */ 644d98d0a99SJulien Thierry WARN_ON(gic_supports_nmi() && group0 && 645d98d0a99SJulien Thierry !gic_dist_security_disabled()); 646d98d0a99SJulien Thierry } 647021f6537SMarc Zyngier 64891ef8442SDaniel Thompson /* 64991ef8442SDaniel Thompson * Some firmwares hand over to the kernel with the BPR changed from 65091ef8442SDaniel Thompson * its reset value (and with a value large enough to prevent 65191ef8442SDaniel Thompson * any pre-emptive interrupts from working at all). Writing a zero 65291ef8442SDaniel Thompson * to BPR restores is reset value. 65391ef8442SDaniel Thompson */ 65491ef8442SDaniel Thompson gic_write_bpr1(0); 65591ef8442SDaniel Thompson 656d01d3274SDavidlohr Bueso if (static_branch_likely(&supports_deactivate_key)) { 6570b6a3da9SMarc Zyngier /* EOI drops priority only (mode 1) */ 6580b6a3da9SMarc Zyngier gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop); 6590b6a3da9SMarc Zyngier } else { 660021f6537SMarc Zyngier /* EOI deactivates interrupt too (mode 0) */ 661021f6537SMarc Zyngier gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop_dir); 6620b6a3da9SMarc Zyngier } 663021f6537SMarc Zyngier 66433625282SMarc Zyngier /* Always whack Group0 before Group1 */ 66533625282SMarc Zyngier if (group0) { 66633625282SMarc Zyngier switch(pribits) { 66733625282SMarc Zyngier case 8: 66833625282SMarc Zyngier case 7: 66933625282SMarc Zyngier write_gicreg(0, ICC_AP0R3_EL1); 67033625282SMarc Zyngier write_gicreg(0, ICC_AP0R2_EL1); 67133625282SMarc Zyngier case 6: 67233625282SMarc Zyngier write_gicreg(0, ICC_AP0R1_EL1); 67333625282SMarc Zyngier case 5: 67433625282SMarc Zyngier case 4: 67533625282SMarc Zyngier write_gicreg(0, ICC_AP0R0_EL1); 67633625282SMarc Zyngier } 677d6062a6dSMarc Zyngier 67833625282SMarc Zyngier isb(); 67933625282SMarc Zyngier } 68033625282SMarc Zyngier 68133625282SMarc Zyngier switch(pribits) { 682d6062a6dSMarc Zyngier case 8: 683d6062a6dSMarc Zyngier case 7: 684d6062a6dSMarc Zyngier write_gicreg(0, ICC_AP1R3_EL1); 685d6062a6dSMarc Zyngier write_gicreg(0, ICC_AP1R2_EL1); 686d6062a6dSMarc Zyngier case 6: 687d6062a6dSMarc Zyngier write_gicreg(0, ICC_AP1R1_EL1); 688d6062a6dSMarc Zyngier case 5: 689d6062a6dSMarc Zyngier case 4: 690d6062a6dSMarc Zyngier write_gicreg(0, ICC_AP1R0_EL1); 691d6062a6dSMarc Zyngier } 692d6062a6dSMarc Zyngier 693d6062a6dSMarc Zyngier isb(); 694d6062a6dSMarc Zyngier 695021f6537SMarc Zyngier /* ... and let's hit the road... */ 696021f6537SMarc Zyngier gic_write_grpen1(1); 697eda0d04aSShanker Donthineni 698eda0d04aSShanker Donthineni /* Keep the RSS capability status in per_cpu variable */ 699eda0d04aSShanker Donthineni per_cpu(has_rss, cpu) = !!(gic_read_ctlr() & ICC_CTLR_EL1_RSS); 700eda0d04aSShanker Donthineni 701eda0d04aSShanker Donthineni /* Check all the CPUs have capable of sending SGIs to other CPUs */ 702eda0d04aSShanker Donthineni for_each_online_cpu(i) { 703eda0d04aSShanker Donthineni bool have_rss = per_cpu(has_rss, i) && per_cpu(has_rss, cpu); 704eda0d04aSShanker Donthineni 705eda0d04aSShanker Donthineni need_rss |= MPIDR_RS(cpu_logical_map(i)); 706eda0d04aSShanker Donthineni if (need_rss && (!have_rss)) 707eda0d04aSShanker Donthineni pr_crit("CPU%d (%lx) can't SGI CPU%d (%lx), no RSS\n", 708eda0d04aSShanker Donthineni cpu, (unsigned long)mpidr, 709eda0d04aSShanker Donthineni i, (unsigned long)cpu_logical_map(i)); 710eda0d04aSShanker Donthineni } 711eda0d04aSShanker Donthineni 712eda0d04aSShanker Donthineni /** 713eda0d04aSShanker Donthineni * GIC spec says, when ICC_CTLR_EL1.RSS==1 and GICD_TYPER.RSS==0, 714eda0d04aSShanker Donthineni * writing ICC_ASGI1R_EL1 register with RS != 0 is a CONSTRAINED 715eda0d04aSShanker Donthineni * UNPREDICTABLE choice of : 716eda0d04aSShanker Donthineni * - The write is ignored. 717eda0d04aSShanker Donthineni * - The RS field is treated as 0. 718eda0d04aSShanker Donthineni */ 719eda0d04aSShanker Donthineni if (need_rss && (!gic_data.has_rss)) 720eda0d04aSShanker Donthineni pr_crit_once("RSS is required but GICD doesn't support it\n"); 721021f6537SMarc Zyngier } 722021f6537SMarc Zyngier 723f736d65dSMarc Zyngier static bool gicv3_nolpi; 724f736d65dSMarc Zyngier 725f736d65dSMarc Zyngier static int __init gicv3_nolpi_cfg(char *buf) 726f736d65dSMarc Zyngier { 727f736d65dSMarc Zyngier return strtobool(buf, &gicv3_nolpi); 728f736d65dSMarc Zyngier } 729f736d65dSMarc Zyngier early_param("irqchip.gicv3_nolpi", gicv3_nolpi_cfg); 730f736d65dSMarc Zyngier 731da33f31dSMarc Zyngier static int gic_dist_supports_lpis(void) 732da33f31dSMarc Zyngier { 733d38a71c5SMarc Zyngier return (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && 734d38a71c5SMarc Zyngier !!(readl_relaxed(gic_data.dist_base + GICD_TYPER) & GICD_TYPER_LPIS) && 735d38a71c5SMarc Zyngier !gicv3_nolpi); 736da33f31dSMarc Zyngier } 737da33f31dSMarc Zyngier 738021f6537SMarc Zyngier static void gic_cpu_init(void) 739021f6537SMarc Zyngier { 740021f6537SMarc Zyngier void __iomem *rbase; 741021f6537SMarc Zyngier 742021f6537SMarc Zyngier /* Register ourselves with the rest of the world */ 743021f6537SMarc Zyngier if (gic_populate_rdist()) 744021f6537SMarc Zyngier return; 745021f6537SMarc Zyngier 746a2c22510SSudeep Holla gic_enable_redist(true); 747021f6537SMarc Zyngier 748021f6537SMarc Zyngier rbase = gic_data_rdist_sgi_base(); 749021f6537SMarc Zyngier 7507c9b9730SMarc Zyngier /* Configure SGIs/PPIs as non-secure Group-1 */ 7517c9b9730SMarc Zyngier writel_relaxed(~0, rbase + GICR_IGROUPR0); 7527c9b9730SMarc Zyngier 753021f6537SMarc Zyngier gic_cpu_config(rbase, gic_redist_wait_for_rwp); 754021f6537SMarc Zyngier 7553708d52fSSudeep Holla /* initialise system registers */ 7563708d52fSSudeep Holla gic_cpu_sys_reg_init(); 757021f6537SMarc Zyngier } 758021f6537SMarc Zyngier 759021f6537SMarc Zyngier #ifdef CONFIG_SMP 760021f6537SMarc Zyngier 761eda0d04aSShanker Donthineni #define MPIDR_TO_SGI_RS(mpidr) (MPIDR_RS(mpidr) << ICC_SGI1R_RS_SHIFT) 762eda0d04aSShanker Donthineni #define MPIDR_TO_SGI_CLUSTER_ID(mpidr) ((mpidr) & ~0xFUL) 763eda0d04aSShanker Donthineni 7646670a6d8SRichard Cochran static int gic_starting_cpu(unsigned int cpu) 7656670a6d8SRichard Cochran { 7666670a6d8SRichard Cochran gic_cpu_init(); 767d38a71c5SMarc Zyngier 768d38a71c5SMarc Zyngier if (gic_dist_supports_lpis()) 769d38a71c5SMarc Zyngier its_cpu_init(); 770d38a71c5SMarc Zyngier 7716670a6d8SRichard Cochran return 0; 7726670a6d8SRichard Cochran } 773021f6537SMarc Zyngier 774021f6537SMarc Zyngier static u16 gic_compute_target_list(int *base_cpu, const struct cpumask *mask, 775f6c86a41SJean-Philippe Brucker unsigned long cluster_id) 776021f6537SMarc Zyngier { 777727653d6SJames Morse int next_cpu, cpu = *base_cpu; 778f6c86a41SJean-Philippe Brucker unsigned long mpidr = cpu_logical_map(cpu); 779021f6537SMarc Zyngier u16 tlist = 0; 780021f6537SMarc Zyngier 781021f6537SMarc Zyngier while (cpu < nr_cpu_ids) { 782021f6537SMarc Zyngier tlist |= 1 << (mpidr & 0xf); 783021f6537SMarc Zyngier 784727653d6SJames Morse next_cpu = cpumask_next(cpu, mask); 785727653d6SJames Morse if (next_cpu >= nr_cpu_ids) 786021f6537SMarc Zyngier goto out; 787727653d6SJames Morse cpu = next_cpu; 788021f6537SMarc Zyngier 789021f6537SMarc Zyngier mpidr = cpu_logical_map(cpu); 790021f6537SMarc Zyngier 791eda0d04aSShanker Donthineni if (cluster_id != MPIDR_TO_SGI_CLUSTER_ID(mpidr)) { 792021f6537SMarc Zyngier cpu--; 793021f6537SMarc Zyngier goto out; 794021f6537SMarc Zyngier } 795021f6537SMarc Zyngier } 796021f6537SMarc Zyngier out: 797021f6537SMarc Zyngier *base_cpu = cpu; 798021f6537SMarc Zyngier return tlist; 799021f6537SMarc Zyngier } 800021f6537SMarc Zyngier 8017e580278SAndre Przywara #define MPIDR_TO_SGI_AFFINITY(cluster_id, level) \ 8027e580278SAndre Przywara (MPIDR_AFFINITY_LEVEL(cluster_id, level) \ 8037e580278SAndre Przywara << ICC_SGI1R_AFFINITY_## level ##_SHIFT) 8047e580278SAndre Przywara 805021f6537SMarc Zyngier static void gic_send_sgi(u64 cluster_id, u16 tlist, unsigned int irq) 806021f6537SMarc Zyngier { 807021f6537SMarc Zyngier u64 val; 808021f6537SMarc Zyngier 8097e580278SAndre Przywara val = (MPIDR_TO_SGI_AFFINITY(cluster_id, 3) | 8107e580278SAndre Przywara MPIDR_TO_SGI_AFFINITY(cluster_id, 2) | 8117e580278SAndre Przywara irq << ICC_SGI1R_SGI_ID_SHIFT | 8127e580278SAndre Przywara MPIDR_TO_SGI_AFFINITY(cluster_id, 1) | 813eda0d04aSShanker Donthineni MPIDR_TO_SGI_RS(cluster_id) | 8147e580278SAndre Przywara tlist << ICC_SGI1R_TARGET_LIST_SHIFT); 815021f6537SMarc Zyngier 816b6dd4d83SMark Salter pr_devel("CPU%d: ICC_SGI1R_EL1 %llx\n", smp_processor_id(), val); 817021f6537SMarc Zyngier gic_write_sgi1r(val); 818021f6537SMarc Zyngier } 819021f6537SMarc Zyngier 820021f6537SMarc Zyngier static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) 821021f6537SMarc Zyngier { 822021f6537SMarc Zyngier int cpu; 823021f6537SMarc Zyngier 824021f6537SMarc Zyngier if (WARN_ON(irq >= 16)) 825021f6537SMarc Zyngier return; 826021f6537SMarc Zyngier 827021f6537SMarc Zyngier /* 828021f6537SMarc Zyngier * Ensure that stores to Normal memory are visible to the 829021f6537SMarc Zyngier * other CPUs before issuing the IPI. 830021f6537SMarc Zyngier */ 83121ec30c0SShanker Donthineni wmb(); 832021f6537SMarc Zyngier 833f9b531feSRusty Russell for_each_cpu(cpu, mask) { 834eda0d04aSShanker Donthineni u64 cluster_id = MPIDR_TO_SGI_CLUSTER_ID(cpu_logical_map(cpu)); 835021f6537SMarc Zyngier u16 tlist; 836021f6537SMarc Zyngier 837021f6537SMarc Zyngier tlist = gic_compute_target_list(&cpu, mask, cluster_id); 838021f6537SMarc Zyngier gic_send_sgi(cluster_id, tlist, irq); 839021f6537SMarc Zyngier } 840021f6537SMarc Zyngier 841021f6537SMarc Zyngier /* Force the above writes to ICC_SGI1R_EL1 to be executed */ 842021f6537SMarc Zyngier isb(); 843021f6537SMarc Zyngier } 844021f6537SMarc Zyngier 845021f6537SMarc Zyngier static void gic_smp_init(void) 846021f6537SMarc Zyngier { 847021f6537SMarc Zyngier set_smp_cross_call(gic_raise_softirq); 8486896bcd1SThomas Gleixner cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_GIC_STARTING, 84973c1b41eSThomas Gleixner "irqchip/arm/gicv3:starting", 85073c1b41eSThomas Gleixner gic_starting_cpu, NULL); 851021f6537SMarc Zyngier } 852021f6537SMarc Zyngier 853021f6537SMarc Zyngier static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, 854021f6537SMarc Zyngier bool force) 855021f6537SMarc Zyngier { 85665a30f8bSSuzuki K Poulose unsigned int cpu; 857021f6537SMarc Zyngier void __iomem *reg; 858021f6537SMarc Zyngier int enabled; 859021f6537SMarc Zyngier u64 val; 860021f6537SMarc Zyngier 86165a30f8bSSuzuki K Poulose if (force) 86265a30f8bSSuzuki K Poulose cpu = cpumask_first(mask_val); 86365a30f8bSSuzuki K Poulose else 86465a30f8bSSuzuki K Poulose cpu = cpumask_any_and(mask_val, cpu_online_mask); 86565a30f8bSSuzuki K Poulose 866866d7c1bSSuzuki K Poulose if (cpu >= nr_cpu_ids) 867866d7c1bSSuzuki K Poulose return -EINVAL; 868866d7c1bSSuzuki K Poulose 869021f6537SMarc Zyngier if (gic_irq_in_rdist(d)) 870021f6537SMarc Zyngier return -EINVAL; 871021f6537SMarc Zyngier 872021f6537SMarc Zyngier /* If interrupt was enabled, disable it first */ 873021f6537SMarc Zyngier enabled = gic_peek_irq(d, GICD_ISENABLER); 874021f6537SMarc Zyngier if (enabled) 875021f6537SMarc Zyngier gic_mask_irq(d); 876021f6537SMarc Zyngier 877021f6537SMarc Zyngier reg = gic_dist_base(d) + GICD_IROUTER + (gic_irq(d) * 8); 878021f6537SMarc Zyngier val = gic_mpidr_to_affinity(cpu_logical_map(cpu)); 879021f6537SMarc Zyngier 88072c97126SJean-Philippe Brucker gic_write_irouter(val, reg); 881021f6537SMarc Zyngier 882021f6537SMarc Zyngier /* 883021f6537SMarc Zyngier * If the interrupt was enabled, enabled it again. Otherwise, 884021f6537SMarc Zyngier * just wait for the distributor to have digested our changes. 885021f6537SMarc Zyngier */ 886021f6537SMarc Zyngier if (enabled) 887021f6537SMarc Zyngier gic_unmask_irq(d); 888021f6537SMarc Zyngier else 889021f6537SMarc Zyngier gic_dist_wait_for_rwp(); 890021f6537SMarc Zyngier 891956ae91aSMarc Zyngier irq_data_update_effective_affinity(d, cpumask_of(cpu)); 892956ae91aSMarc Zyngier 8930fc6fa29SAntoine Tenart return IRQ_SET_MASK_OK_DONE; 894021f6537SMarc Zyngier } 895021f6537SMarc Zyngier #else 896021f6537SMarc Zyngier #define gic_set_affinity NULL 897021f6537SMarc Zyngier #define gic_smp_init() do { } while(0) 898021f6537SMarc Zyngier #endif 899021f6537SMarc Zyngier 9003708d52fSSudeep Holla #ifdef CONFIG_CPU_PM 9013708d52fSSudeep Holla static int gic_cpu_pm_notifier(struct notifier_block *self, 9023708d52fSSudeep Holla unsigned long cmd, void *v) 9033708d52fSSudeep Holla { 9043708d52fSSudeep Holla if (cmd == CPU_PM_EXIT) { 905ccd9432aSSudeep Holla if (gic_dist_security_disabled()) 9063708d52fSSudeep Holla gic_enable_redist(true); 9073708d52fSSudeep Holla gic_cpu_sys_reg_init(); 908ccd9432aSSudeep Holla } else if (cmd == CPU_PM_ENTER && gic_dist_security_disabled()) { 9093708d52fSSudeep Holla gic_write_grpen1(0); 9103708d52fSSudeep Holla gic_enable_redist(false); 9113708d52fSSudeep Holla } 9123708d52fSSudeep Holla return NOTIFY_OK; 9133708d52fSSudeep Holla } 9143708d52fSSudeep Holla 9153708d52fSSudeep Holla static struct notifier_block gic_cpu_pm_notifier_block = { 9163708d52fSSudeep Holla .notifier_call = gic_cpu_pm_notifier, 9173708d52fSSudeep Holla }; 9183708d52fSSudeep Holla 9193708d52fSSudeep Holla static void gic_cpu_pm_init(void) 9203708d52fSSudeep Holla { 9213708d52fSSudeep Holla cpu_pm_register_notifier(&gic_cpu_pm_notifier_block); 9223708d52fSSudeep Holla } 9233708d52fSSudeep Holla 9243708d52fSSudeep Holla #else 9253708d52fSSudeep Holla static inline void gic_cpu_pm_init(void) { } 9263708d52fSSudeep Holla #endif /* CONFIG_CPU_PM */ 9273708d52fSSudeep Holla 928021f6537SMarc Zyngier static struct irq_chip gic_chip = { 929021f6537SMarc Zyngier .name = "GICv3", 930021f6537SMarc Zyngier .irq_mask = gic_mask_irq, 931021f6537SMarc Zyngier .irq_unmask = gic_unmask_irq, 932021f6537SMarc Zyngier .irq_eoi = gic_eoi_irq, 933021f6537SMarc Zyngier .irq_set_type = gic_set_type, 934021f6537SMarc Zyngier .irq_set_affinity = gic_set_affinity, 935b594c6e2SMarc Zyngier .irq_get_irqchip_state = gic_irq_get_irqchip_state, 936b594c6e2SMarc Zyngier .irq_set_irqchip_state = gic_irq_set_irqchip_state, 9374110b5cbSMarc Zyngier .flags = IRQCHIP_SET_TYPE_MASKED | 9384110b5cbSMarc Zyngier IRQCHIP_SKIP_SET_WAKE | 9394110b5cbSMarc Zyngier IRQCHIP_MASK_ON_SUSPEND, 940021f6537SMarc Zyngier }; 941021f6537SMarc Zyngier 9420b6a3da9SMarc Zyngier static struct irq_chip gic_eoimode1_chip = { 9430b6a3da9SMarc Zyngier .name = "GICv3", 9440b6a3da9SMarc Zyngier .irq_mask = gic_eoimode1_mask_irq, 9450b6a3da9SMarc Zyngier .irq_unmask = gic_unmask_irq, 9460b6a3da9SMarc Zyngier .irq_eoi = gic_eoimode1_eoi_irq, 9470b6a3da9SMarc Zyngier .irq_set_type = gic_set_type, 9480b6a3da9SMarc Zyngier .irq_set_affinity = gic_set_affinity, 9490b6a3da9SMarc Zyngier .irq_get_irqchip_state = gic_irq_get_irqchip_state, 9500b6a3da9SMarc Zyngier .irq_set_irqchip_state = gic_irq_set_irqchip_state, 951530bf353SMarc Zyngier .irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity, 9524110b5cbSMarc Zyngier .flags = IRQCHIP_SET_TYPE_MASKED | 9534110b5cbSMarc Zyngier IRQCHIP_SKIP_SET_WAKE | 9544110b5cbSMarc Zyngier IRQCHIP_MASK_ON_SUSPEND, 9550b6a3da9SMarc Zyngier }; 9560b6a3da9SMarc Zyngier 957a4f9edb2SMarc Zyngier #define GIC_ID_NR (1U << GICD_TYPER_ID_BITS(gic_data.rdists.gicd_typer)) 958da33f31dSMarc Zyngier 959021f6537SMarc Zyngier static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq, 960021f6537SMarc Zyngier irq_hw_number_t hw) 961021f6537SMarc Zyngier { 9620b6a3da9SMarc Zyngier struct irq_chip *chip = &gic_chip; 9630b6a3da9SMarc Zyngier 964d01d3274SDavidlohr Bueso if (static_branch_likely(&supports_deactivate_key)) 9650b6a3da9SMarc Zyngier chip = &gic_eoimode1_chip; 9660b6a3da9SMarc Zyngier 967021f6537SMarc Zyngier /* SGIs are private to the core kernel */ 968021f6537SMarc Zyngier if (hw < 16) 969021f6537SMarc Zyngier return -EPERM; 970da33f31dSMarc Zyngier /* Nothing here */ 971da33f31dSMarc Zyngier if (hw >= gic_data.irq_nr && hw < 8192) 972da33f31dSMarc Zyngier return -EPERM; 973da33f31dSMarc Zyngier /* Off limits */ 974da33f31dSMarc Zyngier if (hw >= GIC_ID_NR) 975da33f31dSMarc Zyngier return -EPERM; 976da33f31dSMarc Zyngier 977021f6537SMarc Zyngier /* PPIs */ 978021f6537SMarc Zyngier if (hw < 32) { 979021f6537SMarc Zyngier irq_set_percpu_devid(irq); 9800b6a3da9SMarc Zyngier irq_domain_set_info(d, irq, hw, chip, d->host_data, 981443acc4fSMarc Zyngier handle_percpu_devid_irq, NULL, NULL); 982d17cab44SRob Herring irq_set_status_flags(irq, IRQ_NOAUTOEN); 983021f6537SMarc Zyngier } 984021f6537SMarc Zyngier /* SPIs */ 985021f6537SMarc Zyngier if (hw >= 32 && hw < gic_data.irq_nr) { 9860b6a3da9SMarc Zyngier irq_domain_set_info(d, irq, hw, chip, d->host_data, 987443acc4fSMarc Zyngier handle_fasteoi_irq, NULL, NULL); 988d17cab44SRob Herring irq_set_probe(irq); 989956ae91aSMarc Zyngier irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(irq))); 990021f6537SMarc Zyngier } 991da33f31dSMarc Zyngier /* LPIs */ 992da33f31dSMarc Zyngier if (hw >= 8192 && hw < GIC_ID_NR) { 993da33f31dSMarc Zyngier if (!gic_dist_supports_lpis()) 994da33f31dSMarc Zyngier return -EPERM; 9950b6a3da9SMarc Zyngier irq_domain_set_info(d, irq, hw, chip, d->host_data, 996da33f31dSMarc Zyngier handle_fasteoi_irq, NULL, NULL); 997da33f31dSMarc Zyngier } 998da33f31dSMarc Zyngier 999021f6537SMarc Zyngier return 0; 1000021f6537SMarc Zyngier } 1001021f6537SMarc Zyngier 100265da7d19SMarc Zyngier #define GIC_IRQ_TYPE_PARTITION (GIC_IRQ_TYPE_LPI + 1) 100365da7d19SMarc Zyngier 1004f833f57fSMarc Zyngier static int gic_irq_domain_translate(struct irq_domain *d, 1005f833f57fSMarc Zyngier struct irq_fwspec *fwspec, 1006f833f57fSMarc Zyngier unsigned long *hwirq, 1007f833f57fSMarc Zyngier unsigned int *type) 1008021f6537SMarc Zyngier { 1009f833f57fSMarc Zyngier if (is_of_node(fwspec->fwnode)) { 1010f833f57fSMarc Zyngier if (fwspec->param_count < 3) 1011021f6537SMarc Zyngier return -EINVAL; 1012021f6537SMarc Zyngier 1013db8c70ecSMarc Zyngier switch (fwspec->param[0]) { 1014db8c70ecSMarc Zyngier case 0: /* SPI */ 1015db8c70ecSMarc Zyngier *hwirq = fwspec->param[1] + 32; 1016db8c70ecSMarc Zyngier break; 1017db8c70ecSMarc Zyngier case 1: /* PPI */ 101865da7d19SMarc Zyngier case GIC_IRQ_TYPE_PARTITION: 1019f833f57fSMarc Zyngier *hwirq = fwspec->param[1] + 16; 1020db8c70ecSMarc Zyngier break; 1021db8c70ecSMarc Zyngier case GIC_IRQ_TYPE_LPI: /* LPI */ 1022db8c70ecSMarc Zyngier *hwirq = fwspec->param[1]; 1023db8c70ecSMarc Zyngier break; 1024db8c70ecSMarc Zyngier default: 1025db8c70ecSMarc Zyngier return -EINVAL; 1026db8c70ecSMarc Zyngier } 1027f833f57fSMarc Zyngier 1028f833f57fSMarc Zyngier *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; 10296ef6386eSMarc Zyngier 103065da7d19SMarc Zyngier /* 103165da7d19SMarc Zyngier * Make it clear that broken DTs are... broken. 103265da7d19SMarc Zyngier * Partitionned PPIs are an unfortunate exception. 103365da7d19SMarc Zyngier */ 103465da7d19SMarc Zyngier WARN_ON(*type == IRQ_TYPE_NONE && 103565da7d19SMarc Zyngier fwspec->param[0] != GIC_IRQ_TYPE_PARTITION); 1036f833f57fSMarc Zyngier return 0; 1037021f6537SMarc Zyngier } 1038021f6537SMarc Zyngier 1039ffa7d616STomasz Nowicki if (is_fwnode_irqchip(fwspec->fwnode)) { 1040ffa7d616STomasz Nowicki if(fwspec->param_count != 2) 1041ffa7d616STomasz Nowicki return -EINVAL; 1042ffa7d616STomasz Nowicki 1043ffa7d616STomasz Nowicki *hwirq = fwspec->param[0]; 1044ffa7d616STomasz Nowicki *type = fwspec->param[1]; 10456ef6386eSMarc Zyngier 10466ef6386eSMarc Zyngier WARN_ON(*type == IRQ_TYPE_NONE); 1047ffa7d616STomasz Nowicki return 0; 1048ffa7d616STomasz Nowicki } 1049ffa7d616STomasz Nowicki 1050f833f57fSMarc Zyngier return -EINVAL; 1051021f6537SMarc Zyngier } 1052021f6537SMarc Zyngier 1053443acc4fSMarc Zyngier static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, 1054443acc4fSMarc Zyngier unsigned int nr_irqs, void *arg) 1055443acc4fSMarc Zyngier { 1056443acc4fSMarc Zyngier int i, ret; 1057443acc4fSMarc Zyngier irq_hw_number_t hwirq; 1058443acc4fSMarc Zyngier unsigned int type = IRQ_TYPE_NONE; 1059f833f57fSMarc Zyngier struct irq_fwspec *fwspec = arg; 1060443acc4fSMarc Zyngier 1061f833f57fSMarc Zyngier ret = gic_irq_domain_translate(domain, fwspec, &hwirq, &type); 1062443acc4fSMarc Zyngier if (ret) 1063443acc4fSMarc Zyngier return ret; 1064443acc4fSMarc Zyngier 106563c16c6eSSuzuki K Poulose for (i = 0; i < nr_irqs; i++) { 106663c16c6eSSuzuki K Poulose ret = gic_irq_domain_map(domain, virq + i, hwirq + i); 106763c16c6eSSuzuki K Poulose if (ret) 106863c16c6eSSuzuki K Poulose return ret; 106963c16c6eSSuzuki K Poulose } 1070443acc4fSMarc Zyngier 1071443acc4fSMarc Zyngier return 0; 1072443acc4fSMarc Zyngier } 1073443acc4fSMarc Zyngier 1074443acc4fSMarc Zyngier static void gic_irq_domain_free(struct irq_domain *domain, unsigned int virq, 1075443acc4fSMarc Zyngier unsigned int nr_irqs) 1076443acc4fSMarc Zyngier { 1077443acc4fSMarc Zyngier int i; 1078443acc4fSMarc Zyngier 1079443acc4fSMarc Zyngier for (i = 0; i < nr_irqs; i++) { 1080443acc4fSMarc Zyngier struct irq_data *d = irq_domain_get_irq_data(domain, virq + i); 1081443acc4fSMarc Zyngier irq_set_handler(virq + i, NULL); 1082443acc4fSMarc Zyngier irq_domain_reset_irq_data(d); 1083443acc4fSMarc Zyngier } 1084443acc4fSMarc Zyngier } 1085443acc4fSMarc Zyngier 1086e3825ba1SMarc Zyngier static int gic_irq_domain_select(struct irq_domain *d, 1087e3825ba1SMarc Zyngier struct irq_fwspec *fwspec, 1088e3825ba1SMarc Zyngier enum irq_domain_bus_token bus_token) 1089e3825ba1SMarc Zyngier { 1090e3825ba1SMarc Zyngier /* Not for us */ 1091e3825ba1SMarc Zyngier if (fwspec->fwnode != d->fwnode) 1092e3825ba1SMarc Zyngier return 0; 1093e3825ba1SMarc Zyngier 1094e3825ba1SMarc Zyngier /* If this is not DT, then we have a single domain */ 1095e3825ba1SMarc Zyngier if (!is_of_node(fwspec->fwnode)) 1096e3825ba1SMarc Zyngier return 1; 1097e3825ba1SMarc Zyngier 1098e3825ba1SMarc Zyngier /* 1099e3825ba1SMarc Zyngier * If this is a PPI and we have a 4th (non-null) parameter, 1100e3825ba1SMarc Zyngier * then we need to match the partition domain. 1101e3825ba1SMarc Zyngier */ 1102e3825ba1SMarc Zyngier if (fwspec->param_count >= 4 && 1103e3825ba1SMarc Zyngier fwspec->param[0] == 1 && fwspec->param[3] != 0) 1104e3825ba1SMarc Zyngier return d == partition_get_domain(gic_data.ppi_descs[fwspec->param[1]]); 1105e3825ba1SMarc Zyngier 1106e3825ba1SMarc Zyngier return d == gic_data.domain; 1107e3825ba1SMarc Zyngier } 1108e3825ba1SMarc Zyngier 1109021f6537SMarc Zyngier static const struct irq_domain_ops gic_irq_domain_ops = { 1110f833f57fSMarc Zyngier .translate = gic_irq_domain_translate, 1111443acc4fSMarc Zyngier .alloc = gic_irq_domain_alloc, 1112443acc4fSMarc Zyngier .free = gic_irq_domain_free, 1113e3825ba1SMarc Zyngier .select = gic_irq_domain_select, 1114e3825ba1SMarc Zyngier }; 1115e3825ba1SMarc Zyngier 1116e3825ba1SMarc Zyngier static int partition_domain_translate(struct irq_domain *d, 1117e3825ba1SMarc Zyngier struct irq_fwspec *fwspec, 1118e3825ba1SMarc Zyngier unsigned long *hwirq, 1119e3825ba1SMarc Zyngier unsigned int *type) 1120e3825ba1SMarc Zyngier { 1121e3825ba1SMarc Zyngier struct device_node *np; 1122e3825ba1SMarc Zyngier int ret; 1123e3825ba1SMarc Zyngier 1124e3825ba1SMarc Zyngier np = of_find_node_by_phandle(fwspec->param[3]); 1125e3825ba1SMarc Zyngier if (WARN_ON(!np)) 1126e3825ba1SMarc Zyngier return -EINVAL; 1127e3825ba1SMarc Zyngier 1128e3825ba1SMarc Zyngier ret = partition_translate_id(gic_data.ppi_descs[fwspec->param[1]], 1129e3825ba1SMarc Zyngier of_node_to_fwnode(np)); 1130e3825ba1SMarc Zyngier if (ret < 0) 1131e3825ba1SMarc Zyngier return ret; 1132e3825ba1SMarc Zyngier 1133e3825ba1SMarc Zyngier *hwirq = ret; 1134e3825ba1SMarc Zyngier *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; 1135e3825ba1SMarc Zyngier 1136e3825ba1SMarc Zyngier return 0; 1137e3825ba1SMarc Zyngier } 1138e3825ba1SMarc Zyngier 1139e3825ba1SMarc Zyngier static const struct irq_domain_ops partition_domain_ops = { 1140e3825ba1SMarc Zyngier .translate = partition_domain_translate, 1141e3825ba1SMarc Zyngier .select = gic_irq_domain_select, 1142021f6537SMarc Zyngier }; 1143021f6537SMarc Zyngier 11449c8114c2SSrinivas Kandagatla static bool gic_enable_quirk_msm8996(void *data) 11459c8114c2SSrinivas Kandagatla { 11469c8114c2SSrinivas Kandagatla struct gic_chip_data *d = data; 11479c8114c2SSrinivas Kandagatla 11489c8114c2SSrinivas Kandagatla d->flags |= FLAGS_WORKAROUND_GICR_WAKER_MSM8996; 11499c8114c2SSrinivas Kandagatla 11509c8114c2SSrinivas Kandagatla return true; 11519c8114c2SSrinivas Kandagatla } 11529c8114c2SSrinivas Kandagatla 1153d98d0a99SJulien Thierry static void gic_enable_nmi_support(void) 1154d98d0a99SJulien Thierry { 1155d98d0a99SJulien Thierry static_branch_enable(&supports_pseudo_nmis); 1156d98d0a99SJulien Thierry } 1157d98d0a99SJulien Thierry 1158db57d746STomasz Nowicki static int __init gic_init_bases(void __iomem *dist_base, 1159db57d746STomasz Nowicki struct redist_region *rdist_regs, 1160db57d746STomasz Nowicki u32 nr_redist_regions, 1161db57d746STomasz Nowicki u64 redist_stride, 1162db57d746STomasz Nowicki struct fwnode_handle *handle) 1163db57d746STomasz Nowicki { 1164db57d746STomasz Nowicki u32 typer; 1165db57d746STomasz Nowicki int gic_irqs; 1166db57d746STomasz Nowicki int err; 1167db57d746STomasz Nowicki 1168db57d746STomasz Nowicki if (!is_hyp_mode_available()) 1169d01d3274SDavidlohr Bueso static_branch_disable(&supports_deactivate_key); 1170db57d746STomasz Nowicki 1171d01d3274SDavidlohr Bueso if (static_branch_likely(&supports_deactivate_key)) 1172db57d746STomasz Nowicki pr_info("GIC: Using split EOI/Deactivate mode\n"); 1173db57d746STomasz Nowicki 1174e3825ba1SMarc Zyngier gic_data.fwnode = handle; 1175db57d746STomasz Nowicki gic_data.dist_base = dist_base; 1176db57d746STomasz Nowicki gic_data.redist_regions = rdist_regs; 1177db57d746STomasz Nowicki gic_data.nr_redist_regions = nr_redist_regions; 1178db57d746STomasz Nowicki gic_data.redist_stride = redist_stride; 1179db57d746STomasz Nowicki 1180db57d746STomasz Nowicki /* 1181db57d746STomasz Nowicki * Find out how many interrupts are supported. 1182db57d746STomasz Nowicki * The GIC only supports up to 1020 interrupt sources (SGI+PPI+SPI) 1183db57d746STomasz Nowicki */ 1184db57d746STomasz Nowicki typer = readl_relaxed(gic_data.dist_base + GICD_TYPER); 1185a4f9edb2SMarc Zyngier gic_data.rdists.gicd_typer = typer; 1186db57d746STomasz Nowicki gic_irqs = GICD_TYPER_IRQS(typer); 1187db57d746STomasz Nowicki if (gic_irqs > 1020) 1188db57d746STomasz Nowicki gic_irqs = 1020; 1189db57d746STomasz Nowicki gic_data.irq_nr = gic_irqs; 1190db57d746STomasz Nowicki 1191db57d746STomasz Nowicki gic_data.domain = irq_domain_create_tree(handle, &gic_irq_domain_ops, 1192db57d746STomasz Nowicki &gic_data); 1193b2425b51SMarc Zyngier irq_domain_update_bus_token(gic_data.domain, DOMAIN_BUS_WIRED); 1194db57d746STomasz Nowicki gic_data.rdists.rdist = alloc_percpu(typeof(*gic_data.rdists.rdist)); 11950edc23eaSMarc Zyngier gic_data.rdists.has_vlpis = true; 11960edc23eaSMarc Zyngier gic_data.rdists.has_direct_lpi = true; 1197db57d746STomasz Nowicki 1198db57d746STomasz Nowicki if (WARN_ON(!gic_data.domain) || WARN_ON(!gic_data.rdists.rdist)) { 1199db57d746STomasz Nowicki err = -ENOMEM; 1200db57d746STomasz Nowicki goto out_free; 1201db57d746STomasz Nowicki } 1202db57d746STomasz Nowicki 1203eda0d04aSShanker Donthineni gic_data.has_rss = !!(typer & GICD_TYPER_RSS); 1204eda0d04aSShanker Donthineni pr_info("Distributor has %sRange Selector support\n", 1205eda0d04aSShanker Donthineni gic_data.has_rss ? "" : "no "); 1206eda0d04aSShanker Donthineni 120750528752SMarc Zyngier if (typer & GICD_TYPER_MBIS) { 120850528752SMarc Zyngier err = mbi_init(handle, gic_data.domain); 120950528752SMarc Zyngier if (err) 121050528752SMarc Zyngier pr_err("Failed to initialize MBIs\n"); 121150528752SMarc Zyngier } 121250528752SMarc Zyngier 1213db57d746STomasz Nowicki set_handle_irq(gic_handle_irq); 1214db57d746STomasz Nowicki 12150edc23eaSMarc Zyngier gic_update_vlpi_properties(); 12160edc23eaSMarc Zyngier 1217db57d746STomasz Nowicki gic_smp_init(); 1218db57d746STomasz Nowicki gic_dist_init(); 1219db57d746STomasz Nowicki gic_cpu_init(); 1220db57d746STomasz Nowicki gic_cpu_pm_init(); 1221db57d746STomasz Nowicki 1222d38a71c5SMarc Zyngier if (gic_dist_supports_lpis()) { 1223d38a71c5SMarc Zyngier its_init(handle, &gic_data.rdists, gic_data.domain); 1224d38a71c5SMarc Zyngier its_cpu_init(); 1225d38a71c5SMarc Zyngier } 1226d38a71c5SMarc Zyngier 1227d98d0a99SJulien Thierry if (gic_prio_masking_enabled()) { 1228d98d0a99SJulien Thierry if (!gic_has_group0() || gic_dist_security_disabled()) 1229d98d0a99SJulien Thierry gic_enable_nmi_support(); 1230d98d0a99SJulien Thierry else 1231d98d0a99SJulien Thierry pr_warn("SCR_EL3.FIQ is cleared, cannot enable use of pseudo-NMIs\n"); 1232d98d0a99SJulien Thierry } 1233d98d0a99SJulien Thierry 1234db57d746STomasz Nowicki return 0; 1235db57d746STomasz Nowicki 1236db57d746STomasz Nowicki out_free: 1237db57d746STomasz Nowicki if (gic_data.domain) 1238db57d746STomasz Nowicki irq_domain_remove(gic_data.domain); 1239db57d746STomasz Nowicki free_percpu(gic_data.rdists.rdist); 1240db57d746STomasz Nowicki return err; 1241db57d746STomasz Nowicki } 1242db57d746STomasz Nowicki 1243db57d746STomasz Nowicki static int __init gic_validate_dist_version(void __iomem *dist_base) 1244db57d746STomasz Nowicki { 1245db57d746STomasz Nowicki u32 reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK; 1246db57d746STomasz Nowicki 1247db57d746STomasz Nowicki if (reg != GIC_PIDR2_ARCH_GICv3 && reg != GIC_PIDR2_ARCH_GICv4) 1248db57d746STomasz Nowicki return -ENODEV; 1249db57d746STomasz Nowicki 1250db57d746STomasz Nowicki return 0; 1251db57d746STomasz Nowicki } 1252db57d746STomasz Nowicki 1253e3825ba1SMarc Zyngier /* Create all possible partitions at boot time */ 12547beaa24bSLinus Torvalds static void __init gic_populate_ppi_partitions(struct device_node *gic_node) 1255e3825ba1SMarc Zyngier { 1256e3825ba1SMarc Zyngier struct device_node *parts_node, *child_part; 1257e3825ba1SMarc Zyngier int part_idx = 0, i; 1258e3825ba1SMarc Zyngier int nr_parts; 1259e3825ba1SMarc Zyngier struct partition_affinity *parts; 1260e3825ba1SMarc Zyngier 126100ee9a1cSJohan Hovold parts_node = of_get_child_by_name(gic_node, "ppi-partitions"); 1262e3825ba1SMarc Zyngier if (!parts_node) 1263e3825ba1SMarc Zyngier return; 1264e3825ba1SMarc Zyngier 1265e3825ba1SMarc Zyngier nr_parts = of_get_child_count(parts_node); 1266e3825ba1SMarc Zyngier 1267e3825ba1SMarc Zyngier if (!nr_parts) 126800ee9a1cSJohan Hovold goto out_put_node; 1269e3825ba1SMarc Zyngier 12706396bb22SKees Cook parts = kcalloc(nr_parts, sizeof(*parts), GFP_KERNEL); 1271e3825ba1SMarc Zyngier if (WARN_ON(!parts)) 127200ee9a1cSJohan Hovold goto out_put_node; 1273e3825ba1SMarc Zyngier 1274e3825ba1SMarc Zyngier for_each_child_of_node(parts_node, child_part) { 1275e3825ba1SMarc Zyngier struct partition_affinity *part; 1276e3825ba1SMarc Zyngier int n; 1277e3825ba1SMarc Zyngier 1278e3825ba1SMarc Zyngier part = &parts[part_idx]; 1279e3825ba1SMarc Zyngier 1280e3825ba1SMarc Zyngier part->partition_id = of_node_to_fwnode(child_part); 1281e3825ba1SMarc Zyngier 12822ef790dcSRob Herring pr_info("GIC: PPI partition %pOFn[%d] { ", 12832ef790dcSRob Herring child_part, part_idx); 1284e3825ba1SMarc Zyngier 1285e3825ba1SMarc Zyngier n = of_property_count_elems_of_size(child_part, "affinity", 1286e3825ba1SMarc Zyngier sizeof(u32)); 1287e3825ba1SMarc Zyngier WARN_ON(n <= 0); 1288e3825ba1SMarc Zyngier 1289e3825ba1SMarc Zyngier for (i = 0; i < n; i++) { 1290e3825ba1SMarc Zyngier int err, cpu; 1291e3825ba1SMarc Zyngier u32 cpu_phandle; 1292e3825ba1SMarc Zyngier struct device_node *cpu_node; 1293e3825ba1SMarc Zyngier 1294e3825ba1SMarc Zyngier err = of_property_read_u32_index(child_part, "affinity", 1295e3825ba1SMarc Zyngier i, &cpu_phandle); 1296e3825ba1SMarc Zyngier if (WARN_ON(err)) 1297e3825ba1SMarc Zyngier continue; 1298e3825ba1SMarc Zyngier 1299e3825ba1SMarc Zyngier cpu_node = of_find_node_by_phandle(cpu_phandle); 1300e3825ba1SMarc Zyngier if (WARN_ON(!cpu_node)) 1301e3825ba1SMarc Zyngier continue; 1302e3825ba1SMarc Zyngier 1303c08ec7daSSuzuki K Poulose cpu = of_cpu_node_to_id(cpu_node); 1304c08ec7daSSuzuki K Poulose if (WARN_ON(cpu < 0)) 1305e3825ba1SMarc Zyngier continue; 1306e3825ba1SMarc Zyngier 1307e81f54c6SRob Herring pr_cont("%pOF[%d] ", cpu_node, cpu); 1308e3825ba1SMarc Zyngier 1309e3825ba1SMarc Zyngier cpumask_set_cpu(cpu, &part->mask); 1310e3825ba1SMarc Zyngier } 1311e3825ba1SMarc Zyngier 1312e3825ba1SMarc Zyngier pr_cont("}\n"); 1313e3825ba1SMarc Zyngier part_idx++; 1314e3825ba1SMarc Zyngier } 1315e3825ba1SMarc Zyngier 1316e3825ba1SMarc Zyngier for (i = 0; i < 16; i++) { 1317e3825ba1SMarc Zyngier unsigned int irq; 1318e3825ba1SMarc Zyngier struct partition_desc *desc; 1319e3825ba1SMarc Zyngier struct irq_fwspec ppi_fwspec = { 1320e3825ba1SMarc Zyngier .fwnode = gic_data.fwnode, 1321e3825ba1SMarc Zyngier .param_count = 3, 1322e3825ba1SMarc Zyngier .param = { 132365da7d19SMarc Zyngier [0] = GIC_IRQ_TYPE_PARTITION, 1324e3825ba1SMarc Zyngier [1] = i, 1325e3825ba1SMarc Zyngier [2] = IRQ_TYPE_NONE, 1326e3825ba1SMarc Zyngier }, 1327e3825ba1SMarc Zyngier }; 1328e3825ba1SMarc Zyngier 1329e3825ba1SMarc Zyngier irq = irq_create_fwspec_mapping(&ppi_fwspec); 1330e3825ba1SMarc Zyngier if (WARN_ON(!irq)) 1331e3825ba1SMarc Zyngier continue; 1332e3825ba1SMarc Zyngier desc = partition_create_desc(gic_data.fwnode, parts, nr_parts, 1333e3825ba1SMarc Zyngier irq, &partition_domain_ops); 1334e3825ba1SMarc Zyngier if (WARN_ON(!desc)) 1335e3825ba1SMarc Zyngier continue; 1336e3825ba1SMarc Zyngier 1337e3825ba1SMarc Zyngier gic_data.ppi_descs[i] = desc; 1338e3825ba1SMarc Zyngier } 133900ee9a1cSJohan Hovold 134000ee9a1cSJohan Hovold out_put_node: 134100ee9a1cSJohan Hovold of_node_put(parts_node); 1342e3825ba1SMarc Zyngier } 1343e3825ba1SMarc Zyngier 13441839e576SJulien Grall static void __init gic_of_setup_kvm_info(struct device_node *node) 13451839e576SJulien Grall { 13461839e576SJulien Grall int ret; 13471839e576SJulien Grall struct resource r; 13481839e576SJulien Grall u32 gicv_idx; 13491839e576SJulien Grall 13501839e576SJulien Grall gic_v3_kvm_info.type = GIC_V3; 13511839e576SJulien Grall 13521839e576SJulien Grall gic_v3_kvm_info.maint_irq = irq_of_parse_and_map(node, 0); 13531839e576SJulien Grall if (!gic_v3_kvm_info.maint_irq) 13541839e576SJulien Grall return; 13551839e576SJulien Grall 13561839e576SJulien Grall if (of_property_read_u32(node, "#redistributor-regions", 13571839e576SJulien Grall &gicv_idx)) 13581839e576SJulien Grall gicv_idx = 1; 13591839e576SJulien Grall 13601839e576SJulien Grall gicv_idx += 3; /* Also skip GICD, GICC, GICH */ 13611839e576SJulien Grall ret = of_address_to_resource(node, gicv_idx, &r); 13621839e576SJulien Grall if (!ret) 13631839e576SJulien Grall gic_v3_kvm_info.vcpu = r; 13641839e576SJulien Grall 13654bdf5025SMarc Zyngier gic_v3_kvm_info.has_v4 = gic_data.rdists.has_vlpis; 13661839e576SJulien Grall gic_set_kvm_info(&gic_v3_kvm_info); 13671839e576SJulien Grall } 13681839e576SJulien Grall 1369f70fdb42SSrinivas Kandagatla static const struct gic_quirk gic_quirks[] = { 1370f70fdb42SSrinivas Kandagatla { 13719c8114c2SSrinivas Kandagatla .desc = "GICv3: Qualcomm MSM8996 broken firmware", 13729c8114c2SSrinivas Kandagatla .compatible = "qcom,msm8996-gic-v3", 13739c8114c2SSrinivas Kandagatla .init = gic_enable_quirk_msm8996, 13749c8114c2SSrinivas Kandagatla }, 13759c8114c2SSrinivas Kandagatla { 1376f70fdb42SSrinivas Kandagatla } 1377f70fdb42SSrinivas Kandagatla }; 1378f70fdb42SSrinivas Kandagatla 1379021f6537SMarc Zyngier static int __init gic_of_init(struct device_node *node, struct device_node *parent) 1380021f6537SMarc Zyngier { 1381021f6537SMarc Zyngier void __iomem *dist_base; 1382f5c1434cSMarc Zyngier struct redist_region *rdist_regs; 1383021f6537SMarc Zyngier u64 redist_stride; 1384f5c1434cSMarc Zyngier u32 nr_redist_regions; 1385db57d746STomasz Nowicki int err, i; 1386021f6537SMarc Zyngier 1387021f6537SMarc Zyngier dist_base = of_iomap(node, 0); 1388021f6537SMarc Zyngier if (!dist_base) { 1389e81f54c6SRob Herring pr_err("%pOF: unable to map gic dist registers\n", node); 1390021f6537SMarc Zyngier return -ENXIO; 1391021f6537SMarc Zyngier } 1392021f6537SMarc Zyngier 1393db57d746STomasz Nowicki err = gic_validate_dist_version(dist_base); 1394db57d746STomasz Nowicki if (err) { 1395e81f54c6SRob Herring pr_err("%pOF: no distributor detected, giving up\n", node); 1396021f6537SMarc Zyngier goto out_unmap_dist; 1397021f6537SMarc Zyngier } 1398021f6537SMarc Zyngier 1399f5c1434cSMarc Zyngier if (of_property_read_u32(node, "#redistributor-regions", &nr_redist_regions)) 1400f5c1434cSMarc Zyngier nr_redist_regions = 1; 1401021f6537SMarc Zyngier 14026396bb22SKees Cook rdist_regs = kcalloc(nr_redist_regions, sizeof(*rdist_regs), 14036396bb22SKees Cook GFP_KERNEL); 1404f5c1434cSMarc Zyngier if (!rdist_regs) { 1405021f6537SMarc Zyngier err = -ENOMEM; 1406021f6537SMarc Zyngier goto out_unmap_dist; 1407021f6537SMarc Zyngier } 1408021f6537SMarc Zyngier 1409f5c1434cSMarc Zyngier for (i = 0; i < nr_redist_regions; i++) { 1410f5c1434cSMarc Zyngier struct resource res; 1411f5c1434cSMarc Zyngier int ret; 1412f5c1434cSMarc Zyngier 1413f5c1434cSMarc Zyngier ret = of_address_to_resource(node, 1 + i, &res); 1414f5c1434cSMarc Zyngier rdist_regs[i].redist_base = of_iomap(node, 1 + i); 1415f5c1434cSMarc Zyngier if (ret || !rdist_regs[i].redist_base) { 1416e81f54c6SRob Herring pr_err("%pOF: couldn't map region %d\n", node, i); 1417021f6537SMarc Zyngier err = -ENODEV; 1418021f6537SMarc Zyngier goto out_unmap_rdist; 1419021f6537SMarc Zyngier } 1420f5c1434cSMarc Zyngier rdist_regs[i].phys_base = res.start; 1421021f6537SMarc Zyngier } 1422021f6537SMarc Zyngier 1423021f6537SMarc Zyngier if (of_property_read_u64(node, "redistributor-stride", &redist_stride)) 1424021f6537SMarc Zyngier redist_stride = 0; 1425021f6537SMarc Zyngier 1426f70fdb42SSrinivas Kandagatla gic_enable_of_quirks(node, gic_quirks, &gic_data); 1427f70fdb42SSrinivas Kandagatla 1428db57d746STomasz Nowicki err = gic_init_bases(dist_base, rdist_regs, nr_redist_regions, 1429db57d746STomasz Nowicki redist_stride, &node->fwnode); 1430e3825ba1SMarc Zyngier if (err) 1431e3825ba1SMarc Zyngier goto out_unmap_rdist; 1432e3825ba1SMarc Zyngier 1433e3825ba1SMarc Zyngier gic_populate_ppi_partitions(node); 1434d33a3c8cSChristoffer Dall 1435d01d3274SDavidlohr Bueso if (static_branch_likely(&supports_deactivate_key)) 14361839e576SJulien Grall gic_of_setup_kvm_info(node); 1437021f6537SMarc Zyngier return 0; 1438021f6537SMarc Zyngier 1439021f6537SMarc Zyngier out_unmap_rdist: 1440f5c1434cSMarc Zyngier for (i = 0; i < nr_redist_regions; i++) 1441f5c1434cSMarc Zyngier if (rdist_regs[i].redist_base) 1442f5c1434cSMarc Zyngier iounmap(rdist_regs[i].redist_base); 1443f5c1434cSMarc Zyngier kfree(rdist_regs); 1444021f6537SMarc Zyngier out_unmap_dist: 1445021f6537SMarc Zyngier iounmap(dist_base); 1446021f6537SMarc Zyngier return err; 1447021f6537SMarc Zyngier } 1448021f6537SMarc Zyngier 1449021f6537SMarc Zyngier IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init); 1450ffa7d616STomasz Nowicki 1451ffa7d616STomasz Nowicki #ifdef CONFIG_ACPI 1452611f039fSJulien Grall static struct 1453611f039fSJulien Grall { 1454611f039fSJulien Grall void __iomem *dist_base; 1455611f039fSJulien Grall struct redist_region *redist_regs; 1456611f039fSJulien Grall u32 nr_redist_regions; 1457611f039fSJulien Grall bool single_redist; 14581839e576SJulien Grall u32 maint_irq; 14591839e576SJulien Grall int maint_irq_mode; 14601839e576SJulien Grall phys_addr_t vcpu_base; 1461611f039fSJulien Grall } acpi_data __initdata; 1462b70fb7afSTomasz Nowicki 1463b70fb7afSTomasz Nowicki static void __init 1464b70fb7afSTomasz Nowicki gic_acpi_register_redist(phys_addr_t phys_base, void __iomem *redist_base) 1465b70fb7afSTomasz Nowicki { 1466b70fb7afSTomasz Nowicki static int count = 0; 1467b70fb7afSTomasz Nowicki 1468611f039fSJulien Grall acpi_data.redist_regs[count].phys_base = phys_base; 1469611f039fSJulien Grall acpi_data.redist_regs[count].redist_base = redist_base; 1470611f039fSJulien Grall acpi_data.redist_regs[count].single_redist = acpi_data.single_redist; 1471b70fb7afSTomasz Nowicki count++; 1472b70fb7afSTomasz Nowicki } 1473ffa7d616STomasz Nowicki 1474ffa7d616STomasz Nowicki static int __init 1475ffa7d616STomasz Nowicki gic_acpi_parse_madt_redist(struct acpi_subtable_header *header, 1476ffa7d616STomasz Nowicki const unsigned long end) 1477ffa7d616STomasz Nowicki { 1478ffa7d616STomasz Nowicki struct acpi_madt_generic_redistributor *redist = 1479ffa7d616STomasz Nowicki (struct acpi_madt_generic_redistributor *)header; 1480ffa7d616STomasz Nowicki void __iomem *redist_base; 1481ffa7d616STomasz Nowicki 1482ffa7d616STomasz Nowicki redist_base = ioremap(redist->base_address, redist->length); 1483ffa7d616STomasz Nowicki if (!redist_base) { 1484ffa7d616STomasz Nowicki pr_err("Couldn't map GICR region @%llx\n", redist->base_address); 1485ffa7d616STomasz Nowicki return -ENOMEM; 1486ffa7d616STomasz Nowicki } 1487ffa7d616STomasz Nowicki 1488b70fb7afSTomasz Nowicki gic_acpi_register_redist(redist->base_address, redist_base); 1489ffa7d616STomasz Nowicki return 0; 1490ffa7d616STomasz Nowicki } 1491ffa7d616STomasz Nowicki 1492b70fb7afSTomasz Nowicki static int __init 1493b70fb7afSTomasz Nowicki gic_acpi_parse_madt_gicc(struct acpi_subtable_header *header, 1494b70fb7afSTomasz Nowicki const unsigned long end) 1495b70fb7afSTomasz Nowicki { 1496b70fb7afSTomasz Nowicki struct acpi_madt_generic_interrupt *gicc = 1497b70fb7afSTomasz Nowicki (struct acpi_madt_generic_interrupt *)header; 1498611f039fSJulien Grall u32 reg = readl_relaxed(acpi_data.dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK; 1499b70fb7afSTomasz Nowicki u32 size = reg == GIC_PIDR2_ARCH_GICv4 ? SZ_64K * 4 : SZ_64K * 2; 1500b70fb7afSTomasz Nowicki void __iomem *redist_base; 1501b70fb7afSTomasz Nowicki 1502ebe2f871SShanker Donthineni /* GICC entry which has !ACPI_MADT_ENABLED is not unusable so skip */ 1503ebe2f871SShanker Donthineni if (!(gicc->flags & ACPI_MADT_ENABLED)) 1504ebe2f871SShanker Donthineni return 0; 1505ebe2f871SShanker Donthineni 1506b70fb7afSTomasz Nowicki redist_base = ioremap(gicc->gicr_base_address, size); 1507b70fb7afSTomasz Nowicki if (!redist_base) 1508b70fb7afSTomasz Nowicki return -ENOMEM; 1509b70fb7afSTomasz Nowicki 1510b70fb7afSTomasz Nowicki gic_acpi_register_redist(gicc->gicr_base_address, redist_base); 1511b70fb7afSTomasz Nowicki return 0; 1512b70fb7afSTomasz Nowicki } 1513b70fb7afSTomasz Nowicki 1514b70fb7afSTomasz Nowicki static int __init gic_acpi_collect_gicr_base(void) 1515b70fb7afSTomasz Nowicki { 1516b70fb7afSTomasz Nowicki acpi_tbl_entry_handler redist_parser; 1517b70fb7afSTomasz Nowicki enum acpi_madt_type type; 1518b70fb7afSTomasz Nowicki 1519611f039fSJulien Grall if (acpi_data.single_redist) { 1520b70fb7afSTomasz Nowicki type = ACPI_MADT_TYPE_GENERIC_INTERRUPT; 1521b70fb7afSTomasz Nowicki redist_parser = gic_acpi_parse_madt_gicc; 1522b70fb7afSTomasz Nowicki } else { 1523b70fb7afSTomasz Nowicki type = ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR; 1524b70fb7afSTomasz Nowicki redist_parser = gic_acpi_parse_madt_redist; 1525b70fb7afSTomasz Nowicki } 1526b70fb7afSTomasz Nowicki 1527b70fb7afSTomasz Nowicki /* Collect redistributor base addresses in GICR entries */ 1528b70fb7afSTomasz Nowicki if (acpi_table_parse_madt(type, redist_parser, 0) > 0) 1529b70fb7afSTomasz Nowicki return 0; 1530b70fb7afSTomasz Nowicki 1531b70fb7afSTomasz Nowicki pr_info("No valid GICR entries exist\n"); 1532b70fb7afSTomasz Nowicki return -ENODEV; 1533b70fb7afSTomasz Nowicki } 1534b70fb7afSTomasz Nowicki 1535ffa7d616STomasz Nowicki static int __init gic_acpi_match_gicr(struct acpi_subtable_header *header, 1536ffa7d616STomasz Nowicki const unsigned long end) 1537ffa7d616STomasz Nowicki { 1538ffa7d616STomasz Nowicki /* Subtable presence means that redist exists, that's it */ 1539ffa7d616STomasz Nowicki return 0; 1540ffa7d616STomasz Nowicki } 1541ffa7d616STomasz Nowicki 1542b70fb7afSTomasz Nowicki static int __init gic_acpi_match_gicc(struct acpi_subtable_header *header, 1543b70fb7afSTomasz Nowicki const unsigned long end) 1544b70fb7afSTomasz Nowicki { 1545b70fb7afSTomasz Nowicki struct acpi_madt_generic_interrupt *gicc = 1546b70fb7afSTomasz Nowicki (struct acpi_madt_generic_interrupt *)header; 1547b70fb7afSTomasz Nowicki 1548b70fb7afSTomasz Nowicki /* 1549b70fb7afSTomasz Nowicki * If GICC is enabled and has valid gicr base address, then it means 1550b70fb7afSTomasz Nowicki * GICR base is presented via GICC 1551b70fb7afSTomasz Nowicki */ 1552b70fb7afSTomasz Nowicki if ((gicc->flags & ACPI_MADT_ENABLED) && gicc->gicr_base_address) 1553b70fb7afSTomasz Nowicki return 0; 1554b70fb7afSTomasz Nowicki 1555ebe2f871SShanker Donthineni /* 1556ebe2f871SShanker Donthineni * It's perfectly valid firmware can pass disabled GICC entry, driver 1557ebe2f871SShanker Donthineni * should not treat as errors, skip the entry instead of probe fail. 1558ebe2f871SShanker Donthineni */ 1559ebe2f871SShanker Donthineni if (!(gicc->flags & ACPI_MADT_ENABLED)) 1560ebe2f871SShanker Donthineni return 0; 1561ebe2f871SShanker Donthineni 1562b70fb7afSTomasz Nowicki return -ENODEV; 1563b70fb7afSTomasz Nowicki } 1564b70fb7afSTomasz Nowicki 1565b70fb7afSTomasz Nowicki static int __init gic_acpi_count_gicr_regions(void) 1566b70fb7afSTomasz Nowicki { 1567b70fb7afSTomasz Nowicki int count; 1568b70fb7afSTomasz Nowicki 1569b70fb7afSTomasz Nowicki /* 1570b70fb7afSTomasz Nowicki * Count how many redistributor regions we have. It is not allowed 1571b70fb7afSTomasz Nowicki * to mix redistributor description, GICR and GICC subtables have to be 1572b70fb7afSTomasz Nowicki * mutually exclusive. 1573b70fb7afSTomasz Nowicki */ 1574b70fb7afSTomasz Nowicki count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR, 1575b70fb7afSTomasz Nowicki gic_acpi_match_gicr, 0); 1576b70fb7afSTomasz Nowicki if (count > 0) { 1577611f039fSJulien Grall acpi_data.single_redist = false; 1578b70fb7afSTomasz Nowicki return count; 1579b70fb7afSTomasz Nowicki } 1580b70fb7afSTomasz Nowicki 1581b70fb7afSTomasz Nowicki count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT, 1582b70fb7afSTomasz Nowicki gic_acpi_match_gicc, 0); 1583b70fb7afSTomasz Nowicki if (count > 0) 1584611f039fSJulien Grall acpi_data.single_redist = true; 1585b70fb7afSTomasz Nowicki 1586b70fb7afSTomasz Nowicki return count; 1587b70fb7afSTomasz Nowicki } 1588b70fb7afSTomasz Nowicki 1589ffa7d616STomasz Nowicki static bool __init acpi_validate_gic_table(struct acpi_subtable_header *header, 1590ffa7d616STomasz Nowicki struct acpi_probe_entry *ape) 1591ffa7d616STomasz Nowicki { 1592ffa7d616STomasz Nowicki struct acpi_madt_generic_distributor *dist; 1593ffa7d616STomasz Nowicki int count; 1594ffa7d616STomasz Nowicki 1595ffa7d616STomasz Nowicki dist = (struct acpi_madt_generic_distributor *)header; 1596ffa7d616STomasz Nowicki if (dist->version != ape->driver_data) 1597ffa7d616STomasz Nowicki return false; 1598ffa7d616STomasz Nowicki 1599ffa7d616STomasz Nowicki /* We need to do that exercise anyway, the sooner the better */ 1600b70fb7afSTomasz Nowicki count = gic_acpi_count_gicr_regions(); 1601ffa7d616STomasz Nowicki if (count <= 0) 1602ffa7d616STomasz Nowicki return false; 1603ffa7d616STomasz Nowicki 1604611f039fSJulien Grall acpi_data.nr_redist_regions = count; 1605ffa7d616STomasz Nowicki return true; 1606ffa7d616STomasz Nowicki } 1607ffa7d616STomasz Nowicki 16081839e576SJulien Grall static int __init gic_acpi_parse_virt_madt_gicc(struct acpi_subtable_header *header, 16091839e576SJulien Grall const unsigned long end) 16101839e576SJulien Grall { 16111839e576SJulien Grall struct acpi_madt_generic_interrupt *gicc = 16121839e576SJulien Grall (struct acpi_madt_generic_interrupt *)header; 16131839e576SJulien Grall int maint_irq_mode; 16141839e576SJulien Grall static int first_madt = true; 16151839e576SJulien Grall 16161839e576SJulien Grall /* Skip unusable CPUs */ 16171839e576SJulien Grall if (!(gicc->flags & ACPI_MADT_ENABLED)) 16181839e576SJulien Grall return 0; 16191839e576SJulien Grall 16201839e576SJulien Grall maint_irq_mode = (gicc->flags & ACPI_MADT_VGIC_IRQ_MODE) ? 16211839e576SJulien Grall ACPI_EDGE_SENSITIVE : ACPI_LEVEL_SENSITIVE; 16221839e576SJulien Grall 16231839e576SJulien Grall if (first_madt) { 16241839e576SJulien Grall first_madt = false; 16251839e576SJulien Grall 16261839e576SJulien Grall acpi_data.maint_irq = gicc->vgic_interrupt; 16271839e576SJulien Grall acpi_data.maint_irq_mode = maint_irq_mode; 16281839e576SJulien Grall acpi_data.vcpu_base = gicc->gicv_base_address; 16291839e576SJulien Grall 16301839e576SJulien Grall return 0; 16311839e576SJulien Grall } 16321839e576SJulien Grall 16331839e576SJulien Grall /* 16341839e576SJulien Grall * The maintenance interrupt and GICV should be the same for every CPU 16351839e576SJulien Grall */ 16361839e576SJulien Grall if ((acpi_data.maint_irq != gicc->vgic_interrupt) || 16371839e576SJulien Grall (acpi_data.maint_irq_mode != maint_irq_mode) || 16381839e576SJulien Grall (acpi_data.vcpu_base != gicc->gicv_base_address)) 16391839e576SJulien Grall return -EINVAL; 16401839e576SJulien Grall 16411839e576SJulien Grall return 0; 16421839e576SJulien Grall } 16431839e576SJulien Grall 16441839e576SJulien Grall static bool __init gic_acpi_collect_virt_info(void) 16451839e576SJulien Grall { 16461839e576SJulien Grall int count; 16471839e576SJulien Grall 16481839e576SJulien Grall count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT, 16491839e576SJulien Grall gic_acpi_parse_virt_madt_gicc, 0); 16501839e576SJulien Grall 16511839e576SJulien Grall return (count > 0); 16521839e576SJulien Grall } 16531839e576SJulien Grall 1654ffa7d616STomasz Nowicki #define ACPI_GICV3_DIST_MEM_SIZE (SZ_64K) 16551839e576SJulien Grall #define ACPI_GICV2_VCTRL_MEM_SIZE (SZ_4K) 16561839e576SJulien Grall #define ACPI_GICV2_VCPU_MEM_SIZE (SZ_8K) 16571839e576SJulien Grall 16581839e576SJulien Grall static void __init gic_acpi_setup_kvm_info(void) 16591839e576SJulien Grall { 16601839e576SJulien Grall int irq; 16611839e576SJulien Grall 16621839e576SJulien Grall if (!gic_acpi_collect_virt_info()) { 16631839e576SJulien Grall pr_warn("Unable to get hardware information used for virtualization\n"); 16641839e576SJulien Grall return; 16651839e576SJulien Grall } 16661839e576SJulien Grall 16671839e576SJulien Grall gic_v3_kvm_info.type = GIC_V3; 16681839e576SJulien Grall 16691839e576SJulien Grall irq = acpi_register_gsi(NULL, acpi_data.maint_irq, 16701839e576SJulien Grall acpi_data.maint_irq_mode, 16711839e576SJulien Grall ACPI_ACTIVE_HIGH); 16721839e576SJulien Grall if (irq <= 0) 16731839e576SJulien Grall return; 16741839e576SJulien Grall 16751839e576SJulien Grall gic_v3_kvm_info.maint_irq = irq; 16761839e576SJulien Grall 16771839e576SJulien Grall if (acpi_data.vcpu_base) { 16781839e576SJulien Grall struct resource *vcpu = &gic_v3_kvm_info.vcpu; 16791839e576SJulien Grall 16801839e576SJulien Grall vcpu->flags = IORESOURCE_MEM; 16811839e576SJulien Grall vcpu->start = acpi_data.vcpu_base; 16821839e576SJulien Grall vcpu->end = vcpu->start + ACPI_GICV2_VCPU_MEM_SIZE - 1; 16831839e576SJulien Grall } 16841839e576SJulien Grall 16854bdf5025SMarc Zyngier gic_v3_kvm_info.has_v4 = gic_data.rdists.has_vlpis; 16861839e576SJulien Grall gic_set_kvm_info(&gic_v3_kvm_info); 16871839e576SJulien Grall } 1688ffa7d616STomasz Nowicki 1689ffa7d616STomasz Nowicki static int __init 1690ffa7d616STomasz Nowicki gic_acpi_init(struct acpi_subtable_header *header, const unsigned long end) 1691ffa7d616STomasz Nowicki { 1692ffa7d616STomasz Nowicki struct acpi_madt_generic_distributor *dist; 1693ffa7d616STomasz Nowicki struct fwnode_handle *domain_handle; 1694611f039fSJulien Grall size_t size; 1695b70fb7afSTomasz Nowicki int i, err; 1696ffa7d616STomasz Nowicki 1697ffa7d616STomasz Nowicki /* Get distributor base address */ 1698ffa7d616STomasz Nowicki dist = (struct acpi_madt_generic_distributor *)header; 1699611f039fSJulien Grall acpi_data.dist_base = ioremap(dist->base_address, 1700611f039fSJulien Grall ACPI_GICV3_DIST_MEM_SIZE); 1701611f039fSJulien Grall if (!acpi_data.dist_base) { 1702ffa7d616STomasz Nowicki pr_err("Unable to map GICD registers\n"); 1703ffa7d616STomasz Nowicki return -ENOMEM; 1704ffa7d616STomasz Nowicki } 1705ffa7d616STomasz Nowicki 1706611f039fSJulien Grall err = gic_validate_dist_version(acpi_data.dist_base); 1707ffa7d616STomasz Nowicki if (err) { 170871192a68SArvind Yadav pr_err("No distributor detected at @%p, giving up\n", 1709611f039fSJulien Grall acpi_data.dist_base); 1710ffa7d616STomasz Nowicki goto out_dist_unmap; 1711ffa7d616STomasz Nowicki } 1712ffa7d616STomasz Nowicki 1713611f039fSJulien Grall size = sizeof(*acpi_data.redist_regs) * acpi_data.nr_redist_regions; 1714611f039fSJulien Grall acpi_data.redist_regs = kzalloc(size, GFP_KERNEL); 1715611f039fSJulien Grall if (!acpi_data.redist_regs) { 1716ffa7d616STomasz Nowicki err = -ENOMEM; 1717ffa7d616STomasz Nowicki goto out_dist_unmap; 1718ffa7d616STomasz Nowicki } 1719ffa7d616STomasz Nowicki 1720b70fb7afSTomasz Nowicki err = gic_acpi_collect_gicr_base(); 1721b70fb7afSTomasz Nowicki if (err) 1722ffa7d616STomasz Nowicki goto out_redist_unmap; 1723ffa7d616STomasz Nowicki 1724611f039fSJulien Grall domain_handle = irq_domain_alloc_fwnode(acpi_data.dist_base); 1725ffa7d616STomasz Nowicki if (!domain_handle) { 1726ffa7d616STomasz Nowicki err = -ENOMEM; 1727ffa7d616STomasz Nowicki goto out_redist_unmap; 1728ffa7d616STomasz Nowicki } 1729ffa7d616STomasz Nowicki 1730611f039fSJulien Grall err = gic_init_bases(acpi_data.dist_base, acpi_data.redist_regs, 1731611f039fSJulien Grall acpi_data.nr_redist_regions, 0, domain_handle); 1732ffa7d616STomasz Nowicki if (err) 1733ffa7d616STomasz Nowicki goto out_fwhandle_free; 1734ffa7d616STomasz Nowicki 1735ffa7d616STomasz Nowicki acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, domain_handle); 1736d33a3c8cSChristoffer Dall 1737d01d3274SDavidlohr Bueso if (static_branch_likely(&supports_deactivate_key)) 17381839e576SJulien Grall gic_acpi_setup_kvm_info(); 17391839e576SJulien Grall 1740ffa7d616STomasz Nowicki return 0; 1741ffa7d616STomasz Nowicki 1742ffa7d616STomasz Nowicki out_fwhandle_free: 1743ffa7d616STomasz Nowicki irq_domain_free_fwnode(domain_handle); 1744ffa7d616STomasz Nowicki out_redist_unmap: 1745611f039fSJulien Grall for (i = 0; i < acpi_data.nr_redist_regions; i++) 1746611f039fSJulien Grall if (acpi_data.redist_regs[i].redist_base) 1747611f039fSJulien Grall iounmap(acpi_data.redist_regs[i].redist_base); 1748611f039fSJulien Grall kfree(acpi_data.redist_regs); 1749ffa7d616STomasz Nowicki out_dist_unmap: 1750611f039fSJulien Grall iounmap(acpi_data.dist_base); 1751ffa7d616STomasz Nowicki return err; 1752ffa7d616STomasz Nowicki } 1753ffa7d616STomasz Nowicki IRQCHIP_ACPI_DECLARE(gic_v3, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 1754ffa7d616STomasz Nowicki acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V3, 1755ffa7d616STomasz Nowicki gic_acpi_init); 1756ffa7d616STomasz Nowicki IRQCHIP_ACPI_DECLARE(gic_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 1757ffa7d616STomasz Nowicki acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V4, 1758ffa7d616STomasz Nowicki gic_acpi_init); 1759ffa7d616STomasz Nowicki IRQCHIP_ACPI_DECLARE(gic_v3_or_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 1760ffa7d616STomasz Nowicki acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_NONE, 1761ffa7d616STomasz Nowicki gic_acpi_init); 1762ffa7d616STomasz Nowicki #endif 1763