1caab277bSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 2021f6537SMarc Zyngier /* 30edc23eaSMarc Zyngier * Copyright (C) 2013-2017 ARM Limited, All Rights Reserved. 4021f6537SMarc Zyngier * Author: Marc Zyngier <marc.zyngier@arm.com> 5021f6537SMarc Zyngier */ 6021f6537SMarc Zyngier 768628bb8SJulien Grall #define pr_fmt(fmt) "GICv3: " fmt 868628bb8SJulien Grall 9ffa7d616STomasz Nowicki #include <linux/acpi.h> 10021f6537SMarc Zyngier #include <linux/cpu.h> 113708d52fSSudeep Holla #include <linux/cpu_pm.h> 12021f6537SMarc Zyngier #include <linux/delay.h> 13021f6537SMarc Zyngier #include <linux/interrupt.h> 14ffa7d616STomasz Nowicki #include <linux/irqdomain.h> 15021f6537SMarc Zyngier #include <linux/of.h> 16021f6537SMarc Zyngier #include <linux/of_address.h> 17021f6537SMarc Zyngier #include <linux/of_irq.h> 18021f6537SMarc Zyngier #include <linux/percpu.h> 19101b35f7SJulien Thierry #include <linux/refcount.h> 20021f6537SMarc Zyngier #include <linux/slab.h> 21021f6537SMarc Zyngier 2241a83e06SJoel Porquet #include <linux/irqchip.h> 231839e576SJulien Grall #include <linux/irqchip/arm-gic-common.h> 24021f6537SMarc Zyngier #include <linux/irqchip/arm-gic-v3.h> 25e3825ba1SMarc Zyngier #include <linux/irqchip/irq-partition-percpu.h> 26021f6537SMarc Zyngier 27021f6537SMarc Zyngier #include <asm/cputype.h> 28021f6537SMarc Zyngier #include <asm/exception.h> 29021f6537SMarc Zyngier #include <asm/smp_plat.h> 300b6a3da9SMarc Zyngier #include <asm/virt.h> 31021f6537SMarc Zyngier 32021f6537SMarc Zyngier #include "irq-gic-common.h" 33021f6537SMarc Zyngier 34f32c9266SJulien Thierry #define GICD_INT_NMI_PRI (GICD_INT_DEF_PRI & ~0x80) 35f32c9266SJulien Thierry 369c8114c2SSrinivas Kandagatla #define FLAGS_WORKAROUND_GICR_WAKER_MSM8996 (1ULL << 0) 37d01fd161SMarc Zyngier #define FLAGS_WORKAROUND_CAVIUM_ERRATUM_38539 (1ULL << 1) 389c8114c2SSrinivas Kandagatla 39f5c1434cSMarc Zyngier struct redist_region { 40f5c1434cSMarc Zyngier void __iomem *redist_base; 41f5c1434cSMarc Zyngier phys_addr_t phys_base; 42b70fb7afSTomasz Nowicki bool single_redist; 43f5c1434cSMarc Zyngier }; 44f5c1434cSMarc Zyngier 45021f6537SMarc Zyngier struct gic_chip_data { 46e3825ba1SMarc Zyngier struct fwnode_handle *fwnode; 47021f6537SMarc Zyngier void __iomem *dist_base; 48f5c1434cSMarc Zyngier struct redist_region *redist_regions; 49f5c1434cSMarc Zyngier struct rdists rdists; 50021f6537SMarc Zyngier struct irq_domain *domain; 51021f6537SMarc Zyngier u64 redist_stride; 52f5c1434cSMarc Zyngier u32 nr_redist_regions; 539c8114c2SSrinivas Kandagatla u64 flags; 54eda0d04aSShanker Donthineni bool has_rss; 551a60e1e6SMarc Zyngier unsigned int ppi_nr; 5652085d3fSMarc Zyngier struct partition_desc **ppi_descs; 57021f6537SMarc Zyngier }; 58021f6537SMarc Zyngier 59021f6537SMarc Zyngier static struct gic_chip_data gic_data __read_mostly; 60d01d3274SDavidlohr Bueso static DEFINE_STATIC_KEY_TRUE(supports_deactivate_key); 61021f6537SMarc Zyngier 62211bddd2SMarc Zyngier #define GIC_ID_NR (1U << GICD_TYPER_ID_BITS(gic_data.rdists.gicd_typer)) 63c107d613SZenghui Yu #define GIC_LINE_NR min(GICD_TYPER_SPIS(gic_data.rdists.gicd_typer), 1020U) 64211bddd2SMarc Zyngier #define GIC_ESPI_NR GICD_TYPER_ESPIS(gic_data.rdists.gicd_typer) 65211bddd2SMarc Zyngier 66d98d0a99SJulien Thierry /* 67d98d0a99SJulien Thierry * The behaviours of RPR and PMR registers differ depending on the value of 68d98d0a99SJulien Thierry * SCR_EL3.FIQ, and the behaviour of non-secure priority registers of the 69d98d0a99SJulien Thierry * distributor and redistributors depends on whether security is enabled in the 70d98d0a99SJulien Thierry * GIC. 71d98d0a99SJulien Thierry * 72d98d0a99SJulien Thierry * When security is enabled, non-secure priority values from the (re)distributor 73d98d0a99SJulien Thierry * are presented to the GIC CPUIF as follow: 74d98d0a99SJulien Thierry * (GIC_(R)DIST_PRI[irq] >> 1) | 0x80; 75d98d0a99SJulien Thierry * 76d98d0a99SJulien Thierry * If SCR_EL3.FIQ == 1, the values writen to/read from PMR and RPR at non-secure 77d98d0a99SJulien Thierry * EL1 are subject to a similar operation thus matching the priorities presented 78d98d0a99SJulien Thierry * from the (re)distributor when security is enabled. 79d98d0a99SJulien Thierry * 80d98d0a99SJulien Thierry * see GICv3/GICv4 Architecture Specification (IHI0069D): 81d98d0a99SJulien Thierry * - section 4.8.1 Non-secure accesses to register fields for Secure interrupt 82d98d0a99SJulien Thierry * priorities. 83d98d0a99SJulien Thierry * - Figure 4-7 Secure read of the priority field for a Non-secure Group 1 84d98d0a99SJulien Thierry * interrupt. 85d98d0a99SJulien Thierry * 86d98d0a99SJulien Thierry * For now, we only support pseudo-NMIs if we have non-secure view of 87d98d0a99SJulien Thierry * priorities. 88d98d0a99SJulien Thierry */ 89d98d0a99SJulien Thierry static DEFINE_STATIC_KEY_FALSE(supports_pseudo_nmis); 90d98d0a99SJulien Thierry 91f2266504SMarc Zyngier /* 92f2266504SMarc Zyngier * Global static key controlling whether an update to PMR allowing more 93f2266504SMarc Zyngier * interrupts requires to be propagated to the redistributor (DSB SY). 94f2266504SMarc Zyngier * And this needs to be exported for modules to be able to enable 95f2266504SMarc Zyngier * interrupts... 96f2266504SMarc Zyngier */ 97f2266504SMarc Zyngier DEFINE_STATIC_KEY_FALSE(gic_pmr_sync); 98f2266504SMarc Zyngier EXPORT_SYMBOL(gic_pmr_sync); 99f2266504SMarc Zyngier 100101b35f7SJulien Thierry /* ppi_nmi_refs[n] == number of cpus having ppi[n + 16] set as NMI */ 10181a43273SMarc Zyngier static refcount_t *ppi_nmi_refs; 102101b35f7SJulien Thierry 1031839e576SJulien Grall static struct gic_kvm_info gic_v3_kvm_info; 104eda0d04aSShanker Donthineni static DEFINE_PER_CPU(bool, has_rss); 1051839e576SJulien Grall 106eda0d04aSShanker Donthineni #define MPIDR_RS(mpidr) (((mpidr) & 0xF0UL) >> 4) 107f5c1434cSMarc Zyngier #define gic_data_rdist() (this_cpu_ptr(gic_data.rdists.rdist)) 108f5c1434cSMarc Zyngier #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base) 109021f6537SMarc Zyngier #define gic_data_rdist_sgi_base() (gic_data_rdist_rd_base() + SZ_64K) 110021f6537SMarc Zyngier 111021f6537SMarc Zyngier /* Our default, arbitrary priority value. Linux only uses one anyway. */ 112021f6537SMarc Zyngier #define DEFAULT_PMR_VALUE 0xf0 113021f6537SMarc Zyngier 114e91b036eSMarc Zyngier enum gic_intid_range { 115e91b036eSMarc Zyngier PPI_RANGE, 116e91b036eSMarc Zyngier SPI_RANGE, 1175f51f803SMarc Zyngier EPPI_RANGE, 118211bddd2SMarc Zyngier ESPI_RANGE, 119e91b036eSMarc Zyngier LPI_RANGE, 120e91b036eSMarc Zyngier __INVALID_RANGE__ 121e91b036eSMarc Zyngier }; 122e91b036eSMarc Zyngier 123e91b036eSMarc Zyngier static enum gic_intid_range __get_intid_range(irq_hw_number_t hwirq) 124e91b036eSMarc Zyngier { 125e91b036eSMarc Zyngier switch (hwirq) { 126e91b036eSMarc Zyngier case 16 ... 31: 127e91b036eSMarc Zyngier return PPI_RANGE; 128e91b036eSMarc Zyngier case 32 ... 1019: 129e91b036eSMarc Zyngier return SPI_RANGE; 1305f51f803SMarc Zyngier case EPPI_BASE_INTID ... (EPPI_BASE_INTID + 63): 1315f51f803SMarc Zyngier return EPPI_RANGE; 132211bddd2SMarc Zyngier case ESPI_BASE_INTID ... (ESPI_BASE_INTID + 1023): 133211bddd2SMarc Zyngier return ESPI_RANGE; 134e91b036eSMarc Zyngier case 8192 ... GENMASK(23, 0): 135e91b036eSMarc Zyngier return LPI_RANGE; 136e91b036eSMarc Zyngier default: 137e91b036eSMarc Zyngier return __INVALID_RANGE__; 138e91b036eSMarc Zyngier } 139e91b036eSMarc Zyngier } 140e91b036eSMarc Zyngier 141e91b036eSMarc Zyngier static enum gic_intid_range get_intid_range(struct irq_data *d) 142e91b036eSMarc Zyngier { 143e91b036eSMarc Zyngier return __get_intid_range(d->hwirq); 144e91b036eSMarc Zyngier } 145e91b036eSMarc Zyngier 146021f6537SMarc Zyngier static inline unsigned int gic_irq(struct irq_data *d) 147021f6537SMarc Zyngier { 148021f6537SMarc Zyngier return d->hwirq; 149021f6537SMarc Zyngier } 150021f6537SMarc Zyngier 151021f6537SMarc Zyngier static inline int gic_irq_in_rdist(struct irq_data *d) 152021f6537SMarc Zyngier { 1535f51f803SMarc Zyngier enum gic_intid_range range = get_intid_range(d); 1545f51f803SMarc Zyngier return range == PPI_RANGE || range == EPPI_RANGE; 155021f6537SMarc Zyngier } 156021f6537SMarc Zyngier 157021f6537SMarc Zyngier static inline void __iomem *gic_dist_base(struct irq_data *d) 158021f6537SMarc Zyngier { 159e91b036eSMarc Zyngier switch (get_intid_range(d)) { 160e91b036eSMarc Zyngier case PPI_RANGE: 1615f51f803SMarc Zyngier case EPPI_RANGE: 162e91b036eSMarc Zyngier /* SGI+PPI -> SGI_base for this CPU */ 163021f6537SMarc Zyngier return gic_data_rdist_sgi_base(); 164021f6537SMarc Zyngier 165e91b036eSMarc Zyngier case SPI_RANGE: 166211bddd2SMarc Zyngier case ESPI_RANGE: 167e91b036eSMarc Zyngier /* SPI -> dist_base */ 168021f6537SMarc Zyngier return gic_data.dist_base; 169021f6537SMarc Zyngier 170e91b036eSMarc Zyngier default: 171021f6537SMarc Zyngier return NULL; 172021f6537SMarc Zyngier } 173e91b036eSMarc Zyngier } 174021f6537SMarc Zyngier 175021f6537SMarc Zyngier static void gic_do_wait_for_rwp(void __iomem *base) 176021f6537SMarc Zyngier { 177021f6537SMarc Zyngier u32 count = 1000000; /* 1s! */ 178021f6537SMarc Zyngier 179021f6537SMarc Zyngier while (readl_relaxed(base + GICD_CTLR) & GICD_CTLR_RWP) { 180021f6537SMarc Zyngier count--; 181021f6537SMarc Zyngier if (!count) { 182021f6537SMarc Zyngier pr_err_ratelimited("RWP timeout, gone fishing\n"); 183021f6537SMarc Zyngier return; 184021f6537SMarc Zyngier } 185021f6537SMarc Zyngier cpu_relax(); 186021f6537SMarc Zyngier udelay(1); 1872c542426SDaode Huang } 188021f6537SMarc Zyngier } 189021f6537SMarc Zyngier 190021f6537SMarc Zyngier /* Wait for completion of a distributor change */ 191021f6537SMarc Zyngier static void gic_dist_wait_for_rwp(void) 192021f6537SMarc Zyngier { 193021f6537SMarc Zyngier gic_do_wait_for_rwp(gic_data.dist_base); 194021f6537SMarc Zyngier } 195021f6537SMarc Zyngier 196021f6537SMarc Zyngier /* Wait for completion of a redistributor change */ 197021f6537SMarc Zyngier static void gic_redist_wait_for_rwp(void) 198021f6537SMarc Zyngier { 199021f6537SMarc Zyngier gic_do_wait_for_rwp(gic_data_rdist_rd_base()); 200021f6537SMarc Zyngier } 201021f6537SMarc Zyngier 2027936e914SJean-Philippe Brucker #ifdef CONFIG_ARM64 2036d4e11c5SRobert Richter 2046d4e11c5SRobert Richter static u64 __maybe_unused gic_read_iar(void) 2056d4e11c5SRobert Richter { 206a4023f68SSuzuki K Poulose if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_23154)) 2076d4e11c5SRobert Richter return gic_read_iar_cavium_thunderx(); 2086d4e11c5SRobert Richter else 2096d4e11c5SRobert Richter return gic_read_iar_common(); 2106d4e11c5SRobert Richter } 2117936e914SJean-Philippe Brucker #endif 212021f6537SMarc Zyngier 213a2c22510SSudeep Holla static void gic_enable_redist(bool enable) 214021f6537SMarc Zyngier { 215021f6537SMarc Zyngier void __iomem *rbase; 216021f6537SMarc Zyngier u32 count = 1000000; /* 1s! */ 217021f6537SMarc Zyngier u32 val; 218021f6537SMarc Zyngier 2199c8114c2SSrinivas Kandagatla if (gic_data.flags & FLAGS_WORKAROUND_GICR_WAKER_MSM8996) 2209c8114c2SSrinivas Kandagatla return; 2219c8114c2SSrinivas Kandagatla 222021f6537SMarc Zyngier rbase = gic_data_rdist_rd_base(); 223021f6537SMarc Zyngier 224021f6537SMarc Zyngier val = readl_relaxed(rbase + GICR_WAKER); 225a2c22510SSudeep Holla if (enable) 226a2c22510SSudeep Holla /* Wake up this CPU redistributor */ 227021f6537SMarc Zyngier val &= ~GICR_WAKER_ProcessorSleep; 228a2c22510SSudeep Holla else 229a2c22510SSudeep Holla val |= GICR_WAKER_ProcessorSleep; 230021f6537SMarc Zyngier writel_relaxed(val, rbase + GICR_WAKER); 231021f6537SMarc Zyngier 232a2c22510SSudeep Holla if (!enable) { /* Check that GICR_WAKER is writeable */ 233a2c22510SSudeep Holla val = readl_relaxed(rbase + GICR_WAKER); 234a2c22510SSudeep Holla if (!(val & GICR_WAKER_ProcessorSleep)) 235a2c22510SSudeep Holla return; /* No PM support in this redistributor */ 236021f6537SMarc Zyngier } 237a2c22510SSudeep Holla 238d102eb5cSDan Carpenter while (--count) { 239a2c22510SSudeep Holla val = readl_relaxed(rbase + GICR_WAKER); 240cf1d9d11SAndrew Jones if (enable ^ (bool)(val & GICR_WAKER_ChildrenAsleep)) 241a2c22510SSudeep Holla break; 242021f6537SMarc Zyngier cpu_relax(); 243021f6537SMarc Zyngier udelay(1); 2442c542426SDaode Huang } 245a2c22510SSudeep Holla if (!count) 246a2c22510SSudeep Holla pr_err_ratelimited("redistributor failed to %s...\n", 247a2c22510SSudeep Holla enable ? "wakeup" : "sleep"); 248021f6537SMarc Zyngier } 249021f6537SMarc Zyngier 250021f6537SMarc Zyngier /* 251021f6537SMarc Zyngier * Routines to disable, enable, EOI and route interrupts 252021f6537SMarc Zyngier */ 253e91b036eSMarc Zyngier static u32 convert_offset_index(struct irq_data *d, u32 offset, u32 *index) 254e91b036eSMarc Zyngier { 255e91b036eSMarc Zyngier switch (get_intid_range(d)) { 256e91b036eSMarc Zyngier case PPI_RANGE: 257e91b036eSMarc Zyngier case SPI_RANGE: 258e91b036eSMarc Zyngier *index = d->hwirq; 259e91b036eSMarc Zyngier return offset; 2605f51f803SMarc Zyngier case EPPI_RANGE: 2615f51f803SMarc Zyngier /* 2625f51f803SMarc Zyngier * Contrary to the ESPI range, the EPPI range is contiguous 2635f51f803SMarc Zyngier * to the PPI range in the registers, so let's adjust the 2645f51f803SMarc Zyngier * displacement accordingly. Consistency is overrated. 2655f51f803SMarc Zyngier */ 2665f51f803SMarc Zyngier *index = d->hwirq - EPPI_BASE_INTID + 32; 2675f51f803SMarc Zyngier return offset; 268211bddd2SMarc Zyngier case ESPI_RANGE: 269211bddd2SMarc Zyngier *index = d->hwirq - ESPI_BASE_INTID; 270211bddd2SMarc Zyngier switch (offset) { 271211bddd2SMarc Zyngier case GICD_ISENABLER: 272211bddd2SMarc Zyngier return GICD_ISENABLERnE; 273211bddd2SMarc Zyngier case GICD_ICENABLER: 274211bddd2SMarc Zyngier return GICD_ICENABLERnE; 275211bddd2SMarc Zyngier case GICD_ISPENDR: 276211bddd2SMarc Zyngier return GICD_ISPENDRnE; 277211bddd2SMarc Zyngier case GICD_ICPENDR: 278211bddd2SMarc Zyngier return GICD_ICPENDRnE; 279211bddd2SMarc Zyngier case GICD_ISACTIVER: 280211bddd2SMarc Zyngier return GICD_ISACTIVERnE; 281211bddd2SMarc Zyngier case GICD_ICACTIVER: 282211bddd2SMarc Zyngier return GICD_ICACTIVERnE; 283211bddd2SMarc Zyngier case GICD_IPRIORITYR: 284211bddd2SMarc Zyngier return GICD_IPRIORITYRnE; 285211bddd2SMarc Zyngier case GICD_ICFGR: 286211bddd2SMarc Zyngier return GICD_ICFGRnE; 287211bddd2SMarc Zyngier case GICD_IROUTER: 288211bddd2SMarc Zyngier return GICD_IROUTERnE; 289211bddd2SMarc Zyngier default: 290211bddd2SMarc Zyngier break; 291211bddd2SMarc Zyngier } 292211bddd2SMarc Zyngier break; 293e91b036eSMarc Zyngier default: 294e91b036eSMarc Zyngier break; 295e91b036eSMarc Zyngier } 296e91b036eSMarc Zyngier 297e91b036eSMarc Zyngier WARN_ON(1); 298e91b036eSMarc Zyngier *index = d->hwirq; 299e91b036eSMarc Zyngier return offset; 300e91b036eSMarc Zyngier } 301e91b036eSMarc Zyngier 302b594c6e2SMarc Zyngier static int gic_peek_irq(struct irq_data *d, u32 offset) 303b594c6e2SMarc Zyngier { 304b594c6e2SMarc Zyngier void __iomem *base; 305e91b036eSMarc Zyngier u32 index, mask; 306e91b036eSMarc Zyngier 307e91b036eSMarc Zyngier offset = convert_offset_index(d, offset, &index); 308e91b036eSMarc Zyngier mask = 1 << (index % 32); 309b594c6e2SMarc Zyngier 310b594c6e2SMarc Zyngier if (gic_irq_in_rdist(d)) 311b594c6e2SMarc Zyngier base = gic_data_rdist_sgi_base(); 312b594c6e2SMarc Zyngier else 313b594c6e2SMarc Zyngier base = gic_data.dist_base; 314b594c6e2SMarc Zyngier 315e91b036eSMarc Zyngier return !!(readl_relaxed(base + offset + (index / 32) * 4) & mask); 316b594c6e2SMarc Zyngier } 317b594c6e2SMarc Zyngier 318021f6537SMarc Zyngier static void gic_poke_irq(struct irq_data *d, u32 offset) 319021f6537SMarc Zyngier { 320021f6537SMarc Zyngier void (*rwp_wait)(void); 321021f6537SMarc Zyngier void __iomem *base; 322e91b036eSMarc Zyngier u32 index, mask; 323e91b036eSMarc Zyngier 324e91b036eSMarc Zyngier offset = convert_offset_index(d, offset, &index); 325e91b036eSMarc Zyngier mask = 1 << (index % 32); 326021f6537SMarc Zyngier 327021f6537SMarc Zyngier if (gic_irq_in_rdist(d)) { 328021f6537SMarc Zyngier base = gic_data_rdist_sgi_base(); 329021f6537SMarc Zyngier rwp_wait = gic_redist_wait_for_rwp; 330021f6537SMarc Zyngier } else { 331021f6537SMarc Zyngier base = gic_data.dist_base; 332021f6537SMarc Zyngier rwp_wait = gic_dist_wait_for_rwp; 333021f6537SMarc Zyngier } 334021f6537SMarc Zyngier 335e91b036eSMarc Zyngier writel_relaxed(mask, base + offset + (index / 32) * 4); 336021f6537SMarc Zyngier rwp_wait(); 337021f6537SMarc Zyngier } 338021f6537SMarc Zyngier 339021f6537SMarc Zyngier static void gic_mask_irq(struct irq_data *d) 340021f6537SMarc Zyngier { 341021f6537SMarc Zyngier gic_poke_irq(d, GICD_ICENABLER); 342021f6537SMarc Zyngier } 343021f6537SMarc Zyngier 3440b6a3da9SMarc Zyngier static void gic_eoimode1_mask_irq(struct irq_data *d) 3450b6a3da9SMarc Zyngier { 3460b6a3da9SMarc Zyngier gic_mask_irq(d); 347530bf353SMarc Zyngier /* 348530bf353SMarc Zyngier * When masking a forwarded interrupt, make sure it is 349530bf353SMarc Zyngier * deactivated as well. 350530bf353SMarc Zyngier * 351530bf353SMarc Zyngier * This ensures that an interrupt that is getting 352530bf353SMarc Zyngier * disabled/masked will not get "stuck", because there is 353530bf353SMarc Zyngier * noone to deactivate it (guest is being terminated). 354530bf353SMarc Zyngier */ 3554df7f54dSThomas Gleixner if (irqd_is_forwarded_to_vcpu(d)) 356530bf353SMarc Zyngier gic_poke_irq(d, GICD_ICACTIVER); 3570b6a3da9SMarc Zyngier } 3580b6a3da9SMarc Zyngier 359021f6537SMarc Zyngier static void gic_unmask_irq(struct irq_data *d) 360021f6537SMarc Zyngier { 361021f6537SMarc Zyngier gic_poke_irq(d, GICD_ISENABLER); 362021f6537SMarc Zyngier } 363021f6537SMarc Zyngier 364d98d0a99SJulien Thierry static inline bool gic_supports_nmi(void) 365d98d0a99SJulien Thierry { 366d98d0a99SJulien Thierry return IS_ENABLED(CONFIG_ARM64_PSEUDO_NMI) && 367d98d0a99SJulien Thierry static_branch_likely(&supports_pseudo_nmis); 368d98d0a99SJulien Thierry } 369d98d0a99SJulien Thierry 370b594c6e2SMarc Zyngier static int gic_irq_set_irqchip_state(struct irq_data *d, 371b594c6e2SMarc Zyngier enum irqchip_irq_state which, bool val) 372b594c6e2SMarc Zyngier { 373b594c6e2SMarc Zyngier u32 reg; 374b594c6e2SMarc Zyngier 375211bddd2SMarc Zyngier if (d->hwirq >= 8192) /* PPI/SPI only */ 376b594c6e2SMarc Zyngier return -EINVAL; 377b594c6e2SMarc Zyngier 378b594c6e2SMarc Zyngier switch (which) { 379b594c6e2SMarc Zyngier case IRQCHIP_STATE_PENDING: 380b594c6e2SMarc Zyngier reg = val ? GICD_ISPENDR : GICD_ICPENDR; 381b594c6e2SMarc Zyngier break; 382b594c6e2SMarc Zyngier 383b594c6e2SMarc Zyngier case IRQCHIP_STATE_ACTIVE: 384b594c6e2SMarc Zyngier reg = val ? GICD_ISACTIVER : GICD_ICACTIVER; 385b594c6e2SMarc Zyngier break; 386b594c6e2SMarc Zyngier 387b594c6e2SMarc Zyngier case IRQCHIP_STATE_MASKED: 388b594c6e2SMarc Zyngier reg = val ? GICD_ICENABLER : GICD_ISENABLER; 389b594c6e2SMarc Zyngier break; 390b594c6e2SMarc Zyngier 391b594c6e2SMarc Zyngier default: 392b594c6e2SMarc Zyngier return -EINVAL; 393b594c6e2SMarc Zyngier } 394b594c6e2SMarc Zyngier 395b594c6e2SMarc Zyngier gic_poke_irq(d, reg); 396b594c6e2SMarc Zyngier return 0; 397b594c6e2SMarc Zyngier } 398b594c6e2SMarc Zyngier 399b594c6e2SMarc Zyngier static int gic_irq_get_irqchip_state(struct irq_data *d, 400b594c6e2SMarc Zyngier enum irqchip_irq_state which, bool *val) 401b594c6e2SMarc Zyngier { 402211bddd2SMarc Zyngier if (d->hwirq >= 8192) /* PPI/SPI only */ 403b594c6e2SMarc Zyngier return -EINVAL; 404b594c6e2SMarc Zyngier 405b594c6e2SMarc Zyngier switch (which) { 406b594c6e2SMarc Zyngier case IRQCHIP_STATE_PENDING: 407b594c6e2SMarc Zyngier *val = gic_peek_irq(d, GICD_ISPENDR); 408b594c6e2SMarc Zyngier break; 409b594c6e2SMarc Zyngier 410b594c6e2SMarc Zyngier case IRQCHIP_STATE_ACTIVE: 411b594c6e2SMarc Zyngier *val = gic_peek_irq(d, GICD_ISACTIVER); 412b594c6e2SMarc Zyngier break; 413b594c6e2SMarc Zyngier 414b594c6e2SMarc Zyngier case IRQCHIP_STATE_MASKED: 415b594c6e2SMarc Zyngier *val = !gic_peek_irq(d, GICD_ISENABLER); 416b594c6e2SMarc Zyngier break; 417b594c6e2SMarc Zyngier 418b594c6e2SMarc Zyngier default: 419b594c6e2SMarc Zyngier return -EINVAL; 420b594c6e2SMarc Zyngier } 421b594c6e2SMarc Zyngier 422b594c6e2SMarc Zyngier return 0; 423b594c6e2SMarc Zyngier } 424b594c6e2SMarc Zyngier 425101b35f7SJulien Thierry static void gic_irq_set_prio(struct irq_data *d, u8 prio) 426101b35f7SJulien Thierry { 427101b35f7SJulien Thierry void __iomem *base = gic_dist_base(d); 428e91b036eSMarc Zyngier u32 offset, index; 429101b35f7SJulien Thierry 430e91b036eSMarc Zyngier offset = convert_offset_index(d, GICD_IPRIORITYR, &index); 431e91b036eSMarc Zyngier 432e91b036eSMarc Zyngier writeb_relaxed(prio, base + offset + index); 433101b35f7SJulien Thierry } 434101b35f7SJulien Thierry 43581a43273SMarc Zyngier static u32 gic_get_ppi_index(struct irq_data *d) 43681a43273SMarc Zyngier { 43781a43273SMarc Zyngier switch (get_intid_range(d)) { 43881a43273SMarc Zyngier case PPI_RANGE: 43981a43273SMarc Zyngier return d->hwirq - 16; 4405f51f803SMarc Zyngier case EPPI_RANGE: 4415f51f803SMarc Zyngier return d->hwirq - EPPI_BASE_INTID + 16; 44281a43273SMarc Zyngier default: 44381a43273SMarc Zyngier unreachable(); 44481a43273SMarc Zyngier } 44581a43273SMarc Zyngier } 44681a43273SMarc Zyngier 447101b35f7SJulien Thierry static int gic_irq_nmi_setup(struct irq_data *d) 448101b35f7SJulien Thierry { 449101b35f7SJulien Thierry struct irq_desc *desc = irq_to_desc(d->irq); 450101b35f7SJulien Thierry 451101b35f7SJulien Thierry if (!gic_supports_nmi()) 452101b35f7SJulien Thierry return -EINVAL; 453101b35f7SJulien Thierry 454101b35f7SJulien Thierry if (gic_peek_irq(d, GICD_ISENABLER)) { 455101b35f7SJulien Thierry pr_err("Cannot set NMI property of enabled IRQ %u\n", d->irq); 456101b35f7SJulien Thierry return -EINVAL; 457101b35f7SJulien Thierry } 458101b35f7SJulien Thierry 459101b35f7SJulien Thierry /* 460101b35f7SJulien Thierry * A secondary irq_chip should be in charge of LPI request, 461101b35f7SJulien Thierry * it should not be possible to get there 462101b35f7SJulien Thierry */ 463101b35f7SJulien Thierry if (WARN_ON(gic_irq(d) >= 8192)) 464101b35f7SJulien Thierry return -EINVAL; 465101b35f7SJulien Thierry 466101b35f7SJulien Thierry /* desc lock should already be held */ 46781a43273SMarc Zyngier if (gic_irq_in_rdist(d)) { 46881a43273SMarc Zyngier u32 idx = gic_get_ppi_index(d); 46981a43273SMarc Zyngier 470101b35f7SJulien Thierry /* Setting up PPI as NMI, only switch handler for first NMI */ 47181a43273SMarc Zyngier if (!refcount_inc_not_zero(&ppi_nmi_refs[idx])) { 47281a43273SMarc Zyngier refcount_set(&ppi_nmi_refs[idx], 1); 473101b35f7SJulien Thierry desc->handle_irq = handle_percpu_devid_fasteoi_nmi; 474101b35f7SJulien Thierry } 475101b35f7SJulien Thierry } else { 476101b35f7SJulien Thierry desc->handle_irq = handle_fasteoi_nmi; 477101b35f7SJulien Thierry } 478101b35f7SJulien Thierry 479101b35f7SJulien Thierry gic_irq_set_prio(d, GICD_INT_NMI_PRI); 480101b35f7SJulien Thierry 481101b35f7SJulien Thierry return 0; 482101b35f7SJulien Thierry } 483101b35f7SJulien Thierry 484101b35f7SJulien Thierry static void gic_irq_nmi_teardown(struct irq_data *d) 485101b35f7SJulien Thierry { 486101b35f7SJulien Thierry struct irq_desc *desc = irq_to_desc(d->irq); 487101b35f7SJulien Thierry 488101b35f7SJulien Thierry if (WARN_ON(!gic_supports_nmi())) 489101b35f7SJulien Thierry return; 490101b35f7SJulien Thierry 491101b35f7SJulien Thierry if (gic_peek_irq(d, GICD_ISENABLER)) { 492101b35f7SJulien Thierry pr_err("Cannot set NMI property of enabled IRQ %u\n", d->irq); 493101b35f7SJulien Thierry return; 494101b35f7SJulien Thierry } 495101b35f7SJulien Thierry 496101b35f7SJulien Thierry /* 497101b35f7SJulien Thierry * A secondary irq_chip should be in charge of LPI request, 498101b35f7SJulien Thierry * it should not be possible to get there 499101b35f7SJulien Thierry */ 500101b35f7SJulien Thierry if (WARN_ON(gic_irq(d) >= 8192)) 501101b35f7SJulien Thierry return; 502101b35f7SJulien Thierry 503101b35f7SJulien Thierry /* desc lock should already be held */ 50481a43273SMarc Zyngier if (gic_irq_in_rdist(d)) { 50581a43273SMarc Zyngier u32 idx = gic_get_ppi_index(d); 50681a43273SMarc Zyngier 507101b35f7SJulien Thierry /* Tearing down NMI, only switch handler for last NMI */ 50881a43273SMarc Zyngier if (refcount_dec_and_test(&ppi_nmi_refs[idx])) 509101b35f7SJulien Thierry desc->handle_irq = handle_percpu_devid_irq; 510101b35f7SJulien Thierry } else { 511101b35f7SJulien Thierry desc->handle_irq = handle_fasteoi_irq; 512101b35f7SJulien Thierry } 513101b35f7SJulien Thierry 514101b35f7SJulien Thierry gic_irq_set_prio(d, GICD_INT_DEF_PRI); 515101b35f7SJulien Thierry } 516101b35f7SJulien Thierry 517021f6537SMarc Zyngier static void gic_eoi_irq(struct irq_data *d) 518021f6537SMarc Zyngier { 519021f6537SMarc Zyngier gic_write_eoir(gic_irq(d)); 520021f6537SMarc Zyngier } 521021f6537SMarc Zyngier 5220b6a3da9SMarc Zyngier static void gic_eoimode1_eoi_irq(struct irq_data *d) 5230b6a3da9SMarc Zyngier { 5240b6a3da9SMarc Zyngier /* 525530bf353SMarc Zyngier * No need to deactivate an LPI, or an interrupt that 526530bf353SMarc Zyngier * is is getting forwarded to a vcpu. 5270b6a3da9SMarc Zyngier */ 5284df7f54dSThomas Gleixner if (gic_irq(d) >= 8192 || irqd_is_forwarded_to_vcpu(d)) 5290b6a3da9SMarc Zyngier return; 5300b6a3da9SMarc Zyngier gic_write_dir(gic_irq(d)); 5310b6a3da9SMarc Zyngier } 5320b6a3da9SMarc Zyngier 533021f6537SMarc Zyngier static int gic_set_type(struct irq_data *d, unsigned int type) 534021f6537SMarc Zyngier { 5355f51f803SMarc Zyngier enum gic_intid_range range; 536021f6537SMarc Zyngier unsigned int irq = gic_irq(d); 537021f6537SMarc Zyngier void (*rwp_wait)(void); 538021f6537SMarc Zyngier void __iomem *base; 539e91b036eSMarc Zyngier u32 offset, index; 54013d22e2eSMarc Zyngier int ret; 541021f6537SMarc Zyngier 542021f6537SMarc Zyngier /* Interrupt configuration for SGIs can't be changed */ 543021f6537SMarc Zyngier if (irq < 16) 544021f6537SMarc Zyngier return -EINVAL; 545021f6537SMarc Zyngier 5465f51f803SMarc Zyngier range = get_intid_range(d); 5475f51f803SMarc Zyngier 548fb7e7debSLiviu Dudau /* SPIs have restrictions on the supported types */ 5495f51f803SMarc Zyngier if ((range == SPI_RANGE || range == ESPI_RANGE) && 5505f51f803SMarc Zyngier type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING) 551021f6537SMarc Zyngier return -EINVAL; 552021f6537SMarc Zyngier 553021f6537SMarc Zyngier if (gic_irq_in_rdist(d)) { 554021f6537SMarc Zyngier base = gic_data_rdist_sgi_base(); 555021f6537SMarc Zyngier rwp_wait = gic_redist_wait_for_rwp; 556021f6537SMarc Zyngier } else { 557021f6537SMarc Zyngier base = gic_data.dist_base; 558021f6537SMarc Zyngier rwp_wait = gic_dist_wait_for_rwp; 559021f6537SMarc Zyngier } 560021f6537SMarc Zyngier 561e91b036eSMarc Zyngier offset = convert_offset_index(d, GICD_ICFGR, &index); 56213d22e2eSMarc Zyngier 563e91b036eSMarc Zyngier ret = gic_configure_irq(index, type, base + offset, rwp_wait); 5645f51f803SMarc Zyngier if (ret && (range == PPI_RANGE || range == EPPI_RANGE)) { 56513d22e2eSMarc Zyngier /* Misconfigured PPIs are usually not fatal */ 5665f51f803SMarc Zyngier pr_warn("GIC: PPI INTID%d is secure or misconfigured\n", irq); 56713d22e2eSMarc Zyngier ret = 0; 56813d22e2eSMarc Zyngier } 56913d22e2eSMarc Zyngier 57013d22e2eSMarc Zyngier return ret; 571021f6537SMarc Zyngier } 572021f6537SMarc Zyngier 573530bf353SMarc Zyngier static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu) 574530bf353SMarc Zyngier { 5754df7f54dSThomas Gleixner if (vcpu) 5764df7f54dSThomas Gleixner irqd_set_forwarded_to_vcpu(d); 5774df7f54dSThomas Gleixner else 5784df7f54dSThomas Gleixner irqd_clr_forwarded_to_vcpu(d); 579530bf353SMarc Zyngier return 0; 580530bf353SMarc Zyngier } 581530bf353SMarc Zyngier 582f6c86a41SJean-Philippe Brucker static u64 gic_mpidr_to_affinity(unsigned long mpidr) 583021f6537SMarc Zyngier { 584021f6537SMarc Zyngier u64 aff; 585021f6537SMarc Zyngier 586f6c86a41SJean-Philippe Brucker aff = ((u64)MPIDR_AFFINITY_LEVEL(mpidr, 3) << 32 | 587021f6537SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 | 588021f6537SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | 589021f6537SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 0)); 590021f6537SMarc Zyngier 591021f6537SMarc Zyngier return aff; 592021f6537SMarc Zyngier } 593021f6537SMarc Zyngier 594f32c9266SJulien Thierry static void gic_deactivate_unhandled(u32 irqnr) 595f32c9266SJulien Thierry { 596f32c9266SJulien Thierry if (static_branch_likely(&supports_deactivate_key)) { 597f32c9266SJulien Thierry if (irqnr < 8192) 598f32c9266SJulien Thierry gic_write_dir(irqnr); 599f32c9266SJulien Thierry } else { 600f32c9266SJulien Thierry gic_write_eoir(irqnr); 601f32c9266SJulien Thierry } 602f32c9266SJulien Thierry } 603f32c9266SJulien Thierry 604f32c9266SJulien Thierry static inline void gic_handle_nmi(u32 irqnr, struct pt_regs *regs) 605f32c9266SJulien Thierry { 60617ce302fSJulien Thierry bool irqs_enabled = interrupts_enabled(regs); 607f32c9266SJulien Thierry int err; 608f32c9266SJulien Thierry 60917ce302fSJulien Thierry if (irqs_enabled) 61017ce302fSJulien Thierry nmi_enter(); 61117ce302fSJulien Thierry 612f32c9266SJulien Thierry if (static_branch_likely(&supports_deactivate_key)) 613f32c9266SJulien Thierry gic_write_eoir(irqnr); 614f32c9266SJulien Thierry /* 615f32c9266SJulien Thierry * Leave the PSR.I bit set to prevent other NMIs to be 616f32c9266SJulien Thierry * received while handling this one. 617f32c9266SJulien Thierry * PSR.I will be restored when we ERET to the 618f32c9266SJulien Thierry * interrupted context. 619f32c9266SJulien Thierry */ 620f32c9266SJulien Thierry err = handle_domain_nmi(gic_data.domain, irqnr, regs); 621f32c9266SJulien Thierry if (err) 622f32c9266SJulien Thierry gic_deactivate_unhandled(irqnr); 62317ce302fSJulien Thierry 62417ce302fSJulien Thierry if (irqs_enabled) 62517ce302fSJulien Thierry nmi_exit(); 626f32c9266SJulien Thierry } 627f32c9266SJulien Thierry 628021f6537SMarc Zyngier static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) 629021f6537SMarc Zyngier { 630f6c86a41SJean-Philippe Brucker u32 irqnr; 631021f6537SMarc Zyngier 632021f6537SMarc Zyngier irqnr = gic_read_iar(); 633021f6537SMarc Zyngier 634f32c9266SJulien Thierry if (gic_supports_nmi() && 635f32c9266SJulien Thierry unlikely(gic_read_rpr() == GICD_INT_NMI_PRI)) { 636f32c9266SJulien Thierry gic_handle_nmi(irqnr, regs); 637f32c9266SJulien Thierry return; 638f32c9266SJulien Thierry } 639f32c9266SJulien Thierry 6403f1f3234SJulien Thierry if (gic_prio_masking_enabled()) { 6413f1f3234SJulien Thierry gic_pmr_mask_irqs(); 6423f1f3234SJulien Thierry gic_arch_enable_irqs(); 6433f1f3234SJulien Thierry } 6443f1f3234SJulien Thierry 645211bddd2SMarc Zyngier /* Check for special IDs first */ 646211bddd2SMarc Zyngier if ((irqnr >= 1020 && irqnr <= 1023)) 647211bddd2SMarc Zyngier return; 648211bddd2SMarc Zyngier 649211bddd2SMarc Zyngier /* Treat anything but SGIs in a uniform way */ 650211bddd2SMarc Zyngier if (likely(irqnr > 15)) { 651ebc6de00SMarc Zyngier int err; 6520b6a3da9SMarc Zyngier 653d01d3274SDavidlohr Bueso if (static_branch_likely(&supports_deactivate_key)) 6540b6a3da9SMarc Zyngier gic_write_eoir(irqnr); 65539a06b67SWill Deacon else 65639a06b67SWill Deacon isb(); 6570b6a3da9SMarc Zyngier 658ebc6de00SMarc Zyngier err = handle_domain_irq(gic_data.domain, irqnr, regs); 659ebc6de00SMarc Zyngier if (err) { 660da33f31dSMarc Zyngier WARN_ONCE(true, "Unexpected interrupt received!\n"); 661f32c9266SJulien Thierry gic_deactivate_unhandled(irqnr); 6620b6a3da9SMarc Zyngier } 663342677d7SJulien Thierry return; 664ebc6de00SMarc Zyngier } 665021f6537SMarc Zyngier if (irqnr < 16) { 666021f6537SMarc Zyngier gic_write_eoir(irqnr); 667d01d3274SDavidlohr Bueso if (static_branch_likely(&supports_deactivate_key)) 6680b6a3da9SMarc Zyngier gic_write_dir(irqnr); 669021f6537SMarc Zyngier #ifdef CONFIG_SMP 670f86c4fbdSWill Deacon /* 671f86c4fbdSWill Deacon * Unlike GICv2, we don't need an smp_rmb() here. 672f86c4fbdSWill Deacon * The control dependency from gic_read_iar to 673f86c4fbdSWill Deacon * the ISB in gic_write_eoir is enough to ensure 674f86c4fbdSWill Deacon * that any shared data read by handle_IPI will 675f86c4fbdSWill Deacon * be read after the ACK. 676f86c4fbdSWill Deacon */ 677021f6537SMarc Zyngier handle_IPI(irqnr, regs); 678021f6537SMarc Zyngier #else 679021f6537SMarc Zyngier WARN_ONCE(true, "Unexpected SGI received!\n"); 680021f6537SMarc Zyngier #endif 681021f6537SMarc Zyngier } 682021f6537SMarc Zyngier } 683021f6537SMarc Zyngier 684b5cf6073SJulien Thierry static u32 gic_get_pribits(void) 685b5cf6073SJulien Thierry { 686b5cf6073SJulien Thierry u32 pribits; 687b5cf6073SJulien Thierry 688b5cf6073SJulien Thierry pribits = gic_read_ctlr(); 689b5cf6073SJulien Thierry pribits &= ICC_CTLR_EL1_PRI_BITS_MASK; 690b5cf6073SJulien Thierry pribits >>= ICC_CTLR_EL1_PRI_BITS_SHIFT; 691b5cf6073SJulien Thierry pribits++; 692b5cf6073SJulien Thierry 693b5cf6073SJulien Thierry return pribits; 694b5cf6073SJulien Thierry } 695b5cf6073SJulien Thierry 696b5cf6073SJulien Thierry static bool gic_has_group0(void) 697b5cf6073SJulien Thierry { 698b5cf6073SJulien Thierry u32 val; 699e7932188SJulien Thierry u32 old_pmr; 700e7932188SJulien Thierry 701e7932188SJulien Thierry old_pmr = gic_read_pmr(); 702b5cf6073SJulien Thierry 703b5cf6073SJulien Thierry /* 704b5cf6073SJulien Thierry * Let's find out if Group0 is under control of EL3 or not by 705b5cf6073SJulien Thierry * setting the highest possible, non-zero priority in PMR. 706b5cf6073SJulien Thierry * 707b5cf6073SJulien Thierry * If SCR_EL3.FIQ is set, the priority gets shifted down in 708b5cf6073SJulien Thierry * order for the CPU interface to set bit 7, and keep the 709b5cf6073SJulien Thierry * actual priority in the non-secure range. In the process, it 710b5cf6073SJulien Thierry * looses the least significant bit and the actual priority 711b5cf6073SJulien Thierry * becomes 0x80. Reading it back returns 0, indicating that 712b5cf6073SJulien Thierry * we're don't have access to Group0. 713b5cf6073SJulien Thierry */ 714b5cf6073SJulien Thierry gic_write_pmr(BIT(8 - gic_get_pribits())); 715b5cf6073SJulien Thierry val = gic_read_pmr(); 716b5cf6073SJulien Thierry 717e7932188SJulien Thierry gic_write_pmr(old_pmr); 718e7932188SJulien Thierry 719b5cf6073SJulien Thierry return val != 0; 720b5cf6073SJulien Thierry } 721b5cf6073SJulien Thierry 722021f6537SMarc Zyngier static void __init gic_dist_init(void) 723021f6537SMarc Zyngier { 724021f6537SMarc Zyngier unsigned int i; 725021f6537SMarc Zyngier u64 affinity; 726021f6537SMarc Zyngier void __iomem *base = gic_data.dist_base; 727021f6537SMarc Zyngier 728021f6537SMarc Zyngier /* Disable the distributor */ 729021f6537SMarc Zyngier writel_relaxed(0, base + GICD_CTLR); 730021f6537SMarc Zyngier gic_dist_wait_for_rwp(); 731021f6537SMarc Zyngier 7327c9b9730SMarc Zyngier /* 7337c9b9730SMarc Zyngier * Configure SPIs as non-secure Group-1. This will only matter 7347c9b9730SMarc Zyngier * if the GIC only has a single security state. This will not 7357c9b9730SMarc Zyngier * do the right thing if the kernel is running in secure mode, 7367c9b9730SMarc Zyngier * but that's not the intended use case anyway. 7377c9b9730SMarc Zyngier */ 738211bddd2SMarc Zyngier for (i = 32; i < GIC_LINE_NR; i += 32) 7397c9b9730SMarc Zyngier writel_relaxed(~0, base + GICD_IGROUPR + i / 8); 7407c9b9730SMarc Zyngier 741211bddd2SMarc Zyngier /* Extended SPI range, not handled by the GICv2/GICv3 common code */ 742211bddd2SMarc Zyngier for (i = 0; i < GIC_ESPI_NR; i += 32) { 743211bddd2SMarc Zyngier writel_relaxed(~0U, base + GICD_ICENABLERnE + i / 8); 744211bddd2SMarc Zyngier writel_relaxed(~0U, base + GICD_ICACTIVERnE + i / 8); 745211bddd2SMarc Zyngier } 746211bddd2SMarc Zyngier 747211bddd2SMarc Zyngier for (i = 0; i < GIC_ESPI_NR; i += 32) 748211bddd2SMarc Zyngier writel_relaxed(~0U, base + GICD_IGROUPRnE + i / 8); 749211bddd2SMarc Zyngier 750211bddd2SMarc Zyngier for (i = 0; i < GIC_ESPI_NR; i += 16) 751211bddd2SMarc Zyngier writel_relaxed(0, base + GICD_ICFGRnE + i / 4); 752211bddd2SMarc Zyngier 753211bddd2SMarc Zyngier for (i = 0; i < GIC_ESPI_NR; i += 4) 754211bddd2SMarc Zyngier writel_relaxed(GICD_INT_DEF_PRI_X4, base + GICD_IPRIORITYRnE + i); 755211bddd2SMarc Zyngier 756211bddd2SMarc Zyngier /* Now do the common stuff, and wait for the distributor to drain */ 757211bddd2SMarc Zyngier gic_dist_config(base, GIC_LINE_NR, gic_dist_wait_for_rwp); 758021f6537SMarc Zyngier 759021f6537SMarc Zyngier /* Enable distributor with ARE, Group1 */ 760021f6537SMarc Zyngier writel_relaxed(GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G1A | GICD_CTLR_ENABLE_G1, 761021f6537SMarc Zyngier base + GICD_CTLR); 762021f6537SMarc Zyngier 763021f6537SMarc Zyngier /* 764021f6537SMarc Zyngier * Set all global interrupts to the boot CPU only. ARE must be 765021f6537SMarc Zyngier * enabled. 766021f6537SMarc Zyngier */ 767021f6537SMarc Zyngier affinity = gic_mpidr_to_affinity(cpu_logical_map(smp_processor_id())); 768211bddd2SMarc Zyngier for (i = 32; i < GIC_LINE_NR; i++) 76972c97126SJean-Philippe Brucker gic_write_irouter(affinity, base + GICD_IROUTER + i * 8); 770211bddd2SMarc Zyngier 771211bddd2SMarc Zyngier for (i = 0; i < GIC_ESPI_NR; i++) 772211bddd2SMarc Zyngier gic_write_irouter(affinity, base + GICD_IROUTERnE + i * 8); 773021f6537SMarc Zyngier } 774021f6537SMarc Zyngier 7750d94ded2SMarc Zyngier static int gic_iterate_rdists(int (*fn)(struct redist_region *, void __iomem *)) 776021f6537SMarc Zyngier { 7770d94ded2SMarc Zyngier int ret = -ENODEV; 778021f6537SMarc Zyngier int i; 779021f6537SMarc Zyngier 780f5c1434cSMarc Zyngier for (i = 0; i < gic_data.nr_redist_regions; i++) { 781f5c1434cSMarc Zyngier void __iomem *ptr = gic_data.redist_regions[i].redist_base; 7820d94ded2SMarc Zyngier u64 typer; 783021f6537SMarc Zyngier u32 reg; 784021f6537SMarc Zyngier 785021f6537SMarc Zyngier reg = readl_relaxed(ptr + GICR_PIDR2) & GIC_PIDR2_ARCH_MASK; 786021f6537SMarc Zyngier if (reg != GIC_PIDR2_ARCH_GICv3 && 787021f6537SMarc Zyngier reg != GIC_PIDR2_ARCH_GICv4) { /* We're in trouble... */ 788021f6537SMarc Zyngier pr_warn("No redistributor present @%p\n", ptr); 789021f6537SMarc Zyngier break; 790021f6537SMarc Zyngier } 791021f6537SMarc Zyngier 792021f6537SMarc Zyngier do { 79372c97126SJean-Philippe Brucker typer = gic_read_typer(ptr + GICR_TYPER); 7940d94ded2SMarc Zyngier ret = fn(gic_data.redist_regions + i, ptr); 7950d94ded2SMarc Zyngier if (!ret) 796021f6537SMarc Zyngier return 0; 797021f6537SMarc Zyngier 798b70fb7afSTomasz Nowicki if (gic_data.redist_regions[i].single_redist) 799b70fb7afSTomasz Nowicki break; 800b70fb7afSTomasz Nowicki 801021f6537SMarc Zyngier if (gic_data.redist_stride) { 802021f6537SMarc Zyngier ptr += gic_data.redist_stride; 803021f6537SMarc Zyngier } else { 804021f6537SMarc Zyngier ptr += SZ_64K * 2; /* Skip RD_base + SGI_base */ 805021f6537SMarc Zyngier if (typer & GICR_TYPER_VLPIS) 806021f6537SMarc Zyngier ptr += SZ_64K * 2; /* Skip VLPI_base + reserved page */ 807021f6537SMarc Zyngier } 808021f6537SMarc Zyngier } while (!(typer & GICR_TYPER_LAST)); 809021f6537SMarc Zyngier } 810021f6537SMarc Zyngier 8110d94ded2SMarc Zyngier return ret ? -ENODEV : 0; 8120d94ded2SMarc Zyngier } 8130d94ded2SMarc Zyngier 8140d94ded2SMarc Zyngier static int __gic_populate_rdist(struct redist_region *region, void __iomem *ptr) 8150d94ded2SMarc Zyngier { 8160d94ded2SMarc Zyngier unsigned long mpidr = cpu_logical_map(smp_processor_id()); 8170d94ded2SMarc Zyngier u64 typer; 8180d94ded2SMarc Zyngier u32 aff; 8190d94ded2SMarc Zyngier 8200d94ded2SMarc Zyngier /* 8210d94ded2SMarc Zyngier * Convert affinity to a 32bit value that can be matched to 8220d94ded2SMarc Zyngier * GICR_TYPER bits [63:32]. 8230d94ded2SMarc Zyngier */ 8240d94ded2SMarc Zyngier aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 24 | 8250d94ded2SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 | 8260d94ded2SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | 8270d94ded2SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 0)); 8280d94ded2SMarc Zyngier 8290d94ded2SMarc Zyngier typer = gic_read_typer(ptr + GICR_TYPER); 8300d94ded2SMarc Zyngier if ((typer >> 32) == aff) { 8310d94ded2SMarc Zyngier u64 offset = ptr - region->redist_base; 8320d94ded2SMarc Zyngier gic_data_rdist_rd_base() = ptr; 8330d94ded2SMarc Zyngier gic_data_rdist()->phys_base = region->phys_base + offset; 8340d94ded2SMarc Zyngier 8350d94ded2SMarc Zyngier pr_info("CPU%d: found redistributor %lx region %d:%pa\n", 8360d94ded2SMarc Zyngier smp_processor_id(), mpidr, 8370d94ded2SMarc Zyngier (int)(region - gic_data.redist_regions), 8380d94ded2SMarc Zyngier &gic_data_rdist()->phys_base); 8390d94ded2SMarc Zyngier return 0; 8400d94ded2SMarc Zyngier } 8410d94ded2SMarc Zyngier 8420d94ded2SMarc Zyngier /* Try next one */ 8430d94ded2SMarc Zyngier return 1; 8440d94ded2SMarc Zyngier } 8450d94ded2SMarc Zyngier 8460d94ded2SMarc Zyngier static int gic_populate_rdist(void) 8470d94ded2SMarc Zyngier { 8480d94ded2SMarc Zyngier if (gic_iterate_rdists(__gic_populate_rdist) == 0) 8490d94ded2SMarc Zyngier return 0; 8500d94ded2SMarc Zyngier 851021f6537SMarc Zyngier /* We couldn't even deal with ourselves... */ 852f6c86a41SJean-Philippe Brucker WARN(true, "CPU%d: mpidr %lx has no re-distributor!\n", 8530d94ded2SMarc Zyngier smp_processor_id(), 8540d94ded2SMarc Zyngier (unsigned long)cpu_logical_map(smp_processor_id())); 855021f6537SMarc Zyngier return -ENODEV; 856021f6537SMarc Zyngier } 857021f6537SMarc Zyngier 8581a60e1e6SMarc Zyngier static int __gic_update_rdist_properties(struct redist_region *region, 8590edc23eaSMarc Zyngier void __iomem *ptr) 8600edc23eaSMarc Zyngier { 8610edc23eaSMarc Zyngier u64 typer = gic_read_typer(ptr + GICR_TYPER); 862b25319d2SMarc Zyngier 8630edc23eaSMarc Zyngier gic_data.rdists.has_vlpis &= !!(typer & GICR_TYPER_VLPIS); 864b25319d2SMarc Zyngier 865b25319d2SMarc Zyngier /* RVPEID implies some form of DirectLPI, no matter what the doc says... :-/ */ 866b25319d2SMarc Zyngier gic_data.rdists.has_rvpeid &= !!(typer & GICR_TYPER_RVPEID); 867b25319d2SMarc Zyngier gic_data.rdists.has_direct_lpi &= (!!(typer & GICR_TYPER_DirectLPIS) | 868b25319d2SMarc Zyngier gic_data.rdists.has_rvpeid); 869b25319d2SMarc Zyngier 870b25319d2SMarc Zyngier /* Detect non-sensical configurations */ 871b25319d2SMarc Zyngier if (WARN_ON_ONCE(gic_data.rdists.has_rvpeid && !gic_data.rdists.has_vlpis)) { 872b25319d2SMarc Zyngier gic_data.rdists.has_direct_lpi = false; 873b25319d2SMarc Zyngier gic_data.rdists.has_vlpis = false; 874b25319d2SMarc Zyngier gic_data.rdists.has_rvpeid = false; 875b25319d2SMarc Zyngier } 876b25319d2SMarc Zyngier 8775f51f803SMarc Zyngier gic_data.ppi_nr = min(GICR_TYPER_NR_PPIS(typer), gic_data.ppi_nr); 8780edc23eaSMarc Zyngier 8790edc23eaSMarc Zyngier return 1; 8800edc23eaSMarc Zyngier } 8810edc23eaSMarc Zyngier 8821a60e1e6SMarc Zyngier static void gic_update_rdist_properties(void) 8830edc23eaSMarc Zyngier { 8841a60e1e6SMarc Zyngier gic_data.ppi_nr = UINT_MAX; 8851a60e1e6SMarc Zyngier gic_iterate_rdists(__gic_update_rdist_properties); 8861a60e1e6SMarc Zyngier if (WARN_ON(gic_data.ppi_nr == UINT_MAX)) 8871a60e1e6SMarc Zyngier gic_data.ppi_nr = 0; 8881a60e1e6SMarc Zyngier pr_info("%d PPIs implemented\n", gic_data.ppi_nr); 889b25319d2SMarc Zyngier pr_info("%sVLPI support, %sdirect LPI support, %sRVPEID support\n", 8900edc23eaSMarc Zyngier !gic_data.rdists.has_vlpis ? "no " : "", 891b25319d2SMarc Zyngier !gic_data.rdists.has_direct_lpi ? "no " : "", 892b25319d2SMarc Zyngier !gic_data.rdists.has_rvpeid ? "no " : ""); 8930edc23eaSMarc Zyngier } 8940edc23eaSMarc Zyngier 895d98d0a99SJulien Thierry /* Check whether it's single security state view */ 896d98d0a99SJulien Thierry static inline bool gic_dist_security_disabled(void) 897d98d0a99SJulien Thierry { 898d98d0a99SJulien Thierry return readl_relaxed(gic_data.dist_base + GICD_CTLR) & GICD_CTLR_DS; 899d98d0a99SJulien Thierry } 900d98d0a99SJulien Thierry 9013708d52fSSudeep Holla static void gic_cpu_sys_reg_init(void) 902021f6537SMarc Zyngier { 903eda0d04aSShanker Donthineni int i, cpu = smp_processor_id(); 904eda0d04aSShanker Donthineni u64 mpidr = cpu_logical_map(cpu); 905eda0d04aSShanker Donthineni u64 need_rss = MPIDR_RS(mpidr); 90633625282SMarc Zyngier bool group0; 907b5cf6073SJulien Thierry u32 pribits; 908eda0d04aSShanker Donthineni 9097cabd008SMarc Zyngier /* 9107cabd008SMarc Zyngier * Need to check that the SRE bit has actually been set. If 9117cabd008SMarc Zyngier * not, it means that SRE is disabled at EL2. We're going to 9127cabd008SMarc Zyngier * die painfully, and there is nothing we can do about it. 9137cabd008SMarc Zyngier * 9147cabd008SMarc Zyngier * Kindly inform the luser. 9157cabd008SMarc Zyngier */ 9167cabd008SMarc Zyngier if (!gic_enable_sre()) 9177cabd008SMarc Zyngier pr_err("GIC: unable to set SRE (disabled at EL2), panic ahead\n"); 918021f6537SMarc Zyngier 919b5cf6073SJulien Thierry pribits = gic_get_pribits(); 92033625282SMarc Zyngier 921b5cf6073SJulien Thierry group0 = gic_has_group0(); 92233625282SMarc Zyngier 923021f6537SMarc Zyngier /* Set priority mask register */ 924d98d0a99SJulien Thierry if (!gic_prio_masking_enabled()) { 92533625282SMarc Zyngier write_gicreg(DEFAULT_PMR_VALUE, ICC_PMR_EL1); 926d98d0a99SJulien Thierry } else { 927d98d0a99SJulien Thierry /* 928d98d0a99SJulien Thierry * Mismatch configuration with boot CPU, the system is likely 929d98d0a99SJulien Thierry * to die as interrupt masking will not work properly on all 930d98d0a99SJulien Thierry * CPUs 931d98d0a99SJulien Thierry */ 932d98d0a99SJulien Thierry WARN_ON(gic_supports_nmi() && group0 && 933d98d0a99SJulien Thierry !gic_dist_security_disabled()); 934d98d0a99SJulien Thierry } 935021f6537SMarc Zyngier 93691ef8442SDaniel Thompson /* 93791ef8442SDaniel Thompson * Some firmwares hand over to the kernel with the BPR changed from 93891ef8442SDaniel Thompson * its reset value (and with a value large enough to prevent 93991ef8442SDaniel Thompson * any pre-emptive interrupts from working at all). Writing a zero 94091ef8442SDaniel Thompson * to BPR restores is reset value. 94191ef8442SDaniel Thompson */ 94291ef8442SDaniel Thompson gic_write_bpr1(0); 94391ef8442SDaniel Thompson 944d01d3274SDavidlohr Bueso if (static_branch_likely(&supports_deactivate_key)) { 9450b6a3da9SMarc Zyngier /* EOI drops priority only (mode 1) */ 9460b6a3da9SMarc Zyngier gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop); 9470b6a3da9SMarc Zyngier } else { 948021f6537SMarc Zyngier /* EOI deactivates interrupt too (mode 0) */ 949021f6537SMarc Zyngier gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop_dir); 9500b6a3da9SMarc Zyngier } 951021f6537SMarc Zyngier 95233625282SMarc Zyngier /* Always whack Group0 before Group1 */ 95333625282SMarc Zyngier if (group0) { 95433625282SMarc Zyngier switch(pribits) { 95533625282SMarc Zyngier case 8: 95633625282SMarc Zyngier case 7: 95733625282SMarc Zyngier write_gicreg(0, ICC_AP0R3_EL1); 95833625282SMarc Zyngier write_gicreg(0, ICC_AP0R2_EL1); 95952f8c8b3SAnders Roxell /* Fall through */ 96033625282SMarc Zyngier case 6: 96133625282SMarc Zyngier write_gicreg(0, ICC_AP0R1_EL1); 96252f8c8b3SAnders Roxell /* Fall through */ 96333625282SMarc Zyngier case 5: 96433625282SMarc Zyngier case 4: 96533625282SMarc Zyngier write_gicreg(0, ICC_AP0R0_EL1); 96633625282SMarc Zyngier } 967d6062a6dSMarc Zyngier 96833625282SMarc Zyngier isb(); 96933625282SMarc Zyngier } 97033625282SMarc Zyngier 97133625282SMarc Zyngier switch(pribits) { 972d6062a6dSMarc Zyngier case 8: 973d6062a6dSMarc Zyngier case 7: 974d6062a6dSMarc Zyngier write_gicreg(0, ICC_AP1R3_EL1); 975d6062a6dSMarc Zyngier write_gicreg(0, ICC_AP1R2_EL1); 97652f8c8b3SAnders Roxell /* Fall through */ 977d6062a6dSMarc Zyngier case 6: 978d6062a6dSMarc Zyngier write_gicreg(0, ICC_AP1R1_EL1); 97952f8c8b3SAnders Roxell /* Fall through */ 980d6062a6dSMarc Zyngier case 5: 981d6062a6dSMarc Zyngier case 4: 982d6062a6dSMarc Zyngier write_gicreg(0, ICC_AP1R0_EL1); 983d6062a6dSMarc Zyngier } 984d6062a6dSMarc Zyngier 985d6062a6dSMarc Zyngier isb(); 986d6062a6dSMarc Zyngier 987021f6537SMarc Zyngier /* ... and let's hit the road... */ 988021f6537SMarc Zyngier gic_write_grpen1(1); 989eda0d04aSShanker Donthineni 990eda0d04aSShanker Donthineni /* Keep the RSS capability status in per_cpu variable */ 991eda0d04aSShanker Donthineni per_cpu(has_rss, cpu) = !!(gic_read_ctlr() & ICC_CTLR_EL1_RSS); 992eda0d04aSShanker Donthineni 993eda0d04aSShanker Donthineni /* Check all the CPUs have capable of sending SGIs to other CPUs */ 994eda0d04aSShanker Donthineni for_each_online_cpu(i) { 995eda0d04aSShanker Donthineni bool have_rss = per_cpu(has_rss, i) && per_cpu(has_rss, cpu); 996eda0d04aSShanker Donthineni 997eda0d04aSShanker Donthineni need_rss |= MPIDR_RS(cpu_logical_map(i)); 998eda0d04aSShanker Donthineni if (need_rss && (!have_rss)) 999eda0d04aSShanker Donthineni pr_crit("CPU%d (%lx) can't SGI CPU%d (%lx), no RSS\n", 1000eda0d04aSShanker Donthineni cpu, (unsigned long)mpidr, 1001eda0d04aSShanker Donthineni i, (unsigned long)cpu_logical_map(i)); 1002eda0d04aSShanker Donthineni } 1003eda0d04aSShanker Donthineni 1004eda0d04aSShanker Donthineni /** 1005eda0d04aSShanker Donthineni * GIC spec says, when ICC_CTLR_EL1.RSS==1 and GICD_TYPER.RSS==0, 1006eda0d04aSShanker Donthineni * writing ICC_ASGI1R_EL1 register with RS != 0 is a CONSTRAINED 1007eda0d04aSShanker Donthineni * UNPREDICTABLE choice of : 1008eda0d04aSShanker Donthineni * - The write is ignored. 1009eda0d04aSShanker Donthineni * - The RS field is treated as 0. 1010eda0d04aSShanker Donthineni */ 1011eda0d04aSShanker Donthineni if (need_rss && (!gic_data.has_rss)) 1012eda0d04aSShanker Donthineni pr_crit_once("RSS is required but GICD doesn't support it\n"); 1013021f6537SMarc Zyngier } 1014021f6537SMarc Zyngier 1015f736d65dSMarc Zyngier static bool gicv3_nolpi; 1016f736d65dSMarc Zyngier 1017f736d65dSMarc Zyngier static int __init gicv3_nolpi_cfg(char *buf) 1018f736d65dSMarc Zyngier { 1019f736d65dSMarc Zyngier return strtobool(buf, &gicv3_nolpi); 1020f736d65dSMarc Zyngier } 1021f736d65dSMarc Zyngier early_param("irqchip.gicv3_nolpi", gicv3_nolpi_cfg); 1022f736d65dSMarc Zyngier 1023da33f31dSMarc Zyngier static int gic_dist_supports_lpis(void) 1024da33f31dSMarc Zyngier { 1025d38a71c5SMarc Zyngier return (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && 1026d38a71c5SMarc Zyngier !!(readl_relaxed(gic_data.dist_base + GICD_TYPER) & GICD_TYPER_LPIS) && 1027d38a71c5SMarc Zyngier !gicv3_nolpi); 1028da33f31dSMarc Zyngier } 1029da33f31dSMarc Zyngier 1030021f6537SMarc Zyngier static void gic_cpu_init(void) 1031021f6537SMarc Zyngier { 1032021f6537SMarc Zyngier void __iomem *rbase; 10331a60e1e6SMarc Zyngier int i; 1034021f6537SMarc Zyngier 1035021f6537SMarc Zyngier /* Register ourselves with the rest of the world */ 1036021f6537SMarc Zyngier if (gic_populate_rdist()) 1037021f6537SMarc Zyngier return; 1038021f6537SMarc Zyngier 1039a2c22510SSudeep Holla gic_enable_redist(true); 1040021f6537SMarc Zyngier 1041ad5a78d3SMarc Zyngier WARN((gic_data.ppi_nr > 16 || GIC_ESPI_NR != 0) && 1042ad5a78d3SMarc Zyngier !(gic_read_ctlr() & ICC_CTLR_EL1_ExtRange), 1043ad5a78d3SMarc Zyngier "Distributor has extended ranges, but CPU%d doesn't\n", 1044ad5a78d3SMarc Zyngier smp_processor_id()); 1045ad5a78d3SMarc Zyngier 1046021f6537SMarc Zyngier rbase = gic_data_rdist_sgi_base(); 1047021f6537SMarc Zyngier 10487c9b9730SMarc Zyngier /* Configure SGIs/PPIs as non-secure Group-1 */ 10491a60e1e6SMarc Zyngier for (i = 0; i < gic_data.ppi_nr + 16; i += 32) 10501a60e1e6SMarc Zyngier writel_relaxed(~0, rbase + GICR_IGROUPR0 + i / 8); 10517c9b9730SMarc Zyngier 10521a60e1e6SMarc Zyngier gic_cpu_config(rbase, gic_data.ppi_nr + 16, gic_redist_wait_for_rwp); 1053021f6537SMarc Zyngier 10543708d52fSSudeep Holla /* initialise system registers */ 10553708d52fSSudeep Holla gic_cpu_sys_reg_init(); 1056021f6537SMarc Zyngier } 1057021f6537SMarc Zyngier 1058021f6537SMarc Zyngier #ifdef CONFIG_SMP 1059021f6537SMarc Zyngier 1060eda0d04aSShanker Donthineni #define MPIDR_TO_SGI_RS(mpidr) (MPIDR_RS(mpidr) << ICC_SGI1R_RS_SHIFT) 1061eda0d04aSShanker Donthineni #define MPIDR_TO_SGI_CLUSTER_ID(mpidr) ((mpidr) & ~0xFUL) 1062eda0d04aSShanker Donthineni 10636670a6d8SRichard Cochran static int gic_starting_cpu(unsigned int cpu) 10646670a6d8SRichard Cochran { 10656670a6d8SRichard Cochran gic_cpu_init(); 1066d38a71c5SMarc Zyngier 1067d38a71c5SMarc Zyngier if (gic_dist_supports_lpis()) 1068d38a71c5SMarc Zyngier its_cpu_init(); 1069d38a71c5SMarc Zyngier 10706670a6d8SRichard Cochran return 0; 10716670a6d8SRichard Cochran } 1072021f6537SMarc Zyngier 1073021f6537SMarc Zyngier static u16 gic_compute_target_list(int *base_cpu, const struct cpumask *mask, 1074f6c86a41SJean-Philippe Brucker unsigned long cluster_id) 1075021f6537SMarc Zyngier { 1076727653d6SJames Morse int next_cpu, cpu = *base_cpu; 1077f6c86a41SJean-Philippe Brucker unsigned long mpidr = cpu_logical_map(cpu); 1078021f6537SMarc Zyngier u16 tlist = 0; 1079021f6537SMarc Zyngier 1080021f6537SMarc Zyngier while (cpu < nr_cpu_ids) { 1081021f6537SMarc Zyngier tlist |= 1 << (mpidr & 0xf); 1082021f6537SMarc Zyngier 1083727653d6SJames Morse next_cpu = cpumask_next(cpu, mask); 1084727653d6SJames Morse if (next_cpu >= nr_cpu_ids) 1085021f6537SMarc Zyngier goto out; 1086727653d6SJames Morse cpu = next_cpu; 1087021f6537SMarc Zyngier 1088021f6537SMarc Zyngier mpidr = cpu_logical_map(cpu); 1089021f6537SMarc Zyngier 1090eda0d04aSShanker Donthineni if (cluster_id != MPIDR_TO_SGI_CLUSTER_ID(mpidr)) { 1091021f6537SMarc Zyngier cpu--; 1092021f6537SMarc Zyngier goto out; 1093021f6537SMarc Zyngier } 1094021f6537SMarc Zyngier } 1095021f6537SMarc Zyngier out: 1096021f6537SMarc Zyngier *base_cpu = cpu; 1097021f6537SMarc Zyngier return tlist; 1098021f6537SMarc Zyngier } 1099021f6537SMarc Zyngier 11007e580278SAndre Przywara #define MPIDR_TO_SGI_AFFINITY(cluster_id, level) \ 11017e580278SAndre Przywara (MPIDR_AFFINITY_LEVEL(cluster_id, level) \ 11027e580278SAndre Przywara << ICC_SGI1R_AFFINITY_## level ##_SHIFT) 11037e580278SAndre Przywara 1104021f6537SMarc Zyngier static void gic_send_sgi(u64 cluster_id, u16 tlist, unsigned int irq) 1105021f6537SMarc Zyngier { 1106021f6537SMarc Zyngier u64 val; 1107021f6537SMarc Zyngier 11087e580278SAndre Przywara val = (MPIDR_TO_SGI_AFFINITY(cluster_id, 3) | 11097e580278SAndre Przywara MPIDR_TO_SGI_AFFINITY(cluster_id, 2) | 11107e580278SAndre Przywara irq << ICC_SGI1R_SGI_ID_SHIFT | 11117e580278SAndre Przywara MPIDR_TO_SGI_AFFINITY(cluster_id, 1) | 1112eda0d04aSShanker Donthineni MPIDR_TO_SGI_RS(cluster_id) | 11137e580278SAndre Przywara tlist << ICC_SGI1R_TARGET_LIST_SHIFT); 1114021f6537SMarc Zyngier 1115b6dd4d83SMark Salter pr_devel("CPU%d: ICC_SGI1R_EL1 %llx\n", smp_processor_id(), val); 1116021f6537SMarc Zyngier gic_write_sgi1r(val); 1117021f6537SMarc Zyngier } 1118021f6537SMarc Zyngier 1119021f6537SMarc Zyngier static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) 1120021f6537SMarc Zyngier { 1121021f6537SMarc Zyngier int cpu; 1122021f6537SMarc Zyngier 1123021f6537SMarc Zyngier if (WARN_ON(irq >= 16)) 1124021f6537SMarc Zyngier return; 1125021f6537SMarc Zyngier 1126021f6537SMarc Zyngier /* 1127021f6537SMarc Zyngier * Ensure that stores to Normal memory are visible to the 1128021f6537SMarc Zyngier * other CPUs before issuing the IPI. 1129021f6537SMarc Zyngier */ 113021ec30c0SShanker Donthineni wmb(); 1131021f6537SMarc Zyngier 1132f9b531feSRusty Russell for_each_cpu(cpu, mask) { 1133eda0d04aSShanker Donthineni u64 cluster_id = MPIDR_TO_SGI_CLUSTER_ID(cpu_logical_map(cpu)); 1134021f6537SMarc Zyngier u16 tlist; 1135021f6537SMarc Zyngier 1136021f6537SMarc Zyngier tlist = gic_compute_target_list(&cpu, mask, cluster_id); 1137021f6537SMarc Zyngier gic_send_sgi(cluster_id, tlist, irq); 1138021f6537SMarc Zyngier } 1139021f6537SMarc Zyngier 1140021f6537SMarc Zyngier /* Force the above writes to ICC_SGI1R_EL1 to be executed */ 1141021f6537SMarc Zyngier isb(); 1142021f6537SMarc Zyngier } 1143021f6537SMarc Zyngier 1144021f6537SMarc Zyngier static void gic_smp_init(void) 1145021f6537SMarc Zyngier { 1146021f6537SMarc Zyngier set_smp_cross_call(gic_raise_softirq); 11476896bcd1SThomas Gleixner cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_GIC_STARTING, 114873c1b41eSThomas Gleixner "irqchip/arm/gicv3:starting", 114973c1b41eSThomas Gleixner gic_starting_cpu, NULL); 1150021f6537SMarc Zyngier } 1151021f6537SMarc Zyngier 1152021f6537SMarc Zyngier static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, 1153021f6537SMarc Zyngier bool force) 1154021f6537SMarc Zyngier { 115565a30f8bSSuzuki K Poulose unsigned int cpu; 1156e91b036eSMarc Zyngier u32 offset, index; 1157021f6537SMarc Zyngier void __iomem *reg; 1158021f6537SMarc Zyngier int enabled; 1159021f6537SMarc Zyngier u64 val; 1160021f6537SMarc Zyngier 116165a30f8bSSuzuki K Poulose if (force) 116265a30f8bSSuzuki K Poulose cpu = cpumask_first(mask_val); 116365a30f8bSSuzuki K Poulose else 116465a30f8bSSuzuki K Poulose cpu = cpumask_any_and(mask_val, cpu_online_mask); 116565a30f8bSSuzuki K Poulose 1166866d7c1bSSuzuki K Poulose if (cpu >= nr_cpu_ids) 1167866d7c1bSSuzuki K Poulose return -EINVAL; 1168866d7c1bSSuzuki K Poulose 1169021f6537SMarc Zyngier if (gic_irq_in_rdist(d)) 1170021f6537SMarc Zyngier return -EINVAL; 1171021f6537SMarc Zyngier 1172021f6537SMarc Zyngier /* If interrupt was enabled, disable it first */ 1173021f6537SMarc Zyngier enabled = gic_peek_irq(d, GICD_ISENABLER); 1174021f6537SMarc Zyngier if (enabled) 1175021f6537SMarc Zyngier gic_mask_irq(d); 1176021f6537SMarc Zyngier 1177e91b036eSMarc Zyngier offset = convert_offset_index(d, GICD_IROUTER, &index); 1178e91b036eSMarc Zyngier reg = gic_dist_base(d) + offset + (index * 8); 1179021f6537SMarc Zyngier val = gic_mpidr_to_affinity(cpu_logical_map(cpu)); 1180021f6537SMarc Zyngier 118172c97126SJean-Philippe Brucker gic_write_irouter(val, reg); 1182021f6537SMarc Zyngier 1183021f6537SMarc Zyngier /* 1184021f6537SMarc Zyngier * If the interrupt was enabled, enabled it again. Otherwise, 1185021f6537SMarc Zyngier * just wait for the distributor to have digested our changes. 1186021f6537SMarc Zyngier */ 1187021f6537SMarc Zyngier if (enabled) 1188021f6537SMarc Zyngier gic_unmask_irq(d); 1189021f6537SMarc Zyngier else 1190021f6537SMarc Zyngier gic_dist_wait_for_rwp(); 1191021f6537SMarc Zyngier 1192956ae91aSMarc Zyngier irq_data_update_effective_affinity(d, cpumask_of(cpu)); 1193956ae91aSMarc Zyngier 11940fc6fa29SAntoine Tenart return IRQ_SET_MASK_OK_DONE; 1195021f6537SMarc Zyngier } 1196021f6537SMarc Zyngier #else 1197021f6537SMarc Zyngier #define gic_set_affinity NULL 1198021f6537SMarc Zyngier #define gic_smp_init() do { } while(0) 1199021f6537SMarc Zyngier #endif 1200021f6537SMarc Zyngier 12013708d52fSSudeep Holla #ifdef CONFIG_CPU_PM 12023708d52fSSudeep Holla static int gic_cpu_pm_notifier(struct notifier_block *self, 12033708d52fSSudeep Holla unsigned long cmd, void *v) 12043708d52fSSudeep Holla { 12053708d52fSSudeep Holla if (cmd == CPU_PM_EXIT) { 1206ccd9432aSSudeep Holla if (gic_dist_security_disabled()) 12073708d52fSSudeep Holla gic_enable_redist(true); 12083708d52fSSudeep Holla gic_cpu_sys_reg_init(); 1209ccd9432aSSudeep Holla } else if (cmd == CPU_PM_ENTER && gic_dist_security_disabled()) { 12103708d52fSSudeep Holla gic_write_grpen1(0); 12113708d52fSSudeep Holla gic_enable_redist(false); 12123708d52fSSudeep Holla } 12133708d52fSSudeep Holla return NOTIFY_OK; 12143708d52fSSudeep Holla } 12153708d52fSSudeep Holla 12163708d52fSSudeep Holla static struct notifier_block gic_cpu_pm_notifier_block = { 12173708d52fSSudeep Holla .notifier_call = gic_cpu_pm_notifier, 12183708d52fSSudeep Holla }; 12193708d52fSSudeep Holla 12203708d52fSSudeep Holla static void gic_cpu_pm_init(void) 12213708d52fSSudeep Holla { 12223708d52fSSudeep Holla cpu_pm_register_notifier(&gic_cpu_pm_notifier_block); 12233708d52fSSudeep Holla } 12243708d52fSSudeep Holla 12253708d52fSSudeep Holla #else 12263708d52fSSudeep Holla static inline void gic_cpu_pm_init(void) { } 12273708d52fSSudeep Holla #endif /* CONFIG_CPU_PM */ 12283708d52fSSudeep Holla 1229021f6537SMarc Zyngier static struct irq_chip gic_chip = { 1230021f6537SMarc Zyngier .name = "GICv3", 1231021f6537SMarc Zyngier .irq_mask = gic_mask_irq, 1232021f6537SMarc Zyngier .irq_unmask = gic_unmask_irq, 1233021f6537SMarc Zyngier .irq_eoi = gic_eoi_irq, 1234021f6537SMarc Zyngier .irq_set_type = gic_set_type, 1235021f6537SMarc Zyngier .irq_set_affinity = gic_set_affinity, 1236b594c6e2SMarc Zyngier .irq_get_irqchip_state = gic_irq_get_irqchip_state, 1237b594c6e2SMarc Zyngier .irq_set_irqchip_state = gic_irq_set_irqchip_state, 1238101b35f7SJulien Thierry .irq_nmi_setup = gic_irq_nmi_setup, 1239101b35f7SJulien Thierry .irq_nmi_teardown = gic_irq_nmi_teardown, 12404110b5cbSMarc Zyngier .flags = IRQCHIP_SET_TYPE_MASKED | 12414110b5cbSMarc Zyngier IRQCHIP_SKIP_SET_WAKE | 12424110b5cbSMarc Zyngier IRQCHIP_MASK_ON_SUSPEND, 1243021f6537SMarc Zyngier }; 1244021f6537SMarc Zyngier 12450b6a3da9SMarc Zyngier static struct irq_chip gic_eoimode1_chip = { 12460b6a3da9SMarc Zyngier .name = "GICv3", 12470b6a3da9SMarc Zyngier .irq_mask = gic_eoimode1_mask_irq, 12480b6a3da9SMarc Zyngier .irq_unmask = gic_unmask_irq, 12490b6a3da9SMarc Zyngier .irq_eoi = gic_eoimode1_eoi_irq, 12500b6a3da9SMarc Zyngier .irq_set_type = gic_set_type, 12510b6a3da9SMarc Zyngier .irq_set_affinity = gic_set_affinity, 12520b6a3da9SMarc Zyngier .irq_get_irqchip_state = gic_irq_get_irqchip_state, 12530b6a3da9SMarc Zyngier .irq_set_irqchip_state = gic_irq_set_irqchip_state, 1254530bf353SMarc Zyngier .irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity, 1255101b35f7SJulien Thierry .irq_nmi_setup = gic_irq_nmi_setup, 1256101b35f7SJulien Thierry .irq_nmi_teardown = gic_irq_nmi_teardown, 12574110b5cbSMarc Zyngier .flags = IRQCHIP_SET_TYPE_MASKED | 12584110b5cbSMarc Zyngier IRQCHIP_SKIP_SET_WAKE | 12594110b5cbSMarc Zyngier IRQCHIP_MASK_ON_SUSPEND, 12600b6a3da9SMarc Zyngier }; 12610b6a3da9SMarc Zyngier 1262021f6537SMarc Zyngier static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq, 1263021f6537SMarc Zyngier irq_hw_number_t hw) 1264021f6537SMarc Zyngier { 12650b6a3da9SMarc Zyngier struct irq_chip *chip = &gic_chip; 12660b6a3da9SMarc Zyngier 1267d01d3274SDavidlohr Bueso if (static_branch_likely(&supports_deactivate_key)) 12680b6a3da9SMarc Zyngier chip = &gic_eoimode1_chip; 12690b6a3da9SMarc Zyngier 1270e91b036eSMarc Zyngier switch (__get_intid_range(hw)) { 1271e91b036eSMarc Zyngier case PPI_RANGE: 12725f51f803SMarc Zyngier case EPPI_RANGE: 1273021f6537SMarc Zyngier irq_set_percpu_devid(irq); 12740b6a3da9SMarc Zyngier irq_domain_set_info(d, irq, hw, chip, d->host_data, 1275443acc4fSMarc Zyngier handle_percpu_devid_irq, NULL, NULL); 1276d17cab44SRob Herring irq_set_status_flags(irq, IRQ_NOAUTOEN); 1277e91b036eSMarc Zyngier break; 1278e91b036eSMarc Zyngier 1279e91b036eSMarc Zyngier case SPI_RANGE: 1280211bddd2SMarc Zyngier case ESPI_RANGE: 12810b6a3da9SMarc Zyngier irq_domain_set_info(d, irq, hw, chip, d->host_data, 1282443acc4fSMarc Zyngier handle_fasteoi_irq, NULL, NULL); 1283d17cab44SRob Herring irq_set_probe(irq); 1284956ae91aSMarc Zyngier irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(irq))); 1285e91b036eSMarc Zyngier break; 1286e91b036eSMarc Zyngier 1287e91b036eSMarc Zyngier case LPI_RANGE: 1288da33f31dSMarc Zyngier if (!gic_dist_supports_lpis()) 1289da33f31dSMarc Zyngier return -EPERM; 12900b6a3da9SMarc Zyngier irq_domain_set_info(d, irq, hw, chip, d->host_data, 1291da33f31dSMarc Zyngier handle_fasteoi_irq, NULL, NULL); 1292e91b036eSMarc Zyngier break; 1293e91b036eSMarc Zyngier 1294e91b036eSMarc Zyngier default: 1295e91b036eSMarc Zyngier return -EPERM; 1296da33f31dSMarc Zyngier } 1297da33f31dSMarc Zyngier 1298021f6537SMarc Zyngier return 0; 1299021f6537SMarc Zyngier } 1300021f6537SMarc Zyngier 130165da7d19SMarc Zyngier #define GIC_IRQ_TYPE_PARTITION (GIC_IRQ_TYPE_LPI + 1) 130265da7d19SMarc Zyngier 1303f833f57fSMarc Zyngier static int gic_irq_domain_translate(struct irq_domain *d, 1304f833f57fSMarc Zyngier struct irq_fwspec *fwspec, 1305f833f57fSMarc Zyngier unsigned long *hwirq, 1306f833f57fSMarc Zyngier unsigned int *type) 1307021f6537SMarc Zyngier { 1308f833f57fSMarc Zyngier if (is_of_node(fwspec->fwnode)) { 1309f833f57fSMarc Zyngier if (fwspec->param_count < 3) 1310021f6537SMarc Zyngier return -EINVAL; 1311021f6537SMarc Zyngier 1312db8c70ecSMarc Zyngier switch (fwspec->param[0]) { 1313db8c70ecSMarc Zyngier case 0: /* SPI */ 1314db8c70ecSMarc Zyngier *hwirq = fwspec->param[1] + 32; 1315db8c70ecSMarc Zyngier break; 1316db8c70ecSMarc Zyngier case 1: /* PPI */ 1317f833f57fSMarc Zyngier *hwirq = fwspec->param[1] + 16; 1318db8c70ecSMarc Zyngier break; 1319211bddd2SMarc Zyngier case 2: /* ESPI */ 1320211bddd2SMarc Zyngier *hwirq = fwspec->param[1] + ESPI_BASE_INTID; 1321211bddd2SMarc Zyngier break; 13225f51f803SMarc Zyngier case 3: /* EPPI */ 13235f51f803SMarc Zyngier *hwirq = fwspec->param[1] + EPPI_BASE_INTID; 13245f51f803SMarc Zyngier break; 1325db8c70ecSMarc Zyngier case GIC_IRQ_TYPE_LPI: /* LPI */ 1326db8c70ecSMarc Zyngier *hwirq = fwspec->param[1]; 1327db8c70ecSMarc Zyngier break; 13285f51f803SMarc Zyngier case GIC_IRQ_TYPE_PARTITION: 13295f51f803SMarc Zyngier *hwirq = fwspec->param[1]; 13305f51f803SMarc Zyngier if (fwspec->param[1] >= 16) 13315f51f803SMarc Zyngier *hwirq += EPPI_BASE_INTID - 16; 13325f51f803SMarc Zyngier else 13335f51f803SMarc Zyngier *hwirq += 16; 13345f51f803SMarc Zyngier break; 1335db8c70ecSMarc Zyngier default: 1336db8c70ecSMarc Zyngier return -EINVAL; 1337db8c70ecSMarc Zyngier } 1338f833f57fSMarc Zyngier 1339f833f57fSMarc Zyngier *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; 13406ef6386eSMarc Zyngier 134165da7d19SMarc Zyngier /* 134265da7d19SMarc Zyngier * Make it clear that broken DTs are... broken. 134365da7d19SMarc Zyngier * Partitionned PPIs are an unfortunate exception. 134465da7d19SMarc Zyngier */ 134565da7d19SMarc Zyngier WARN_ON(*type == IRQ_TYPE_NONE && 134665da7d19SMarc Zyngier fwspec->param[0] != GIC_IRQ_TYPE_PARTITION); 1347f833f57fSMarc Zyngier return 0; 1348021f6537SMarc Zyngier } 1349021f6537SMarc Zyngier 1350ffa7d616STomasz Nowicki if (is_fwnode_irqchip(fwspec->fwnode)) { 1351ffa7d616STomasz Nowicki if(fwspec->param_count != 2) 1352ffa7d616STomasz Nowicki return -EINVAL; 1353ffa7d616STomasz Nowicki 1354ffa7d616STomasz Nowicki *hwirq = fwspec->param[0]; 1355ffa7d616STomasz Nowicki *type = fwspec->param[1]; 13566ef6386eSMarc Zyngier 13576ef6386eSMarc Zyngier WARN_ON(*type == IRQ_TYPE_NONE); 1358ffa7d616STomasz Nowicki return 0; 1359ffa7d616STomasz Nowicki } 1360ffa7d616STomasz Nowicki 1361f833f57fSMarc Zyngier return -EINVAL; 1362021f6537SMarc Zyngier } 1363021f6537SMarc Zyngier 1364443acc4fSMarc Zyngier static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, 1365443acc4fSMarc Zyngier unsigned int nr_irqs, void *arg) 1366443acc4fSMarc Zyngier { 1367443acc4fSMarc Zyngier int i, ret; 1368443acc4fSMarc Zyngier irq_hw_number_t hwirq; 1369443acc4fSMarc Zyngier unsigned int type = IRQ_TYPE_NONE; 1370f833f57fSMarc Zyngier struct irq_fwspec *fwspec = arg; 1371443acc4fSMarc Zyngier 1372f833f57fSMarc Zyngier ret = gic_irq_domain_translate(domain, fwspec, &hwirq, &type); 1373443acc4fSMarc Zyngier if (ret) 1374443acc4fSMarc Zyngier return ret; 1375443acc4fSMarc Zyngier 137663c16c6eSSuzuki K Poulose for (i = 0; i < nr_irqs; i++) { 137763c16c6eSSuzuki K Poulose ret = gic_irq_domain_map(domain, virq + i, hwirq + i); 137863c16c6eSSuzuki K Poulose if (ret) 137963c16c6eSSuzuki K Poulose return ret; 138063c16c6eSSuzuki K Poulose } 1381443acc4fSMarc Zyngier 1382443acc4fSMarc Zyngier return 0; 1383443acc4fSMarc Zyngier } 1384443acc4fSMarc Zyngier 1385443acc4fSMarc Zyngier static void gic_irq_domain_free(struct irq_domain *domain, unsigned int virq, 1386443acc4fSMarc Zyngier unsigned int nr_irqs) 1387443acc4fSMarc Zyngier { 1388443acc4fSMarc Zyngier int i; 1389443acc4fSMarc Zyngier 1390443acc4fSMarc Zyngier for (i = 0; i < nr_irqs; i++) { 1391443acc4fSMarc Zyngier struct irq_data *d = irq_domain_get_irq_data(domain, virq + i); 1392443acc4fSMarc Zyngier irq_set_handler(virq + i, NULL); 1393443acc4fSMarc Zyngier irq_domain_reset_irq_data(d); 1394443acc4fSMarc Zyngier } 1395443acc4fSMarc Zyngier } 1396443acc4fSMarc Zyngier 1397e3825ba1SMarc Zyngier static int gic_irq_domain_select(struct irq_domain *d, 1398e3825ba1SMarc Zyngier struct irq_fwspec *fwspec, 1399e3825ba1SMarc Zyngier enum irq_domain_bus_token bus_token) 1400e3825ba1SMarc Zyngier { 1401e3825ba1SMarc Zyngier /* Not for us */ 1402e3825ba1SMarc Zyngier if (fwspec->fwnode != d->fwnode) 1403e3825ba1SMarc Zyngier return 0; 1404e3825ba1SMarc Zyngier 1405e3825ba1SMarc Zyngier /* If this is not DT, then we have a single domain */ 1406e3825ba1SMarc Zyngier if (!is_of_node(fwspec->fwnode)) 1407e3825ba1SMarc Zyngier return 1; 1408e3825ba1SMarc Zyngier 1409e3825ba1SMarc Zyngier /* 1410e3825ba1SMarc Zyngier * If this is a PPI and we have a 4th (non-null) parameter, 1411e3825ba1SMarc Zyngier * then we need to match the partition domain. 1412e3825ba1SMarc Zyngier */ 1413e3825ba1SMarc Zyngier if (fwspec->param_count >= 4 && 141452085d3fSMarc Zyngier fwspec->param[0] == 1 && fwspec->param[3] != 0 && 141552085d3fSMarc Zyngier gic_data.ppi_descs) 1416e3825ba1SMarc Zyngier return d == partition_get_domain(gic_data.ppi_descs[fwspec->param[1]]); 1417e3825ba1SMarc Zyngier 1418e3825ba1SMarc Zyngier return d == gic_data.domain; 1419e3825ba1SMarc Zyngier } 1420e3825ba1SMarc Zyngier 1421021f6537SMarc Zyngier static const struct irq_domain_ops gic_irq_domain_ops = { 1422f833f57fSMarc Zyngier .translate = gic_irq_domain_translate, 1423443acc4fSMarc Zyngier .alloc = gic_irq_domain_alloc, 1424443acc4fSMarc Zyngier .free = gic_irq_domain_free, 1425e3825ba1SMarc Zyngier .select = gic_irq_domain_select, 1426e3825ba1SMarc Zyngier }; 1427e3825ba1SMarc Zyngier 1428e3825ba1SMarc Zyngier static int partition_domain_translate(struct irq_domain *d, 1429e3825ba1SMarc Zyngier struct irq_fwspec *fwspec, 1430e3825ba1SMarc Zyngier unsigned long *hwirq, 1431e3825ba1SMarc Zyngier unsigned int *type) 1432e3825ba1SMarc Zyngier { 1433e3825ba1SMarc Zyngier struct device_node *np; 1434e3825ba1SMarc Zyngier int ret; 1435e3825ba1SMarc Zyngier 143652085d3fSMarc Zyngier if (!gic_data.ppi_descs) 143752085d3fSMarc Zyngier return -ENOMEM; 143852085d3fSMarc Zyngier 1439e3825ba1SMarc Zyngier np = of_find_node_by_phandle(fwspec->param[3]); 1440e3825ba1SMarc Zyngier if (WARN_ON(!np)) 1441e3825ba1SMarc Zyngier return -EINVAL; 1442e3825ba1SMarc Zyngier 1443e3825ba1SMarc Zyngier ret = partition_translate_id(gic_data.ppi_descs[fwspec->param[1]], 1444e3825ba1SMarc Zyngier of_node_to_fwnode(np)); 1445e3825ba1SMarc Zyngier if (ret < 0) 1446e3825ba1SMarc Zyngier return ret; 1447e3825ba1SMarc Zyngier 1448e3825ba1SMarc Zyngier *hwirq = ret; 1449e3825ba1SMarc Zyngier *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; 1450e3825ba1SMarc Zyngier 1451e3825ba1SMarc Zyngier return 0; 1452e3825ba1SMarc Zyngier } 1453e3825ba1SMarc Zyngier 1454e3825ba1SMarc Zyngier static const struct irq_domain_ops partition_domain_ops = { 1455e3825ba1SMarc Zyngier .translate = partition_domain_translate, 1456e3825ba1SMarc Zyngier .select = gic_irq_domain_select, 1457021f6537SMarc Zyngier }; 1458021f6537SMarc Zyngier 14599c8114c2SSrinivas Kandagatla static bool gic_enable_quirk_msm8996(void *data) 14609c8114c2SSrinivas Kandagatla { 14619c8114c2SSrinivas Kandagatla struct gic_chip_data *d = data; 14629c8114c2SSrinivas Kandagatla 14639c8114c2SSrinivas Kandagatla d->flags |= FLAGS_WORKAROUND_GICR_WAKER_MSM8996; 14649c8114c2SSrinivas Kandagatla 14659c8114c2SSrinivas Kandagatla return true; 14669c8114c2SSrinivas Kandagatla } 14679c8114c2SSrinivas Kandagatla 1468d01fd161SMarc Zyngier static bool gic_enable_quirk_cavium_38539(void *data) 1469d01fd161SMarc Zyngier { 1470d01fd161SMarc Zyngier struct gic_chip_data *d = data; 1471d01fd161SMarc Zyngier 1472d01fd161SMarc Zyngier d->flags |= FLAGS_WORKAROUND_CAVIUM_ERRATUM_38539; 1473d01fd161SMarc Zyngier 1474d01fd161SMarc Zyngier return true; 1475d01fd161SMarc Zyngier } 1476d01fd161SMarc Zyngier 14777f2481b3SMarc Zyngier static bool gic_enable_quirk_hip06_07(void *data) 14787f2481b3SMarc Zyngier { 14797f2481b3SMarc Zyngier struct gic_chip_data *d = data; 14807f2481b3SMarc Zyngier 14817f2481b3SMarc Zyngier /* 14827f2481b3SMarc Zyngier * HIP06 GICD_IIDR clashes with GIC-600 product number (despite 14837f2481b3SMarc Zyngier * not being an actual ARM implementation). The saving grace is 14847f2481b3SMarc Zyngier * that GIC-600 doesn't have ESPI, so nothing to do in that case. 14857f2481b3SMarc Zyngier * HIP07 doesn't even have a proper IIDR, and still pretends to 14867f2481b3SMarc Zyngier * have ESPI. In both cases, put them right. 14877f2481b3SMarc Zyngier */ 14887f2481b3SMarc Zyngier if (d->rdists.gicd_typer & GICD_TYPER_ESPI) { 14897f2481b3SMarc Zyngier /* Zero both ESPI and the RES0 field next to it... */ 14907f2481b3SMarc Zyngier d->rdists.gicd_typer &= ~GENMASK(9, 8); 14917f2481b3SMarc Zyngier return true; 14927f2481b3SMarc Zyngier } 14937f2481b3SMarc Zyngier 14947f2481b3SMarc Zyngier return false; 14957f2481b3SMarc Zyngier } 14967f2481b3SMarc Zyngier 14977f2481b3SMarc Zyngier static const struct gic_quirk gic_quirks[] = { 14987f2481b3SMarc Zyngier { 14997f2481b3SMarc Zyngier .desc = "GICv3: Qualcomm MSM8996 broken firmware", 15007f2481b3SMarc Zyngier .compatible = "qcom,msm8996-gic-v3", 15017f2481b3SMarc Zyngier .init = gic_enable_quirk_msm8996, 15027f2481b3SMarc Zyngier }, 15037f2481b3SMarc Zyngier { 15047f2481b3SMarc Zyngier .desc = "GICv3: HIP06 erratum 161010803", 15057f2481b3SMarc Zyngier .iidr = 0x0204043b, 15067f2481b3SMarc Zyngier .mask = 0xffffffff, 15077f2481b3SMarc Zyngier .init = gic_enable_quirk_hip06_07, 15087f2481b3SMarc Zyngier }, 15097f2481b3SMarc Zyngier { 15107f2481b3SMarc Zyngier .desc = "GICv3: HIP07 erratum 161010803", 15117f2481b3SMarc Zyngier .iidr = 0x00000000, 15127f2481b3SMarc Zyngier .mask = 0xffffffff, 15137f2481b3SMarc Zyngier .init = gic_enable_quirk_hip06_07, 15147f2481b3SMarc Zyngier }, 15157f2481b3SMarc Zyngier { 1516d01fd161SMarc Zyngier /* 1517d01fd161SMarc Zyngier * Reserved register accesses generate a Synchronous 1518d01fd161SMarc Zyngier * External Abort. This erratum applies to: 1519d01fd161SMarc Zyngier * - ThunderX: CN88xx 1520d01fd161SMarc Zyngier * - OCTEON TX: CN83xx, CN81xx 1521d01fd161SMarc Zyngier * - OCTEON TX2: CN93xx, CN96xx, CN98xx, CNF95xx* 1522d01fd161SMarc Zyngier */ 1523d01fd161SMarc Zyngier .desc = "GICv3: Cavium erratum 38539", 1524d01fd161SMarc Zyngier .iidr = 0xa000034c, 1525d01fd161SMarc Zyngier .mask = 0xe8f00fff, 1526d01fd161SMarc Zyngier .init = gic_enable_quirk_cavium_38539, 1527d01fd161SMarc Zyngier }, 1528d01fd161SMarc Zyngier { 15297f2481b3SMarc Zyngier } 15307f2481b3SMarc Zyngier }; 15317f2481b3SMarc Zyngier 1532d98d0a99SJulien Thierry static void gic_enable_nmi_support(void) 1533d98d0a99SJulien Thierry { 1534101b35f7SJulien Thierry int i; 1535101b35f7SJulien Thierry 153681a43273SMarc Zyngier if (!gic_prio_masking_enabled()) 153781a43273SMarc Zyngier return; 153881a43273SMarc Zyngier 153981a43273SMarc Zyngier if (gic_has_group0() && !gic_dist_security_disabled()) { 154081a43273SMarc Zyngier pr_warn("SCR_EL3.FIQ is cleared, cannot enable use of pseudo-NMIs\n"); 154181a43273SMarc Zyngier return; 154281a43273SMarc Zyngier } 154381a43273SMarc Zyngier 154481a43273SMarc Zyngier ppi_nmi_refs = kcalloc(gic_data.ppi_nr, sizeof(*ppi_nmi_refs), GFP_KERNEL); 154581a43273SMarc Zyngier if (!ppi_nmi_refs) 154681a43273SMarc Zyngier return; 154781a43273SMarc Zyngier 154881a43273SMarc Zyngier for (i = 0; i < gic_data.ppi_nr; i++) 1549101b35f7SJulien Thierry refcount_set(&ppi_nmi_refs[i], 0); 1550101b35f7SJulien Thierry 1551f2266504SMarc Zyngier /* 1552f2266504SMarc Zyngier * Linux itself doesn't use 1:N distribution, so has no need to 1553f2266504SMarc Zyngier * set PMHE. The only reason to have it set is if EL3 requires it 1554f2266504SMarc Zyngier * (and we can't change it). 1555f2266504SMarc Zyngier */ 1556f2266504SMarc Zyngier if (gic_read_ctlr() & ICC_CTLR_EL1_PMHE_MASK) 1557f2266504SMarc Zyngier static_branch_enable(&gic_pmr_sync); 1558f2266504SMarc Zyngier 1559f2266504SMarc Zyngier pr_info("%s ICC_PMR_EL1 synchronisation\n", 1560f2266504SMarc Zyngier static_branch_unlikely(&gic_pmr_sync) ? "Forcing" : "Relaxing"); 1561f2266504SMarc Zyngier 1562d98d0a99SJulien Thierry static_branch_enable(&supports_pseudo_nmis); 1563101b35f7SJulien Thierry 1564101b35f7SJulien Thierry if (static_branch_likely(&supports_deactivate_key)) 1565101b35f7SJulien Thierry gic_eoimode1_chip.flags |= IRQCHIP_SUPPORTS_NMI; 1566101b35f7SJulien Thierry else 1567101b35f7SJulien Thierry gic_chip.flags |= IRQCHIP_SUPPORTS_NMI; 1568d98d0a99SJulien Thierry } 1569d98d0a99SJulien Thierry 1570db57d746STomasz Nowicki static int __init gic_init_bases(void __iomem *dist_base, 1571db57d746STomasz Nowicki struct redist_region *rdist_regs, 1572db57d746STomasz Nowicki u32 nr_redist_regions, 1573db57d746STomasz Nowicki u64 redist_stride, 1574db57d746STomasz Nowicki struct fwnode_handle *handle) 1575db57d746STomasz Nowicki { 1576db57d746STomasz Nowicki u32 typer; 1577db57d746STomasz Nowicki int err; 1578db57d746STomasz Nowicki 1579db57d746STomasz Nowicki if (!is_hyp_mode_available()) 1580d01d3274SDavidlohr Bueso static_branch_disable(&supports_deactivate_key); 1581db57d746STomasz Nowicki 1582d01d3274SDavidlohr Bueso if (static_branch_likely(&supports_deactivate_key)) 1583db57d746STomasz Nowicki pr_info("GIC: Using split EOI/Deactivate mode\n"); 1584db57d746STomasz Nowicki 1585e3825ba1SMarc Zyngier gic_data.fwnode = handle; 1586db57d746STomasz Nowicki gic_data.dist_base = dist_base; 1587db57d746STomasz Nowicki gic_data.redist_regions = rdist_regs; 1588db57d746STomasz Nowicki gic_data.nr_redist_regions = nr_redist_regions; 1589db57d746STomasz Nowicki gic_data.redist_stride = redist_stride; 1590db57d746STomasz Nowicki 1591db57d746STomasz Nowicki /* 1592db57d746STomasz Nowicki * Find out how many interrupts are supported. 1593db57d746STomasz Nowicki */ 1594db57d746STomasz Nowicki typer = readl_relaxed(gic_data.dist_base + GICD_TYPER); 1595a4f9edb2SMarc Zyngier gic_data.rdists.gicd_typer = typer; 15967f2481b3SMarc Zyngier 15977f2481b3SMarc Zyngier gic_enable_quirks(readl_relaxed(gic_data.dist_base + GICD_IIDR), 15987f2481b3SMarc Zyngier gic_quirks, &gic_data); 15997f2481b3SMarc Zyngier 1600211bddd2SMarc Zyngier pr_info("%d SPIs implemented\n", GIC_LINE_NR - 32); 1601211bddd2SMarc Zyngier pr_info("%d Extended SPIs implemented\n", GIC_ESPI_NR); 1602f2d83409SMarc Zyngier 1603d01fd161SMarc Zyngier /* 1604d01fd161SMarc Zyngier * ThunderX1 explodes on reading GICD_TYPER2, in violation of the 1605d01fd161SMarc Zyngier * architecture spec (which says that reserved registers are RES0). 1606d01fd161SMarc Zyngier */ 1607d01fd161SMarc Zyngier if (!(gic_data.flags & FLAGS_WORKAROUND_CAVIUM_ERRATUM_38539)) 1608f2d83409SMarc Zyngier gic_data.rdists.gicd_typer2 = readl_relaxed(gic_data.dist_base + GICD_TYPER2); 1609f2d83409SMarc Zyngier 1610db57d746STomasz Nowicki gic_data.domain = irq_domain_create_tree(handle, &gic_irq_domain_ops, 1611db57d746STomasz Nowicki &gic_data); 1612b2425b51SMarc Zyngier irq_domain_update_bus_token(gic_data.domain, DOMAIN_BUS_WIRED); 1613db57d746STomasz Nowicki gic_data.rdists.rdist = alloc_percpu(typeof(*gic_data.rdists.rdist)); 1614b25319d2SMarc Zyngier gic_data.rdists.has_rvpeid = true; 16150edc23eaSMarc Zyngier gic_data.rdists.has_vlpis = true; 16160edc23eaSMarc Zyngier gic_data.rdists.has_direct_lpi = true; 1617db57d746STomasz Nowicki 1618db57d746STomasz Nowicki if (WARN_ON(!gic_data.domain) || WARN_ON(!gic_data.rdists.rdist)) { 1619db57d746STomasz Nowicki err = -ENOMEM; 1620db57d746STomasz Nowicki goto out_free; 1621db57d746STomasz Nowicki } 1622db57d746STomasz Nowicki 1623eda0d04aSShanker Donthineni gic_data.has_rss = !!(typer & GICD_TYPER_RSS); 1624eda0d04aSShanker Donthineni pr_info("Distributor has %sRange Selector support\n", 1625eda0d04aSShanker Donthineni gic_data.has_rss ? "" : "no "); 1626eda0d04aSShanker Donthineni 162750528752SMarc Zyngier if (typer & GICD_TYPER_MBIS) { 162850528752SMarc Zyngier err = mbi_init(handle, gic_data.domain); 162950528752SMarc Zyngier if (err) 163050528752SMarc Zyngier pr_err("Failed to initialize MBIs\n"); 163150528752SMarc Zyngier } 163250528752SMarc Zyngier 1633db57d746STomasz Nowicki set_handle_irq(gic_handle_irq); 1634db57d746STomasz Nowicki 16351a60e1e6SMarc Zyngier gic_update_rdist_properties(); 16360edc23eaSMarc Zyngier 1637db57d746STomasz Nowicki gic_smp_init(); 1638db57d746STomasz Nowicki gic_dist_init(); 1639db57d746STomasz Nowicki gic_cpu_init(); 1640db57d746STomasz Nowicki gic_cpu_pm_init(); 1641db57d746STomasz Nowicki 1642d38a71c5SMarc Zyngier if (gic_dist_supports_lpis()) { 1643d38a71c5SMarc Zyngier its_init(handle, &gic_data.rdists, gic_data.domain); 1644d38a71c5SMarc Zyngier its_cpu_init(); 164590b4c555SZeev Zilberman } else { 164690b4c555SZeev Zilberman if (IS_ENABLED(CONFIG_ARM_GIC_V2M)) 164790b4c555SZeev Zilberman gicv2m_init(handle, gic_data.domain); 1648d38a71c5SMarc Zyngier } 1649d38a71c5SMarc Zyngier 1650d98d0a99SJulien Thierry gic_enable_nmi_support(); 1651d98d0a99SJulien Thierry 1652db57d746STomasz Nowicki return 0; 1653db57d746STomasz Nowicki 1654db57d746STomasz Nowicki out_free: 1655db57d746STomasz Nowicki if (gic_data.domain) 1656db57d746STomasz Nowicki irq_domain_remove(gic_data.domain); 1657db57d746STomasz Nowicki free_percpu(gic_data.rdists.rdist); 1658db57d746STomasz Nowicki return err; 1659db57d746STomasz Nowicki } 1660db57d746STomasz Nowicki 1661db57d746STomasz Nowicki static int __init gic_validate_dist_version(void __iomem *dist_base) 1662db57d746STomasz Nowicki { 1663db57d746STomasz Nowicki u32 reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK; 1664db57d746STomasz Nowicki 1665db57d746STomasz Nowicki if (reg != GIC_PIDR2_ARCH_GICv3 && reg != GIC_PIDR2_ARCH_GICv4) 1666db57d746STomasz Nowicki return -ENODEV; 1667db57d746STomasz Nowicki 1668db57d746STomasz Nowicki return 0; 1669db57d746STomasz Nowicki } 1670db57d746STomasz Nowicki 1671e3825ba1SMarc Zyngier /* Create all possible partitions at boot time */ 16727beaa24bSLinus Torvalds static void __init gic_populate_ppi_partitions(struct device_node *gic_node) 1673e3825ba1SMarc Zyngier { 1674e3825ba1SMarc Zyngier struct device_node *parts_node, *child_part; 1675e3825ba1SMarc Zyngier int part_idx = 0, i; 1676e3825ba1SMarc Zyngier int nr_parts; 1677e3825ba1SMarc Zyngier struct partition_affinity *parts; 1678e3825ba1SMarc Zyngier 167900ee9a1cSJohan Hovold parts_node = of_get_child_by_name(gic_node, "ppi-partitions"); 1680e3825ba1SMarc Zyngier if (!parts_node) 1681e3825ba1SMarc Zyngier return; 1682e3825ba1SMarc Zyngier 168352085d3fSMarc Zyngier gic_data.ppi_descs = kcalloc(gic_data.ppi_nr, sizeof(*gic_data.ppi_descs), GFP_KERNEL); 168452085d3fSMarc Zyngier if (!gic_data.ppi_descs) 168552085d3fSMarc Zyngier return; 168652085d3fSMarc Zyngier 1687e3825ba1SMarc Zyngier nr_parts = of_get_child_count(parts_node); 1688e3825ba1SMarc Zyngier 1689e3825ba1SMarc Zyngier if (!nr_parts) 169000ee9a1cSJohan Hovold goto out_put_node; 1691e3825ba1SMarc Zyngier 16926396bb22SKees Cook parts = kcalloc(nr_parts, sizeof(*parts), GFP_KERNEL); 1693e3825ba1SMarc Zyngier if (WARN_ON(!parts)) 169400ee9a1cSJohan Hovold goto out_put_node; 1695e3825ba1SMarc Zyngier 1696e3825ba1SMarc Zyngier for_each_child_of_node(parts_node, child_part) { 1697e3825ba1SMarc Zyngier struct partition_affinity *part; 1698e3825ba1SMarc Zyngier int n; 1699e3825ba1SMarc Zyngier 1700e3825ba1SMarc Zyngier part = &parts[part_idx]; 1701e3825ba1SMarc Zyngier 1702e3825ba1SMarc Zyngier part->partition_id = of_node_to_fwnode(child_part); 1703e3825ba1SMarc Zyngier 17042ef790dcSRob Herring pr_info("GIC: PPI partition %pOFn[%d] { ", 17052ef790dcSRob Herring child_part, part_idx); 1706e3825ba1SMarc Zyngier 1707e3825ba1SMarc Zyngier n = of_property_count_elems_of_size(child_part, "affinity", 1708e3825ba1SMarc Zyngier sizeof(u32)); 1709e3825ba1SMarc Zyngier WARN_ON(n <= 0); 1710e3825ba1SMarc Zyngier 1711e3825ba1SMarc Zyngier for (i = 0; i < n; i++) { 1712e3825ba1SMarc Zyngier int err, cpu; 1713e3825ba1SMarc Zyngier u32 cpu_phandle; 1714e3825ba1SMarc Zyngier struct device_node *cpu_node; 1715e3825ba1SMarc Zyngier 1716e3825ba1SMarc Zyngier err = of_property_read_u32_index(child_part, "affinity", 1717e3825ba1SMarc Zyngier i, &cpu_phandle); 1718e3825ba1SMarc Zyngier if (WARN_ON(err)) 1719e3825ba1SMarc Zyngier continue; 1720e3825ba1SMarc Zyngier 1721e3825ba1SMarc Zyngier cpu_node = of_find_node_by_phandle(cpu_phandle); 1722e3825ba1SMarc Zyngier if (WARN_ON(!cpu_node)) 1723e3825ba1SMarc Zyngier continue; 1724e3825ba1SMarc Zyngier 1725c08ec7daSSuzuki K Poulose cpu = of_cpu_node_to_id(cpu_node); 1726c08ec7daSSuzuki K Poulose if (WARN_ON(cpu < 0)) 1727e3825ba1SMarc Zyngier continue; 1728e3825ba1SMarc Zyngier 1729e81f54c6SRob Herring pr_cont("%pOF[%d] ", cpu_node, cpu); 1730e3825ba1SMarc Zyngier 1731e3825ba1SMarc Zyngier cpumask_set_cpu(cpu, &part->mask); 1732e3825ba1SMarc Zyngier } 1733e3825ba1SMarc Zyngier 1734e3825ba1SMarc Zyngier pr_cont("}\n"); 1735e3825ba1SMarc Zyngier part_idx++; 1736e3825ba1SMarc Zyngier } 1737e3825ba1SMarc Zyngier 173852085d3fSMarc Zyngier for (i = 0; i < gic_data.ppi_nr; i++) { 1739e3825ba1SMarc Zyngier unsigned int irq; 1740e3825ba1SMarc Zyngier struct partition_desc *desc; 1741e3825ba1SMarc Zyngier struct irq_fwspec ppi_fwspec = { 1742e3825ba1SMarc Zyngier .fwnode = gic_data.fwnode, 1743e3825ba1SMarc Zyngier .param_count = 3, 1744e3825ba1SMarc Zyngier .param = { 174565da7d19SMarc Zyngier [0] = GIC_IRQ_TYPE_PARTITION, 1746e3825ba1SMarc Zyngier [1] = i, 1747e3825ba1SMarc Zyngier [2] = IRQ_TYPE_NONE, 1748e3825ba1SMarc Zyngier }, 1749e3825ba1SMarc Zyngier }; 1750e3825ba1SMarc Zyngier 1751e3825ba1SMarc Zyngier irq = irq_create_fwspec_mapping(&ppi_fwspec); 1752e3825ba1SMarc Zyngier if (WARN_ON(!irq)) 1753e3825ba1SMarc Zyngier continue; 1754e3825ba1SMarc Zyngier desc = partition_create_desc(gic_data.fwnode, parts, nr_parts, 1755e3825ba1SMarc Zyngier irq, &partition_domain_ops); 1756e3825ba1SMarc Zyngier if (WARN_ON(!desc)) 1757e3825ba1SMarc Zyngier continue; 1758e3825ba1SMarc Zyngier 1759e3825ba1SMarc Zyngier gic_data.ppi_descs[i] = desc; 1760e3825ba1SMarc Zyngier } 176100ee9a1cSJohan Hovold 176200ee9a1cSJohan Hovold out_put_node: 176300ee9a1cSJohan Hovold of_node_put(parts_node); 1764e3825ba1SMarc Zyngier } 1765e3825ba1SMarc Zyngier 17661839e576SJulien Grall static void __init gic_of_setup_kvm_info(struct device_node *node) 17671839e576SJulien Grall { 17681839e576SJulien Grall int ret; 17691839e576SJulien Grall struct resource r; 17701839e576SJulien Grall u32 gicv_idx; 17711839e576SJulien Grall 17721839e576SJulien Grall gic_v3_kvm_info.type = GIC_V3; 17731839e576SJulien Grall 17741839e576SJulien Grall gic_v3_kvm_info.maint_irq = irq_of_parse_and_map(node, 0); 17751839e576SJulien Grall if (!gic_v3_kvm_info.maint_irq) 17761839e576SJulien Grall return; 17771839e576SJulien Grall 17781839e576SJulien Grall if (of_property_read_u32(node, "#redistributor-regions", 17791839e576SJulien Grall &gicv_idx)) 17801839e576SJulien Grall gicv_idx = 1; 17811839e576SJulien Grall 17821839e576SJulien Grall gicv_idx += 3; /* Also skip GICD, GICC, GICH */ 17831839e576SJulien Grall ret = of_address_to_resource(node, gicv_idx, &r); 17841839e576SJulien Grall if (!ret) 17851839e576SJulien Grall gic_v3_kvm_info.vcpu = r; 17861839e576SJulien Grall 17874bdf5025SMarc Zyngier gic_v3_kvm_info.has_v4 = gic_data.rdists.has_vlpis; 17881839e576SJulien Grall gic_set_kvm_info(&gic_v3_kvm_info); 17891839e576SJulien Grall } 17901839e576SJulien Grall 1791021f6537SMarc Zyngier static int __init gic_of_init(struct device_node *node, struct device_node *parent) 1792021f6537SMarc Zyngier { 1793021f6537SMarc Zyngier void __iomem *dist_base; 1794f5c1434cSMarc Zyngier struct redist_region *rdist_regs; 1795021f6537SMarc Zyngier u64 redist_stride; 1796f5c1434cSMarc Zyngier u32 nr_redist_regions; 1797db57d746STomasz Nowicki int err, i; 1798021f6537SMarc Zyngier 1799021f6537SMarc Zyngier dist_base = of_iomap(node, 0); 1800021f6537SMarc Zyngier if (!dist_base) { 1801e81f54c6SRob Herring pr_err("%pOF: unable to map gic dist registers\n", node); 1802021f6537SMarc Zyngier return -ENXIO; 1803021f6537SMarc Zyngier } 1804021f6537SMarc Zyngier 1805db57d746STomasz Nowicki err = gic_validate_dist_version(dist_base); 1806db57d746STomasz Nowicki if (err) { 1807e81f54c6SRob Herring pr_err("%pOF: no distributor detected, giving up\n", node); 1808021f6537SMarc Zyngier goto out_unmap_dist; 1809021f6537SMarc Zyngier } 1810021f6537SMarc Zyngier 1811f5c1434cSMarc Zyngier if (of_property_read_u32(node, "#redistributor-regions", &nr_redist_regions)) 1812f5c1434cSMarc Zyngier nr_redist_regions = 1; 1813021f6537SMarc Zyngier 18146396bb22SKees Cook rdist_regs = kcalloc(nr_redist_regions, sizeof(*rdist_regs), 18156396bb22SKees Cook GFP_KERNEL); 1816f5c1434cSMarc Zyngier if (!rdist_regs) { 1817021f6537SMarc Zyngier err = -ENOMEM; 1818021f6537SMarc Zyngier goto out_unmap_dist; 1819021f6537SMarc Zyngier } 1820021f6537SMarc Zyngier 1821f5c1434cSMarc Zyngier for (i = 0; i < nr_redist_regions; i++) { 1822f5c1434cSMarc Zyngier struct resource res; 1823f5c1434cSMarc Zyngier int ret; 1824f5c1434cSMarc Zyngier 1825f5c1434cSMarc Zyngier ret = of_address_to_resource(node, 1 + i, &res); 1826f5c1434cSMarc Zyngier rdist_regs[i].redist_base = of_iomap(node, 1 + i); 1827f5c1434cSMarc Zyngier if (ret || !rdist_regs[i].redist_base) { 1828e81f54c6SRob Herring pr_err("%pOF: couldn't map region %d\n", node, i); 1829021f6537SMarc Zyngier err = -ENODEV; 1830021f6537SMarc Zyngier goto out_unmap_rdist; 1831021f6537SMarc Zyngier } 1832f5c1434cSMarc Zyngier rdist_regs[i].phys_base = res.start; 1833021f6537SMarc Zyngier } 1834021f6537SMarc Zyngier 1835021f6537SMarc Zyngier if (of_property_read_u64(node, "redistributor-stride", &redist_stride)) 1836021f6537SMarc Zyngier redist_stride = 0; 1837021f6537SMarc Zyngier 1838f70fdb42SSrinivas Kandagatla gic_enable_of_quirks(node, gic_quirks, &gic_data); 1839f70fdb42SSrinivas Kandagatla 1840db57d746STomasz Nowicki err = gic_init_bases(dist_base, rdist_regs, nr_redist_regions, 1841db57d746STomasz Nowicki redist_stride, &node->fwnode); 1842e3825ba1SMarc Zyngier if (err) 1843e3825ba1SMarc Zyngier goto out_unmap_rdist; 1844e3825ba1SMarc Zyngier 1845e3825ba1SMarc Zyngier gic_populate_ppi_partitions(node); 1846d33a3c8cSChristoffer Dall 1847d01d3274SDavidlohr Bueso if (static_branch_likely(&supports_deactivate_key)) 18481839e576SJulien Grall gic_of_setup_kvm_info(node); 1849021f6537SMarc Zyngier return 0; 1850021f6537SMarc Zyngier 1851021f6537SMarc Zyngier out_unmap_rdist: 1852f5c1434cSMarc Zyngier for (i = 0; i < nr_redist_regions; i++) 1853f5c1434cSMarc Zyngier if (rdist_regs[i].redist_base) 1854f5c1434cSMarc Zyngier iounmap(rdist_regs[i].redist_base); 1855f5c1434cSMarc Zyngier kfree(rdist_regs); 1856021f6537SMarc Zyngier out_unmap_dist: 1857021f6537SMarc Zyngier iounmap(dist_base); 1858021f6537SMarc Zyngier return err; 1859021f6537SMarc Zyngier } 1860021f6537SMarc Zyngier 1861021f6537SMarc Zyngier IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init); 1862ffa7d616STomasz Nowicki 1863ffa7d616STomasz Nowicki #ifdef CONFIG_ACPI 1864611f039fSJulien Grall static struct 1865611f039fSJulien Grall { 1866611f039fSJulien Grall void __iomem *dist_base; 1867611f039fSJulien Grall struct redist_region *redist_regs; 1868611f039fSJulien Grall u32 nr_redist_regions; 1869611f039fSJulien Grall bool single_redist; 1870926b5dfaSMarc Zyngier int enabled_rdists; 18711839e576SJulien Grall u32 maint_irq; 18721839e576SJulien Grall int maint_irq_mode; 18731839e576SJulien Grall phys_addr_t vcpu_base; 1874611f039fSJulien Grall } acpi_data __initdata; 1875b70fb7afSTomasz Nowicki 1876b70fb7afSTomasz Nowicki static void __init 1877b70fb7afSTomasz Nowicki gic_acpi_register_redist(phys_addr_t phys_base, void __iomem *redist_base) 1878b70fb7afSTomasz Nowicki { 1879b70fb7afSTomasz Nowicki static int count = 0; 1880b70fb7afSTomasz Nowicki 1881611f039fSJulien Grall acpi_data.redist_regs[count].phys_base = phys_base; 1882611f039fSJulien Grall acpi_data.redist_regs[count].redist_base = redist_base; 1883611f039fSJulien Grall acpi_data.redist_regs[count].single_redist = acpi_data.single_redist; 1884b70fb7afSTomasz Nowicki count++; 1885b70fb7afSTomasz Nowicki } 1886ffa7d616STomasz Nowicki 1887ffa7d616STomasz Nowicki static int __init 188860574d1eSKeith Busch gic_acpi_parse_madt_redist(union acpi_subtable_headers *header, 1889ffa7d616STomasz Nowicki const unsigned long end) 1890ffa7d616STomasz Nowicki { 1891ffa7d616STomasz Nowicki struct acpi_madt_generic_redistributor *redist = 1892ffa7d616STomasz Nowicki (struct acpi_madt_generic_redistributor *)header; 1893ffa7d616STomasz Nowicki void __iomem *redist_base; 1894ffa7d616STomasz Nowicki 1895ffa7d616STomasz Nowicki redist_base = ioremap(redist->base_address, redist->length); 1896ffa7d616STomasz Nowicki if (!redist_base) { 1897ffa7d616STomasz Nowicki pr_err("Couldn't map GICR region @%llx\n", redist->base_address); 1898ffa7d616STomasz Nowicki return -ENOMEM; 1899ffa7d616STomasz Nowicki } 1900ffa7d616STomasz Nowicki 1901b70fb7afSTomasz Nowicki gic_acpi_register_redist(redist->base_address, redist_base); 1902ffa7d616STomasz Nowicki return 0; 1903ffa7d616STomasz Nowicki } 1904ffa7d616STomasz Nowicki 1905b70fb7afSTomasz Nowicki static int __init 190660574d1eSKeith Busch gic_acpi_parse_madt_gicc(union acpi_subtable_headers *header, 1907b70fb7afSTomasz Nowicki const unsigned long end) 1908b70fb7afSTomasz Nowicki { 1909b70fb7afSTomasz Nowicki struct acpi_madt_generic_interrupt *gicc = 1910b70fb7afSTomasz Nowicki (struct acpi_madt_generic_interrupt *)header; 1911611f039fSJulien Grall u32 reg = readl_relaxed(acpi_data.dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK; 1912b70fb7afSTomasz Nowicki u32 size = reg == GIC_PIDR2_ARCH_GICv4 ? SZ_64K * 4 : SZ_64K * 2; 1913b70fb7afSTomasz Nowicki void __iomem *redist_base; 1914b70fb7afSTomasz Nowicki 1915ebe2f871SShanker Donthineni /* GICC entry which has !ACPI_MADT_ENABLED is not unusable so skip */ 1916ebe2f871SShanker Donthineni if (!(gicc->flags & ACPI_MADT_ENABLED)) 1917ebe2f871SShanker Donthineni return 0; 1918ebe2f871SShanker Donthineni 1919b70fb7afSTomasz Nowicki redist_base = ioremap(gicc->gicr_base_address, size); 1920b70fb7afSTomasz Nowicki if (!redist_base) 1921b70fb7afSTomasz Nowicki return -ENOMEM; 1922b70fb7afSTomasz Nowicki 1923b70fb7afSTomasz Nowicki gic_acpi_register_redist(gicc->gicr_base_address, redist_base); 1924b70fb7afSTomasz Nowicki return 0; 1925b70fb7afSTomasz Nowicki } 1926b70fb7afSTomasz Nowicki 1927b70fb7afSTomasz Nowicki static int __init gic_acpi_collect_gicr_base(void) 1928b70fb7afSTomasz Nowicki { 1929b70fb7afSTomasz Nowicki acpi_tbl_entry_handler redist_parser; 1930b70fb7afSTomasz Nowicki enum acpi_madt_type type; 1931b70fb7afSTomasz Nowicki 1932611f039fSJulien Grall if (acpi_data.single_redist) { 1933b70fb7afSTomasz Nowicki type = ACPI_MADT_TYPE_GENERIC_INTERRUPT; 1934b70fb7afSTomasz Nowicki redist_parser = gic_acpi_parse_madt_gicc; 1935b70fb7afSTomasz Nowicki } else { 1936b70fb7afSTomasz Nowicki type = ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR; 1937b70fb7afSTomasz Nowicki redist_parser = gic_acpi_parse_madt_redist; 1938b70fb7afSTomasz Nowicki } 1939b70fb7afSTomasz Nowicki 1940b70fb7afSTomasz Nowicki /* Collect redistributor base addresses in GICR entries */ 1941b70fb7afSTomasz Nowicki if (acpi_table_parse_madt(type, redist_parser, 0) > 0) 1942b70fb7afSTomasz Nowicki return 0; 1943b70fb7afSTomasz Nowicki 1944b70fb7afSTomasz Nowicki pr_info("No valid GICR entries exist\n"); 1945b70fb7afSTomasz Nowicki return -ENODEV; 1946b70fb7afSTomasz Nowicki } 1947b70fb7afSTomasz Nowicki 194860574d1eSKeith Busch static int __init gic_acpi_match_gicr(union acpi_subtable_headers *header, 1949ffa7d616STomasz Nowicki const unsigned long end) 1950ffa7d616STomasz Nowicki { 1951ffa7d616STomasz Nowicki /* Subtable presence means that redist exists, that's it */ 1952ffa7d616STomasz Nowicki return 0; 1953ffa7d616STomasz Nowicki } 1954ffa7d616STomasz Nowicki 195560574d1eSKeith Busch static int __init gic_acpi_match_gicc(union acpi_subtable_headers *header, 1956b70fb7afSTomasz Nowicki const unsigned long end) 1957b70fb7afSTomasz Nowicki { 1958b70fb7afSTomasz Nowicki struct acpi_madt_generic_interrupt *gicc = 1959b70fb7afSTomasz Nowicki (struct acpi_madt_generic_interrupt *)header; 1960b70fb7afSTomasz Nowicki 1961b70fb7afSTomasz Nowicki /* 1962b70fb7afSTomasz Nowicki * If GICC is enabled and has valid gicr base address, then it means 1963b70fb7afSTomasz Nowicki * GICR base is presented via GICC 1964b70fb7afSTomasz Nowicki */ 1965926b5dfaSMarc Zyngier if ((gicc->flags & ACPI_MADT_ENABLED) && gicc->gicr_base_address) { 1966926b5dfaSMarc Zyngier acpi_data.enabled_rdists++; 1967b70fb7afSTomasz Nowicki return 0; 1968926b5dfaSMarc Zyngier } 1969b70fb7afSTomasz Nowicki 1970ebe2f871SShanker Donthineni /* 1971ebe2f871SShanker Donthineni * It's perfectly valid firmware can pass disabled GICC entry, driver 1972ebe2f871SShanker Donthineni * should not treat as errors, skip the entry instead of probe fail. 1973ebe2f871SShanker Donthineni */ 1974ebe2f871SShanker Donthineni if (!(gicc->flags & ACPI_MADT_ENABLED)) 1975ebe2f871SShanker Donthineni return 0; 1976ebe2f871SShanker Donthineni 1977b70fb7afSTomasz Nowicki return -ENODEV; 1978b70fb7afSTomasz Nowicki } 1979b70fb7afSTomasz Nowicki 1980b70fb7afSTomasz Nowicki static int __init gic_acpi_count_gicr_regions(void) 1981b70fb7afSTomasz Nowicki { 1982b70fb7afSTomasz Nowicki int count; 1983b70fb7afSTomasz Nowicki 1984b70fb7afSTomasz Nowicki /* 1985b70fb7afSTomasz Nowicki * Count how many redistributor regions we have. It is not allowed 1986b70fb7afSTomasz Nowicki * to mix redistributor description, GICR and GICC subtables have to be 1987b70fb7afSTomasz Nowicki * mutually exclusive. 1988b70fb7afSTomasz Nowicki */ 1989b70fb7afSTomasz Nowicki count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR, 1990b70fb7afSTomasz Nowicki gic_acpi_match_gicr, 0); 1991b70fb7afSTomasz Nowicki if (count > 0) { 1992611f039fSJulien Grall acpi_data.single_redist = false; 1993b70fb7afSTomasz Nowicki return count; 1994b70fb7afSTomasz Nowicki } 1995b70fb7afSTomasz Nowicki 1996b70fb7afSTomasz Nowicki count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT, 1997b70fb7afSTomasz Nowicki gic_acpi_match_gicc, 0); 1998926b5dfaSMarc Zyngier if (count > 0) { 1999611f039fSJulien Grall acpi_data.single_redist = true; 2000926b5dfaSMarc Zyngier count = acpi_data.enabled_rdists; 2001926b5dfaSMarc Zyngier } 2002b70fb7afSTomasz Nowicki 2003b70fb7afSTomasz Nowicki return count; 2004b70fb7afSTomasz Nowicki } 2005b70fb7afSTomasz Nowicki 2006ffa7d616STomasz Nowicki static bool __init acpi_validate_gic_table(struct acpi_subtable_header *header, 2007ffa7d616STomasz Nowicki struct acpi_probe_entry *ape) 2008ffa7d616STomasz Nowicki { 2009ffa7d616STomasz Nowicki struct acpi_madt_generic_distributor *dist; 2010ffa7d616STomasz Nowicki int count; 2011ffa7d616STomasz Nowicki 2012ffa7d616STomasz Nowicki dist = (struct acpi_madt_generic_distributor *)header; 2013ffa7d616STomasz Nowicki if (dist->version != ape->driver_data) 2014ffa7d616STomasz Nowicki return false; 2015ffa7d616STomasz Nowicki 2016ffa7d616STomasz Nowicki /* We need to do that exercise anyway, the sooner the better */ 2017b70fb7afSTomasz Nowicki count = gic_acpi_count_gicr_regions(); 2018ffa7d616STomasz Nowicki if (count <= 0) 2019ffa7d616STomasz Nowicki return false; 2020ffa7d616STomasz Nowicki 2021611f039fSJulien Grall acpi_data.nr_redist_regions = count; 2022ffa7d616STomasz Nowicki return true; 2023ffa7d616STomasz Nowicki } 2024ffa7d616STomasz Nowicki 202560574d1eSKeith Busch static int __init gic_acpi_parse_virt_madt_gicc(union acpi_subtable_headers *header, 20261839e576SJulien Grall const unsigned long end) 20271839e576SJulien Grall { 20281839e576SJulien Grall struct acpi_madt_generic_interrupt *gicc = 20291839e576SJulien Grall (struct acpi_madt_generic_interrupt *)header; 20301839e576SJulien Grall int maint_irq_mode; 20311839e576SJulien Grall static int first_madt = true; 20321839e576SJulien Grall 20331839e576SJulien Grall /* Skip unusable CPUs */ 20341839e576SJulien Grall if (!(gicc->flags & ACPI_MADT_ENABLED)) 20351839e576SJulien Grall return 0; 20361839e576SJulien Grall 20371839e576SJulien Grall maint_irq_mode = (gicc->flags & ACPI_MADT_VGIC_IRQ_MODE) ? 20381839e576SJulien Grall ACPI_EDGE_SENSITIVE : ACPI_LEVEL_SENSITIVE; 20391839e576SJulien Grall 20401839e576SJulien Grall if (first_madt) { 20411839e576SJulien Grall first_madt = false; 20421839e576SJulien Grall 20431839e576SJulien Grall acpi_data.maint_irq = gicc->vgic_interrupt; 20441839e576SJulien Grall acpi_data.maint_irq_mode = maint_irq_mode; 20451839e576SJulien Grall acpi_data.vcpu_base = gicc->gicv_base_address; 20461839e576SJulien Grall 20471839e576SJulien Grall return 0; 20481839e576SJulien Grall } 20491839e576SJulien Grall 20501839e576SJulien Grall /* 20511839e576SJulien Grall * The maintenance interrupt and GICV should be the same for every CPU 20521839e576SJulien Grall */ 20531839e576SJulien Grall if ((acpi_data.maint_irq != gicc->vgic_interrupt) || 20541839e576SJulien Grall (acpi_data.maint_irq_mode != maint_irq_mode) || 20551839e576SJulien Grall (acpi_data.vcpu_base != gicc->gicv_base_address)) 20561839e576SJulien Grall return -EINVAL; 20571839e576SJulien Grall 20581839e576SJulien Grall return 0; 20591839e576SJulien Grall } 20601839e576SJulien Grall 20611839e576SJulien Grall static bool __init gic_acpi_collect_virt_info(void) 20621839e576SJulien Grall { 20631839e576SJulien Grall int count; 20641839e576SJulien Grall 20651839e576SJulien Grall count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT, 20661839e576SJulien Grall gic_acpi_parse_virt_madt_gicc, 0); 20671839e576SJulien Grall 20681839e576SJulien Grall return (count > 0); 20691839e576SJulien Grall } 20701839e576SJulien Grall 2071ffa7d616STomasz Nowicki #define ACPI_GICV3_DIST_MEM_SIZE (SZ_64K) 20721839e576SJulien Grall #define ACPI_GICV2_VCTRL_MEM_SIZE (SZ_4K) 20731839e576SJulien Grall #define ACPI_GICV2_VCPU_MEM_SIZE (SZ_8K) 20741839e576SJulien Grall 20751839e576SJulien Grall static void __init gic_acpi_setup_kvm_info(void) 20761839e576SJulien Grall { 20771839e576SJulien Grall int irq; 20781839e576SJulien Grall 20791839e576SJulien Grall if (!gic_acpi_collect_virt_info()) { 20801839e576SJulien Grall pr_warn("Unable to get hardware information used for virtualization\n"); 20811839e576SJulien Grall return; 20821839e576SJulien Grall } 20831839e576SJulien Grall 20841839e576SJulien Grall gic_v3_kvm_info.type = GIC_V3; 20851839e576SJulien Grall 20861839e576SJulien Grall irq = acpi_register_gsi(NULL, acpi_data.maint_irq, 20871839e576SJulien Grall acpi_data.maint_irq_mode, 20881839e576SJulien Grall ACPI_ACTIVE_HIGH); 20891839e576SJulien Grall if (irq <= 0) 20901839e576SJulien Grall return; 20911839e576SJulien Grall 20921839e576SJulien Grall gic_v3_kvm_info.maint_irq = irq; 20931839e576SJulien Grall 20941839e576SJulien Grall if (acpi_data.vcpu_base) { 20951839e576SJulien Grall struct resource *vcpu = &gic_v3_kvm_info.vcpu; 20961839e576SJulien Grall 20971839e576SJulien Grall vcpu->flags = IORESOURCE_MEM; 20981839e576SJulien Grall vcpu->start = acpi_data.vcpu_base; 20991839e576SJulien Grall vcpu->end = vcpu->start + ACPI_GICV2_VCPU_MEM_SIZE - 1; 21001839e576SJulien Grall } 21011839e576SJulien Grall 21024bdf5025SMarc Zyngier gic_v3_kvm_info.has_v4 = gic_data.rdists.has_vlpis; 21031839e576SJulien Grall gic_set_kvm_info(&gic_v3_kvm_info); 21041839e576SJulien Grall } 2105ffa7d616STomasz Nowicki 2106ffa7d616STomasz Nowicki static int __init 2107ffa7d616STomasz Nowicki gic_acpi_init(struct acpi_subtable_header *header, const unsigned long end) 2108ffa7d616STomasz Nowicki { 2109ffa7d616STomasz Nowicki struct acpi_madt_generic_distributor *dist; 2110ffa7d616STomasz Nowicki struct fwnode_handle *domain_handle; 2111611f039fSJulien Grall size_t size; 2112b70fb7afSTomasz Nowicki int i, err; 2113ffa7d616STomasz Nowicki 2114ffa7d616STomasz Nowicki /* Get distributor base address */ 2115ffa7d616STomasz Nowicki dist = (struct acpi_madt_generic_distributor *)header; 2116611f039fSJulien Grall acpi_data.dist_base = ioremap(dist->base_address, 2117611f039fSJulien Grall ACPI_GICV3_DIST_MEM_SIZE); 2118611f039fSJulien Grall if (!acpi_data.dist_base) { 2119ffa7d616STomasz Nowicki pr_err("Unable to map GICD registers\n"); 2120ffa7d616STomasz Nowicki return -ENOMEM; 2121ffa7d616STomasz Nowicki } 2122ffa7d616STomasz Nowicki 2123611f039fSJulien Grall err = gic_validate_dist_version(acpi_data.dist_base); 2124ffa7d616STomasz Nowicki if (err) { 212571192a68SArvind Yadav pr_err("No distributor detected at @%p, giving up\n", 2126611f039fSJulien Grall acpi_data.dist_base); 2127ffa7d616STomasz Nowicki goto out_dist_unmap; 2128ffa7d616STomasz Nowicki } 2129ffa7d616STomasz Nowicki 2130611f039fSJulien Grall size = sizeof(*acpi_data.redist_regs) * acpi_data.nr_redist_regions; 2131611f039fSJulien Grall acpi_data.redist_regs = kzalloc(size, GFP_KERNEL); 2132611f039fSJulien Grall if (!acpi_data.redist_regs) { 2133ffa7d616STomasz Nowicki err = -ENOMEM; 2134ffa7d616STomasz Nowicki goto out_dist_unmap; 2135ffa7d616STomasz Nowicki } 2136ffa7d616STomasz Nowicki 2137b70fb7afSTomasz Nowicki err = gic_acpi_collect_gicr_base(); 2138b70fb7afSTomasz Nowicki if (err) 2139ffa7d616STomasz Nowicki goto out_redist_unmap; 2140ffa7d616STomasz Nowicki 2141eeee0d09SMarc Zyngier domain_handle = irq_domain_alloc_fwnode(&dist->base_address); 2142ffa7d616STomasz Nowicki if (!domain_handle) { 2143ffa7d616STomasz Nowicki err = -ENOMEM; 2144ffa7d616STomasz Nowicki goto out_redist_unmap; 2145ffa7d616STomasz Nowicki } 2146ffa7d616STomasz Nowicki 2147611f039fSJulien Grall err = gic_init_bases(acpi_data.dist_base, acpi_data.redist_regs, 2148611f039fSJulien Grall acpi_data.nr_redist_regions, 0, domain_handle); 2149ffa7d616STomasz Nowicki if (err) 2150ffa7d616STomasz Nowicki goto out_fwhandle_free; 2151ffa7d616STomasz Nowicki 2152ffa7d616STomasz Nowicki acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, domain_handle); 2153d33a3c8cSChristoffer Dall 2154d01d3274SDavidlohr Bueso if (static_branch_likely(&supports_deactivate_key)) 21551839e576SJulien Grall gic_acpi_setup_kvm_info(); 21561839e576SJulien Grall 2157ffa7d616STomasz Nowicki return 0; 2158ffa7d616STomasz Nowicki 2159ffa7d616STomasz Nowicki out_fwhandle_free: 2160ffa7d616STomasz Nowicki irq_domain_free_fwnode(domain_handle); 2161ffa7d616STomasz Nowicki out_redist_unmap: 2162611f039fSJulien Grall for (i = 0; i < acpi_data.nr_redist_regions; i++) 2163611f039fSJulien Grall if (acpi_data.redist_regs[i].redist_base) 2164611f039fSJulien Grall iounmap(acpi_data.redist_regs[i].redist_base); 2165611f039fSJulien Grall kfree(acpi_data.redist_regs); 2166ffa7d616STomasz Nowicki out_dist_unmap: 2167611f039fSJulien Grall iounmap(acpi_data.dist_base); 2168ffa7d616STomasz Nowicki return err; 2169ffa7d616STomasz Nowicki } 2170ffa7d616STomasz Nowicki IRQCHIP_ACPI_DECLARE(gic_v3, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 2171ffa7d616STomasz Nowicki acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V3, 2172ffa7d616STomasz Nowicki gic_acpi_init); 2173ffa7d616STomasz Nowicki IRQCHIP_ACPI_DECLARE(gic_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 2174ffa7d616STomasz Nowicki acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V4, 2175ffa7d616STomasz Nowicki gic_acpi_init); 2176ffa7d616STomasz Nowicki IRQCHIP_ACPI_DECLARE(gic_v3_or_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 2177ffa7d616STomasz Nowicki acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_NONE, 2178ffa7d616STomasz Nowicki gic_acpi_init); 2179ffa7d616STomasz Nowicki #endif 2180