1caab277bSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 2021f6537SMarc Zyngier /* 30edc23eaSMarc Zyngier * Copyright (C) 2013-2017 ARM Limited, All Rights Reserved. 4021f6537SMarc Zyngier * Author: Marc Zyngier <marc.zyngier@arm.com> 5021f6537SMarc Zyngier */ 6021f6537SMarc Zyngier 768628bb8SJulien Grall #define pr_fmt(fmt) "GICv3: " fmt 868628bb8SJulien Grall 9ffa7d616STomasz Nowicki #include <linux/acpi.h> 10021f6537SMarc Zyngier #include <linux/cpu.h> 113708d52fSSudeep Holla #include <linux/cpu_pm.h> 12021f6537SMarc Zyngier #include <linux/delay.h> 13021f6537SMarc Zyngier #include <linux/interrupt.h> 14ffa7d616STomasz Nowicki #include <linux/irqdomain.h> 15021f6537SMarc Zyngier #include <linux/of.h> 16021f6537SMarc Zyngier #include <linux/of_address.h> 17021f6537SMarc Zyngier #include <linux/of_irq.h> 18021f6537SMarc Zyngier #include <linux/percpu.h> 19101b35f7SJulien Thierry #include <linux/refcount.h> 20021f6537SMarc Zyngier #include <linux/slab.h> 21021f6537SMarc Zyngier 2241a83e06SJoel Porquet #include <linux/irqchip.h> 231839e576SJulien Grall #include <linux/irqchip/arm-gic-common.h> 24021f6537SMarc Zyngier #include <linux/irqchip/arm-gic-v3.h> 25e3825ba1SMarc Zyngier #include <linux/irqchip/irq-partition-percpu.h> 26021f6537SMarc Zyngier 27021f6537SMarc Zyngier #include <asm/cputype.h> 28021f6537SMarc Zyngier #include <asm/exception.h> 29021f6537SMarc Zyngier #include <asm/smp_plat.h> 300b6a3da9SMarc Zyngier #include <asm/virt.h> 31021f6537SMarc Zyngier 32021f6537SMarc Zyngier #include "irq-gic-common.h" 33021f6537SMarc Zyngier 34f32c9266SJulien Thierry #define GICD_INT_NMI_PRI (GICD_INT_DEF_PRI & ~0x80) 35f32c9266SJulien Thierry 369c8114c2SSrinivas Kandagatla #define FLAGS_WORKAROUND_GICR_WAKER_MSM8996 (1ULL << 0) 379c8114c2SSrinivas Kandagatla 38f5c1434cSMarc Zyngier struct redist_region { 39f5c1434cSMarc Zyngier void __iomem *redist_base; 40f5c1434cSMarc Zyngier phys_addr_t phys_base; 41b70fb7afSTomasz Nowicki bool single_redist; 42f5c1434cSMarc Zyngier }; 43f5c1434cSMarc Zyngier 44021f6537SMarc Zyngier struct gic_chip_data { 45e3825ba1SMarc Zyngier struct fwnode_handle *fwnode; 46021f6537SMarc Zyngier void __iomem *dist_base; 47f5c1434cSMarc Zyngier struct redist_region *redist_regions; 48f5c1434cSMarc Zyngier struct rdists rdists; 49021f6537SMarc Zyngier struct irq_domain *domain; 50021f6537SMarc Zyngier u64 redist_stride; 51f5c1434cSMarc Zyngier u32 nr_redist_regions; 529c8114c2SSrinivas Kandagatla u64 flags; 53eda0d04aSShanker Donthineni bool has_rss; 54021f6537SMarc Zyngier unsigned int irq_nr; 55e3825ba1SMarc Zyngier struct partition_desc *ppi_descs[16]; 56021f6537SMarc Zyngier }; 57021f6537SMarc Zyngier 58021f6537SMarc Zyngier static struct gic_chip_data gic_data __read_mostly; 59d01d3274SDavidlohr Bueso static DEFINE_STATIC_KEY_TRUE(supports_deactivate_key); 60021f6537SMarc Zyngier 61d98d0a99SJulien Thierry /* 62d98d0a99SJulien Thierry * The behaviours of RPR and PMR registers differ depending on the value of 63d98d0a99SJulien Thierry * SCR_EL3.FIQ, and the behaviour of non-secure priority registers of the 64d98d0a99SJulien Thierry * distributor and redistributors depends on whether security is enabled in the 65d98d0a99SJulien Thierry * GIC. 66d98d0a99SJulien Thierry * 67d98d0a99SJulien Thierry * When security is enabled, non-secure priority values from the (re)distributor 68d98d0a99SJulien Thierry * are presented to the GIC CPUIF as follow: 69d98d0a99SJulien Thierry * (GIC_(R)DIST_PRI[irq] >> 1) | 0x80; 70d98d0a99SJulien Thierry * 71d98d0a99SJulien Thierry * If SCR_EL3.FIQ == 1, the values writen to/read from PMR and RPR at non-secure 72d98d0a99SJulien Thierry * EL1 are subject to a similar operation thus matching the priorities presented 73d98d0a99SJulien Thierry * from the (re)distributor when security is enabled. 74d98d0a99SJulien Thierry * 75d98d0a99SJulien Thierry * see GICv3/GICv4 Architecture Specification (IHI0069D): 76d98d0a99SJulien Thierry * - section 4.8.1 Non-secure accesses to register fields for Secure interrupt 77d98d0a99SJulien Thierry * priorities. 78d98d0a99SJulien Thierry * - Figure 4-7 Secure read of the priority field for a Non-secure Group 1 79d98d0a99SJulien Thierry * interrupt. 80d98d0a99SJulien Thierry * 81d98d0a99SJulien Thierry * For now, we only support pseudo-NMIs if we have non-secure view of 82d98d0a99SJulien Thierry * priorities. 83d98d0a99SJulien Thierry */ 84d98d0a99SJulien Thierry static DEFINE_STATIC_KEY_FALSE(supports_pseudo_nmis); 85d98d0a99SJulien Thierry 86101b35f7SJulien Thierry /* ppi_nmi_refs[n] == number of cpus having ppi[n + 16] set as NMI */ 87101b35f7SJulien Thierry static refcount_t ppi_nmi_refs[16]; 88101b35f7SJulien Thierry 891839e576SJulien Grall static struct gic_kvm_info gic_v3_kvm_info; 90eda0d04aSShanker Donthineni static DEFINE_PER_CPU(bool, has_rss); 911839e576SJulien Grall 92eda0d04aSShanker Donthineni #define MPIDR_RS(mpidr) (((mpidr) & 0xF0UL) >> 4) 93f5c1434cSMarc Zyngier #define gic_data_rdist() (this_cpu_ptr(gic_data.rdists.rdist)) 94f5c1434cSMarc Zyngier #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base) 95021f6537SMarc Zyngier #define gic_data_rdist_sgi_base() (gic_data_rdist_rd_base() + SZ_64K) 96021f6537SMarc Zyngier 97021f6537SMarc Zyngier /* Our default, arbitrary priority value. Linux only uses one anyway. */ 98021f6537SMarc Zyngier #define DEFAULT_PMR_VALUE 0xf0 99021f6537SMarc Zyngier 100021f6537SMarc Zyngier static inline unsigned int gic_irq(struct irq_data *d) 101021f6537SMarc Zyngier { 102021f6537SMarc Zyngier return d->hwirq; 103021f6537SMarc Zyngier } 104021f6537SMarc Zyngier 105021f6537SMarc Zyngier static inline int gic_irq_in_rdist(struct irq_data *d) 106021f6537SMarc Zyngier { 107021f6537SMarc Zyngier return gic_irq(d) < 32; 108021f6537SMarc Zyngier } 109021f6537SMarc Zyngier 110021f6537SMarc Zyngier static inline void __iomem *gic_dist_base(struct irq_data *d) 111021f6537SMarc Zyngier { 112021f6537SMarc Zyngier if (gic_irq_in_rdist(d)) /* SGI+PPI -> SGI_base for this CPU */ 113021f6537SMarc Zyngier return gic_data_rdist_sgi_base(); 114021f6537SMarc Zyngier 115021f6537SMarc Zyngier if (d->hwirq <= 1023) /* SPI -> dist_base */ 116021f6537SMarc Zyngier return gic_data.dist_base; 117021f6537SMarc Zyngier 118021f6537SMarc Zyngier return NULL; 119021f6537SMarc Zyngier } 120021f6537SMarc Zyngier 121021f6537SMarc Zyngier static void gic_do_wait_for_rwp(void __iomem *base) 122021f6537SMarc Zyngier { 123021f6537SMarc Zyngier u32 count = 1000000; /* 1s! */ 124021f6537SMarc Zyngier 125021f6537SMarc Zyngier while (readl_relaxed(base + GICD_CTLR) & GICD_CTLR_RWP) { 126021f6537SMarc Zyngier count--; 127021f6537SMarc Zyngier if (!count) { 128021f6537SMarc Zyngier pr_err_ratelimited("RWP timeout, gone fishing\n"); 129021f6537SMarc Zyngier return; 130021f6537SMarc Zyngier } 131021f6537SMarc Zyngier cpu_relax(); 132021f6537SMarc Zyngier udelay(1); 133021f6537SMarc Zyngier }; 134021f6537SMarc Zyngier } 135021f6537SMarc Zyngier 136021f6537SMarc Zyngier /* Wait for completion of a distributor change */ 137021f6537SMarc Zyngier static void gic_dist_wait_for_rwp(void) 138021f6537SMarc Zyngier { 139021f6537SMarc Zyngier gic_do_wait_for_rwp(gic_data.dist_base); 140021f6537SMarc Zyngier } 141021f6537SMarc Zyngier 142021f6537SMarc Zyngier /* Wait for completion of a redistributor change */ 143021f6537SMarc Zyngier static void gic_redist_wait_for_rwp(void) 144021f6537SMarc Zyngier { 145021f6537SMarc Zyngier gic_do_wait_for_rwp(gic_data_rdist_rd_base()); 146021f6537SMarc Zyngier } 147021f6537SMarc Zyngier 1487936e914SJean-Philippe Brucker #ifdef CONFIG_ARM64 1496d4e11c5SRobert Richter 1506d4e11c5SRobert Richter static u64 __maybe_unused gic_read_iar(void) 1516d4e11c5SRobert Richter { 152a4023f68SSuzuki K Poulose if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_23154)) 1536d4e11c5SRobert Richter return gic_read_iar_cavium_thunderx(); 1546d4e11c5SRobert Richter else 1556d4e11c5SRobert Richter return gic_read_iar_common(); 1566d4e11c5SRobert Richter } 1577936e914SJean-Philippe Brucker #endif 158021f6537SMarc Zyngier 159a2c22510SSudeep Holla static void gic_enable_redist(bool enable) 160021f6537SMarc Zyngier { 161021f6537SMarc Zyngier void __iomem *rbase; 162021f6537SMarc Zyngier u32 count = 1000000; /* 1s! */ 163021f6537SMarc Zyngier u32 val; 164021f6537SMarc Zyngier 1659c8114c2SSrinivas Kandagatla if (gic_data.flags & FLAGS_WORKAROUND_GICR_WAKER_MSM8996) 1669c8114c2SSrinivas Kandagatla return; 1679c8114c2SSrinivas Kandagatla 168021f6537SMarc Zyngier rbase = gic_data_rdist_rd_base(); 169021f6537SMarc Zyngier 170021f6537SMarc Zyngier val = readl_relaxed(rbase + GICR_WAKER); 171a2c22510SSudeep Holla if (enable) 172a2c22510SSudeep Holla /* Wake up this CPU redistributor */ 173021f6537SMarc Zyngier val &= ~GICR_WAKER_ProcessorSleep; 174a2c22510SSudeep Holla else 175a2c22510SSudeep Holla val |= GICR_WAKER_ProcessorSleep; 176021f6537SMarc Zyngier writel_relaxed(val, rbase + GICR_WAKER); 177021f6537SMarc Zyngier 178a2c22510SSudeep Holla if (!enable) { /* Check that GICR_WAKER is writeable */ 179a2c22510SSudeep Holla val = readl_relaxed(rbase + GICR_WAKER); 180a2c22510SSudeep Holla if (!(val & GICR_WAKER_ProcessorSleep)) 181a2c22510SSudeep Holla return; /* No PM support in this redistributor */ 182021f6537SMarc Zyngier } 183a2c22510SSudeep Holla 184d102eb5cSDan Carpenter while (--count) { 185a2c22510SSudeep Holla val = readl_relaxed(rbase + GICR_WAKER); 186cf1d9d11SAndrew Jones if (enable ^ (bool)(val & GICR_WAKER_ChildrenAsleep)) 187a2c22510SSudeep Holla break; 188021f6537SMarc Zyngier cpu_relax(); 189021f6537SMarc Zyngier udelay(1); 190021f6537SMarc Zyngier }; 191a2c22510SSudeep Holla if (!count) 192a2c22510SSudeep Holla pr_err_ratelimited("redistributor failed to %s...\n", 193a2c22510SSudeep Holla enable ? "wakeup" : "sleep"); 194021f6537SMarc Zyngier } 195021f6537SMarc Zyngier 196021f6537SMarc Zyngier /* 197021f6537SMarc Zyngier * Routines to disable, enable, EOI and route interrupts 198021f6537SMarc Zyngier */ 199b594c6e2SMarc Zyngier static int gic_peek_irq(struct irq_data *d, u32 offset) 200b594c6e2SMarc Zyngier { 201b594c6e2SMarc Zyngier u32 mask = 1 << (gic_irq(d) % 32); 202b594c6e2SMarc Zyngier void __iomem *base; 203b594c6e2SMarc Zyngier 204b594c6e2SMarc Zyngier if (gic_irq_in_rdist(d)) 205b594c6e2SMarc Zyngier base = gic_data_rdist_sgi_base(); 206b594c6e2SMarc Zyngier else 207b594c6e2SMarc Zyngier base = gic_data.dist_base; 208b594c6e2SMarc Zyngier 209b594c6e2SMarc Zyngier return !!(readl_relaxed(base + offset + (gic_irq(d) / 32) * 4) & mask); 210b594c6e2SMarc Zyngier } 211b594c6e2SMarc Zyngier 212021f6537SMarc Zyngier static void gic_poke_irq(struct irq_data *d, u32 offset) 213021f6537SMarc Zyngier { 214021f6537SMarc Zyngier u32 mask = 1 << (gic_irq(d) % 32); 215021f6537SMarc Zyngier void (*rwp_wait)(void); 216021f6537SMarc Zyngier void __iomem *base; 217021f6537SMarc Zyngier 218021f6537SMarc Zyngier if (gic_irq_in_rdist(d)) { 219021f6537SMarc Zyngier base = gic_data_rdist_sgi_base(); 220021f6537SMarc Zyngier rwp_wait = gic_redist_wait_for_rwp; 221021f6537SMarc Zyngier } else { 222021f6537SMarc Zyngier base = gic_data.dist_base; 223021f6537SMarc Zyngier rwp_wait = gic_dist_wait_for_rwp; 224021f6537SMarc Zyngier } 225021f6537SMarc Zyngier 226021f6537SMarc Zyngier writel_relaxed(mask, base + offset + (gic_irq(d) / 32) * 4); 227021f6537SMarc Zyngier rwp_wait(); 228021f6537SMarc Zyngier } 229021f6537SMarc Zyngier 230021f6537SMarc Zyngier static void gic_mask_irq(struct irq_data *d) 231021f6537SMarc Zyngier { 232021f6537SMarc Zyngier gic_poke_irq(d, GICD_ICENABLER); 233021f6537SMarc Zyngier } 234021f6537SMarc Zyngier 2350b6a3da9SMarc Zyngier static void gic_eoimode1_mask_irq(struct irq_data *d) 2360b6a3da9SMarc Zyngier { 2370b6a3da9SMarc Zyngier gic_mask_irq(d); 238530bf353SMarc Zyngier /* 239530bf353SMarc Zyngier * When masking a forwarded interrupt, make sure it is 240530bf353SMarc Zyngier * deactivated as well. 241530bf353SMarc Zyngier * 242530bf353SMarc Zyngier * This ensures that an interrupt that is getting 243530bf353SMarc Zyngier * disabled/masked will not get "stuck", because there is 244530bf353SMarc Zyngier * noone to deactivate it (guest is being terminated). 245530bf353SMarc Zyngier */ 2464df7f54dSThomas Gleixner if (irqd_is_forwarded_to_vcpu(d)) 247530bf353SMarc Zyngier gic_poke_irq(d, GICD_ICACTIVER); 2480b6a3da9SMarc Zyngier } 2490b6a3da9SMarc Zyngier 250021f6537SMarc Zyngier static void gic_unmask_irq(struct irq_data *d) 251021f6537SMarc Zyngier { 252021f6537SMarc Zyngier gic_poke_irq(d, GICD_ISENABLER); 253021f6537SMarc Zyngier } 254021f6537SMarc Zyngier 255d98d0a99SJulien Thierry static inline bool gic_supports_nmi(void) 256d98d0a99SJulien Thierry { 257d98d0a99SJulien Thierry return IS_ENABLED(CONFIG_ARM64_PSEUDO_NMI) && 258d98d0a99SJulien Thierry static_branch_likely(&supports_pseudo_nmis); 259d98d0a99SJulien Thierry } 260d98d0a99SJulien Thierry 261b594c6e2SMarc Zyngier static int gic_irq_set_irqchip_state(struct irq_data *d, 262b594c6e2SMarc Zyngier enum irqchip_irq_state which, bool val) 263b594c6e2SMarc Zyngier { 264b594c6e2SMarc Zyngier u32 reg; 265b594c6e2SMarc Zyngier 266b594c6e2SMarc Zyngier if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */ 267b594c6e2SMarc Zyngier return -EINVAL; 268b594c6e2SMarc Zyngier 269b594c6e2SMarc Zyngier switch (which) { 270b594c6e2SMarc Zyngier case IRQCHIP_STATE_PENDING: 271b594c6e2SMarc Zyngier reg = val ? GICD_ISPENDR : GICD_ICPENDR; 272b594c6e2SMarc Zyngier break; 273b594c6e2SMarc Zyngier 274b594c6e2SMarc Zyngier case IRQCHIP_STATE_ACTIVE: 275b594c6e2SMarc Zyngier reg = val ? GICD_ISACTIVER : GICD_ICACTIVER; 276b594c6e2SMarc Zyngier break; 277b594c6e2SMarc Zyngier 278b594c6e2SMarc Zyngier case IRQCHIP_STATE_MASKED: 279b594c6e2SMarc Zyngier reg = val ? GICD_ICENABLER : GICD_ISENABLER; 280b594c6e2SMarc Zyngier break; 281b594c6e2SMarc Zyngier 282b594c6e2SMarc Zyngier default: 283b594c6e2SMarc Zyngier return -EINVAL; 284b594c6e2SMarc Zyngier } 285b594c6e2SMarc Zyngier 286b594c6e2SMarc Zyngier gic_poke_irq(d, reg); 287b594c6e2SMarc Zyngier return 0; 288b594c6e2SMarc Zyngier } 289b594c6e2SMarc Zyngier 290b594c6e2SMarc Zyngier static int gic_irq_get_irqchip_state(struct irq_data *d, 291b594c6e2SMarc Zyngier enum irqchip_irq_state which, bool *val) 292b594c6e2SMarc Zyngier { 293b594c6e2SMarc Zyngier if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */ 294b594c6e2SMarc Zyngier return -EINVAL; 295b594c6e2SMarc Zyngier 296b594c6e2SMarc Zyngier switch (which) { 297b594c6e2SMarc Zyngier case IRQCHIP_STATE_PENDING: 298b594c6e2SMarc Zyngier *val = gic_peek_irq(d, GICD_ISPENDR); 299b594c6e2SMarc Zyngier break; 300b594c6e2SMarc Zyngier 301b594c6e2SMarc Zyngier case IRQCHIP_STATE_ACTIVE: 302b594c6e2SMarc Zyngier *val = gic_peek_irq(d, GICD_ISACTIVER); 303b594c6e2SMarc Zyngier break; 304b594c6e2SMarc Zyngier 305b594c6e2SMarc Zyngier case IRQCHIP_STATE_MASKED: 306b594c6e2SMarc Zyngier *val = !gic_peek_irq(d, GICD_ISENABLER); 307b594c6e2SMarc Zyngier break; 308b594c6e2SMarc Zyngier 309b594c6e2SMarc Zyngier default: 310b594c6e2SMarc Zyngier return -EINVAL; 311b594c6e2SMarc Zyngier } 312b594c6e2SMarc Zyngier 313b594c6e2SMarc Zyngier return 0; 314b594c6e2SMarc Zyngier } 315b594c6e2SMarc Zyngier 316101b35f7SJulien Thierry static void gic_irq_set_prio(struct irq_data *d, u8 prio) 317101b35f7SJulien Thierry { 318101b35f7SJulien Thierry void __iomem *base = gic_dist_base(d); 319101b35f7SJulien Thierry 320101b35f7SJulien Thierry writeb_relaxed(prio, base + GICD_IPRIORITYR + gic_irq(d)); 321101b35f7SJulien Thierry } 322101b35f7SJulien Thierry 323101b35f7SJulien Thierry static int gic_irq_nmi_setup(struct irq_data *d) 324101b35f7SJulien Thierry { 325101b35f7SJulien Thierry struct irq_desc *desc = irq_to_desc(d->irq); 326101b35f7SJulien Thierry 327101b35f7SJulien Thierry if (!gic_supports_nmi()) 328101b35f7SJulien Thierry return -EINVAL; 329101b35f7SJulien Thierry 330101b35f7SJulien Thierry if (gic_peek_irq(d, GICD_ISENABLER)) { 331101b35f7SJulien Thierry pr_err("Cannot set NMI property of enabled IRQ %u\n", d->irq); 332101b35f7SJulien Thierry return -EINVAL; 333101b35f7SJulien Thierry } 334101b35f7SJulien Thierry 335101b35f7SJulien Thierry /* 336101b35f7SJulien Thierry * A secondary irq_chip should be in charge of LPI request, 337101b35f7SJulien Thierry * it should not be possible to get there 338101b35f7SJulien Thierry */ 339101b35f7SJulien Thierry if (WARN_ON(gic_irq(d) >= 8192)) 340101b35f7SJulien Thierry return -EINVAL; 341101b35f7SJulien Thierry 342101b35f7SJulien Thierry /* desc lock should already be held */ 343101b35f7SJulien Thierry if (gic_irq(d) < 32) { 344101b35f7SJulien Thierry /* Setting up PPI as NMI, only switch handler for first NMI */ 345101b35f7SJulien Thierry if (!refcount_inc_not_zero(&ppi_nmi_refs[gic_irq(d) - 16])) { 346101b35f7SJulien Thierry refcount_set(&ppi_nmi_refs[gic_irq(d) - 16], 1); 347101b35f7SJulien Thierry desc->handle_irq = handle_percpu_devid_fasteoi_nmi; 348101b35f7SJulien Thierry } 349101b35f7SJulien Thierry } else { 350101b35f7SJulien Thierry desc->handle_irq = handle_fasteoi_nmi; 351101b35f7SJulien Thierry } 352101b35f7SJulien Thierry 353101b35f7SJulien Thierry gic_irq_set_prio(d, GICD_INT_NMI_PRI); 354101b35f7SJulien Thierry 355101b35f7SJulien Thierry return 0; 356101b35f7SJulien Thierry } 357101b35f7SJulien Thierry 358101b35f7SJulien Thierry static void gic_irq_nmi_teardown(struct irq_data *d) 359101b35f7SJulien Thierry { 360101b35f7SJulien Thierry struct irq_desc *desc = irq_to_desc(d->irq); 361101b35f7SJulien Thierry 362101b35f7SJulien Thierry if (WARN_ON(!gic_supports_nmi())) 363101b35f7SJulien Thierry return; 364101b35f7SJulien Thierry 365101b35f7SJulien Thierry if (gic_peek_irq(d, GICD_ISENABLER)) { 366101b35f7SJulien Thierry pr_err("Cannot set NMI property of enabled IRQ %u\n", d->irq); 367101b35f7SJulien Thierry return; 368101b35f7SJulien Thierry } 369101b35f7SJulien Thierry 370101b35f7SJulien Thierry /* 371101b35f7SJulien Thierry * A secondary irq_chip should be in charge of LPI request, 372101b35f7SJulien Thierry * it should not be possible to get there 373101b35f7SJulien Thierry */ 374101b35f7SJulien Thierry if (WARN_ON(gic_irq(d) >= 8192)) 375101b35f7SJulien Thierry return; 376101b35f7SJulien Thierry 377101b35f7SJulien Thierry /* desc lock should already be held */ 378101b35f7SJulien Thierry if (gic_irq(d) < 32) { 379101b35f7SJulien Thierry /* Tearing down NMI, only switch handler for last NMI */ 380101b35f7SJulien Thierry if (refcount_dec_and_test(&ppi_nmi_refs[gic_irq(d) - 16])) 381101b35f7SJulien Thierry desc->handle_irq = handle_percpu_devid_irq; 382101b35f7SJulien Thierry } else { 383101b35f7SJulien Thierry desc->handle_irq = handle_fasteoi_irq; 384101b35f7SJulien Thierry } 385101b35f7SJulien Thierry 386101b35f7SJulien Thierry gic_irq_set_prio(d, GICD_INT_DEF_PRI); 387101b35f7SJulien Thierry } 388101b35f7SJulien Thierry 389021f6537SMarc Zyngier static void gic_eoi_irq(struct irq_data *d) 390021f6537SMarc Zyngier { 391021f6537SMarc Zyngier gic_write_eoir(gic_irq(d)); 392021f6537SMarc Zyngier } 393021f6537SMarc Zyngier 3940b6a3da9SMarc Zyngier static void gic_eoimode1_eoi_irq(struct irq_data *d) 3950b6a3da9SMarc Zyngier { 3960b6a3da9SMarc Zyngier /* 397530bf353SMarc Zyngier * No need to deactivate an LPI, or an interrupt that 398530bf353SMarc Zyngier * is is getting forwarded to a vcpu. 3990b6a3da9SMarc Zyngier */ 4004df7f54dSThomas Gleixner if (gic_irq(d) >= 8192 || irqd_is_forwarded_to_vcpu(d)) 4010b6a3da9SMarc Zyngier return; 4020b6a3da9SMarc Zyngier gic_write_dir(gic_irq(d)); 4030b6a3da9SMarc Zyngier } 4040b6a3da9SMarc Zyngier 405021f6537SMarc Zyngier static int gic_set_type(struct irq_data *d, unsigned int type) 406021f6537SMarc Zyngier { 407021f6537SMarc Zyngier unsigned int irq = gic_irq(d); 408021f6537SMarc Zyngier void (*rwp_wait)(void); 409021f6537SMarc Zyngier void __iomem *base; 410021f6537SMarc Zyngier 411021f6537SMarc Zyngier /* Interrupt configuration for SGIs can't be changed */ 412021f6537SMarc Zyngier if (irq < 16) 413021f6537SMarc Zyngier return -EINVAL; 414021f6537SMarc Zyngier 415fb7e7debSLiviu Dudau /* SPIs have restrictions on the supported types */ 416fb7e7debSLiviu Dudau if (irq >= 32 && type != IRQ_TYPE_LEVEL_HIGH && 417fb7e7debSLiviu Dudau type != IRQ_TYPE_EDGE_RISING) 418021f6537SMarc Zyngier return -EINVAL; 419021f6537SMarc Zyngier 420021f6537SMarc Zyngier if (gic_irq_in_rdist(d)) { 421021f6537SMarc Zyngier base = gic_data_rdist_sgi_base(); 422021f6537SMarc Zyngier rwp_wait = gic_redist_wait_for_rwp; 423021f6537SMarc Zyngier } else { 424021f6537SMarc Zyngier base = gic_data.dist_base; 425021f6537SMarc Zyngier rwp_wait = gic_dist_wait_for_rwp; 426021f6537SMarc Zyngier } 427021f6537SMarc Zyngier 428fb7e7debSLiviu Dudau return gic_configure_irq(irq, type, base, rwp_wait); 429021f6537SMarc Zyngier } 430021f6537SMarc Zyngier 431530bf353SMarc Zyngier static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu) 432530bf353SMarc Zyngier { 4334df7f54dSThomas Gleixner if (vcpu) 4344df7f54dSThomas Gleixner irqd_set_forwarded_to_vcpu(d); 4354df7f54dSThomas Gleixner else 4364df7f54dSThomas Gleixner irqd_clr_forwarded_to_vcpu(d); 437530bf353SMarc Zyngier return 0; 438530bf353SMarc Zyngier } 439530bf353SMarc Zyngier 440f6c86a41SJean-Philippe Brucker static u64 gic_mpidr_to_affinity(unsigned long mpidr) 441021f6537SMarc Zyngier { 442021f6537SMarc Zyngier u64 aff; 443021f6537SMarc Zyngier 444f6c86a41SJean-Philippe Brucker aff = ((u64)MPIDR_AFFINITY_LEVEL(mpidr, 3) << 32 | 445021f6537SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 | 446021f6537SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | 447021f6537SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 0)); 448021f6537SMarc Zyngier 449021f6537SMarc Zyngier return aff; 450021f6537SMarc Zyngier } 451021f6537SMarc Zyngier 452f32c9266SJulien Thierry static void gic_deactivate_unhandled(u32 irqnr) 453f32c9266SJulien Thierry { 454f32c9266SJulien Thierry if (static_branch_likely(&supports_deactivate_key)) { 455f32c9266SJulien Thierry if (irqnr < 8192) 456f32c9266SJulien Thierry gic_write_dir(irqnr); 457f32c9266SJulien Thierry } else { 458f32c9266SJulien Thierry gic_write_eoir(irqnr); 459f32c9266SJulien Thierry } 460f32c9266SJulien Thierry } 461f32c9266SJulien Thierry 462f32c9266SJulien Thierry static inline void gic_handle_nmi(u32 irqnr, struct pt_regs *regs) 463f32c9266SJulien Thierry { 464f32c9266SJulien Thierry int err; 465f32c9266SJulien Thierry 466f32c9266SJulien Thierry if (static_branch_likely(&supports_deactivate_key)) 467f32c9266SJulien Thierry gic_write_eoir(irqnr); 468f32c9266SJulien Thierry /* 469f32c9266SJulien Thierry * Leave the PSR.I bit set to prevent other NMIs to be 470f32c9266SJulien Thierry * received while handling this one. 471f32c9266SJulien Thierry * PSR.I will be restored when we ERET to the 472f32c9266SJulien Thierry * interrupted context. 473f32c9266SJulien Thierry */ 474f32c9266SJulien Thierry err = handle_domain_nmi(gic_data.domain, irqnr, regs); 475f32c9266SJulien Thierry if (err) 476f32c9266SJulien Thierry gic_deactivate_unhandled(irqnr); 477f32c9266SJulien Thierry } 478f32c9266SJulien Thierry 479021f6537SMarc Zyngier static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) 480021f6537SMarc Zyngier { 481f6c86a41SJean-Philippe Brucker u32 irqnr; 482021f6537SMarc Zyngier 483021f6537SMarc Zyngier irqnr = gic_read_iar(); 484021f6537SMarc Zyngier 485f32c9266SJulien Thierry if (gic_supports_nmi() && 486f32c9266SJulien Thierry unlikely(gic_read_rpr() == GICD_INT_NMI_PRI)) { 487f32c9266SJulien Thierry gic_handle_nmi(irqnr, regs); 488f32c9266SJulien Thierry return; 489f32c9266SJulien Thierry } 490f32c9266SJulien Thierry 4913f1f3234SJulien Thierry if (gic_prio_masking_enabled()) { 4923f1f3234SJulien Thierry gic_pmr_mask_irqs(); 4933f1f3234SJulien Thierry gic_arch_enable_irqs(); 4943f1f3234SJulien Thierry } 4953f1f3234SJulien Thierry 496da33f31dSMarc Zyngier if (likely(irqnr > 15 && irqnr < 1020) || irqnr >= 8192) { 497ebc6de00SMarc Zyngier int err; 4980b6a3da9SMarc Zyngier 499d01d3274SDavidlohr Bueso if (static_branch_likely(&supports_deactivate_key)) 5000b6a3da9SMarc Zyngier gic_write_eoir(irqnr); 50139a06b67SWill Deacon else 50239a06b67SWill Deacon isb(); 5030b6a3da9SMarc Zyngier 504ebc6de00SMarc Zyngier err = handle_domain_irq(gic_data.domain, irqnr, regs); 505ebc6de00SMarc Zyngier if (err) { 506da33f31dSMarc Zyngier WARN_ONCE(true, "Unexpected interrupt received!\n"); 507f32c9266SJulien Thierry gic_deactivate_unhandled(irqnr); 5080b6a3da9SMarc Zyngier } 509342677d7SJulien Thierry return; 510ebc6de00SMarc Zyngier } 511021f6537SMarc Zyngier if (irqnr < 16) { 512021f6537SMarc Zyngier gic_write_eoir(irqnr); 513d01d3274SDavidlohr Bueso if (static_branch_likely(&supports_deactivate_key)) 5140b6a3da9SMarc Zyngier gic_write_dir(irqnr); 515021f6537SMarc Zyngier #ifdef CONFIG_SMP 516f86c4fbdSWill Deacon /* 517f86c4fbdSWill Deacon * Unlike GICv2, we don't need an smp_rmb() here. 518f86c4fbdSWill Deacon * The control dependency from gic_read_iar to 519f86c4fbdSWill Deacon * the ISB in gic_write_eoir is enough to ensure 520f86c4fbdSWill Deacon * that any shared data read by handle_IPI will 521f86c4fbdSWill Deacon * be read after the ACK. 522f86c4fbdSWill Deacon */ 523021f6537SMarc Zyngier handle_IPI(irqnr, regs); 524021f6537SMarc Zyngier #else 525021f6537SMarc Zyngier WARN_ONCE(true, "Unexpected SGI received!\n"); 526021f6537SMarc Zyngier #endif 527021f6537SMarc Zyngier } 528021f6537SMarc Zyngier } 529021f6537SMarc Zyngier 530b5cf6073SJulien Thierry static u32 gic_get_pribits(void) 531b5cf6073SJulien Thierry { 532b5cf6073SJulien Thierry u32 pribits; 533b5cf6073SJulien Thierry 534b5cf6073SJulien Thierry pribits = gic_read_ctlr(); 535b5cf6073SJulien Thierry pribits &= ICC_CTLR_EL1_PRI_BITS_MASK; 536b5cf6073SJulien Thierry pribits >>= ICC_CTLR_EL1_PRI_BITS_SHIFT; 537b5cf6073SJulien Thierry pribits++; 538b5cf6073SJulien Thierry 539b5cf6073SJulien Thierry return pribits; 540b5cf6073SJulien Thierry } 541b5cf6073SJulien Thierry 542b5cf6073SJulien Thierry static bool gic_has_group0(void) 543b5cf6073SJulien Thierry { 544b5cf6073SJulien Thierry u32 val; 545e7932188SJulien Thierry u32 old_pmr; 546e7932188SJulien Thierry 547e7932188SJulien Thierry old_pmr = gic_read_pmr(); 548b5cf6073SJulien Thierry 549b5cf6073SJulien Thierry /* 550b5cf6073SJulien Thierry * Let's find out if Group0 is under control of EL3 or not by 551b5cf6073SJulien Thierry * setting the highest possible, non-zero priority in PMR. 552b5cf6073SJulien Thierry * 553b5cf6073SJulien Thierry * If SCR_EL3.FIQ is set, the priority gets shifted down in 554b5cf6073SJulien Thierry * order for the CPU interface to set bit 7, and keep the 555b5cf6073SJulien Thierry * actual priority in the non-secure range. In the process, it 556b5cf6073SJulien Thierry * looses the least significant bit and the actual priority 557b5cf6073SJulien Thierry * becomes 0x80. Reading it back returns 0, indicating that 558b5cf6073SJulien Thierry * we're don't have access to Group0. 559b5cf6073SJulien Thierry */ 560b5cf6073SJulien Thierry gic_write_pmr(BIT(8 - gic_get_pribits())); 561b5cf6073SJulien Thierry val = gic_read_pmr(); 562b5cf6073SJulien Thierry 563e7932188SJulien Thierry gic_write_pmr(old_pmr); 564e7932188SJulien Thierry 565b5cf6073SJulien Thierry return val != 0; 566b5cf6073SJulien Thierry } 567b5cf6073SJulien Thierry 568021f6537SMarc Zyngier static void __init gic_dist_init(void) 569021f6537SMarc Zyngier { 570021f6537SMarc Zyngier unsigned int i; 571021f6537SMarc Zyngier u64 affinity; 572021f6537SMarc Zyngier void __iomem *base = gic_data.dist_base; 573021f6537SMarc Zyngier 574021f6537SMarc Zyngier /* Disable the distributor */ 575021f6537SMarc Zyngier writel_relaxed(0, base + GICD_CTLR); 576021f6537SMarc Zyngier gic_dist_wait_for_rwp(); 577021f6537SMarc Zyngier 5787c9b9730SMarc Zyngier /* 5797c9b9730SMarc Zyngier * Configure SPIs as non-secure Group-1. This will only matter 5807c9b9730SMarc Zyngier * if the GIC only has a single security state. This will not 5817c9b9730SMarc Zyngier * do the right thing if the kernel is running in secure mode, 5827c9b9730SMarc Zyngier * but that's not the intended use case anyway. 5837c9b9730SMarc Zyngier */ 5847c9b9730SMarc Zyngier for (i = 32; i < gic_data.irq_nr; i += 32) 5857c9b9730SMarc Zyngier writel_relaxed(~0, base + GICD_IGROUPR + i / 8); 5867c9b9730SMarc Zyngier 587021f6537SMarc Zyngier gic_dist_config(base, gic_data.irq_nr, gic_dist_wait_for_rwp); 588021f6537SMarc Zyngier 589021f6537SMarc Zyngier /* Enable distributor with ARE, Group1 */ 590021f6537SMarc Zyngier writel_relaxed(GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G1A | GICD_CTLR_ENABLE_G1, 591021f6537SMarc Zyngier base + GICD_CTLR); 592021f6537SMarc Zyngier 593021f6537SMarc Zyngier /* 594021f6537SMarc Zyngier * Set all global interrupts to the boot CPU only. ARE must be 595021f6537SMarc Zyngier * enabled. 596021f6537SMarc Zyngier */ 597021f6537SMarc Zyngier affinity = gic_mpidr_to_affinity(cpu_logical_map(smp_processor_id())); 598021f6537SMarc Zyngier for (i = 32; i < gic_data.irq_nr; i++) 59972c97126SJean-Philippe Brucker gic_write_irouter(affinity, base + GICD_IROUTER + i * 8); 600021f6537SMarc Zyngier } 601021f6537SMarc Zyngier 6020d94ded2SMarc Zyngier static int gic_iterate_rdists(int (*fn)(struct redist_region *, void __iomem *)) 603021f6537SMarc Zyngier { 6040d94ded2SMarc Zyngier int ret = -ENODEV; 605021f6537SMarc Zyngier int i; 606021f6537SMarc Zyngier 607f5c1434cSMarc Zyngier for (i = 0; i < gic_data.nr_redist_regions; i++) { 608f5c1434cSMarc Zyngier void __iomem *ptr = gic_data.redist_regions[i].redist_base; 6090d94ded2SMarc Zyngier u64 typer; 610021f6537SMarc Zyngier u32 reg; 611021f6537SMarc Zyngier 612021f6537SMarc Zyngier reg = readl_relaxed(ptr + GICR_PIDR2) & GIC_PIDR2_ARCH_MASK; 613021f6537SMarc Zyngier if (reg != GIC_PIDR2_ARCH_GICv3 && 614021f6537SMarc Zyngier reg != GIC_PIDR2_ARCH_GICv4) { /* We're in trouble... */ 615021f6537SMarc Zyngier pr_warn("No redistributor present @%p\n", ptr); 616021f6537SMarc Zyngier break; 617021f6537SMarc Zyngier } 618021f6537SMarc Zyngier 619021f6537SMarc Zyngier do { 62072c97126SJean-Philippe Brucker typer = gic_read_typer(ptr + GICR_TYPER); 6210d94ded2SMarc Zyngier ret = fn(gic_data.redist_regions + i, ptr); 6220d94ded2SMarc Zyngier if (!ret) 623021f6537SMarc Zyngier return 0; 624021f6537SMarc Zyngier 625b70fb7afSTomasz Nowicki if (gic_data.redist_regions[i].single_redist) 626b70fb7afSTomasz Nowicki break; 627b70fb7afSTomasz Nowicki 628021f6537SMarc Zyngier if (gic_data.redist_stride) { 629021f6537SMarc Zyngier ptr += gic_data.redist_stride; 630021f6537SMarc Zyngier } else { 631021f6537SMarc Zyngier ptr += SZ_64K * 2; /* Skip RD_base + SGI_base */ 632021f6537SMarc Zyngier if (typer & GICR_TYPER_VLPIS) 633021f6537SMarc Zyngier ptr += SZ_64K * 2; /* Skip VLPI_base + reserved page */ 634021f6537SMarc Zyngier } 635021f6537SMarc Zyngier } while (!(typer & GICR_TYPER_LAST)); 636021f6537SMarc Zyngier } 637021f6537SMarc Zyngier 6380d94ded2SMarc Zyngier return ret ? -ENODEV : 0; 6390d94ded2SMarc Zyngier } 6400d94ded2SMarc Zyngier 6410d94ded2SMarc Zyngier static int __gic_populate_rdist(struct redist_region *region, void __iomem *ptr) 6420d94ded2SMarc Zyngier { 6430d94ded2SMarc Zyngier unsigned long mpidr = cpu_logical_map(smp_processor_id()); 6440d94ded2SMarc Zyngier u64 typer; 6450d94ded2SMarc Zyngier u32 aff; 6460d94ded2SMarc Zyngier 6470d94ded2SMarc Zyngier /* 6480d94ded2SMarc Zyngier * Convert affinity to a 32bit value that can be matched to 6490d94ded2SMarc Zyngier * GICR_TYPER bits [63:32]. 6500d94ded2SMarc Zyngier */ 6510d94ded2SMarc Zyngier aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 24 | 6520d94ded2SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 | 6530d94ded2SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | 6540d94ded2SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 0)); 6550d94ded2SMarc Zyngier 6560d94ded2SMarc Zyngier typer = gic_read_typer(ptr + GICR_TYPER); 6570d94ded2SMarc Zyngier if ((typer >> 32) == aff) { 6580d94ded2SMarc Zyngier u64 offset = ptr - region->redist_base; 6590d94ded2SMarc Zyngier gic_data_rdist_rd_base() = ptr; 6600d94ded2SMarc Zyngier gic_data_rdist()->phys_base = region->phys_base + offset; 6610d94ded2SMarc Zyngier 6620d94ded2SMarc Zyngier pr_info("CPU%d: found redistributor %lx region %d:%pa\n", 6630d94ded2SMarc Zyngier smp_processor_id(), mpidr, 6640d94ded2SMarc Zyngier (int)(region - gic_data.redist_regions), 6650d94ded2SMarc Zyngier &gic_data_rdist()->phys_base); 6660d94ded2SMarc Zyngier return 0; 6670d94ded2SMarc Zyngier } 6680d94ded2SMarc Zyngier 6690d94ded2SMarc Zyngier /* Try next one */ 6700d94ded2SMarc Zyngier return 1; 6710d94ded2SMarc Zyngier } 6720d94ded2SMarc Zyngier 6730d94ded2SMarc Zyngier static int gic_populate_rdist(void) 6740d94ded2SMarc Zyngier { 6750d94ded2SMarc Zyngier if (gic_iterate_rdists(__gic_populate_rdist) == 0) 6760d94ded2SMarc Zyngier return 0; 6770d94ded2SMarc Zyngier 678021f6537SMarc Zyngier /* We couldn't even deal with ourselves... */ 679f6c86a41SJean-Philippe Brucker WARN(true, "CPU%d: mpidr %lx has no re-distributor!\n", 6800d94ded2SMarc Zyngier smp_processor_id(), 6810d94ded2SMarc Zyngier (unsigned long)cpu_logical_map(smp_processor_id())); 682021f6537SMarc Zyngier return -ENODEV; 683021f6537SMarc Zyngier } 684021f6537SMarc Zyngier 6850edc23eaSMarc Zyngier static int __gic_update_vlpi_properties(struct redist_region *region, 6860edc23eaSMarc Zyngier void __iomem *ptr) 6870edc23eaSMarc Zyngier { 6880edc23eaSMarc Zyngier u64 typer = gic_read_typer(ptr + GICR_TYPER); 6890edc23eaSMarc Zyngier gic_data.rdists.has_vlpis &= !!(typer & GICR_TYPER_VLPIS); 6900edc23eaSMarc Zyngier gic_data.rdists.has_direct_lpi &= !!(typer & GICR_TYPER_DirectLPIS); 6910edc23eaSMarc Zyngier 6920edc23eaSMarc Zyngier return 1; 6930edc23eaSMarc Zyngier } 6940edc23eaSMarc Zyngier 6950edc23eaSMarc Zyngier static void gic_update_vlpi_properties(void) 6960edc23eaSMarc Zyngier { 6970edc23eaSMarc Zyngier gic_iterate_rdists(__gic_update_vlpi_properties); 6980edc23eaSMarc Zyngier pr_info("%sVLPI support, %sdirect LPI support\n", 6990edc23eaSMarc Zyngier !gic_data.rdists.has_vlpis ? "no " : "", 7000edc23eaSMarc Zyngier !gic_data.rdists.has_direct_lpi ? "no " : ""); 7010edc23eaSMarc Zyngier } 7020edc23eaSMarc Zyngier 703d98d0a99SJulien Thierry /* Check whether it's single security state view */ 704d98d0a99SJulien Thierry static inline bool gic_dist_security_disabled(void) 705d98d0a99SJulien Thierry { 706d98d0a99SJulien Thierry return readl_relaxed(gic_data.dist_base + GICD_CTLR) & GICD_CTLR_DS; 707d98d0a99SJulien Thierry } 708d98d0a99SJulien Thierry 7093708d52fSSudeep Holla static void gic_cpu_sys_reg_init(void) 710021f6537SMarc Zyngier { 711eda0d04aSShanker Donthineni int i, cpu = smp_processor_id(); 712eda0d04aSShanker Donthineni u64 mpidr = cpu_logical_map(cpu); 713eda0d04aSShanker Donthineni u64 need_rss = MPIDR_RS(mpidr); 71433625282SMarc Zyngier bool group0; 715b5cf6073SJulien Thierry u32 pribits; 716eda0d04aSShanker Donthineni 7177cabd008SMarc Zyngier /* 7187cabd008SMarc Zyngier * Need to check that the SRE bit has actually been set. If 7197cabd008SMarc Zyngier * not, it means that SRE is disabled at EL2. We're going to 7207cabd008SMarc Zyngier * die painfully, and there is nothing we can do about it. 7217cabd008SMarc Zyngier * 7227cabd008SMarc Zyngier * Kindly inform the luser. 7237cabd008SMarc Zyngier */ 7247cabd008SMarc Zyngier if (!gic_enable_sre()) 7257cabd008SMarc Zyngier pr_err("GIC: unable to set SRE (disabled at EL2), panic ahead\n"); 726021f6537SMarc Zyngier 727b5cf6073SJulien Thierry pribits = gic_get_pribits(); 72833625282SMarc Zyngier 729b5cf6073SJulien Thierry group0 = gic_has_group0(); 73033625282SMarc Zyngier 731021f6537SMarc Zyngier /* Set priority mask register */ 732d98d0a99SJulien Thierry if (!gic_prio_masking_enabled()) { 73333625282SMarc Zyngier write_gicreg(DEFAULT_PMR_VALUE, ICC_PMR_EL1); 734d98d0a99SJulien Thierry } else { 735d98d0a99SJulien Thierry /* 736d98d0a99SJulien Thierry * Mismatch configuration with boot CPU, the system is likely 737d98d0a99SJulien Thierry * to die as interrupt masking will not work properly on all 738d98d0a99SJulien Thierry * CPUs 739d98d0a99SJulien Thierry */ 740d98d0a99SJulien Thierry WARN_ON(gic_supports_nmi() && group0 && 741d98d0a99SJulien Thierry !gic_dist_security_disabled()); 742d98d0a99SJulien Thierry } 743021f6537SMarc Zyngier 74491ef8442SDaniel Thompson /* 74591ef8442SDaniel Thompson * Some firmwares hand over to the kernel with the BPR changed from 74691ef8442SDaniel Thompson * its reset value (and with a value large enough to prevent 74791ef8442SDaniel Thompson * any pre-emptive interrupts from working at all). Writing a zero 74891ef8442SDaniel Thompson * to BPR restores is reset value. 74991ef8442SDaniel Thompson */ 75091ef8442SDaniel Thompson gic_write_bpr1(0); 75191ef8442SDaniel Thompson 752d01d3274SDavidlohr Bueso if (static_branch_likely(&supports_deactivate_key)) { 7530b6a3da9SMarc Zyngier /* EOI drops priority only (mode 1) */ 7540b6a3da9SMarc Zyngier gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop); 7550b6a3da9SMarc Zyngier } else { 756021f6537SMarc Zyngier /* EOI deactivates interrupt too (mode 0) */ 757021f6537SMarc Zyngier gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop_dir); 7580b6a3da9SMarc Zyngier } 759021f6537SMarc Zyngier 76033625282SMarc Zyngier /* Always whack Group0 before Group1 */ 76133625282SMarc Zyngier if (group0) { 76233625282SMarc Zyngier switch(pribits) { 76333625282SMarc Zyngier case 8: 76433625282SMarc Zyngier case 7: 76533625282SMarc Zyngier write_gicreg(0, ICC_AP0R3_EL1); 76633625282SMarc Zyngier write_gicreg(0, ICC_AP0R2_EL1); 76733625282SMarc Zyngier case 6: 76833625282SMarc Zyngier write_gicreg(0, ICC_AP0R1_EL1); 76933625282SMarc Zyngier case 5: 77033625282SMarc Zyngier case 4: 77133625282SMarc Zyngier write_gicreg(0, ICC_AP0R0_EL1); 77233625282SMarc Zyngier } 773d6062a6dSMarc Zyngier 77433625282SMarc Zyngier isb(); 77533625282SMarc Zyngier } 77633625282SMarc Zyngier 77733625282SMarc Zyngier switch(pribits) { 778d6062a6dSMarc Zyngier case 8: 779d6062a6dSMarc Zyngier case 7: 780d6062a6dSMarc Zyngier write_gicreg(0, ICC_AP1R3_EL1); 781d6062a6dSMarc Zyngier write_gicreg(0, ICC_AP1R2_EL1); 782d6062a6dSMarc Zyngier case 6: 783d6062a6dSMarc Zyngier write_gicreg(0, ICC_AP1R1_EL1); 784d6062a6dSMarc Zyngier case 5: 785d6062a6dSMarc Zyngier case 4: 786d6062a6dSMarc Zyngier write_gicreg(0, ICC_AP1R0_EL1); 787d6062a6dSMarc Zyngier } 788d6062a6dSMarc Zyngier 789d6062a6dSMarc Zyngier isb(); 790d6062a6dSMarc Zyngier 791021f6537SMarc Zyngier /* ... and let's hit the road... */ 792021f6537SMarc Zyngier gic_write_grpen1(1); 793eda0d04aSShanker Donthineni 794eda0d04aSShanker Donthineni /* Keep the RSS capability status in per_cpu variable */ 795eda0d04aSShanker Donthineni per_cpu(has_rss, cpu) = !!(gic_read_ctlr() & ICC_CTLR_EL1_RSS); 796eda0d04aSShanker Donthineni 797eda0d04aSShanker Donthineni /* Check all the CPUs have capable of sending SGIs to other CPUs */ 798eda0d04aSShanker Donthineni for_each_online_cpu(i) { 799eda0d04aSShanker Donthineni bool have_rss = per_cpu(has_rss, i) && per_cpu(has_rss, cpu); 800eda0d04aSShanker Donthineni 801eda0d04aSShanker Donthineni need_rss |= MPIDR_RS(cpu_logical_map(i)); 802eda0d04aSShanker Donthineni if (need_rss && (!have_rss)) 803eda0d04aSShanker Donthineni pr_crit("CPU%d (%lx) can't SGI CPU%d (%lx), no RSS\n", 804eda0d04aSShanker Donthineni cpu, (unsigned long)mpidr, 805eda0d04aSShanker Donthineni i, (unsigned long)cpu_logical_map(i)); 806eda0d04aSShanker Donthineni } 807eda0d04aSShanker Donthineni 808eda0d04aSShanker Donthineni /** 809eda0d04aSShanker Donthineni * GIC spec says, when ICC_CTLR_EL1.RSS==1 and GICD_TYPER.RSS==0, 810eda0d04aSShanker Donthineni * writing ICC_ASGI1R_EL1 register with RS != 0 is a CONSTRAINED 811eda0d04aSShanker Donthineni * UNPREDICTABLE choice of : 812eda0d04aSShanker Donthineni * - The write is ignored. 813eda0d04aSShanker Donthineni * - The RS field is treated as 0. 814eda0d04aSShanker Donthineni */ 815eda0d04aSShanker Donthineni if (need_rss && (!gic_data.has_rss)) 816eda0d04aSShanker Donthineni pr_crit_once("RSS is required but GICD doesn't support it\n"); 817021f6537SMarc Zyngier } 818021f6537SMarc Zyngier 819f736d65dSMarc Zyngier static bool gicv3_nolpi; 820f736d65dSMarc Zyngier 821f736d65dSMarc Zyngier static int __init gicv3_nolpi_cfg(char *buf) 822f736d65dSMarc Zyngier { 823f736d65dSMarc Zyngier return strtobool(buf, &gicv3_nolpi); 824f736d65dSMarc Zyngier } 825f736d65dSMarc Zyngier early_param("irqchip.gicv3_nolpi", gicv3_nolpi_cfg); 826f736d65dSMarc Zyngier 827da33f31dSMarc Zyngier static int gic_dist_supports_lpis(void) 828da33f31dSMarc Zyngier { 829d38a71c5SMarc Zyngier return (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && 830d38a71c5SMarc Zyngier !!(readl_relaxed(gic_data.dist_base + GICD_TYPER) & GICD_TYPER_LPIS) && 831d38a71c5SMarc Zyngier !gicv3_nolpi); 832da33f31dSMarc Zyngier } 833da33f31dSMarc Zyngier 834021f6537SMarc Zyngier static void gic_cpu_init(void) 835021f6537SMarc Zyngier { 836021f6537SMarc Zyngier void __iomem *rbase; 837021f6537SMarc Zyngier 838021f6537SMarc Zyngier /* Register ourselves with the rest of the world */ 839021f6537SMarc Zyngier if (gic_populate_rdist()) 840021f6537SMarc Zyngier return; 841021f6537SMarc Zyngier 842a2c22510SSudeep Holla gic_enable_redist(true); 843021f6537SMarc Zyngier 844021f6537SMarc Zyngier rbase = gic_data_rdist_sgi_base(); 845021f6537SMarc Zyngier 8467c9b9730SMarc Zyngier /* Configure SGIs/PPIs as non-secure Group-1 */ 8477c9b9730SMarc Zyngier writel_relaxed(~0, rbase + GICR_IGROUPR0); 8487c9b9730SMarc Zyngier 849021f6537SMarc Zyngier gic_cpu_config(rbase, gic_redist_wait_for_rwp); 850021f6537SMarc Zyngier 8513708d52fSSudeep Holla /* initialise system registers */ 8523708d52fSSudeep Holla gic_cpu_sys_reg_init(); 853021f6537SMarc Zyngier } 854021f6537SMarc Zyngier 855021f6537SMarc Zyngier #ifdef CONFIG_SMP 856021f6537SMarc Zyngier 857eda0d04aSShanker Donthineni #define MPIDR_TO_SGI_RS(mpidr) (MPIDR_RS(mpidr) << ICC_SGI1R_RS_SHIFT) 858eda0d04aSShanker Donthineni #define MPIDR_TO_SGI_CLUSTER_ID(mpidr) ((mpidr) & ~0xFUL) 859eda0d04aSShanker Donthineni 8606670a6d8SRichard Cochran static int gic_starting_cpu(unsigned int cpu) 8616670a6d8SRichard Cochran { 8626670a6d8SRichard Cochran gic_cpu_init(); 863d38a71c5SMarc Zyngier 864d38a71c5SMarc Zyngier if (gic_dist_supports_lpis()) 865d38a71c5SMarc Zyngier its_cpu_init(); 866d38a71c5SMarc Zyngier 8676670a6d8SRichard Cochran return 0; 8686670a6d8SRichard Cochran } 869021f6537SMarc Zyngier 870021f6537SMarc Zyngier static u16 gic_compute_target_list(int *base_cpu, const struct cpumask *mask, 871f6c86a41SJean-Philippe Brucker unsigned long cluster_id) 872021f6537SMarc Zyngier { 873727653d6SJames Morse int next_cpu, cpu = *base_cpu; 874f6c86a41SJean-Philippe Brucker unsigned long mpidr = cpu_logical_map(cpu); 875021f6537SMarc Zyngier u16 tlist = 0; 876021f6537SMarc Zyngier 877021f6537SMarc Zyngier while (cpu < nr_cpu_ids) { 878021f6537SMarc Zyngier tlist |= 1 << (mpidr & 0xf); 879021f6537SMarc Zyngier 880727653d6SJames Morse next_cpu = cpumask_next(cpu, mask); 881727653d6SJames Morse if (next_cpu >= nr_cpu_ids) 882021f6537SMarc Zyngier goto out; 883727653d6SJames Morse cpu = next_cpu; 884021f6537SMarc Zyngier 885021f6537SMarc Zyngier mpidr = cpu_logical_map(cpu); 886021f6537SMarc Zyngier 887eda0d04aSShanker Donthineni if (cluster_id != MPIDR_TO_SGI_CLUSTER_ID(mpidr)) { 888021f6537SMarc Zyngier cpu--; 889021f6537SMarc Zyngier goto out; 890021f6537SMarc Zyngier } 891021f6537SMarc Zyngier } 892021f6537SMarc Zyngier out: 893021f6537SMarc Zyngier *base_cpu = cpu; 894021f6537SMarc Zyngier return tlist; 895021f6537SMarc Zyngier } 896021f6537SMarc Zyngier 8977e580278SAndre Przywara #define MPIDR_TO_SGI_AFFINITY(cluster_id, level) \ 8987e580278SAndre Przywara (MPIDR_AFFINITY_LEVEL(cluster_id, level) \ 8997e580278SAndre Przywara << ICC_SGI1R_AFFINITY_## level ##_SHIFT) 9007e580278SAndre Przywara 901021f6537SMarc Zyngier static void gic_send_sgi(u64 cluster_id, u16 tlist, unsigned int irq) 902021f6537SMarc Zyngier { 903021f6537SMarc Zyngier u64 val; 904021f6537SMarc Zyngier 9057e580278SAndre Przywara val = (MPIDR_TO_SGI_AFFINITY(cluster_id, 3) | 9067e580278SAndre Przywara MPIDR_TO_SGI_AFFINITY(cluster_id, 2) | 9077e580278SAndre Przywara irq << ICC_SGI1R_SGI_ID_SHIFT | 9087e580278SAndre Przywara MPIDR_TO_SGI_AFFINITY(cluster_id, 1) | 909eda0d04aSShanker Donthineni MPIDR_TO_SGI_RS(cluster_id) | 9107e580278SAndre Przywara tlist << ICC_SGI1R_TARGET_LIST_SHIFT); 911021f6537SMarc Zyngier 912b6dd4d83SMark Salter pr_devel("CPU%d: ICC_SGI1R_EL1 %llx\n", smp_processor_id(), val); 913021f6537SMarc Zyngier gic_write_sgi1r(val); 914021f6537SMarc Zyngier } 915021f6537SMarc Zyngier 916021f6537SMarc Zyngier static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) 917021f6537SMarc Zyngier { 918021f6537SMarc Zyngier int cpu; 919021f6537SMarc Zyngier 920021f6537SMarc Zyngier if (WARN_ON(irq >= 16)) 921021f6537SMarc Zyngier return; 922021f6537SMarc Zyngier 923021f6537SMarc Zyngier /* 924021f6537SMarc Zyngier * Ensure that stores to Normal memory are visible to the 925021f6537SMarc Zyngier * other CPUs before issuing the IPI. 926021f6537SMarc Zyngier */ 92721ec30c0SShanker Donthineni wmb(); 928021f6537SMarc Zyngier 929f9b531feSRusty Russell for_each_cpu(cpu, mask) { 930eda0d04aSShanker Donthineni u64 cluster_id = MPIDR_TO_SGI_CLUSTER_ID(cpu_logical_map(cpu)); 931021f6537SMarc Zyngier u16 tlist; 932021f6537SMarc Zyngier 933021f6537SMarc Zyngier tlist = gic_compute_target_list(&cpu, mask, cluster_id); 934021f6537SMarc Zyngier gic_send_sgi(cluster_id, tlist, irq); 935021f6537SMarc Zyngier } 936021f6537SMarc Zyngier 937021f6537SMarc Zyngier /* Force the above writes to ICC_SGI1R_EL1 to be executed */ 938021f6537SMarc Zyngier isb(); 939021f6537SMarc Zyngier } 940021f6537SMarc Zyngier 941021f6537SMarc Zyngier static void gic_smp_init(void) 942021f6537SMarc Zyngier { 943021f6537SMarc Zyngier set_smp_cross_call(gic_raise_softirq); 9446896bcd1SThomas Gleixner cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_GIC_STARTING, 94573c1b41eSThomas Gleixner "irqchip/arm/gicv3:starting", 94673c1b41eSThomas Gleixner gic_starting_cpu, NULL); 947021f6537SMarc Zyngier } 948021f6537SMarc Zyngier 949021f6537SMarc Zyngier static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, 950021f6537SMarc Zyngier bool force) 951021f6537SMarc Zyngier { 95265a30f8bSSuzuki K Poulose unsigned int cpu; 953021f6537SMarc Zyngier void __iomem *reg; 954021f6537SMarc Zyngier int enabled; 955021f6537SMarc Zyngier u64 val; 956021f6537SMarc Zyngier 95765a30f8bSSuzuki K Poulose if (force) 95865a30f8bSSuzuki K Poulose cpu = cpumask_first(mask_val); 95965a30f8bSSuzuki K Poulose else 96065a30f8bSSuzuki K Poulose cpu = cpumask_any_and(mask_val, cpu_online_mask); 96165a30f8bSSuzuki K Poulose 962866d7c1bSSuzuki K Poulose if (cpu >= nr_cpu_ids) 963866d7c1bSSuzuki K Poulose return -EINVAL; 964866d7c1bSSuzuki K Poulose 965021f6537SMarc Zyngier if (gic_irq_in_rdist(d)) 966021f6537SMarc Zyngier return -EINVAL; 967021f6537SMarc Zyngier 968021f6537SMarc Zyngier /* If interrupt was enabled, disable it first */ 969021f6537SMarc Zyngier enabled = gic_peek_irq(d, GICD_ISENABLER); 970021f6537SMarc Zyngier if (enabled) 971021f6537SMarc Zyngier gic_mask_irq(d); 972021f6537SMarc Zyngier 973021f6537SMarc Zyngier reg = gic_dist_base(d) + GICD_IROUTER + (gic_irq(d) * 8); 974021f6537SMarc Zyngier val = gic_mpidr_to_affinity(cpu_logical_map(cpu)); 975021f6537SMarc Zyngier 97672c97126SJean-Philippe Brucker gic_write_irouter(val, reg); 977021f6537SMarc Zyngier 978021f6537SMarc Zyngier /* 979021f6537SMarc Zyngier * If the interrupt was enabled, enabled it again. Otherwise, 980021f6537SMarc Zyngier * just wait for the distributor to have digested our changes. 981021f6537SMarc Zyngier */ 982021f6537SMarc Zyngier if (enabled) 983021f6537SMarc Zyngier gic_unmask_irq(d); 984021f6537SMarc Zyngier else 985021f6537SMarc Zyngier gic_dist_wait_for_rwp(); 986021f6537SMarc Zyngier 987956ae91aSMarc Zyngier irq_data_update_effective_affinity(d, cpumask_of(cpu)); 988956ae91aSMarc Zyngier 9890fc6fa29SAntoine Tenart return IRQ_SET_MASK_OK_DONE; 990021f6537SMarc Zyngier } 991021f6537SMarc Zyngier #else 992021f6537SMarc Zyngier #define gic_set_affinity NULL 993021f6537SMarc Zyngier #define gic_smp_init() do { } while(0) 994021f6537SMarc Zyngier #endif 995021f6537SMarc Zyngier 9963708d52fSSudeep Holla #ifdef CONFIG_CPU_PM 9973708d52fSSudeep Holla static int gic_cpu_pm_notifier(struct notifier_block *self, 9983708d52fSSudeep Holla unsigned long cmd, void *v) 9993708d52fSSudeep Holla { 10003708d52fSSudeep Holla if (cmd == CPU_PM_EXIT) { 1001ccd9432aSSudeep Holla if (gic_dist_security_disabled()) 10023708d52fSSudeep Holla gic_enable_redist(true); 10033708d52fSSudeep Holla gic_cpu_sys_reg_init(); 1004ccd9432aSSudeep Holla } else if (cmd == CPU_PM_ENTER && gic_dist_security_disabled()) { 10053708d52fSSudeep Holla gic_write_grpen1(0); 10063708d52fSSudeep Holla gic_enable_redist(false); 10073708d52fSSudeep Holla } 10083708d52fSSudeep Holla return NOTIFY_OK; 10093708d52fSSudeep Holla } 10103708d52fSSudeep Holla 10113708d52fSSudeep Holla static struct notifier_block gic_cpu_pm_notifier_block = { 10123708d52fSSudeep Holla .notifier_call = gic_cpu_pm_notifier, 10133708d52fSSudeep Holla }; 10143708d52fSSudeep Holla 10153708d52fSSudeep Holla static void gic_cpu_pm_init(void) 10163708d52fSSudeep Holla { 10173708d52fSSudeep Holla cpu_pm_register_notifier(&gic_cpu_pm_notifier_block); 10183708d52fSSudeep Holla } 10193708d52fSSudeep Holla 10203708d52fSSudeep Holla #else 10213708d52fSSudeep Holla static inline void gic_cpu_pm_init(void) { } 10223708d52fSSudeep Holla #endif /* CONFIG_CPU_PM */ 10233708d52fSSudeep Holla 1024021f6537SMarc Zyngier static struct irq_chip gic_chip = { 1025021f6537SMarc Zyngier .name = "GICv3", 1026021f6537SMarc Zyngier .irq_mask = gic_mask_irq, 1027021f6537SMarc Zyngier .irq_unmask = gic_unmask_irq, 1028021f6537SMarc Zyngier .irq_eoi = gic_eoi_irq, 1029021f6537SMarc Zyngier .irq_set_type = gic_set_type, 1030021f6537SMarc Zyngier .irq_set_affinity = gic_set_affinity, 1031b594c6e2SMarc Zyngier .irq_get_irqchip_state = gic_irq_get_irqchip_state, 1032b594c6e2SMarc Zyngier .irq_set_irqchip_state = gic_irq_set_irqchip_state, 1033101b35f7SJulien Thierry .irq_nmi_setup = gic_irq_nmi_setup, 1034101b35f7SJulien Thierry .irq_nmi_teardown = gic_irq_nmi_teardown, 10354110b5cbSMarc Zyngier .flags = IRQCHIP_SET_TYPE_MASKED | 10364110b5cbSMarc Zyngier IRQCHIP_SKIP_SET_WAKE | 10374110b5cbSMarc Zyngier IRQCHIP_MASK_ON_SUSPEND, 1038021f6537SMarc Zyngier }; 1039021f6537SMarc Zyngier 10400b6a3da9SMarc Zyngier static struct irq_chip gic_eoimode1_chip = { 10410b6a3da9SMarc Zyngier .name = "GICv3", 10420b6a3da9SMarc Zyngier .irq_mask = gic_eoimode1_mask_irq, 10430b6a3da9SMarc Zyngier .irq_unmask = gic_unmask_irq, 10440b6a3da9SMarc Zyngier .irq_eoi = gic_eoimode1_eoi_irq, 10450b6a3da9SMarc Zyngier .irq_set_type = gic_set_type, 10460b6a3da9SMarc Zyngier .irq_set_affinity = gic_set_affinity, 10470b6a3da9SMarc Zyngier .irq_get_irqchip_state = gic_irq_get_irqchip_state, 10480b6a3da9SMarc Zyngier .irq_set_irqchip_state = gic_irq_set_irqchip_state, 1049530bf353SMarc Zyngier .irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity, 1050101b35f7SJulien Thierry .irq_nmi_setup = gic_irq_nmi_setup, 1051101b35f7SJulien Thierry .irq_nmi_teardown = gic_irq_nmi_teardown, 10524110b5cbSMarc Zyngier .flags = IRQCHIP_SET_TYPE_MASKED | 10534110b5cbSMarc Zyngier IRQCHIP_SKIP_SET_WAKE | 10544110b5cbSMarc Zyngier IRQCHIP_MASK_ON_SUSPEND, 10550b6a3da9SMarc Zyngier }; 10560b6a3da9SMarc Zyngier 1057a4f9edb2SMarc Zyngier #define GIC_ID_NR (1U << GICD_TYPER_ID_BITS(gic_data.rdists.gicd_typer)) 1058da33f31dSMarc Zyngier 1059021f6537SMarc Zyngier static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq, 1060021f6537SMarc Zyngier irq_hw_number_t hw) 1061021f6537SMarc Zyngier { 10620b6a3da9SMarc Zyngier struct irq_chip *chip = &gic_chip; 10630b6a3da9SMarc Zyngier 1064d01d3274SDavidlohr Bueso if (static_branch_likely(&supports_deactivate_key)) 10650b6a3da9SMarc Zyngier chip = &gic_eoimode1_chip; 10660b6a3da9SMarc Zyngier 1067021f6537SMarc Zyngier /* SGIs are private to the core kernel */ 1068021f6537SMarc Zyngier if (hw < 16) 1069021f6537SMarc Zyngier return -EPERM; 1070da33f31dSMarc Zyngier /* Nothing here */ 1071da33f31dSMarc Zyngier if (hw >= gic_data.irq_nr && hw < 8192) 1072da33f31dSMarc Zyngier return -EPERM; 1073da33f31dSMarc Zyngier /* Off limits */ 1074da33f31dSMarc Zyngier if (hw >= GIC_ID_NR) 1075da33f31dSMarc Zyngier return -EPERM; 1076da33f31dSMarc Zyngier 1077021f6537SMarc Zyngier /* PPIs */ 1078021f6537SMarc Zyngier if (hw < 32) { 1079021f6537SMarc Zyngier irq_set_percpu_devid(irq); 10800b6a3da9SMarc Zyngier irq_domain_set_info(d, irq, hw, chip, d->host_data, 1081443acc4fSMarc Zyngier handle_percpu_devid_irq, NULL, NULL); 1082d17cab44SRob Herring irq_set_status_flags(irq, IRQ_NOAUTOEN); 1083021f6537SMarc Zyngier } 1084021f6537SMarc Zyngier /* SPIs */ 1085021f6537SMarc Zyngier if (hw >= 32 && hw < gic_data.irq_nr) { 10860b6a3da9SMarc Zyngier irq_domain_set_info(d, irq, hw, chip, d->host_data, 1087443acc4fSMarc Zyngier handle_fasteoi_irq, NULL, NULL); 1088d17cab44SRob Herring irq_set_probe(irq); 1089956ae91aSMarc Zyngier irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(irq))); 1090021f6537SMarc Zyngier } 1091da33f31dSMarc Zyngier /* LPIs */ 1092da33f31dSMarc Zyngier if (hw >= 8192 && hw < GIC_ID_NR) { 1093da33f31dSMarc Zyngier if (!gic_dist_supports_lpis()) 1094da33f31dSMarc Zyngier return -EPERM; 10950b6a3da9SMarc Zyngier irq_domain_set_info(d, irq, hw, chip, d->host_data, 1096da33f31dSMarc Zyngier handle_fasteoi_irq, NULL, NULL); 1097da33f31dSMarc Zyngier } 1098da33f31dSMarc Zyngier 1099021f6537SMarc Zyngier return 0; 1100021f6537SMarc Zyngier } 1101021f6537SMarc Zyngier 110265da7d19SMarc Zyngier #define GIC_IRQ_TYPE_PARTITION (GIC_IRQ_TYPE_LPI + 1) 110365da7d19SMarc Zyngier 1104f833f57fSMarc Zyngier static int gic_irq_domain_translate(struct irq_domain *d, 1105f833f57fSMarc Zyngier struct irq_fwspec *fwspec, 1106f833f57fSMarc Zyngier unsigned long *hwirq, 1107f833f57fSMarc Zyngier unsigned int *type) 1108021f6537SMarc Zyngier { 1109f833f57fSMarc Zyngier if (is_of_node(fwspec->fwnode)) { 1110f833f57fSMarc Zyngier if (fwspec->param_count < 3) 1111021f6537SMarc Zyngier return -EINVAL; 1112021f6537SMarc Zyngier 1113db8c70ecSMarc Zyngier switch (fwspec->param[0]) { 1114db8c70ecSMarc Zyngier case 0: /* SPI */ 1115db8c70ecSMarc Zyngier *hwirq = fwspec->param[1] + 32; 1116db8c70ecSMarc Zyngier break; 1117db8c70ecSMarc Zyngier case 1: /* PPI */ 111865da7d19SMarc Zyngier case GIC_IRQ_TYPE_PARTITION: 1119f833f57fSMarc Zyngier *hwirq = fwspec->param[1] + 16; 1120db8c70ecSMarc Zyngier break; 1121db8c70ecSMarc Zyngier case GIC_IRQ_TYPE_LPI: /* LPI */ 1122db8c70ecSMarc Zyngier *hwirq = fwspec->param[1]; 1123db8c70ecSMarc Zyngier break; 1124db8c70ecSMarc Zyngier default: 1125db8c70ecSMarc Zyngier return -EINVAL; 1126db8c70ecSMarc Zyngier } 1127f833f57fSMarc Zyngier 1128f833f57fSMarc Zyngier *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; 11296ef6386eSMarc Zyngier 113065da7d19SMarc Zyngier /* 113165da7d19SMarc Zyngier * Make it clear that broken DTs are... broken. 113265da7d19SMarc Zyngier * Partitionned PPIs are an unfortunate exception. 113365da7d19SMarc Zyngier */ 113465da7d19SMarc Zyngier WARN_ON(*type == IRQ_TYPE_NONE && 113565da7d19SMarc Zyngier fwspec->param[0] != GIC_IRQ_TYPE_PARTITION); 1136f833f57fSMarc Zyngier return 0; 1137021f6537SMarc Zyngier } 1138021f6537SMarc Zyngier 1139ffa7d616STomasz Nowicki if (is_fwnode_irqchip(fwspec->fwnode)) { 1140ffa7d616STomasz Nowicki if(fwspec->param_count != 2) 1141ffa7d616STomasz Nowicki return -EINVAL; 1142ffa7d616STomasz Nowicki 1143ffa7d616STomasz Nowicki *hwirq = fwspec->param[0]; 1144ffa7d616STomasz Nowicki *type = fwspec->param[1]; 11456ef6386eSMarc Zyngier 11466ef6386eSMarc Zyngier WARN_ON(*type == IRQ_TYPE_NONE); 1147ffa7d616STomasz Nowicki return 0; 1148ffa7d616STomasz Nowicki } 1149ffa7d616STomasz Nowicki 1150f833f57fSMarc Zyngier return -EINVAL; 1151021f6537SMarc Zyngier } 1152021f6537SMarc Zyngier 1153443acc4fSMarc Zyngier static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, 1154443acc4fSMarc Zyngier unsigned int nr_irqs, void *arg) 1155443acc4fSMarc Zyngier { 1156443acc4fSMarc Zyngier int i, ret; 1157443acc4fSMarc Zyngier irq_hw_number_t hwirq; 1158443acc4fSMarc Zyngier unsigned int type = IRQ_TYPE_NONE; 1159f833f57fSMarc Zyngier struct irq_fwspec *fwspec = arg; 1160443acc4fSMarc Zyngier 1161f833f57fSMarc Zyngier ret = gic_irq_domain_translate(domain, fwspec, &hwirq, &type); 1162443acc4fSMarc Zyngier if (ret) 1163443acc4fSMarc Zyngier return ret; 1164443acc4fSMarc Zyngier 116563c16c6eSSuzuki K Poulose for (i = 0; i < nr_irqs; i++) { 116663c16c6eSSuzuki K Poulose ret = gic_irq_domain_map(domain, virq + i, hwirq + i); 116763c16c6eSSuzuki K Poulose if (ret) 116863c16c6eSSuzuki K Poulose return ret; 116963c16c6eSSuzuki K Poulose } 1170443acc4fSMarc Zyngier 1171443acc4fSMarc Zyngier return 0; 1172443acc4fSMarc Zyngier } 1173443acc4fSMarc Zyngier 1174443acc4fSMarc Zyngier static void gic_irq_domain_free(struct irq_domain *domain, unsigned int virq, 1175443acc4fSMarc Zyngier unsigned int nr_irqs) 1176443acc4fSMarc Zyngier { 1177443acc4fSMarc Zyngier int i; 1178443acc4fSMarc Zyngier 1179443acc4fSMarc Zyngier for (i = 0; i < nr_irqs; i++) { 1180443acc4fSMarc Zyngier struct irq_data *d = irq_domain_get_irq_data(domain, virq + i); 1181443acc4fSMarc Zyngier irq_set_handler(virq + i, NULL); 1182443acc4fSMarc Zyngier irq_domain_reset_irq_data(d); 1183443acc4fSMarc Zyngier } 1184443acc4fSMarc Zyngier } 1185443acc4fSMarc Zyngier 1186e3825ba1SMarc Zyngier static int gic_irq_domain_select(struct irq_domain *d, 1187e3825ba1SMarc Zyngier struct irq_fwspec *fwspec, 1188e3825ba1SMarc Zyngier enum irq_domain_bus_token bus_token) 1189e3825ba1SMarc Zyngier { 1190e3825ba1SMarc Zyngier /* Not for us */ 1191e3825ba1SMarc Zyngier if (fwspec->fwnode != d->fwnode) 1192e3825ba1SMarc Zyngier return 0; 1193e3825ba1SMarc Zyngier 1194e3825ba1SMarc Zyngier /* If this is not DT, then we have a single domain */ 1195e3825ba1SMarc Zyngier if (!is_of_node(fwspec->fwnode)) 1196e3825ba1SMarc Zyngier return 1; 1197e3825ba1SMarc Zyngier 1198e3825ba1SMarc Zyngier /* 1199e3825ba1SMarc Zyngier * If this is a PPI and we have a 4th (non-null) parameter, 1200e3825ba1SMarc Zyngier * then we need to match the partition domain. 1201e3825ba1SMarc Zyngier */ 1202e3825ba1SMarc Zyngier if (fwspec->param_count >= 4 && 1203e3825ba1SMarc Zyngier fwspec->param[0] == 1 && fwspec->param[3] != 0) 1204e3825ba1SMarc Zyngier return d == partition_get_domain(gic_data.ppi_descs[fwspec->param[1]]); 1205e3825ba1SMarc Zyngier 1206e3825ba1SMarc Zyngier return d == gic_data.domain; 1207e3825ba1SMarc Zyngier } 1208e3825ba1SMarc Zyngier 1209021f6537SMarc Zyngier static const struct irq_domain_ops gic_irq_domain_ops = { 1210f833f57fSMarc Zyngier .translate = gic_irq_domain_translate, 1211443acc4fSMarc Zyngier .alloc = gic_irq_domain_alloc, 1212443acc4fSMarc Zyngier .free = gic_irq_domain_free, 1213e3825ba1SMarc Zyngier .select = gic_irq_domain_select, 1214e3825ba1SMarc Zyngier }; 1215e3825ba1SMarc Zyngier 1216e3825ba1SMarc Zyngier static int partition_domain_translate(struct irq_domain *d, 1217e3825ba1SMarc Zyngier struct irq_fwspec *fwspec, 1218e3825ba1SMarc Zyngier unsigned long *hwirq, 1219e3825ba1SMarc Zyngier unsigned int *type) 1220e3825ba1SMarc Zyngier { 1221e3825ba1SMarc Zyngier struct device_node *np; 1222e3825ba1SMarc Zyngier int ret; 1223e3825ba1SMarc Zyngier 1224e3825ba1SMarc Zyngier np = of_find_node_by_phandle(fwspec->param[3]); 1225e3825ba1SMarc Zyngier if (WARN_ON(!np)) 1226e3825ba1SMarc Zyngier return -EINVAL; 1227e3825ba1SMarc Zyngier 1228e3825ba1SMarc Zyngier ret = partition_translate_id(gic_data.ppi_descs[fwspec->param[1]], 1229e3825ba1SMarc Zyngier of_node_to_fwnode(np)); 1230e3825ba1SMarc Zyngier if (ret < 0) 1231e3825ba1SMarc Zyngier return ret; 1232e3825ba1SMarc Zyngier 1233e3825ba1SMarc Zyngier *hwirq = ret; 1234e3825ba1SMarc Zyngier *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; 1235e3825ba1SMarc Zyngier 1236e3825ba1SMarc Zyngier return 0; 1237e3825ba1SMarc Zyngier } 1238e3825ba1SMarc Zyngier 1239e3825ba1SMarc Zyngier static const struct irq_domain_ops partition_domain_ops = { 1240e3825ba1SMarc Zyngier .translate = partition_domain_translate, 1241e3825ba1SMarc Zyngier .select = gic_irq_domain_select, 1242021f6537SMarc Zyngier }; 1243021f6537SMarc Zyngier 12449c8114c2SSrinivas Kandagatla static bool gic_enable_quirk_msm8996(void *data) 12459c8114c2SSrinivas Kandagatla { 12469c8114c2SSrinivas Kandagatla struct gic_chip_data *d = data; 12479c8114c2SSrinivas Kandagatla 12489c8114c2SSrinivas Kandagatla d->flags |= FLAGS_WORKAROUND_GICR_WAKER_MSM8996; 12499c8114c2SSrinivas Kandagatla 12509c8114c2SSrinivas Kandagatla return true; 12519c8114c2SSrinivas Kandagatla } 12529c8114c2SSrinivas Kandagatla 1253d98d0a99SJulien Thierry static void gic_enable_nmi_support(void) 1254d98d0a99SJulien Thierry { 1255101b35f7SJulien Thierry int i; 1256101b35f7SJulien Thierry 1257101b35f7SJulien Thierry for (i = 0; i < 16; i++) 1258101b35f7SJulien Thierry refcount_set(&ppi_nmi_refs[i], 0); 1259101b35f7SJulien Thierry 1260d98d0a99SJulien Thierry static_branch_enable(&supports_pseudo_nmis); 1261101b35f7SJulien Thierry 1262101b35f7SJulien Thierry if (static_branch_likely(&supports_deactivate_key)) 1263101b35f7SJulien Thierry gic_eoimode1_chip.flags |= IRQCHIP_SUPPORTS_NMI; 1264101b35f7SJulien Thierry else 1265101b35f7SJulien Thierry gic_chip.flags |= IRQCHIP_SUPPORTS_NMI; 1266d98d0a99SJulien Thierry } 1267d98d0a99SJulien Thierry 1268db57d746STomasz Nowicki static int __init gic_init_bases(void __iomem *dist_base, 1269db57d746STomasz Nowicki struct redist_region *rdist_regs, 1270db57d746STomasz Nowicki u32 nr_redist_regions, 1271db57d746STomasz Nowicki u64 redist_stride, 1272db57d746STomasz Nowicki struct fwnode_handle *handle) 1273db57d746STomasz Nowicki { 1274db57d746STomasz Nowicki u32 typer; 1275db57d746STomasz Nowicki int gic_irqs; 1276db57d746STomasz Nowicki int err; 1277db57d746STomasz Nowicki 1278db57d746STomasz Nowicki if (!is_hyp_mode_available()) 1279d01d3274SDavidlohr Bueso static_branch_disable(&supports_deactivate_key); 1280db57d746STomasz Nowicki 1281d01d3274SDavidlohr Bueso if (static_branch_likely(&supports_deactivate_key)) 1282db57d746STomasz Nowicki pr_info("GIC: Using split EOI/Deactivate mode\n"); 1283db57d746STomasz Nowicki 1284e3825ba1SMarc Zyngier gic_data.fwnode = handle; 1285db57d746STomasz Nowicki gic_data.dist_base = dist_base; 1286db57d746STomasz Nowicki gic_data.redist_regions = rdist_regs; 1287db57d746STomasz Nowicki gic_data.nr_redist_regions = nr_redist_regions; 1288db57d746STomasz Nowicki gic_data.redist_stride = redist_stride; 1289db57d746STomasz Nowicki 1290db57d746STomasz Nowicki /* 1291db57d746STomasz Nowicki * Find out how many interrupts are supported. 1292db57d746STomasz Nowicki * The GIC only supports up to 1020 interrupt sources (SGI+PPI+SPI) 1293db57d746STomasz Nowicki */ 1294db57d746STomasz Nowicki typer = readl_relaxed(gic_data.dist_base + GICD_TYPER); 1295a4f9edb2SMarc Zyngier gic_data.rdists.gicd_typer = typer; 1296db57d746STomasz Nowicki gic_irqs = GICD_TYPER_IRQS(typer); 1297db57d746STomasz Nowicki if (gic_irqs > 1020) 1298db57d746STomasz Nowicki gic_irqs = 1020; 1299db57d746STomasz Nowicki gic_data.irq_nr = gic_irqs; 1300db57d746STomasz Nowicki 1301db57d746STomasz Nowicki gic_data.domain = irq_domain_create_tree(handle, &gic_irq_domain_ops, 1302db57d746STomasz Nowicki &gic_data); 1303b2425b51SMarc Zyngier irq_domain_update_bus_token(gic_data.domain, DOMAIN_BUS_WIRED); 1304db57d746STomasz Nowicki gic_data.rdists.rdist = alloc_percpu(typeof(*gic_data.rdists.rdist)); 13050edc23eaSMarc Zyngier gic_data.rdists.has_vlpis = true; 13060edc23eaSMarc Zyngier gic_data.rdists.has_direct_lpi = true; 1307db57d746STomasz Nowicki 1308db57d746STomasz Nowicki if (WARN_ON(!gic_data.domain) || WARN_ON(!gic_data.rdists.rdist)) { 1309db57d746STomasz Nowicki err = -ENOMEM; 1310db57d746STomasz Nowicki goto out_free; 1311db57d746STomasz Nowicki } 1312db57d746STomasz Nowicki 1313eda0d04aSShanker Donthineni gic_data.has_rss = !!(typer & GICD_TYPER_RSS); 1314eda0d04aSShanker Donthineni pr_info("Distributor has %sRange Selector support\n", 1315eda0d04aSShanker Donthineni gic_data.has_rss ? "" : "no "); 1316eda0d04aSShanker Donthineni 131750528752SMarc Zyngier if (typer & GICD_TYPER_MBIS) { 131850528752SMarc Zyngier err = mbi_init(handle, gic_data.domain); 131950528752SMarc Zyngier if (err) 132050528752SMarc Zyngier pr_err("Failed to initialize MBIs\n"); 132150528752SMarc Zyngier } 132250528752SMarc Zyngier 1323db57d746STomasz Nowicki set_handle_irq(gic_handle_irq); 1324db57d746STomasz Nowicki 13250edc23eaSMarc Zyngier gic_update_vlpi_properties(); 13260edc23eaSMarc Zyngier 1327db57d746STomasz Nowicki gic_smp_init(); 1328db57d746STomasz Nowicki gic_dist_init(); 1329db57d746STomasz Nowicki gic_cpu_init(); 1330db57d746STomasz Nowicki gic_cpu_pm_init(); 1331db57d746STomasz Nowicki 1332d38a71c5SMarc Zyngier if (gic_dist_supports_lpis()) { 1333d38a71c5SMarc Zyngier its_init(handle, &gic_data.rdists, gic_data.domain); 1334d38a71c5SMarc Zyngier its_cpu_init(); 1335d38a71c5SMarc Zyngier } 1336d38a71c5SMarc Zyngier 1337d98d0a99SJulien Thierry if (gic_prio_masking_enabled()) { 1338d98d0a99SJulien Thierry if (!gic_has_group0() || gic_dist_security_disabled()) 1339d98d0a99SJulien Thierry gic_enable_nmi_support(); 1340d98d0a99SJulien Thierry else 1341d98d0a99SJulien Thierry pr_warn("SCR_EL3.FIQ is cleared, cannot enable use of pseudo-NMIs\n"); 1342d98d0a99SJulien Thierry } 1343d98d0a99SJulien Thierry 1344db57d746STomasz Nowicki return 0; 1345db57d746STomasz Nowicki 1346db57d746STomasz Nowicki out_free: 1347db57d746STomasz Nowicki if (gic_data.domain) 1348db57d746STomasz Nowicki irq_domain_remove(gic_data.domain); 1349db57d746STomasz Nowicki free_percpu(gic_data.rdists.rdist); 1350db57d746STomasz Nowicki return err; 1351db57d746STomasz Nowicki } 1352db57d746STomasz Nowicki 1353db57d746STomasz Nowicki static int __init gic_validate_dist_version(void __iomem *dist_base) 1354db57d746STomasz Nowicki { 1355db57d746STomasz Nowicki u32 reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK; 1356db57d746STomasz Nowicki 1357db57d746STomasz Nowicki if (reg != GIC_PIDR2_ARCH_GICv3 && reg != GIC_PIDR2_ARCH_GICv4) 1358db57d746STomasz Nowicki return -ENODEV; 1359db57d746STomasz Nowicki 1360db57d746STomasz Nowicki return 0; 1361db57d746STomasz Nowicki } 1362db57d746STomasz Nowicki 1363e3825ba1SMarc Zyngier /* Create all possible partitions at boot time */ 13647beaa24bSLinus Torvalds static void __init gic_populate_ppi_partitions(struct device_node *gic_node) 1365e3825ba1SMarc Zyngier { 1366e3825ba1SMarc Zyngier struct device_node *parts_node, *child_part; 1367e3825ba1SMarc Zyngier int part_idx = 0, i; 1368e3825ba1SMarc Zyngier int nr_parts; 1369e3825ba1SMarc Zyngier struct partition_affinity *parts; 1370e3825ba1SMarc Zyngier 137100ee9a1cSJohan Hovold parts_node = of_get_child_by_name(gic_node, "ppi-partitions"); 1372e3825ba1SMarc Zyngier if (!parts_node) 1373e3825ba1SMarc Zyngier return; 1374e3825ba1SMarc Zyngier 1375e3825ba1SMarc Zyngier nr_parts = of_get_child_count(parts_node); 1376e3825ba1SMarc Zyngier 1377e3825ba1SMarc Zyngier if (!nr_parts) 137800ee9a1cSJohan Hovold goto out_put_node; 1379e3825ba1SMarc Zyngier 13806396bb22SKees Cook parts = kcalloc(nr_parts, sizeof(*parts), GFP_KERNEL); 1381e3825ba1SMarc Zyngier if (WARN_ON(!parts)) 138200ee9a1cSJohan Hovold goto out_put_node; 1383e3825ba1SMarc Zyngier 1384e3825ba1SMarc Zyngier for_each_child_of_node(parts_node, child_part) { 1385e3825ba1SMarc Zyngier struct partition_affinity *part; 1386e3825ba1SMarc Zyngier int n; 1387e3825ba1SMarc Zyngier 1388e3825ba1SMarc Zyngier part = &parts[part_idx]; 1389e3825ba1SMarc Zyngier 1390e3825ba1SMarc Zyngier part->partition_id = of_node_to_fwnode(child_part); 1391e3825ba1SMarc Zyngier 13922ef790dcSRob Herring pr_info("GIC: PPI partition %pOFn[%d] { ", 13932ef790dcSRob Herring child_part, part_idx); 1394e3825ba1SMarc Zyngier 1395e3825ba1SMarc Zyngier n = of_property_count_elems_of_size(child_part, "affinity", 1396e3825ba1SMarc Zyngier sizeof(u32)); 1397e3825ba1SMarc Zyngier WARN_ON(n <= 0); 1398e3825ba1SMarc Zyngier 1399e3825ba1SMarc Zyngier for (i = 0; i < n; i++) { 1400e3825ba1SMarc Zyngier int err, cpu; 1401e3825ba1SMarc Zyngier u32 cpu_phandle; 1402e3825ba1SMarc Zyngier struct device_node *cpu_node; 1403e3825ba1SMarc Zyngier 1404e3825ba1SMarc Zyngier err = of_property_read_u32_index(child_part, "affinity", 1405e3825ba1SMarc Zyngier i, &cpu_phandle); 1406e3825ba1SMarc Zyngier if (WARN_ON(err)) 1407e3825ba1SMarc Zyngier continue; 1408e3825ba1SMarc Zyngier 1409e3825ba1SMarc Zyngier cpu_node = of_find_node_by_phandle(cpu_phandle); 1410e3825ba1SMarc Zyngier if (WARN_ON(!cpu_node)) 1411e3825ba1SMarc Zyngier continue; 1412e3825ba1SMarc Zyngier 1413c08ec7daSSuzuki K Poulose cpu = of_cpu_node_to_id(cpu_node); 1414c08ec7daSSuzuki K Poulose if (WARN_ON(cpu < 0)) 1415e3825ba1SMarc Zyngier continue; 1416e3825ba1SMarc Zyngier 1417e81f54c6SRob Herring pr_cont("%pOF[%d] ", cpu_node, cpu); 1418e3825ba1SMarc Zyngier 1419e3825ba1SMarc Zyngier cpumask_set_cpu(cpu, &part->mask); 1420e3825ba1SMarc Zyngier } 1421e3825ba1SMarc Zyngier 1422e3825ba1SMarc Zyngier pr_cont("}\n"); 1423e3825ba1SMarc Zyngier part_idx++; 1424e3825ba1SMarc Zyngier } 1425e3825ba1SMarc Zyngier 1426e3825ba1SMarc Zyngier for (i = 0; i < 16; i++) { 1427e3825ba1SMarc Zyngier unsigned int irq; 1428e3825ba1SMarc Zyngier struct partition_desc *desc; 1429e3825ba1SMarc Zyngier struct irq_fwspec ppi_fwspec = { 1430e3825ba1SMarc Zyngier .fwnode = gic_data.fwnode, 1431e3825ba1SMarc Zyngier .param_count = 3, 1432e3825ba1SMarc Zyngier .param = { 143365da7d19SMarc Zyngier [0] = GIC_IRQ_TYPE_PARTITION, 1434e3825ba1SMarc Zyngier [1] = i, 1435e3825ba1SMarc Zyngier [2] = IRQ_TYPE_NONE, 1436e3825ba1SMarc Zyngier }, 1437e3825ba1SMarc Zyngier }; 1438e3825ba1SMarc Zyngier 1439e3825ba1SMarc Zyngier irq = irq_create_fwspec_mapping(&ppi_fwspec); 1440e3825ba1SMarc Zyngier if (WARN_ON(!irq)) 1441e3825ba1SMarc Zyngier continue; 1442e3825ba1SMarc Zyngier desc = partition_create_desc(gic_data.fwnode, parts, nr_parts, 1443e3825ba1SMarc Zyngier irq, &partition_domain_ops); 1444e3825ba1SMarc Zyngier if (WARN_ON(!desc)) 1445e3825ba1SMarc Zyngier continue; 1446e3825ba1SMarc Zyngier 1447e3825ba1SMarc Zyngier gic_data.ppi_descs[i] = desc; 1448e3825ba1SMarc Zyngier } 144900ee9a1cSJohan Hovold 145000ee9a1cSJohan Hovold out_put_node: 145100ee9a1cSJohan Hovold of_node_put(parts_node); 1452e3825ba1SMarc Zyngier } 1453e3825ba1SMarc Zyngier 14541839e576SJulien Grall static void __init gic_of_setup_kvm_info(struct device_node *node) 14551839e576SJulien Grall { 14561839e576SJulien Grall int ret; 14571839e576SJulien Grall struct resource r; 14581839e576SJulien Grall u32 gicv_idx; 14591839e576SJulien Grall 14601839e576SJulien Grall gic_v3_kvm_info.type = GIC_V3; 14611839e576SJulien Grall 14621839e576SJulien Grall gic_v3_kvm_info.maint_irq = irq_of_parse_and_map(node, 0); 14631839e576SJulien Grall if (!gic_v3_kvm_info.maint_irq) 14641839e576SJulien Grall return; 14651839e576SJulien Grall 14661839e576SJulien Grall if (of_property_read_u32(node, "#redistributor-regions", 14671839e576SJulien Grall &gicv_idx)) 14681839e576SJulien Grall gicv_idx = 1; 14691839e576SJulien Grall 14701839e576SJulien Grall gicv_idx += 3; /* Also skip GICD, GICC, GICH */ 14711839e576SJulien Grall ret = of_address_to_resource(node, gicv_idx, &r); 14721839e576SJulien Grall if (!ret) 14731839e576SJulien Grall gic_v3_kvm_info.vcpu = r; 14741839e576SJulien Grall 14754bdf5025SMarc Zyngier gic_v3_kvm_info.has_v4 = gic_data.rdists.has_vlpis; 14761839e576SJulien Grall gic_set_kvm_info(&gic_v3_kvm_info); 14771839e576SJulien Grall } 14781839e576SJulien Grall 1479f70fdb42SSrinivas Kandagatla static const struct gic_quirk gic_quirks[] = { 1480f70fdb42SSrinivas Kandagatla { 14819c8114c2SSrinivas Kandagatla .desc = "GICv3: Qualcomm MSM8996 broken firmware", 14829c8114c2SSrinivas Kandagatla .compatible = "qcom,msm8996-gic-v3", 14839c8114c2SSrinivas Kandagatla .init = gic_enable_quirk_msm8996, 14849c8114c2SSrinivas Kandagatla }, 14859c8114c2SSrinivas Kandagatla { 1486f70fdb42SSrinivas Kandagatla } 1487f70fdb42SSrinivas Kandagatla }; 1488f70fdb42SSrinivas Kandagatla 1489021f6537SMarc Zyngier static int __init gic_of_init(struct device_node *node, struct device_node *parent) 1490021f6537SMarc Zyngier { 1491021f6537SMarc Zyngier void __iomem *dist_base; 1492f5c1434cSMarc Zyngier struct redist_region *rdist_regs; 1493021f6537SMarc Zyngier u64 redist_stride; 1494f5c1434cSMarc Zyngier u32 nr_redist_regions; 1495db57d746STomasz Nowicki int err, i; 1496021f6537SMarc Zyngier 1497021f6537SMarc Zyngier dist_base = of_iomap(node, 0); 1498021f6537SMarc Zyngier if (!dist_base) { 1499e81f54c6SRob Herring pr_err("%pOF: unable to map gic dist registers\n", node); 1500021f6537SMarc Zyngier return -ENXIO; 1501021f6537SMarc Zyngier } 1502021f6537SMarc Zyngier 1503db57d746STomasz Nowicki err = gic_validate_dist_version(dist_base); 1504db57d746STomasz Nowicki if (err) { 1505e81f54c6SRob Herring pr_err("%pOF: no distributor detected, giving up\n", node); 1506021f6537SMarc Zyngier goto out_unmap_dist; 1507021f6537SMarc Zyngier } 1508021f6537SMarc Zyngier 1509f5c1434cSMarc Zyngier if (of_property_read_u32(node, "#redistributor-regions", &nr_redist_regions)) 1510f5c1434cSMarc Zyngier nr_redist_regions = 1; 1511021f6537SMarc Zyngier 15126396bb22SKees Cook rdist_regs = kcalloc(nr_redist_regions, sizeof(*rdist_regs), 15136396bb22SKees Cook GFP_KERNEL); 1514f5c1434cSMarc Zyngier if (!rdist_regs) { 1515021f6537SMarc Zyngier err = -ENOMEM; 1516021f6537SMarc Zyngier goto out_unmap_dist; 1517021f6537SMarc Zyngier } 1518021f6537SMarc Zyngier 1519f5c1434cSMarc Zyngier for (i = 0; i < nr_redist_regions; i++) { 1520f5c1434cSMarc Zyngier struct resource res; 1521f5c1434cSMarc Zyngier int ret; 1522f5c1434cSMarc Zyngier 1523f5c1434cSMarc Zyngier ret = of_address_to_resource(node, 1 + i, &res); 1524f5c1434cSMarc Zyngier rdist_regs[i].redist_base = of_iomap(node, 1 + i); 1525f5c1434cSMarc Zyngier if (ret || !rdist_regs[i].redist_base) { 1526e81f54c6SRob Herring pr_err("%pOF: couldn't map region %d\n", node, i); 1527021f6537SMarc Zyngier err = -ENODEV; 1528021f6537SMarc Zyngier goto out_unmap_rdist; 1529021f6537SMarc Zyngier } 1530f5c1434cSMarc Zyngier rdist_regs[i].phys_base = res.start; 1531021f6537SMarc Zyngier } 1532021f6537SMarc Zyngier 1533021f6537SMarc Zyngier if (of_property_read_u64(node, "redistributor-stride", &redist_stride)) 1534021f6537SMarc Zyngier redist_stride = 0; 1535021f6537SMarc Zyngier 1536f70fdb42SSrinivas Kandagatla gic_enable_of_quirks(node, gic_quirks, &gic_data); 1537f70fdb42SSrinivas Kandagatla 1538db57d746STomasz Nowicki err = gic_init_bases(dist_base, rdist_regs, nr_redist_regions, 1539db57d746STomasz Nowicki redist_stride, &node->fwnode); 1540e3825ba1SMarc Zyngier if (err) 1541e3825ba1SMarc Zyngier goto out_unmap_rdist; 1542e3825ba1SMarc Zyngier 1543e3825ba1SMarc Zyngier gic_populate_ppi_partitions(node); 1544d33a3c8cSChristoffer Dall 1545d01d3274SDavidlohr Bueso if (static_branch_likely(&supports_deactivate_key)) 15461839e576SJulien Grall gic_of_setup_kvm_info(node); 1547021f6537SMarc Zyngier return 0; 1548021f6537SMarc Zyngier 1549021f6537SMarc Zyngier out_unmap_rdist: 1550f5c1434cSMarc Zyngier for (i = 0; i < nr_redist_regions; i++) 1551f5c1434cSMarc Zyngier if (rdist_regs[i].redist_base) 1552f5c1434cSMarc Zyngier iounmap(rdist_regs[i].redist_base); 1553f5c1434cSMarc Zyngier kfree(rdist_regs); 1554021f6537SMarc Zyngier out_unmap_dist: 1555021f6537SMarc Zyngier iounmap(dist_base); 1556021f6537SMarc Zyngier return err; 1557021f6537SMarc Zyngier } 1558021f6537SMarc Zyngier 1559021f6537SMarc Zyngier IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init); 1560ffa7d616STomasz Nowicki 1561ffa7d616STomasz Nowicki #ifdef CONFIG_ACPI 1562611f039fSJulien Grall static struct 1563611f039fSJulien Grall { 1564611f039fSJulien Grall void __iomem *dist_base; 1565611f039fSJulien Grall struct redist_region *redist_regs; 1566611f039fSJulien Grall u32 nr_redist_regions; 1567611f039fSJulien Grall bool single_redist; 15681839e576SJulien Grall u32 maint_irq; 15691839e576SJulien Grall int maint_irq_mode; 15701839e576SJulien Grall phys_addr_t vcpu_base; 1571611f039fSJulien Grall } acpi_data __initdata; 1572b70fb7afSTomasz Nowicki 1573b70fb7afSTomasz Nowicki static void __init 1574b70fb7afSTomasz Nowicki gic_acpi_register_redist(phys_addr_t phys_base, void __iomem *redist_base) 1575b70fb7afSTomasz Nowicki { 1576b70fb7afSTomasz Nowicki static int count = 0; 1577b70fb7afSTomasz Nowicki 1578611f039fSJulien Grall acpi_data.redist_regs[count].phys_base = phys_base; 1579611f039fSJulien Grall acpi_data.redist_regs[count].redist_base = redist_base; 1580611f039fSJulien Grall acpi_data.redist_regs[count].single_redist = acpi_data.single_redist; 1581b70fb7afSTomasz Nowicki count++; 1582b70fb7afSTomasz Nowicki } 1583ffa7d616STomasz Nowicki 1584ffa7d616STomasz Nowicki static int __init 158560574d1eSKeith Busch gic_acpi_parse_madt_redist(union acpi_subtable_headers *header, 1586ffa7d616STomasz Nowicki const unsigned long end) 1587ffa7d616STomasz Nowicki { 1588ffa7d616STomasz Nowicki struct acpi_madt_generic_redistributor *redist = 1589ffa7d616STomasz Nowicki (struct acpi_madt_generic_redistributor *)header; 1590ffa7d616STomasz Nowicki void __iomem *redist_base; 1591ffa7d616STomasz Nowicki 1592ffa7d616STomasz Nowicki redist_base = ioremap(redist->base_address, redist->length); 1593ffa7d616STomasz Nowicki if (!redist_base) { 1594ffa7d616STomasz Nowicki pr_err("Couldn't map GICR region @%llx\n", redist->base_address); 1595ffa7d616STomasz Nowicki return -ENOMEM; 1596ffa7d616STomasz Nowicki } 1597ffa7d616STomasz Nowicki 1598b70fb7afSTomasz Nowicki gic_acpi_register_redist(redist->base_address, redist_base); 1599ffa7d616STomasz Nowicki return 0; 1600ffa7d616STomasz Nowicki } 1601ffa7d616STomasz Nowicki 1602b70fb7afSTomasz Nowicki static int __init 160360574d1eSKeith Busch gic_acpi_parse_madt_gicc(union acpi_subtable_headers *header, 1604b70fb7afSTomasz Nowicki const unsigned long end) 1605b70fb7afSTomasz Nowicki { 1606b70fb7afSTomasz Nowicki struct acpi_madt_generic_interrupt *gicc = 1607b70fb7afSTomasz Nowicki (struct acpi_madt_generic_interrupt *)header; 1608611f039fSJulien Grall u32 reg = readl_relaxed(acpi_data.dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK; 1609b70fb7afSTomasz Nowicki u32 size = reg == GIC_PIDR2_ARCH_GICv4 ? SZ_64K * 4 : SZ_64K * 2; 1610b70fb7afSTomasz Nowicki void __iomem *redist_base; 1611b70fb7afSTomasz Nowicki 1612ebe2f871SShanker Donthineni /* GICC entry which has !ACPI_MADT_ENABLED is not unusable so skip */ 1613ebe2f871SShanker Donthineni if (!(gicc->flags & ACPI_MADT_ENABLED)) 1614ebe2f871SShanker Donthineni return 0; 1615ebe2f871SShanker Donthineni 1616b70fb7afSTomasz Nowicki redist_base = ioremap(gicc->gicr_base_address, size); 1617b70fb7afSTomasz Nowicki if (!redist_base) 1618b70fb7afSTomasz Nowicki return -ENOMEM; 1619b70fb7afSTomasz Nowicki 1620b70fb7afSTomasz Nowicki gic_acpi_register_redist(gicc->gicr_base_address, redist_base); 1621b70fb7afSTomasz Nowicki return 0; 1622b70fb7afSTomasz Nowicki } 1623b70fb7afSTomasz Nowicki 1624b70fb7afSTomasz Nowicki static int __init gic_acpi_collect_gicr_base(void) 1625b70fb7afSTomasz Nowicki { 1626b70fb7afSTomasz Nowicki acpi_tbl_entry_handler redist_parser; 1627b70fb7afSTomasz Nowicki enum acpi_madt_type type; 1628b70fb7afSTomasz Nowicki 1629611f039fSJulien Grall if (acpi_data.single_redist) { 1630b70fb7afSTomasz Nowicki type = ACPI_MADT_TYPE_GENERIC_INTERRUPT; 1631b70fb7afSTomasz Nowicki redist_parser = gic_acpi_parse_madt_gicc; 1632b70fb7afSTomasz Nowicki } else { 1633b70fb7afSTomasz Nowicki type = ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR; 1634b70fb7afSTomasz Nowicki redist_parser = gic_acpi_parse_madt_redist; 1635b70fb7afSTomasz Nowicki } 1636b70fb7afSTomasz Nowicki 1637b70fb7afSTomasz Nowicki /* Collect redistributor base addresses in GICR entries */ 1638b70fb7afSTomasz Nowicki if (acpi_table_parse_madt(type, redist_parser, 0) > 0) 1639b70fb7afSTomasz Nowicki return 0; 1640b70fb7afSTomasz Nowicki 1641b70fb7afSTomasz Nowicki pr_info("No valid GICR entries exist\n"); 1642b70fb7afSTomasz Nowicki return -ENODEV; 1643b70fb7afSTomasz Nowicki } 1644b70fb7afSTomasz Nowicki 164560574d1eSKeith Busch static int __init gic_acpi_match_gicr(union acpi_subtable_headers *header, 1646ffa7d616STomasz Nowicki const unsigned long end) 1647ffa7d616STomasz Nowicki { 1648ffa7d616STomasz Nowicki /* Subtable presence means that redist exists, that's it */ 1649ffa7d616STomasz Nowicki return 0; 1650ffa7d616STomasz Nowicki } 1651ffa7d616STomasz Nowicki 165260574d1eSKeith Busch static int __init gic_acpi_match_gicc(union acpi_subtable_headers *header, 1653b70fb7afSTomasz Nowicki const unsigned long end) 1654b70fb7afSTomasz Nowicki { 1655b70fb7afSTomasz Nowicki struct acpi_madt_generic_interrupt *gicc = 1656b70fb7afSTomasz Nowicki (struct acpi_madt_generic_interrupt *)header; 1657b70fb7afSTomasz Nowicki 1658b70fb7afSTomasz Nowicki /* 1659b70fb7afSTomasz Nowicki * If GICC is enabled and has valid gicr base address, then it means 1660b70fb7afSTomasz Nowicki * GICR base is presented via GICC 1661b70fb7afSTomasz Nowicki */ 1662b70fb7afSTomasz Nowicki if ((gicc->flags & ACPI_MADT_ENABLED) && gicc->gicr_base_address) 1663b70fb7afSTomasz Nowicki return 0; 1664b70fb7afSTomasz Nowicki 1665ebe2f871SShanker Donthineni /* 1666ebe2f871SShanker Donthineni * It's perfectly valid firmware can pass disabled GICC entry, driver 1667ebe2f871SShanker Donthineni * should not treat as errors, skip the entry instead of probe fail. 1668ebe2f871SShanker Donthineni */ 1669ebe2f871SShanker Donthineni if (!(gicc->flags & ACPI_MADT_ENABLED)) 1670ebe2f871SShanker Donthineni return 0; 1671ebe2f871SShanker Donthineni 1672b70fb7afSTomasz Nowicki return -ENODEV; 1673b70fb7afSTomasz Nowicki } 1674b70fb7afSTomasz Nowicki 1675b70fb7afSTomasz Nowicki static int __init gic_acpi_count_gicr_regions(void) 1676b70fb7afSTomasz Nowicki { 1677b70fb7afSTomasz Nowicki int count; 1678b70fb7afSTomasz Nowicki 1679b70fb7afSTomasz Nowicki /* 1680b70fb7afSTomasz Nowicki * Count how many redistributor regions we have. It is not allowed 1681b70fb7afSTomasz Nowicki * to mix redistributor description, GICR and GICC subtables have to be 1682b70fb7afSTomasz Nowicki * mutually exclusive. 1683b70fb7afSTomasz Nowicki */ 1684b70fb7afSTomasz Nowicki count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR, 1685b70fb7afSTomasz Nowicki gic_acpi_match_gicr, 0); 1686b70fb7afSTomasz Nowicki if (count > 0) { 1687611f039fSJulien Grall acpi_data.single_redist = false; 1688b70fb7afSTomasz Nowicki return count; 1689b70fb7afSTomasz Nowicki } 1690b70fb7afSTomasz Nowicki 1691b70fb7afSTomasz Nowicki count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT, 1692b70fb7afSTomasz Nowicki gic_acpi_match_gicc, 0); 1693b70fb7afSTomasz Nowicki if (count > 0) 1694611f039fSJulien Grall acpi_data.single_redist = true; 1695b70fb7afSTomasz Nowicki 1696b70fb7afSTomasz Nowicki return count; 1697b70fb7afSTomasz Nowicki } 1698b70fb7afSTomasz Nowicki 1699ffa7d616STomasz Nowicki static bool __init acpi_validate_gic_table(struct acpi_subtable_header *header, 1700ffa7d616STomasz Nowicki struct acpi_probe_entry *ape) 1701ffa7d616STomasz Nowicki { 1702ffa7d616STomasz Nowicki struct acpi_madt_generic_distributor *dist; 1703ffa7d616STomasz Nowicki int count; 1704ffa7d616STomasz Nowicki 1705ffa7d616STomasz Nowicki dist = (struct acpi_madt_generic_distributor *)header; 1706ffa7d616STomasz Nowicki if (dist->version != ape->driver_data) 1707ffa7d616STomasz Nowicki return false; 1708ffa7d616STomasz Nowicki 1709ffa7d616STomasz Nowicki /* We need to do that exercise anyway, the sooner the better */ 1710b70fb7afSTomasz Nowicki count = gic_acpi_count_gicr_regions(); 1711ffa7d616STomasz Nowicki if (count <= 0) 1712ffa7d616STomasz Nowicki return false; 1713ffa7d616STomasz Nowicki 1714611f039fSJulien Grall acpi_data.nr_redist_regions = count; 1715ffa7d616STomasz Nowicki return true; 1716ffa7d616STomasz Nowicki } 1717ffa7d616STomasz Nowicki 171860574d1eSKeith Busch static int __init gic_acpi_parse_virt_madt_gicc(union acpi_subtable_headers *header, 17191839e576SJulien Grall const unsigned long end) 17201839e576SJulien Grall { 17211839e576SJulien Grall struct acpi_madt_generic_interrupt *gicc = 17221839e576SJulien Grall (struct acpi_madt_generic_interrupt *)header; 17231839e576SJulien Grall int maint_irq_mode; 17241839e576SJulien Grall static int first_madt = true; 17251839e576SJulien Grall 17261839e576SJulien Grall /* Skip unusable CPUs */ 17271839e576SJulien Grall if (!(gicc->flags & ACPI_MADT_ENABLED)) 17281839e576SJulien Grall return 0; 17291839e576SJulien Grall 17301839e576SJulien Grall maint_irq_mode = (gicc->flags & ACPI_MADT_VGIC_IRQ_MODE) ? 17311839e576SJulien Grall ACPI_EDGE_SENSITIVE : ACPI_LEVEL_SENSITIVE; 17321839e576SJulien Grall 17331839e576SJulien Grall if (first_madt) { 17341839e576SJulien Grall first_madt = false; 17351839e576SJulien Grall 17361839e576SJulien Grall acpi_data.maint_irq = gicc->vgic_interrupt; 17371839e576SJulien Grall acpi_data.maint_irq_mode = maint_irq_mode; 17381839e576SJulien Grall acpi_data.vcpu_base = gicc->gicv_base_address; 17391839e576SJulien Grall 17401839e576SJulien Grall return 0; 17411839e576SJulien Grall } 17421839e576SJulien Grall 17431839e576SJulien Grall /* 17441839e576SJulien Grall * The maintenance interrupt and GICV should be the same for every CPU 17451839e576SJulien Grall */ 17461839e576SJulien Grall if ((acpi_data.maint_irq != gicc->vgic_interrupt) || 17471839e576SJulien Grall (acpi_data.maint_irq_mode != maint_irq_mode) || 17481839e576SJulien Grall (acpi_data.vcpu_base != gicc->gicv_base_address)) 17491839e576SJulien Grall return -EINVAL; 17501839e576SJulien Grall 17511839e576SJulien Grall return 0; 17521839e576SJulien Grall } 17531839e576SJulien Grall 17541839e576SJulien Grall static bool __init gic_acpi_collect_virt_info(void) 17551839e576SJulien Grall { 17561839e576SJulien Grall int count; 17571839e576SJulien Grall 17581839e576SJulien Grall count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT, 17591839e576SJulien Grall gic_acpi_parse_virt_madt_gicc, 0); 17601839e576SJulien Grall 17611839e576SJulien Grall return (count > 0); 17621839e576SJulien Grall } 17631839e576SJulien Grall 1764ffa7d616STomasz Nowicki #define ACPI_GICV3_DIST_MEM_SIZE (SZ_64K) 17651839e576SJulien Grall #define ACPI_GICV2_VCTRL_MEM_SIZE (SZ_4K) 17661839e576SJulien Grall #define ACPI_GICV2_VCPU_MEM_SIZE (SZ_8K) 17671839e576SJulien Grall 17681839e576SJulien Grall static void __init gic_acpi_setup_kvm_info(void) 17691839e576SJulien Grall { 17701839e576SJulien Grall int irq; 17711839e576SJulien Grall 17721839e576SJulien Grall if (!gic_acpi_collect_virt_info()) { 17731839e576SJulien Grall pr_warn("Unable to get hardware information used for virtualization\n"); 17741839e576SJulien Grall return; 17751839e576SJulien Grall } 17761839e576SJulien Grall 17771839e576SJulien Grall gic_v3_kvm_info.type = GIC_V3; 17781839e576SJulien Grall 17791839e576SJulien Grall irq = acpi_register_gsi(NULL, acpi_data.maint_irq, 17801839e576SJulien Grall acpi_data.maint_irq_mode, 17811839e576SJulien Grall ACPI_ACTIVE_HIGH); 17821839e576SJulien Grall if (irq <= 0) 17831839e576SJulien Grall return; 17841839e576SJulien Grall 17851839e576SJulien Grall gic_v3_kvm_info.maint_irq = irq; 17861839e576SJulien Grall 17871839e576SJulien Grall if (acpi_data.vcpu_base) { 17881839e576SJulien Grall struct resource *vcpu = &gic_v3_kvm_info.vcpu; 17891839e576SJulien Grall 17901839e576SJulien Grall vcpu->flags = IORESOURCE_MEM; 17911839e576SJulien Grall vcpu->start = acpi_data.vcpu_base; 17921839e576SJulien Grall vcpu->end = vcpu->start + ACPI_GICV2_VCPU_MEM_SIZE - 1; 17931839e576SJulien Grall } 17941839e576SJulien Grall 17954bdf5025SMarc Zyngier gic_v3_kvm_info.has_v4 = gic_data.rdists.has_vlpis; 17961839e576SJulien Grall gic_set_kvm_info(&gic_v3_kvm_info); 17971839e576SJulien Grall } 1798ffa7d616STomasz Nowicki 1799ffa7d616STomasz Nowicki static int __init 1800ffa7d616STomasz Nowicki gic_acpi_init(struct acpi_subtable_header *header, const unsigned long end) 1801ffa7d616STomasz Nowicki { 1802ffa7d616STomasz Nowicki struct acpi_madt_generic_distributor *dist; 1803ffa7d616STomasz Nowicki struct fwnode_handle *domain_handle; 1804611f039fSJulien Grall size_t size; 1805b70fb7afSTomasz Nowicki int i, err; 1806ffa7d616STomasz Nowicki 1807ffa7d616STomasz Nowicki /* Get distributor base address */ 1808ffa7d616STomasz Nowicki dist = (struct acpi_madt_generic_distributor *)header; 1809611f039fSJulien Grall acpi_data.dist_base = ioremap(dist->base_address, 1810611f039fSJulien Grall ACPI_GICV3_DIST_MEM_SIZE); 1811611f039fSJulien Grall if (!acpi_data.dist_base) { 1812ffa7d616STomasz Nowicki pr_err("Unable to map GICD registers\n"); 1813ffa7d616STomasz Nowicki return -ENOMEM; 1814ffa7d616STomasz Nowicki } 1815ffa7d616STomasz Nowicki 1816611f039fSJulien Grall err = gic_validate_dist_version(acpi_data.dist_base); 1817ffa7d616STomasz Nowicki if (err) { 181871192a68SArvind Yadav pr_err("No distributor detected at @%p, giving up\n", 1819611f039fSJulien Grall acpi_data.dist_base); 1820ffa7d616STomasz Nowicki goto out_dist_unmap; 1821ffa7d616STomasz Nowicki } 1822ffa7d616STomasz Nowicki 1823611f039fSJulien Grall size = sizeof(*acpi_data.redist_regs) * acpi_data.nr_redist_regions; 1824611f039fSJulien Grall acpi_data.redist_regs = kzalloc(size, GFP_KERNEL); 1825611f039fSJulien Grall if (!acpi_data.redist_regs) { 1826ffa7d616STomasz Nowicki err = -ENOMEM; 1827ffa7d616STomasz Nowicki goto out_dist_unmap; 1828ffa7d616STomasz Nowicki } 1829ffa7d616STomasz Nowicki 1830b70fb7afSTomasz Nowicki err = gic_acpi_collect_gicr_base(); 1831b70fb7afSTomasz Nowicki if (err) 1832ffa7d616STomasz Nowicki goto out_redist_unmap; 1833ffa7d616STomasz Nowicki 1834611f039fSJulien Grall domain_handle = irq_domain_alloc_fwnode(acpi_data.dist_base); 1835ffa7d616STomasz Nowicki if (!domain_handle) { 1836ffa7d616STomasz Nowicki err = -ENOMEM; 1837ffa7d616STomasz Nowicki goto out_redist_unmap; 1838ffa7d616STomasz Nowicki } 1839ffa7d616STomasz Nowicki 1840611f039fSJulien Grall err = gic_init_bases(acpi_data.dist_base, acpi_data.redist_regs, 1841611f039fSJulien Grall acpi_data.nr_redist_regions, 0, domain_handle); 1842ffa7d616STomasz Nowicki if (err) 1843ffa7d616STomasz Nowicki goto out_fwhandle_free; 1844ffa7d616STomasz Nowicki 1845ffa7d616STomasz Nowicki acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, domain_handle); 1846d33a3c8cSChristoffer Dall 1847d01d3274SDavidlohr Bueso if (static_branch_likely(&supports_deactivate_key)) 18481839e576SJulien Grall gic_acpi_setup_kvm_info(); 18491839e576SJulien Grall 1850ffa7d616STomasz Nowicki return 0; 1851ffa7d616STomasz Nowicki 1852ffa7d616STomasz Nowicki out_fwhandle_free: 1853ffa7d616STomasz Nowicki irq_domain_free_fwnode(domain_handle); 1854ffa7d616STomasz Nowicki out_redist_unmap: 1855611f039fSJulien Grall for (i = 0; i < acpi_data.nr_redist_regions; i++) 1856611f039fSJulien Grall if (acpi_data.redist_regs[i].redist_base) 1857611f039fSJulien Grall iounmap(acpi_data.redist_regs[i].redist_base); 1858611f039fSJulien Grall kfree(acpi_data.redist_regs); 1859ffa7d616STomasz Nowicki out_dist_unmap: 1860611f039fSJulien Grall iounmap(acpi_data.dist_base); 1861ffa7d616STomasz Nowicki return err; 1862ffa7d616STomasz Nowicki } 1863ffa7d616STomasz Nowicki IRQCHIP_ACPI_DECLARE(gic_v3, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 1864ffa7d616STomasz Nowicki acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V3, 1865ffa7d616STomasz Nowicki gic_acpi_init); 1866ffa7d616STomasz Nowicki IRQCHIP_ACPI_DECLARE(gic_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 1867ffa7d616STomasz Nowicki acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V4, 1868ffa7d616STomasz Nowicki gic_acpi_init); 1869ffa7d616STomasz Nowicki IRQCHIP_ACPI_DECLARE(gic_v3_or_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 1870ffa7d616STomasz Nowicki acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_NONE, 1871ffa7d616STomasz Nowicki gic_acpi_init); 1872ffa7d616STomasz Nowicki #endif 1873