1021f6537SMarc Zyngier /* 2021f6537SMarc Zyngier * Copyright (C) 2013, 2014 ARM Limited, All Rights Reserved. 3021f6537SMarc Zyngier * Author: Marc Zyngier <marc.zyngier@arm.com> 4021f6537SMarc Zyngier * 5021f6537SMarc Zyngier * This program is free software; you can redistribute it and/or modify 6021f6537SMarc Zyngier * it under the terms of the GNU General Public License version 2 as 7021f6537SMarc Zyngier * published by the Free Software Foundation. 8021f6537SMarc Zyngier * 9021f6537SMarc Zyngier * This program is distributed in the hope that it will be useful, 10021f6537SMarc Zyngier * but WITHOUT ANY WARRANTY; without even the implied warranty of 11021f6537SMarc Zyngier * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12021f6537SMarc Zyngier * GNU General Public License for more details. 13021f6537SMarc Zyngier * 14021f6537SMarc Zyngier * You should have received a copy of the GNU General Public License 15021f6537SMarc Zyngier * along with this program. If not, see <http://www.gnu.org/licenses/>. 16021f6537SMarc Zyngier */ 17021f6537SMarc Zyngier 18ffa7d616STomasz Nowicki #include <linux/acpi.h> 19021f6537SMarc Zyngier #include <linux/cpu.h> 203708d52fSSudeep Holla #include <linux/cpu_pm.h> 21021f6537SMarc Zyngier #include <linux/delay.h> 22021f6537SMarc Zyngier #include <linux/interrupt.h> 23ffa7d616STomasz Nowicki #include <linux/irqdomain.h> 24021f6537SMarc Zyngier #include <linux/of.h> 25021f6537SMarc Zyngier #include <linux/of_address.h> 26021f6537SMarc Zyngier #include <linux/of_irq.h> 27021f6537SMarc Zyngier #include <linux/percpu.h> 28021f6537SMarc Zyngier #include <linux/slab.h> 29021f6537SMarc Zyngier 3041a83e06SJoel Porquet #include <linux/irqchip.h> 31021f6537SMarc Zyngier #include <linux/irqchip/arm-gic-v3.h> 32021f6537SMarc Zyngier 33021f6537SMarc Zyngier #include <asm/cputype.h> 34021f6537SMarc Zyngier #include <asm/exception.h> 35021f6537SMarc Zyngier #include <asm/smp_plat.h> 360b6a3da9SMarc Zyngier #include <asm/virt.h> 37021f6537SMarc Zyngier 38021f6537SMarc Zyngier #include "irq-gic-common.h" 39021f6537SMarc Zyngier 40f5c1434cSMarc Zyngier struct redist_region { 41f5c1434cSMarc Zyngier void __iomem *redist_base; 42f5c1434cSMarc Zyngier phys_addr_t phys_base; 43b70fb7afSTomasz Nowicki bool single_redist; 44f5c1434cSMarc Zyngier }; 45f5c1434cSMarc Zyngier 46021f6537SMarc Zyngier struct gic_chip_data { 47021f6537SMarc Zyngier void __iomem *dist_base; 48f5c1434cSMarc Zyngier struct redist_region *redist_regions; 49f5c1434cSMarc Zyngier struct rdists rdists; 50021f6537SMarc Zyngier struct irq_domain *domain; 51021f6537SMarc Zyngier u64 redist_stride; 52f5c1434cSMarc Zyngier u32 nr_redist_regions; 53021f6537SMarc Zyngier unsigned int irq_nr; 54021f6537SMarc Zyngier }; 55021f6537SMarc Zyngier 56021f6537SMarc Zyngier static struct gic_chip_data gic_data __read_mostly; 570b6a3da9SMarc Zyngier static struct static_key supports_deactivate = STATIC_KEY_INIT_TRUE; 58021f6537SMarc Zyngier 59f5c1434cSMarc Zyngier #define gic_data_rdist() (this_cpu_ptr(gic_data.rdists.rdist)) 60f5c1434cSMarc Zyngier #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base) 61021f6537SMarc Zyngier #define gic_data_rdist_sgi_base() (gic_data_rdist_rd_base() + SZ_64K) 62021f6537SMarc Zyngier 63021f6537SMarc Zyngier /* Our default, arbitrary priority value. Linux only uses one anyway. */ 64021f6537SMarc Zyngier #define DEFAULT_PMR_VALUE 0xf0 65021f6537SMarc Zyngier 66021f6537SMarc Zyngier static inline unsigned int gic_irq(struct irq_data *d) 67021f6537SMarc Zyngier { 68021f6537SMarc Zyngier return d->hwirq; 69021f6537SMarc Zyngier } 70021f6537SMarc Zyngier 71021f6537SMarc Zyngier static inline int gic_irq_in_rdist(struct irq_data *d) 72021f6537SMarc Zyngier { 73021f6537SMarc Zyngier return gic_irq(d) < 32; 74021f6537SMarc Zyngier } 75021f6537SMarc Zyngier 76021f6537SMarc Zyngier static inline void __iomem *gic_dist_base(struct irq_data *d) 77021f6537SMarc Zyngier { 78021f6537SMarc Zyngier if (gic_irq_in_rdist(d)) /* SGI+PPI -> SGI_base for this CPU */ 79021f6537SMarc Zyngier return gic_data_rdist_sgi_base(); 80021f6537SMarc Zyngier 81021f6537SMarc Zyngier if (d->hwirq <= 1023) /* SPI -> dist_base */ 82021f6537SMarc Zyngier return gic_data.dist_base; 83021f6537SMarc Zyngier 84021f6537SMarc Zyngier return NULL; 85021f6537SMarc Zyngier } 86021f6537SMarc Zyngier 87021f6537SMarc Zyngier static void gic_do_wait_for_rwp(void __iomem *base) 88021f6537SMarc Zyngier { 89021f6537SMarc Zyngier u32 count = 1000000; /* 1s! */ 90021f6537SMarc Zyngier 91021f6537SMarc Zyngier while (readl_relaxed(base + GICD_CTLR) & GICD_CTLR_RWP) { 92021f6537SMarc Zyngier count--; 93021f6537SMarc Zyngier if (!count) { 94021f6537SMarc Zyngier pr_err_ratelimited("RWP timeout, gone fishing\n"); 95021f6537SMarc Zyngier return; 96021f6537SMarc Zyngier } 97021f6537SMarc Zyngier cpu_relax(); 98021f6537SMarc Zyngier udelay(1); 99021f6537SMarc Zyngier }; 100021f6537SMarc Zyngier } 101021f6537SMarc Zyngier 102021f6537SMarc Zyngier /* Wait for completion of a distributor change */ 103021f6537SMarc Zyngier static void gic_dist_wait_for_rwp(void) 104021f6537SMarc Zyngier { 105021f6537SMarc Zyngier gic_do_wait_for_rwp(gic_data.dist_base); 106021f6537SMarc Zyngier } 107021f6537SMarc Zyngier 108021f6537SMarc Zyngier /* Wait for completion of a redistributor change */ 109021f6537SMarc Zyngier static void gic_redist_wait_for_rwp(void) 110021f6537SMarc Zyngier { 111021f6537SMarc Zyngier gic_do_wait_for_rwp(gic_data_rdist_rd_base()); 112021f6537SMarc Zyngier } 113021f6537SMarc Zyngier 1147936e914SJean-Philippe Brucker #ifdef CONFIG_ARM64 1158ac2a170SRobert Richter static DEFINE_STATIC_KEY_FALSE(is_cavium_thunderx); 1166d4e11c5SRobert Richter 1176d4e11c5SRobert Richter static u64 __maybe_unused gic_read_iar(void) 1186d4e11c5SRobert Richter { 1198ac2a170SRobert Richter if (static_branch_unlikely(&is_cavium_thunderx)) 1206d4e11c5SRobert Richter return gic_read_iar_cavium_thunderx(); 1216d4e11c5SRobert Richter else 1226d4e11c5SRobert Richter return gic_read_iar_common(); 1236d4e11c5SRobert Richter } 1247936e914SJean-Philippe Brucker #endif 125021f6537SMarc Zyngier 126a2c22510SSudeep Holla static void gic_enable_redist(bool enable) 127021f6537SMarc Zyngier { 128021f6537SMarc Zyngier void __iomem *rbase; 129021f6537SMarc Zyngier u32 count = 1000000; /* 1s! */ 130021f6537SMarc Zyngier u32 val; 131021f6537SMarc Zyngier 132021f6537SMarc Zyngier rbase = gic_data_rdist_rd_base(); 133021f6537SMarc Zyngier 134021f6537SMarc Zyngier val = readl_relaxed(rbase + GICR_WAKER); 135a2c22510SSudeep Holla if (enable) 136a2c22510SSudeep Holla /* Wake up this CPU redistributor */ 137021f6537SMarc Zyngier val &= ~GICR_WAKER_ProcessorSleep; 138a2c22510SSudeep Holla else 139a2c22510SSudeep Holla val |= GICR_WAKER_ProcessorSleep; 140021f6537SMarc Zyngier writel_relaxed(val, rbase + GICR_WAKER); 141021f6537SMarc Zyngier 142a2c22510SSudeep Holla if (!enable) { /* Check that GICR_WAKER is writeable */ 143a2c22510SSudeep Holla val = readl_relaxed(rbase + GICR_WAKER); 144a2c22510SSudeep Holla if (!(val & GICR_WAKER_ProcessorSleep)) 145a2c22510SSudeep Holla return; /* No PM support in this redistributor */ 146021f6537SMarc Zyngier } 147a2c22510SSudeep Holla 148a2c22510SSudeep Holla while (count--) { 149a2c22510SSudeep Holla val = readl_relaxed(rbase + GICR_WAKER); 150a2c22510SSudeep Holla if (enable ^ (val & GICR_WAKER_ChildrenAsleep)) 151a2c22510SSudeep Holla break; 152021f6537SMarc Zyngier cpu_relax(); 153021f6537SMarc Zyngier udelay(1); 154021f6537SMarc Zyngier }; 155a2c22510SSudeep Holla if (!count) 156a2c22510SSudeep Holla pr_err_ratelimited("redistributor failed to %s...\n", 157a2c22510SSudeep Holla enable ? "wakeup" : "sleep"); 158021f6537SMarc Zyngier } 159021f6537SMarc Zyngier 160021f6537SMarc Zyngier /* 161021f6537SMarc Zyngier * Routines to disable, enable, EOI and route interrupts 162021f6537SMarc Zyngier */ 163b594c6e2SMarc Zyngier static int gic_peek_irq(struct irq_data *d, u32 offset) 164b594c6e2SMarc Zyngier { 165b594c6e2SMarc Zyngier u32 mask = 1 << (gic_irq(d) % 32); 166b594c6e2SMarc Zyngier void __iomem *base; 167b594c6e2SMarc Zyngier 168b594c6e2SMarc Zyngier if (gic_irq_in_rdist(d)) 169b594c6e2SMarc Zyngier base = gic_data_rdist_sgi_base(); 170b594c6e2SMarc Zyngier else 171b594c6e2SMarc Zyngier base = gic_data.dist_base; 172b594c6e2SMarc Zyngier 173b594c6e2SMarc Zyngier return !!(readl_relaxed(base + offset + (gic_irq(d) / 32) * 4) & mask); 174b594c6e2SMarc Zyngier } 175b594c6e2SMarc Zyngier 176021f6537SMarc Zyngier static void gic_poke_irq(struct irq_data *d, u32 offset) 177021f6537SMarc Zyngier { 178021f6537SMarc Zyngier u32 mask = 1 << (gic_irq(d) % 32); 179021f6537SMarc Zyngier void (*rwp_wait)(void); 180021f6537SMarc Zyngier void __iomem *base; 181021f6537SMarc Zyngier 182021f6537SMarc Zyngier if (gic_irq_in_rdist(d)) { 183021f6537SMarc Zyngier base = gic_data_rdist_sgi_base(); 184021f6537SMarc Zyngier rwp_wait = gic_redist_wait_for_rwp; 185021f6537SMarc Zyngier } else { 186021f6537SMarc Zyngier base = gic_data.dist_base; 187021f6537SMarc Zyngier rwp_wait = gic_dist_wait_for_rwp; 188021f6537SMarc Zyngier } 189021f6537SMarc Zyngier 190021f6537SMarc Zyngier writel_relaxed(mask, base + offset + (gic_irq(d) / 32) * 4); 191021f6537SMarc Zyngier rwp_wait(); 192021f6537SMarc Zyngier } 193021f6537SMarc Zyngier 194021f6537SMarc Zyngier static void gic_mask_irq(struct irq_data *d) 195021f6537SMarc Zyngier { 196021f6537SMarc Zyngier gic_poke_irq(d, GICD_ICENABLER); 197021f6537SMarc Zyngier } 198021f6537SMarc Zyngier 1990b6a3da9SMarc Zyngier static void gic_eoimode1_mask_irq(struct irq_data *d) 2000b6a3da9SMarc Zyngier { 2010b6a3da9SMarc Zyngier gic_mask_irq(d); 202530bf353SMarc Zyngier /* 203530bf353SMarc Zyngier * When masking a forwarded interrupt, make sure it is 204530bf353SMarc Zyngier * deactivated as well. 205530bf353SMarc Zyngier * 206530bf353SMarc Zyngier * This ensures that an interrupt that is getting 207530bf353SMarc Zyngier * disabled/masked will not get "stuck", because there is 208530bf353SMarc Zyngier * noone to deactivate it (guest is being terminated). 209530bf353SMarc Zyngier */ 2104df7f54dSThomas Gleixner if (irqd_is_forwarded_to_vcpu(d)) 211530bf353SMarc Zyngier gic_poke_irq(d, GICD_ICACTIVER); 2120b6a3da9SMarc Zyngier } 2130b6a3da9SMarc Zyngier 214021f6537SMarc Zyngier static void gic_unmask_irq(struct irq_data *d) 215021f6537SMarc Zyngier { 216021f6537SMarc Zyngier gic_poke_irq(d, GICD_ISENABLER); 217021f6537SMarc Zyngier } 218021f6537SMarc Zyngier 219b594c6e2SMarc Zyngier static int gic_irq_set_irqchip_state(struct irq_data *d, 220b594c6e2SMarc Zyngier enum irqchip_irq_state which, bool val) 221b594c6e2SMarc Zyngier { 222b594c6e2SMarc Zyngier u32 reg; 223b594c6e2SMarc Zyngier 224b594c6e2SMarc Zyngier if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */ 225b594c6e2SMarc Zyngier return -EINVAL; 226b594c6e2SMarc Zyngier 227b594c6e2SMarc Zyngier switch (which) { 228b594c6e2SMarc Zyngier case IRQCHIP_STATE_PENDING: 229b594c6e2SMarc Zyngier reg = val ? GICD_ISPENDR : GICD_ICPENDR; 230b594c6e2SMarc Zyngier break; 231b594c6e2SMarc Zyngier 232b594c6e2SMarc Zyngier case IRQCHIP_STATE_ACTIVE: 233b594c6e2SMarc Zyngier reg = val ? GICD_ISACTIVER : GICD_ICACTIVER; 234b594c6e2SMarc Zyngier break; 235b594c6e2SMarc Zyngier 236b594c6e2SMarc Zyngier case IRQCHIP_STATE_MASKED: 237b594c6e2SMarc Zyngier reg = val ? GICD_ICENABLER : GICD_ISENABLER; 238b594c6e2SMarc Zyngier break; 239b594c6e2SMarc Zyngier 240b594c6e2SMarc Zyngier default: 241b594c6e2SMarc Zyngier return -EINVAL; 242b594c6e2SMarc Zyngier } 243b594c6e2SMarc Zyngier 244b594c6e2SMarc Zyngier gic_poke_irq(d, reg); 245b594c6e2SMarc Zyngier return 0; 246b594c6e2SMarc Zyngier } 247b594c6e2SMarc Zyngier 248b594c6e2SMarc Zyngier static int gic_irq_get_irqchip_state(struct irq_data *d, 249b594c6e2SMarc Zyngier enum irqchip_irq_state which, bool *val) 250b594c6e2SMarc Zyngier { 251b594c6e2SMarc Zyngier if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */ 252b594c6e2SMarc Zyngier return -EINVAL; 253b594c6e2SMarc Zyngier 254b594c6e2SMarc Zyngier switch (which) { 255b594c6e2SMarc Zyngier case IRQCHIP_STATE_PENDING: 256b594c6e2SMarc Zyngier *val = gic_peek_irq(d, GICD_ISPENDR); 257b594c6e2SMarc Zyngier break; 258b594c6e2SMarc Zyngier 259b594c6e2SMarc Zyngier case IRQCHIP_STATE_ACTIVE: 260b594c6e2SMarc Zyngier *val = gic_peek_irq(d, GICD_ISACTIVER); 261b594c6e2SMarc Zyngier break; 262b594c6e2SMarc Zyngier 263b594c6e2SMarc Zyngier case IRQCHIP_STATE_MASKED: 264b594c6e2SMarc Zyngier *val = !gic_peek_irq(d, GICD_ISENABLER); 265b594c6e2SMarc Zyngier break; 266b594c6e2SMarc Zyngier 267b594c6e2SMarc Zyngier default: 268b594c6e2SMarc Zyngier return -EINVAL; 269b594c6e2SMarc Zyngier } 270b594c6e2SMarc Zyngier 271b594c6e2SMarc Zyngier return 0; 272b594c6e2SMarc Zyngier } 273b594c6e2SMarc Zyngier 274021f6537SMarc Zyngier static void gic_eoi_irq(struct irq_data *d) 275021f6537SMarc Zyngier { 276021f6537SMarc Zyngier gic_write_eoir(gic_irq(d)); 277021f6537SMarc Zyngier } 278021f6537SMarc Zyngier 2790b6a3da9SMarc Zyngier static void gic_eoimode1_eoi_irq(struct irq_data *d) 2800b6a3da9SMarc Zyngier { 2810b6a3da9SMarc Zyngier /* 282530bf353SMarc Zyngier * No need to deactivate an LPI, or an interrupt that 283530bf353SMarc Zyngier * is is getting forwarded to a vcpu. 2840b6a3da9SMarc Zyngier */ 2854df7f54dSThomas Gleixner if (gic_irq(d) >= 8192 || irqd_is_forwarded_to_vcpu(d)) 2860b6a3da9SMarc Zyngier return; 2870b6a3da9SMarc Zyngier gic_write_dir(gic_irq(d)); 2880b6a3da9SMarc Zyngier } 2890b6a3da9SMarc Zyngier 290021f6537SMarc Zyngier static int gic_set_type(struct irq_data *d, unsigned int type) 291021f6537SMarc Zyngier { 292021f6537SMarc Zyngier unsigned int irq = gic_irq(d); 293021f6537SMarc Zyngier void (*rwp_wait)(void); 294021f6537SMarc Zyngier void __iomem *base; 295021f6537SMarc Zyngier 296021f6537SMarc Zyngier /* Interrupt configuration for SGIs can't be changed */ 297021f6537SMarc Zyngier if (irq < 16) 298021f6537SMarc Zyngier return -EINVAL; 299021f6537SMarc Zyngier 300fb7e7debSLiviu Dudau /* SPIs have restrictions on the supported types */ 301fb7e7debSLiviu Dudau if (irq >= 32 && type != IRQ_TYPE_LEVEL_HIGH && 302fb7e7debSLiviu Dudau type != IRQ_TYPE_EDGE_RISING) 303021f6537SMarc Zyngier return -EINVAL; 304021f6537SMarc Zyngier 305021f6537SMarc Zyngier if (gic_irq_in_rdist(d)) { 306021f6537SMarc Zyngier base = gic_data_rdist_sgi_base(); 307021f6537SMarc Zyngier rwp_wait = gic_redist_wait_for_rwp; 308021f6537SMarc Zyngier } else { 309021f6537SMarc Zyngier base = gic_data.dist_base; 310021f6537SMarc Zyngier rwp_wait = gic_dist_wait_for_rwp; 311021f6537SMarc Zyngier } 312021f6537SMarc Zyngier 313fb7e7debSLiviu Dudau return gic_configure_irq(irq, type, base, rwp_wait); 314021f6537SMarc Zyngier } 315021f6537SMarc Zyngier 316530bf353SMarc Zyngier static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu) 317530bf353SMarc Zyngier { 3184df7f54dSThomas Gleixner if (vcpu) 3194df7f54dSThomas Gleixner irqd_set_forwarded_to_vcpu(d); 3204df7f54dSThomas Gleixner else 3214df7f54dSThomas Gleixner irqd_clr_forwarded_to_vcpu(d); 322530bf353SMarc Zyngier return 0; 323530bf353SMarc Zyngier } 324530bf353SMarc Zyngier 325f6c86a41SJean-Philippe Brucker static u64 gic_mpidr_to_affinity(unsigned long mpidr) 326021f6537SMarc Zyngier { 327021f6537SMarc Zyngier u64 aff; 328021f6537SMarc Zyngier 329f6c86a41SJean-Philippe Brucker aff = ((u64)MPIDR_AFFINITY_LEVEL(mpidr, 3) << 32 | 330021f6537SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 | 331021f6537SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | 332021f6537SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 0)); 333021f6537SMarc Zyngier 334021f6537SMarc Zyngier return aff; 335021f6537SMarc Zyngier } 336021f6537SMarc Zyngier 337021f6537SMarc Zyngier static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) 338021f6537SMarc Zyngier { 339f6c86a41SJean-Philippe Brucker u32 irqnr; 340021f6537SMarc Zyngier 341021f6537SMarc Zyngier do { 342021f6537SMarc Zyngier irqnr = gic_read_iar(); 343021f6537SMarc Zyngier 344da33f31dSMarc Zyngier if (likely(irqnr > 15 && irqnr < 1020) || irqnr >= 8192) { 345ebc6de00SMarc Zyngier int err; 3460b6a3da9SMarc Zyngier 3470b6a3da9SMarc Zyngier if (static_key_true(&supports_deactivate)) 3480b6a3da9SMarc Zyngier gic_write_eoir(irqnr); 3490b6a3da9SMarc Zyngier 350ebc6de00SMarc Zyngier err = handle_domain_irq(gic_data.domain, irqnr, regs); 351ebc6de00SMarc Zyngier if (err) { 352da33f31dSMarc Zyngier WARN_ONCE(true, "Unexpected interrupt received!\n"); 3530b6a3da9SMarc Zyngier if (static_key_true(&supports_deactivate)) { 3540b6a3da9SMarc Zyngier if (irqnr < 8192) 3550b6a3da9SMarc Zyngier gic_write_dir(irqnr); 3560b6a3da9SMarc Zyngier } else { 357021f6537SMarc Zyngier gic_write_eoir(irqnr); 358021f6537SMarc Zyngier } 3590b6a3da9SMarc Zyngier } 360ebc6de00SMarc Zyngier continue; 361ebc6de00SMarc Zyngier } 362021f6537SMarc Zyngier if (irqnr < 16) { 363021f6537SMarc Zyngier gic_write_eoir(irqnr); 3640b6a3da9SMarc Zyngier if (static_key_true(&supports_deactivate)) 3650b6a3da9SMarc Zyngier gic_write_dir(irqnr); 366021f6537SMarc Zyngier #ifdef CONFIG_SMP 367021f6537SMarc Zyngier handle_IPI(irqnr, regs); 368021f6537SMarc Zyngier #else 369021f6537SMarc Zyngier WARN_ONCE(true, "Unexpected SGI received!\n"); 370021f6537SMarc Zyngier #endif 371021f6537SMarc Zyngier continue; 372021f6537SMarc Zyngier } 373021f6537SMarc Zyngier } while (irqnr != ICC_IAR1_EL1_SPURIOUS); 374021f6537SMarc Zyngier } 375021f6537SMarc Zyngier 376021f6537SMarc Zyngier static void __init gic_dist_init(void) 377021f6537SMarc Zyngier { 378021f6537SMarc Zyngier unsigned int i; 379021f6537SMarc Zyngier u64 affinity; 380021f6537SMarc Zyngier void __iomem *base = gic_data.dist_base; 381021f6537SMarc Zyngier 382021f6537SMarc Zyngier /* Disable the distributor */ 383021f6537SMarc Zyngier writel_relaxed(0, base + GICD_CTLR); 384021f6537SMarc Zyngier gic_dist_wait_for_rwp(); 385021f6537SMarc Zyngier 386021f6537SMarc Zyngier gic_dist_config(base, gic_data.irq_nr, gic_dist_wait_for_rwp); 387021f6537SMarc Zyngier 388021f6537SMarc Zyngier /* Enable distributor with ARE, Group1 */ 389021f6537SMarc Zyngier writel_relaxed(GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G1A | GICD_CTLR_ENABLE_G1, 390021f6537SMarc Zyngier base + GICD_CTLR); 391021f6537SMarc Zyngier 392021f6537SMarc Zyngier /* 393021f6537SMarc Zyngier * Set all global interrupts to the boot CPU only. ARE must be 394021f6537SMarc Zyngier * enabled. 395021f6537SMarc Zyngier */ 396021f6537SMarc Zyngier affinity = gic_mpidr_to_affinity(cpu_logical_map(smp_processor_id())); 397021f6537SMarc Zyngier for (i = 32; i < gic_data.irq_nr; i++) 39872c97126SJean-Philippe Brucker gic_write_irouter(affinity, base + GICD_IROUTER + i * 8); 399021f6537SMarc Zyngier } 400021f6537SMarc Zyngier 401021f6537SMarc Zyngier static int gic_populate_rdist(void) 402021f6537SMarc Zyngier { 403f6c86a41SJean-Philippe Brucker unsigned long mpidr = cpu_logical_map(smp_processor_id()); 404021f6537SMarc Zyngier u64 typer; 405021f6537SMarc Zyngier u32 aff; 406021f6537SMarc Zyngier int i; 407021f6537SMarc Zyngier 408021f6537SMarc Zyngier /* 409021f6537SMarc Zyngier * Convert affinity to a 32bit value that can be matched to 410021f6537SMarc Zyngier * GICR_TYPER bits [63:32]. 411021f6537SMarc Zyngier */ 412021f6537SMarc Zyngier aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 24 | 413021f6537SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 | 414021f6537SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | 415021f6537SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 0)); 416021f6537SMarc Zyngier 417f5c1434cSMarc Zyngier for (i = 0; i < gic_data.nr_redist_regions; i++) { 418f5c1434cSMarc Zyngier void __iomem *ptr = gic_data.redist_regions[i].redist_base; 419021f6537SMarc Zyngier u32 reg; 420021f6537SMarc Zyngier 421021f6537SMarc Zyngier reg = readl_relaxed(ptr + GICR_PIDR2) & GIC_PIDR2_ARCH_MASK; 422021f6537SMarc Zyngier if (reg != GIC_PIDR2_ARCH_GICv3 && 423021f6537SMarc Zyngier reg != GIC_PIDR2_ARCH_GICv4) { /* We're in trouble... */ 424021f6537SMarc Zyngier pr_warn("No redistributor present @%p\n", ptr); 425021f6537SMarc Zyngier break; 426021f6537SMarc Zyngier } 427021f6537SMarc Zyngier 428021f6537SMarc Zyngier do { 42972c97126SJean-Philippe Brucker typer = gic_read_typer(ptr + GICR_TYPER); 430021f6537SMarc Zyngier if ((typer >> 32) == aff) { 431f5c1434cSMarc Zyngier u64 offset = ptr - gic_data.redist_regions[i].redist_base; 432021f6537SMarc Zyngier gic_data_rdist_rd_base() = ptr; 433f5c1434cSMarc Zyngier gic_data_rdist()->phys_base = gic_data.redist_regions[i].phys_base + offset; 434f6c86a41SJean-Philippe Brucker pr_info("CPU%d: found redistributor %lx region %d:%pa\n", 435f6c86a41SJean-Philippe Brucker smp_processor_id(), mpidr, i, 436f6c86a41SJean-Philippe Brucker &gic_data_rdist()->phys_base); 437021f6537SMarc Zyngier return 0; 438021f6537SMarc Zyngier } 439021f6537SMarc Zyngier 440b70fb7afSTomasz Nowicki if (gic_data.redist_regions[i].single_redist) 441b70fb7afSTomasz Nowicki break; 442b70fb7afSTomasz Nowicki 443021f6537SMarc Zyngier if (gic_data.redist_stride) { 444021f6537SMarc Zyngier ptr += gic_data.redist_stride; 445021f6537SMarc Zyngier } else { 446021f6537SMarc Zyngier ptr += SZ_64K * 2; /* Skip RD_base + SGI_base */ 447021f6537SMarc Zyngier if (typer & GICR_TYPER_VLPIS) 448021f6537SMarc Zyngier ptr += SZ_64K * 2; /* Skip VLPI_base + reserved page */ 449021f6537SMarc Zyngier } 450021f6537SMarc Zyngier } while (!(typer & GICR_TYPER_LAST)); 451021f6537SMarc Zyngier } 452021f6537SMarc Zyngier 453021f6537SMarc Zyngier /* We couldn't even deal with ourselves... */ 454f6c86a41SJean-Philippe Brucker WARN(true, "CPU%d: mpidr %lx has no re-distributor!\n", 455f6c86a41SJean-Philippe Brucker smp_processor_id(), mpidr); 456021f6537SMarc Zyngier return -ENODEV; 457021f6537SMarc Zyngier } 458021f6537SMarc Zyngier 4593708d52fSSudeep Holla static void gic_cpu_sys_reg_init(void) 460021f6537SMarc Zyngier { 4617cabd008SMarc Zyngier /* 4627cabd008SMarc Zyngier * Need to check that the SRE bit has actually been set. If 4637cabd008SMarc Zyngier * not, it means that SRE is disabled at EL2. We're going to 4647cabd008SMarc Zyngier * die painfully, and there is nothing we can do about it. 4657cabd008SMarc Zyngier * 4667cabd008SMarc Zyngier * Kindly inform the luser. 4677cabd008SMarc Zyngier */ 4687cabd008SMarc Zyngier if (!gic_enable_sre()) 4697cabd008SMarc Zyngier pr_err("GIC: unable to set SRE (disabled at EL2), panic ahead\n"); 470021f6537SMarc Zyngier 471021f6537SMarc Zyngier /* Set priority mask register */ 472021f6537SMarc Zyngier gic_write_pmr(DEFAULT_PMR_VALUE); 473021f6537SMarc Zyngier 4740b6a3da9SMarc Zyngier if (static_key_true(&supports_deactivate)) { 4750b6a3da9SMarc Zyngier /* EOI drops priority only (mode 1) */ 4760b6a3da9SMarc Zyngier gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop); 4770b6a3da9SMarc Zyngier } else { 478021f6537SMarc Zyngier /* EOI deactivates interrupt too (mode 0) */ 479021f6537SMarc Zyngier gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop_dir); 4800b6a3da9SMarc Zyngier } 481021f6537SMarc Zyngier 482021f6537SMarc Zyngier /* ... and let's hit the road... */ 483021f6537SMarc Zyngier gic_write_grpen1(1); 484021f6537SMarc Zyngier } 485021f6537SMarc Zyngier 486da33f31dSMarc Zyngier static int gic_dist_supports_lpis(void) 487da33f31dSMarc Zyngier { 488da33f31dSMarc Zyngier return !!(readl_relaxed(gic_data.dist_base + GICD_TYPER) & GICD_TYPER_LPIS); 489da33f31dSMarc Zyngier } 490da33f31dSMarc Zyngier 491021f6537SMarc Zyngier static void gic_cpu_init(void) 492021f6537SMarc Zyngier { 493021f6537SMarc Zyngier void __iomem *rbase; 494021f6537SMarc Zyngier 495021f6537SMarc Zyngier /* Register ourselves with the rest of the world */ 496021f6537SMarc Zyngier if (gic_populate_rdist()) 497021f6537SMarc Zyngier return; 498021f6537SMarc Zyngier 499a2c22510SSudeep Holla gic_enable_redist(true); 500021f6537SMarc Zyngier 501021f6537SMarc Zyngier rbase = gic_data_rdist_sgi_base(); 502021f6537SMarc Zyngier 503021f6537SMarc Zyngier gic_cpu_config(rbase, gic_redist_wait_for_rwp); 504021f6537SMarc Zyngier 505da33f31dSMarc Zyngier /* Give LPIs a spin */ 506da33f31dSMarc Zyngier if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis()) 507da33f31dSMarc Zyngier its_cpu_init(); 508da33f31dSMarc Zyngier 5093708d52fSSudeep Holla /* initialise system registers */ 5103708d52fSSudeep Holla gic_cpu_sys_reg_init(); 511021f6537SMarc Zyngier } 512021f6537SMarc Zyngier 513021f6537SMarc Zyngier #ifdef CONFIG_SMP 514021f6537SMarc Zyngier static int gic_secondary_init(struct notifier_block *nfb, 515021f6537SMarc Zyngier unsigned long action, void *hcpu) 516021f6537SMarc Zyngier { 517021f6537SMarc Zyngier if (action == CPU_STARTING || action == CPU_STARTING_FROZEN) 518021f6537SMarc Zyngier gic_cpu_init(); 519021f6537SMarc Zyngier return NOTIFY_OK; 520021f6537SMarc Zyngier } 521021f6537SMarc Zyngier 522021f6537SMarc Zyngier /* 523021f6537SMarc Zyngier * Notifier for enabling the GIC CPU interface. Set an arbitrarily high 524021f6537SMarc Zyngier * priority because the GIC needs to be up before the ARM generic timers. 525021f6537SMarc Zyngier */ 526021f6537SMarc Zyngier static struct notifier_block gic_cpu_notifier = { 527021f6537SMarc Zyngier .notifier_call = gic_secondary_init, 528021f6537SMarc Zyngier .priority = 100, 529021f6537SMarc Zyngier }; 530021f6537SMarc Zyngier 531021f6537SMarc Zyngier static u16 gic_compute_target_list(int *base_cpu, const struct cpumask *mask, 532f6c86a41SJean-Philippe Brucker unsigned long cluster_id) 533021f6537SMarc Zyngier { 534021f6537SMarc Zyngier int cpu = *base_cpu; 535f6c86a41SJean-Philippe Brucker unsigned long mpidr = cpu_logical_map(cpu); 536021f6537SMarc Zyngier u16 tlist = 0; 537021f6537SMarc Zyngier 538021f6537SMarc Zyngier while (cpu < nr_cpu_ids) { 539021f6537SMarc Zyngier /* 540021f6537SMarc Zyngier * If we ever get a cluster of more than 16 CPUs, just 541021f6537SMarc Zyngier * scream and skip that CPU. 542021f6537SMarc Zyngier */ 543021f6537SMarc Zyngier if (WARN_ON((mpidr & 0xff) >= 16)) 544021f6537SMarc Zyngier goto out; 545021f6537SMarc Zyngier 546021f6537SMarc Zyngier tlist |= 1 << (mpidr & 0xf); 547021f6537SMarc Zyngier 548021f6537SMarc Zyngier cpu = cpumask_next(cpu, mask); 549614be385SVladimir Murzin if (cpu >= nr_cpu_ids) 550021f6537SMarc Zyngier goto out; 551021f6537SMarc Zyngier 552021f6537SMarc Zyngier mpidr = cpu_logical_map(cpu); 553021f6537SMarc Zyngier 554021f6537SMarc Zyngier if (cluster_id != (mpidr & ~0xffUL)) { 555021f6537SMarc Zyngier cpu--; 556021f6537SMarc Zyngier goto out; 557021f6537SMarc Zyngier } 558021f6537SMarc Zyngier } 559021f6537SMarc Zyngier out: 560021f6537SMarc Zyngier *base_cpu = cpu; 561021f6537SMarc Zyngier return tlist; 562021f6537SMarc Zyngier } 563021f6537SMarc Zyngier 5647e580278SAndre Przywara #define MPIDR_TO_SGI_AFFINITY(cluster_id, level) \ 5657e580278SAndre Przywara (MPIDR_AFFINITY_LEVEL(cluster_id, level) \ 5667e580278SAndre Przywara << ICC_SGI1R_AFFINITY_## level ##_SHIFT) 5677e580278SAndre Przywara 568021f6537SMarc Zyngier static void gic_send_sgi(u64 cluster_id, u16 tlist, unsigned int irq) 569021f6537SMarc Zyngier { 570021f6537SMarc Zyngier u64 val; 571021f6537SMarc Zyngier 5727e580278SAndre Przywara val = (MPIDR_TO_SGI_AFFINITY(cluster_id, 3) | 5737e580278SAndre Przywara MPIDR_TO_SGI_AFFINITY(cluster_id, 2) | 5747e580278SAndre Przywara irq << ICC_SGI1R_SGI_ID_SHIFT | 5757e580278SAndre Przywara MPIDR_TO_SGI_AFFINITY(cluster_id, 1) | 5767e580278SAndre Przywara tlist << ICC_SGI1R_TARGET_LIST_SHIFT); 577021f6537SMarc Zyngier 578021f6537SMarc Zyngier pr_debug("CPU%d: ICC_SGI1R_EL1 %llx\n", smp_processor_id(), val); 579021f6537SMarc Zyngier gic_write_sgi1r(val); 580021f6537SMarc Zyngier } 581021f6537SMarc Zyngier 582021f6537SMarc Zyngier static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) 583021f6537SMarc Zyngier { 584021f6537SMarc Zyngier int cpu; 585021f6537SMarc Zyngier 586021f6537SMarc Zyngier if (WARN_ON(irq >= 16)) 587021f6537SMarc Zyngier return; 588021f6537SMarc Zyngier 589021f6537SMarc Zyngier /* 590021f6537SMarc Zyngier * Ensure that stores to Normal memory are visible to the 591021f6537SMarc Zyngier * other CPUs before issuing the IPI. 592021f6537SMarc Zyngier */ 593021f6537SMarc Zyngier smp_wmb(); 594021f6537SMarc Zyngier 595f9b531feSRusty Russell for_each_cpu(cpu, mask) { 596f6c86a41SJean-Philippe Brucker unsigned long cluster_id = cpu_logical_map(cpu) & ~0xffUL; 597021f6537SMarc Zyngier u16 tlist; 598021f6537SMarc Zyngier 599021f6537SMarc Zyngier tlist = gic_compute_target_list(&cpu, mask, cluster_id); 600021f6537SMarc Zyngier gic_send_sgi(cluster_id, tlist, irq); 601021f6537SMarc Zyngier } 602021f6537SMarc Zyngier 603021f6537SMarc Zyngier /* Force the above writes to ICC_SGI1R_EL1 to be executed */ 604021f6537SMarc Zyngier isb(); 605021f6537SMarc Zyngier } 606021f6537SMarc Zyngier 607021f6537SMarc Zyngier static void gic_smp_init(void) 608021f6537SMarc Zyngier { 609021f6537SMarc Zyngier set_smp_cross_call(gic_raise_softirq); 610021f6537SMarc Zyngier register_cpu_notifier(&gic_cpu_notifier); 611021f6537SMarc Zyngier } 612021f6537SMarc Zyngier 613021f6537SMarc Zyngier static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, 614021f6537SMarc Zyngier bool force) 615021f6537SMarc Zyngier { 616021f6537SMarc Zyngier unsigned int cpu = cpumask_any_and(mask_val, cpu_online_mask); 617021f6537SMarc Zyngier void __iomem *reg; 618021f6537SMarc Zyngier int enabled; 619021f6537SMarc Zyngier u64 val; 620021f6537SMarc Zyngier 621021f6537SMarc Zyngier if (gic_irq_in_rdist(d)) 622021f6537SMarc Zyngier return -EINVAL; 623021f6537SMarc Zyngier 624021f6537SMarc Zyngier /* If interrupt was enabled, disable it first */ 625021f6537SMarc Zyngier enabled = gic_peek_irq(d, GICD_ISENABLER); 626021f6537SMarc Zyngier if (enabled) 627021f6537SMarc Zyngier gic_mask_irq(d); 628021f6537SMarc Zyngier 629021f6537SMarc Zyngier reg = gic_dist_base(d) + GICD_IROUTER + (gic_irq(d) * 8); 630021f6537SMarc Zyngier val = gic_mpidr_to_affinity(cpu_logical_map(cpu)); 631021f6537SMarc Zyngier 63272c97126SJean-Philippe Brucker gic_write_irouter(val, reg); 633021f6537SMarc Zyngier 634021f6537SMarc Zyngier /* 635021f6537SMarc Zyngier * If the interrupt was enabled, enabled it again. Otherwise, 636021f6537SMarc Zyngier * just wait for the distributor to have digested our changes. 637021f6537SMarc Zyngier */ 638021f6537SMarc Zyngier if (enabled) 639021f6537SMarc Zyngier gic_unmask_irq(d); 640021f6537SMarc Zyngier else 641021f6537SMarc Zyngier gic_dist_wait_for_rwp(); 642021f6537SMarc Zyngier 643021f6537SMarc Zyngier return IRQ_SET_MASK_OK; 644021f6537SMarc Zyngier } 645021f6537SMarc Zyngier #else 646021f6537SMarc Zyngier #define gic_set_affinity NULL 647021f6537SMarc Zyngier #define gic_smp_init() do { } while(0) 648021f6537SMarc Zyngier #endif 649021f6537SMarc Zyngier 6503708d52fSSudeep Holla #ifdef CONFIG_CPU_PM 6513708d52fSSudeep Holla static int gic_cpu_pm_notifier(struct notifier_block *self, 6523708d52fSSudeep Holla unsigned long cmd, void *v) 6533708d52fSSudeep Holla { 6543708d52fSSudeep Holla if (cmd == CPU_PM_EXIT) { 6553708d52fSSudeep Holla gic_enable_redist(true); 6563708d52fSSudeep Holla gic_cpu_sys_reg_init(); 6573708d52fSSudeep Holla } else if (cmd == CPU_PM_ENTER) { 6583708d52fSSudeep Holla gic_write_grpen1(0); 6593708d52fSSudeep Holla gic_enable_redist(false); 6603708d52fSSudeep Holla } 6613708d52fSSudeep Holla return NOTIFY_OK; 6623708d52fSSudeep Holla } 6633708d52fSSudeep Holla 6643708d52fSSudeep Holla static struct notifier_block gic_cpu_pm_notifier_block = { 6653708d52fSSudeep Holla .notifier_call = gic_cpu_pm_notifier, 6663708d52fSSudeep Holla }; 6673708d52fSSudeep Holla 6683708d52fSSudeep Holla static void gic_cpu_pm_init(void) 6693708d52fSSudeep Holla { 6703708d52fSSudeep Holla cpu_pm_register_notifier(&gic_cpu_pm_notifier_block); 6713708d52fSSudeep Holla } 6723708d52fSSudeep Holla 6733708d52fSSudeep Holla #else 6743708d52fSSudeep Holla static inline void gic_cpu_pm_init(void) { } 6753708d52fSSudeep Holla #endif /* CONFIG_CPU_PM */ 6763708d52fSSudeep Holla 677021f6537SMarc Zyngier static struct irq_chip gic_chip = { 678021f6537SMarc Zyngier .name = "GICv3", 679021f6537SMarc Zyngier .irq_mask = gic_mask_irq, 680021f6537SMarc Zyngier .irq_unmask = gic_unmask_irq, 681021f6537SMarc Zyngier .irq_eoi = gic_eoi_irq, 682021f6537SMarc Zyngier .irq_set_type = gic_set_type, 683021f6537SMarc Zyngier .irq_set_affinity = gic_set_affinity, 684b594c6e2SMarc Zyngier .irq_get_irqchip_state = gic_irq_get_irqchip_state, 685b594c6e2SMarc Zyngier .irq_set_irqchip_state = gic_irq_set_irqchip_state, 68655963c9fSSudeep Holla .flags = IRQCHIP_SET_TYPE_MASKED, 687021f6537SMarc Zyngier }; 688021f6537SMarc Zyngier 6890b6a3da9SMarc Zyngier static struct irq_chip gic_eoimode1_chip = { 6900b6a3da9SMarc Zyngier .name = "GICv3", 6910b6a3da9SMarc Zyngier .irq_mask = gic_eoimode1_mask_irq, 6920b6a3da9SMarc Zyngier .irq_unmask = gic_unmask_irq, 6930b6a3da9SMarc Zyngier .irq_eoi = gic_eoimode1_eoi_irq, 6940b6a3da9SMarc Zyngier .irq_set_type = gic_set_type, 6950b6a3da9SMarc Zyngier .irq_set_affinity = gic_set_affinity, 6960b6a3da9SMarc Zyngier .irq_get_irqchip_state = gic_irq_get_irqchip_state, 6970b6a3da9SMarc Zyngier .irq_set_irqchip_state = gic_irq_set_irqchip_state, 698530bf353SMarc Zyngier .irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity, 6990b6a3da9SMarc Zyngier .flags = IRQCHIP_SET_TYPE_MASKED, 7000b6a3da9SMarc Zyngier }; 7010b6a3da9SMarc Zyngier 702da33f31dSMarc Zyngier #define GIC_ID_NR (1U << gic_data.rdists.id_bits) 703da33f31dSMarc Zyngier 704021f6537SMarc Zyngier static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq, 705021f6537SMarc Zyngier irq_hw_number_t hw) 706021f6537SMarc Zyngier { 7070b6a3da9SMarc Zyngier struct irq_chip *chip = &gic_chip; 7080b6a3da9SMarc Zyngier 7090b6a3da9SMarc Zyngier if (static_key_true(&supports_deactivate)) 7100b6a3da9SMarc Zyngier chip = &gic_eoimode1_chip; 7110b6a3da9SMarc Zyngier 712021f6537SMarc Zyngier /* SGIs are private to the core kernel */ 713021f6537SMarc Zyngier if (hw < 16) 714021f6537SMarc Zyngier return -EPERM; 715da33f31dSMarc Zyngier /* Nothing here */ 716da33f31dSMarc Zyngier if (hw >= gic_data.irq_nr && hw < 8192) 717da33f31dSMarc Zyngier return -EPERM; 718da33f31dSMarc Zyngier /* Off limits */ 719da33f31dSMarc Zyngier if (hw >= GIC_ID_NR) 720da33f31dSMarc Zyngier return -EPERM; 721da33f31dSMarc Zyngier 722021f6537SMarc Zyngier /* PPIs */ 723021f6537SMarc Zyngier if (hw < 32) { 724021f6537SMarc Zyngier irq_set_percpu_devid(irq); 7250b6a3da9SMarc Zyngier irq_domain_set_info(d, irq, hw, chip, d->host_data, 726443acc4fSMarc Zyngier handle_percpu_devid_irq, NULL, NULL); 727d17cab44SRob Herring irq_set_status_flags(irq, IRQ_NOAUTOEN); 728021f6537SMarc Zyngier } 729021f6537SMarc Zyngier /* SPIs */ 730021f6537SMarc Zyngier if (hw >= 32 && hw < gic_data.irq_nr) { 7310b6a3da9SMarc Zyngier irq_domain_set_info(d, irq, hw, chip, d->host_data, 732443acc4fSMarc Zyngier handle_fasteoi_irq, NULL, NULL); 733d17cab44SRob Herring irq_set_probe(irq); 734021f6537SMarc Zyngier } 735da33f31dSMarc Zyngier /* LPIs */ 736da33f31dSMarc Zyngier if (hw >= 8192 && hw < GIC_ID_NR) { 737da33f31dSMarc Zyngier if (!gic_dist_supports_lpis()) 738da33f31dSMarc Zyngier return -EPERM; 7390b6a3da9SMarc Zyngier irq_domain_set_info(d, irq, hw, chip, d->host_data, 740da33f31dSMarc Zyngier handle_fasteoi_irq, NULL, NULL); 741da33f31dSMarc Zyngier } 742da33f31dSMarc Zyngier 743021f6537SMarc Zyngier return 0; 744021f6537SMarc Zyngier } 745021f6537SMarc Zyngier 746f833f57fSMarc Zyngier static int gic_irq_domain_translate(struct irq_domain *d, 747f833f57fSMarc Zyngier struct irq_fwspec *fwspec, 748f833f57fSMarc Zyngier unsigned long *hwirq, 749f833f57fSMarc Zyngier unsigned int *type) 750021f6537SMarc Zyngier { 751f833f57fSMarc Zyngier if (is_of_node(fwspec->fwnode)) { 752f833f57fSMarc Zyngier if (fwspec->param_count < 3) 753021f6537SMarc Zyngier return -EINVAL; 754021f6537SMarc Zyngier 755db8c70ecSMarc Zyngier switch (fwspec->param[0]) { 756db8c70ecSMarc Zyngier case 0: /* SPI */ 757db8c70ecSMarc Zyngier *hwirq = fwspec->param[1] + 32; 758db8c70ecSMarc Zyngier break; 759db8c70ecSMarc Zyngier case 1: /* PPI */ 760f833f57fSMarc Zyngier *hwirq = fwspec->param[1] + 16; 761db8c70ecSMarc Zyngier break; 762db8c70ecSMarc Zyngier case GIC_IRQ_TYPE_LPI: /* LPI */ 763db8c70ecSMarc Zyngier *hwirq = fwspec->param[1]; 764db8c70ecSMarc Zyngier break; 765db8c70ecSMarc Zyngier default: 766db8c70ecSMarc Zyngier return -EINVAL; 767db8c70ecSMarc Zyngier } 768f833f57fSMarc Zyngier 769f833f57fSMarc Zyngier *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; 770f833f57fSMarc Zyngier return 0; 771021f6537SMarc Zyngier } 772021f6537SMarc Zyngier 773ffa7d616STomasz Nowicki if (is_fwnode_irqchip(fwspec->fwnode)) { 774ffa7d616STomasz Nowicki if(fwspec->param_count != 2) 775ffa7d616STomasz Nowicki return -EINVAL; 776ffa7d616STomasz Nowicki 777ffa7d616STomasz Nowicki *hwirq = fwspec->param[0]; 778ffa7d616STomasz Nowicki *type = fwspec->param[1]; 779ffa7d616STomasz Nowicki return 0; 780ffa7d616STomasz Nowicki } 781ffa7d616STomasz Nowicki 782f833f57fSMarc Zyngier return -EINVAL; 783021f6537SMarc Zyngier } 784021f6537SMarc Zyngier 785443acc4fSMarc Zyngier static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, 786443acc4fSMarc Zyngier unsigned int nr_irqs, void *arg) 787443acc4fSMarc Zyngier { 788443acc4fSMarc Zyngier int i, ret; 789443acc4fSMarc Zyngier irq_hw_number_t hwirq; 790443acc4fSMarc Zyngier unsigned int type = IRQ_TYPE_NONE; 791f833f57fSMarc Zyngier struct irq_fwspec *fwspec = arg; 792443acc4fSMarc Zyngier 793f833f57fSMarc Zyngier ret = gic_irq_domain_translate(domain, fwspec, &hwirq, &type); 794443acc4fSMarc Zyngier if (ret) 795443acc4fSMarc Zyngier return ret; 796443acc4fSMarc Zyngier 797443acc4fSMarc Zyngier for (i = 0; i < nr_irqs; i++) 798443acc4fSMarc Zyngier gic_irq_domain_map(domain, virq + i, hwirq + i); 799443acc4fSMarc Zyngier 800443acc4fSMarc Zyngier return 0; 801443acc4fSMarc Zyngier } 802443acc4fSMarc Zyngier 803443acc4fSMarc Zyngier static void gic_irq_domain_free(struct irq_domain *domain, unsigned int virq, 804443acc4fSMarc Zyngier unsigned int nr_irqs) 805443acc4fSMarc Zyngier { 806443acc4fSMarc Zyngier int i; 807443acc4fSMarc Zyngier 808443acc4fSMarc Zyngier for (i = 0; i < nr_irqs; i++) { 809443acc4fSMarc Zyngier struct irq_data *d = irq_domain_get_irq_data(domain, virq + i); 810443acc4fSMarc Zyngier irq_set_handler(virq + i, NULL); 811443acc4fSMarc Zyngier irq_domain_reset_irq_data(d); 812443acc4fSMarc Zyngier } 813443acc4fSMarc Zyngier } 814443acc4fSMarc Zyngier 815021f6537SMarc Zyngier static const struct irq_domain_ops gic_irq_domain_ops = { 816f833f57fSMarc Zyngier .translate = gic_irq_domain_translate, 817443acc4fSMarc Zyngier .alloc = gic_irq_domain_alloc, 818443acc4fSMarc Zyngier .free = gic_irq_domain_free, 819021f6537SMarc Zyngier }; 820021f6537SMarc Zyngier 8216d4e11c5SRobert Richter static void gicv3_enable_quirks(void) 8226d4e11c5SRobert Richter { 8237936e914SJean-Philippe Brucker #ifdef CONFIG_ARM64 8246d4e11c5SRobert Richter if (cpus_have_cap(ARM64_WORKAROUND_CAVIUM_23154)) 8258ac2a170SRobert Richter static_branch_enable(&is_cavium_thunderx); 8267936e914SJean-Philippe Brucker #endif 8276d4e11c5SRobert Richter } 8286d4e11c5SRobert Richter 829db57d746STomasz Nowicki static int __init gic_init_bases(void __iomem *dist_base, 830db57d746STomasz Nowicki struct redist_region *rdist_regs, 831db57d746STomasz Nowicki u32 nr_redist_regions, 832db57d746STomasz Nowicki u64 redist_stride, 833db57d746STomasz Nowicki struct fwnode_handle *handle) 834db57d746STomasz Nowicki { 835db57d746STomasz Nowicki struct device_node *node; 836db57d746STomasz Nowicki u32 typer; 837db57d746STomasz Nowicki int gic_irqs; 838db57d746STomasz Nowicki int err; 839db57d746STomasz Nowicki 840db57d746STomasz Nowicki if (!is_hyp_mode_available()) 841db57d746STomasz Nowicki static_key_slow_dec(&supports_deactivate); 842db57d746STomasz Nowicki 843db57d746STomasz Nowicki if (static_key_true(&supports_deactivate)) 844db57d746STomasz Nowicki pr_info("GIC: Using split EOI/Deactivate mode\n"); 845db57d746STomasz Nowicki 846db57d746STomasz Nowicki gic_data.dist_base = dist_base; 847db57d746STomasz Nowicki gic_data.redist_regions = rdist_regs; 848db57d746STomasz Nowicki gic_data.nr_redist_regions = nr_redist_regions; 849db57d746STomasz Nowicki gic_data.redist_stride = redist_stride; 850db57d746STomasz Nowicki 851db57d746STomasz Nowicki gicv3_enable_quirks(); 852db57d746STomasz Nowicki 853db57d746STomasz Nowicki /* 854db57d746STomasz Nowicki * Find out how many interrupts are supported. 855db57d746STomasz Nowicki * The GIC only supports up to 1020 interrupt sources (SGI+PPI+SPI) 856db57d746STomasz Nowicki */ 857db57d746STomasz Nowicki typer = readl_relaxed(gic_data.dist_base + GICD_TYPER); 858db57d746STomasz Nowicki gic_data.rdists.id_bits = GICD_TYPER_ID_BITS(typer); 859db57d746STomasz Nowicki gic_irqs = GICD_TYPER_IRQS(typer); 860db57d746STomasz Nowicki if (gic_irqs > 1020) 861db57d746STomasz Nowicki gic_irqs = 1020; 862db57d746STomasz Nowicki gic_data.irq_nr = gic_irqs; 863db57d746STomasz Nowicki 864db57d746STomasz Nowicki gic_data.domain = irq_domain_create_tree(handle, &gic_irq_domain_ops, 865db57d746STomasz Nowicki &gic_data); 866db57d746STomasz Nowicki gic_data.rdists.rdist = alloc_percpu(typeof(*gic_data.rdists.rdist)); 867db57d746STomasz Nowicki 868db57d746STomasz Nowicki if (WARN_ON(!gic_data.domain) || WARN_ON(!gic_data.rdists.rdist)) { 869db57d746STomasz Nowicki err = -ENOMEM; 870db57d746STomasz Nowicki goto out_free; 871db57d746STomasz Nowicki } 872db57d746STomasz Nowicki 873db57d746STomasz Nowicki set_handle_irq(gic_handle_irq); 874db57d746STomasz Nowicki 875db57d746STomasz Nowicki node = to_of_node(handle); 876db57d746STomasz Nowicki if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis() && 877db57d746STomasz Nowicki node) /* Temp hack to prevent ITS init for ACPI */ 878db57d746STomasz Nowicki its_init(node, &gic_data.rdists, gic_data.domain); 879db57d746STomasz Nowicki 880db57d746STomasz Nowicki gic_smp_init(); 881db57d746STomasz Nowicki gic_dist_init(); 882db57d746STomasz Nowicki gic_cpu_init(); 883db57d746STomasz Nowicki gic_cpu_pm_init(); 884db57d746STomasz Nowicki 885db57d746STomasz Nowicki return 0; 886db57d746STomasz Nowicki 887db57d746STomasz Nowicki out_free: 888db57d746STomasz Nowicki if (gic_data.domain) 889db57d746STomasz Nowicki irq_domain_remove(gic_data.domain); 890db57d746STomasz Nowicki free_percpu(gic_data.rdists.rdist); 891db57d746STomasz Nowicki return err; 892db57d746STomasz Nowicki } 893db57d746STomasz Nowicki 894db57d746STomasz Nowicki static int __init gic_validate_dist_version(void __iomem *dist_base) 895db57d746STomasz Nowicki { 896db57d746STomasz Nowicki u32 reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK; 897db57d746STomasz Nowicki 898db57d746STomasz Nowicki if (reg != GIC_PIDR2_ARCH_GICv3 && reg != GIC_PIDR2_ARCH_GICv4) 899db57d746STomasz Nowicki return -ENODEV; 900db57d746STomasz Nowicki 901db57d746STomasz Nowicki return 0; 902db57d746STomasz Nowicki } 903db57d746STomasz Nowicki 904021f6537SMarc Zyngier static int __init gic_of_init(struct device_node *node, struct device_node *parent) 905021f6537SMarc Zyngier { 906021f6537SMarc Zyngier void __iomem *dist_base; 907f5c1434cSMarc Zyngier struct redist_region *rdist_regs; 908021f6537SMarc Zyngier u64 redist_stride; 909f5c1434cSMarc Zyngier u32 nr_redist_regions; 910db57d746STomasz Nowicki int err, i; 911021f6537SMarc Zyngier 912021f6537SMarc Zyngier dist_base = of_iomap(node, 0); 913021f6537SMarc Zyngier if (!dist_base) { 914021f6537SMarc Zyngier pr_err("%s: unable to map gic dist registers\n", 915021f6537SMarc Zyngier node->full_name); 916021f6537SMarc Zyngier return -ENXIO; 917021f6537SMarc Zyngier } 918021f6537SMarc Zyngier 919db57d746STomasz Nowicki err = gic_validate_dist_version(dist_base); 920db57d746STomasz Nowicki if (err) { 921021f6537SMarc Zyngier pr_err("%s: no distributor detected, giving up\n", 922021f6537SMarc Zyngier node->full_name); 923021f6537SMarc Zyngier goto out_unmap_dist; 924021f6537SMarc Zyngier } 925021f6537SMarc Zyngier 926f5c1434cSMarc Zyngier if (of_property_read_u32(node, "#redistributor-regions", &nr_redist_regions)) 927f5c1434cSMarc Zyngier nr_redist_regions = 1; 928021f6537SMarc Zyngier 929f5c1434cSMarc Zyngier rdist_regs = kzalloc(sizeof(*rdist_regs) * nr_redist_regions, GFP_KERNEL); 930f5c1434cSMarc Zyngier if (!rdist_regs) { 931021f6537SMarc Zyngier err = -ENOMEM; 932021f6537SMarc Zyngier goto out_unmap_dist; 933021f6537SMarc Zyngier } 934021f6537SMarc Zyngier 935f5c1434cSMarc Zyngier for (i = 0; i < nr_redist_regions; i++) { 936f5c1434cSMarc Zyngier struct resource res; 937f5c1434cSMarc Zyngier int ret; 938f5c1434cSMarc Zyngier 939f5c1434cSMarc Zyngier ret = of_address_to_resource(node, 1 + i, &res); 940f5c1434cSMarc Zyngier rdist_regs[i].redist_base = of_iomap(node, 1 + i); 941f5c1434cSMarc Zyngier if (ret || !rdist_regs[i].redist_base) { 942021f6537SMarc Zyngier pr_err("%s: couldn't map region %d\n", 943021f6537SMarc Zyngier node->full_name, i); 944021f6537SMarc Zyngier err = -ENODEV; 945021f6537SMarc Zyngier goto out_unmap_rdist; 946021f6537SMarc Zyngier } 947f5c1434cSMarc Zyngier rdist_regs[i].phys_base = res.start; 948021f6537SMarc Zyngier } 949021f6537SMarc Zyngier 950021f6537SMarc Zyngier if (of_property_read_u64(node, "redistributor-stride", &redist_stride)) 951021f6537SMarc Zyngier redist_stride = 0; 952021f6537SMarc Zyngier 953db57d746STomasz Nowicki err = gic_init_bases(dist_base, rdist_regs, nr_redist_regions, 954db57d746STomasz Nowicki redist_stride, &node->fwnode); 955db57d746STomasz Nowicki if (!err) 956021f6537SMarc Zyngier return 0; 957021f6537SMarc Zyngier 958021f6537SMarc Zyngier out_unmap_rdist: 959f5c1434cSMarc Zyngier for (i = 0; i < nr_redist_regions; i++) 960f5c1434cSMarc Zyngier if (rdist_regs[i].redist_base) 961f5c1434cSMarc Zyngier iounmap(rdist_regs[i].redist_base); 962f5c1434cSMarc Zyngier kfree(rdist_regs); 963021f6537SMarc Zyngier out_unmap_dist: 964021f6537SMarc Zyngier iounmap(dist_base); 965021f6537SMarc Zyngier return err; 966021f6537SMarc Zyngier } 967021f6537SMarc Zyngier 968021f6537SMarc Zyngier IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init); 969ffa7d616STomasz Nowicki 970ffa7d616STomasz Nowicki #ifdef CONFIG_ACPI 971b70fb7afSTomasz Nowicki static void __iomem *dist_base; 972ffa7d616STomasz Nowicki static struct redist_region *redist_regs __initdata; 973ffa7d616STomasz Nowicki static u32 nr_redist_regions __initdata; 974b70fb7afSTomasz Nowicki static bool single_redist; 975b70fb7afSTomasz Nowicki 976b70fb7afSTomasz Nowicki static void __init 977b70fb7afSTomasz Nowicki gic_acpi_register_redist(phys_addr_t phys_base, void __iomem *redist_base) 978b70fb7afSTomasz Nowicki { 979b70fb7afSTomasz Nowicki static int count = 0; 980b70fb7afSTomasz Nowicki 981b70fb7afSTomasz Nowicki redist_regs[count].phys_base = phys_base; 982b70fb7afSTomasz Nowicki redist_regs[count].redist_base = redist_base; 983b70fb7afSTomasz Nowicki redist_regs[count].single_redist = single_redist; 984b70fb7afSTomasz Nowicki count++; 985b70fb7afSTomasz Nowicki } 986ffa7d616STomasz Nowicki 987ffa7d616STomasz Nowicki static int __init 988ffa7d616STomasz Nowicki gic_acpi_parse_madt_redist(struct acpi_subtable_header *header, 989ffa7d616STomasz Nowicki const unsigned long end) 990ffa7d616STomasz Nowicki { 991ffa7d616STomasz Nowicki struct acpi_madt_generic_redistributor *redist = 992ffa7d616STomasz Nowicki (struct acpi_madt_generic_redistributor *)header; 993ffa7d616STomasz Nowicki void __iomem *redist_base; 994ffa7d616STomasz Nowicki 995ffa7d616STomasz Nowicki redist_base = ioremap(redist->base_address, redist->length); 996ffa7d616STomasz Nowicki if (!redist_base) { 997ffa7d616STomasz Nowicki pr_err("Couldn't map GICR region @%llx\n", redist->base_address); 998ffa7d616STomasz Nowicki return -ENOMEM; 999ffa7d616STomasz Nowicki } 1000ffa7d616STomasz Nowicki 1001b70fb7afSTomasz Nowicki gic_acpi_register_redist(redist->base_address, redist_base); 1002ffa7d616STomasz Nowicki return 0; 1003ffa7d616STomasz Nowicki } 1004ffa7d616STomasz Nowicki 1005b70fb7afSTomasz Nowicki static int __init 1006b70fb7afSTomasz Nowicki gic_acpi_parse_madt_gicc(struct acpi_subtable_header *header, 1007b70fb7afSTomasz Nowicki const unsigned long end) 1008b70fb7afSTomasz Nowicki { 1009b70fb7afSTomasz Nowicki struct acpi_madt_generic_interrupt *gicc = 1010b70fb7afSTomasz Nowicki (struct acpi_madt_generic_interrupt *)header; 1011b70fb7afSTomasz Nowicki u32 reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK; 1012b70fb7afSTomasz Nowicki u32 size = reg == GIC_PIDR2_ARCH_GICv4 ? SZ_64K * 4 : SZ_64K * 2; 1013b70fb7afSTomasz Nowicki void __iomem *redist_base; 1014b70fb7afSTomasz Nowicki 1015b70fb7afSTomasz Nowicki redist_base = ioremap(gicc->gicr_base_address, size); 1016b70fb7afSTomasz Nowicki if (!redist_base) 1017b70fb7afSTomasz Nowicki return -ENOMEM; 1018b70fb7afSTomasz Nowicki 1019b70fb7afSTomasz Nowicki gic_acpi_register_redist(gicc->gicr_base_address, redist_base); 1020b70fb7afSTomasz Nowicki return 0; 1021b70fb7afSTomasz Nowicki } 1022b70fb7afSTomasz Nowicki 1023b70fb7afSTomasz Nowicki static int __init gic_acpi_collect_gicr_base(void) 1024b70fb7afSTomasz Nowicki { 1025b70fb7afSTomasz Nowicki acpi_tbl_entry_handler redist_parser; 1026b70fb7afSTomasz Nowicki enum acpi_madt_type type; 1027b70fb7afSTomasz Nowicki 1028b70fb7afSTomasz Nowicki if (single_redist) { 1029b70fb7afSTomasz Nowicki type = ACPI_MADT_TYPE_GENERIC_INTERRUPT; 1030b70fb7afSTomasz Nowicki redist_parser = gic_acpi_parse_madt_gicc; 1031b70fb7afSTomasz Nowicki } else { 1032b70fb7afSTomasz Nowicki type = ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR; 1033b70fb7afSTomasz Nowicki redist_parser = gic_acpi_parse_madt_redist; 1034b70fb7afSTomasz Nowicki } 1035b70fb7afSTomasz Nowicki 1036b70fb7afSTomasz Nowicki /* Collect redistributor base addresses in GICR entries */ 1037b70fb7afSTomasz Nowicki if (acpi_table_parse_madt(type, redist_parser, 0) > 0) 1038b70fb7afSTomasz Nowicki return 0; 1039b70fb7afSTomasz Nowicki 1040b70fb7afSTomasz Nowicki pr_info("No valid GICR entries exist\n"); 1041b70fb7afSTomasz Nowicki return -ENODEV; 1042b70fb7afSTomasz Nowicki } 1043b70fb7afSTomasz Nowicki 1044ffa7d616STomasz Nowicki static int __init gic_acpi_match_gicr(struct acpi_subtable_header *header, 1045ffa7d616STomasz Nowicki const unsigned long end) 1046ffa7d616STomasz Nowicki { 1047ffa7d616STomasz Nowicki /* Subtable presence means that redist exists, that's it */ 1048ffa7d616STomasz Nowicki return 0; 1049ffa7d616STomasz Nowicki } 1050ffa7d616STomasz Nowicki 1051b70fb7afSTomasz Nowicki static int __init gic_acpi_match_gicc(struct acpi_subtable_header *header, 1052b70fb7afSTomasz Nowicki const unsigned long end) 1053b70fb7afSTomasz Nowicki { 1054b70fb7afSTomasz Nowicki struct acpi_madt_generic_interrupt *gicc = 1055b70fb7afSTomasz Nowicki (struct acpi_madt_generic_interrupt *)header; 1056b70fb7afSTomasz Nowicki 1057b70fb7afSTomasz Nowicki /* 1058b70fb7afSTomasz Nowicki * If GICC is enabled and has valid gicr base address, then it means 1059b70fb7afSTomasz Nowicki * GICR base is presented via GICC 1060b70fb7afSTomasz Nowicki */ 1061b70fb7afSTomasz Nowicki if ((gicc->flags & ACPI_MADT_ENABLED) && gicc->gicr_base_address) 1062b70fb7afSTomasz Nowicki return 0; 1063b70fb7afSTomasz Nowicki 1064b70fb7afSTomasz Nowicki return -ENODEV; 1065b70fb7afSTomasz Nowicki } 1066b70fb7afSTomasz Nowicki 1067b70fb7afSTomasz Nowicki static int __init gic_acpi_count_gicr_regions(void) 1068b70fb7afSTomasz Nowicki { 1069b70fb7afSTomasz Nowicki int count; 1070b70fb7afSTomasz Nowicki 1071b70fb7afSTomasz Nowicki /* 1072b70fb7afSTomasz Nowicki * Count how many redistributor regions we have. It is not allowed 1073b70fb7afSTomasz Nowicki * to mix redistributor description, GICR and GICC subtables have to be 1074b70fb7afSTomasz Nowicki * mutually exclusive. 1075b70fb7afSTomasz Nowicki */ 1076b70fb7afSTomasz Nowicki count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR, 1077b70fb7afSTomasz Nowicki gic_acpi_match_gicr, 0); 1078b70fb7afSTomasz Nowicki if (count > 0) { 1079b70fb7afSTomasz Nowicki single_redist = false; 1080b70fb7afSTomasz Nowicki return count; 1081b70fb7afSTomasz Nowicki } 1082b70fb7afSTomasz Nowicki 1083b70fb7afSTomasz Nowicki count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT, 1084b70fb7afSTomasz Nowicki gic_acpi_match_gicc, 0); 1085b70fb7afSTomasz Nowicki if (count > 0) 1086b70fb7afSTomasz Nowicki single_redist = true; 1087b70fb7afSTomasz Nowicki 1088b70fb7afSTomasz Nowicki return count; 1089b70fb7afSTomasz Nowicki } 1090b70fb7afSTomasz Nowicki 1091ffa7d616STomasz Nowicki static bool __init acpi_validate_gic_table(struct acpi_subtable_header *header, 1092ffa7d616STomasz Nowicki struct acpi_probe_entry *ape) 1093ffa7d616STomasz Nowicki { 1094ffa7d616STomasz Nowicki struct acpi_madt_generic_distributor *dist; 1095ffa7d616STomasz Nowicki int count; 1096ffa7d616STomasz Nowicki 1097ffa7d616STomasz Nowicki dist = (struct acpi_madt_generic_distributor *)header; 1098ffa7d616STomasz Nowicki if (dist->version != ape->driver_data) 1099ffa7d616STomasz Nowicki return false; 1100ffa7d616STomasz Nowicki 1101ffa7d616STomasz Nowicki /* We need to do that exercise anyway, the sooner the better */ 1102b70fb7afSTomasz Nowicki count = gic_acpi_count_gicr_regions(); 1103ffa7d616STomasz Nowicki if (count <= 0) 1104ffa7d616STomasz Nowicki return false; 1105ffa7d616STomasz Nowicki 1106ffa7d616STomasz Nowicki nr_redist_regions = count; 1107ffa7d616STomasz Nowicki return true; 1108ffa7d616STomasz Nowicki } 1109ffa7d616STomasz Nowicki 1110ffa7d616STomasz Nowicki #define ACPI_GICV3_DIST_MEM_SIZE (SZ_64K) 1111ffa7d616STomasz Nowicki 1112ffa7d616STomasz Nowicki static int __init 1113ffa7d616STomasz Nowicki gic_acpi_init(struct acpi_subtable_header *header, const unsigned long end) 1114ffa7d616STomasz Nowicki { 1115ffa7d616STomasz Nowicki struct acpi_madt_generic_distributor *dist; 1116ffa7d616STomasz Nowicki struct fwnode_handle *domain_handle; 1117b70fb7afSTomasz Nowicki int i, err; 1118ffa7d616STomasz Nowicki 1119ffa7d616STomasz Nowicki /* Get distributor base address */ 1120ffa7d616STomasz Nowicki dist = (struct acpi_madt_generic_distributor *)header; 1121ffa7d616STomasz Nowicki dist_base = ioremap(dist->base_address, ACPI_GICV3_DIST_MEM_SIZE); 1122ffa7d616STomasz Nowicki if (!dist_base) { 1123ffa7d616STomasz Nowicki pr_err("Unable to map GICD registers\n"); 1124ffa7d616STomasz Nowicki return -ENOMEM; 1125ffa7d616STomasz Nowicki } 1126ffa7d616STomasz Nowicki 1127ffa7d616STomasz Nowicki err = gic_validate_dist_version(dist_base); 1128ffa7d616STomasz Nowicki if (err) { 1129ffa7d616STomasz Nowicki pr_err("No distributor detected at @%p, giving up", dist_base); 1130ffa7d616STomasz Nowicki goto out_dist_unmap; 1131ffa7d616STomasz Nowicki } 1132ffa7d616STomasz Nowicki 1133ffa7d616STomasz Nowicki redist_regs = kzalloc(sizeof(*redist_regs) * nr_redist_regions, 1134ffa7d616STomasz Nowicki GFP_KERNEL); 1135ffa7d616STomasz Nowicki if (!redist_regs) { 1136ffa7d616STomasz Nowicki err = -ENOMEM; 1137ffa7d616STomasz Nowicki goto out_dist_unmap; 1138ffa7d616STomasz Nowicki } 1139ffa7d616STomasz Nowicki 1140b70fb7afSTomasz Nowicki err = gic_acpi_collect_gicr_base(); 1141b70fb7afSTomasz Nowicki if (err) 1142ffa7d616STomasz Nowicki goto out_redist_unmap; 1143ffa7d616STomasz Nowicki 1144ffa7d616STomasz Nowicki domain_handle = irq_domain_alloc_fwnode(dist_base); 1145ffa7d616STomasz Nowicki if (!domain_handle) { 1146ffa7d616STomasz Nowicki err = -ENOMEM; 1147ffa7d616STomasz Nowicki goto out_redist_unmap; 1148ffa7d616STomasz Nowicki } 1149ffa7d616STomasz Nowicki 1150ffa7d616STomasz Nowicki err = gic_init_bases(dist_base, redist_regs, nr_redist_regions, 0, 1151ffa7d616STomasz Nowicki domain_handle); 1152ffa7d616STomasz Nowicki if (err) 1153ffa7d616STomasz Nowicki goto out_fwhandle_free; 1154ffa7d616STomasz Nowicki 1155ffa7d616STomasz Nowicki acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, domain_handle); 1156ffa7d616STomasz Nowicki return 0; 1157ffa7d616STomasz Nowicki 1158ffa7d616STomasz Nowicki out_fwhandle_free: 1159ffa7d616STomasz Nowicki irq_domain_free_fwnode(domain_handle); 1160ffa7d616STomasz Nowicki out_redist_unmap: 1161ffa7d616STomasz Nowicki for (i = 0; i < nr_redist_regions; i++) 1162ffa7d616STomasz Nowicki if (redist_regs[i].redist_base) 1163ffa7d616STomasz Nowicki iounmap(redist_regs[i].redist_base); 1164ffa7d616STomasz Nowicki kfree(redist_regs); 1165ffa7d616STomasz Nowicki out_dist_unmap: 1166ffa7d616STomasz Nowicki iounmap(dist_base); 1167ffa7d616STomasz Nowicki return err; 1168ffa7d616STomasz Nowicki } 1169ffa7d616STomasz Nowicki IRQCHIP_ACPI_DECLARE(gic_v3, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 1170ffa7d616STomasz Nowicki acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V3, 1171ffa7d616STomasz Nowicki gic_acpi_init); 1172ffa7d616STomasz Nowicki IRQCHIP_ACPI_DECLARE(gic_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 1173ffa7d616STomasz Nowicki acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V4, 1174ffa7d616STomasz Nowicki gic_acpi_init); 1175ffa7d616STomasz Nowicki IRQCHIP_ACPI_DECLARE(gic_v3_or_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 1176ffa7d616STomasz Nowicki acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_NONE, 1177ffa7d616STomasz Nowicki gic_acpi_init); 1178ffa7d616STomasz Nowicki #endif 1179