1caab277bSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 2021f6537SMarc Zyngier /* 30edc23eaSMarc Zyngier * Copyright (C) 2013-2017 ARM Limited, All Rights Reserved. 4021f6537SMarc Zyngier * Author: Marc Zyngier <marc.zyngier@arm.com> 5021f6537SMarc Zyngier */ 6021f6537SMarc Zyngier 768628bb8SJulien Grall #define pr_fmt(fmt) "GICv3: " fmt 868628bb8SJulien Grall 9ffa7d616STomasz Nowicki #include <linux/acpi.h> 10021f6537SMarc Zyngier #include <linux/cpu.h> 113708d52fSSudeep Holla #include <linux/cpu_pm.h> 12021f6537SMarc Zyngier #include <linux/delay.h> 13021f6537SMarc Zyngier #include <linux/interrupt.h> 14ffa7d616STomasz Nowicki #include <linux/irqdomain.h> 15021f6537SMarc Zyngier #include <linux/of.h> 16021f6537SMarc Zyngier #include <linux/of_address.h> 17021f6537SMarc Zyngier #include <linux/of_irq.h> 18021f6537SMarc Zyngier #include <linux/percpu.h> 19101b35f7SJulien Thierry #include <linux/refcount.h> 20021f6537SMarc Zyngier #include <linux/slab.h> 21021f6537SMarc Zyngier 2241a83e06SJoel Porquet #include <linux/irqchip.h> 231839e576SJulien Grall #include <linux/irqchip/arm-gic-common.h> 24021f6537SMarc Zyngier #include <linux/irqchip/arm-gic-v3.h> 25e3825ba1SMarc Zyngier #include <linux/irqchip/irq-partition-percpu.h> 26021f6537SMarc Zyngier 27021f6537SMarc Zyngier #include <asm/cputype.h> 28021f6537SMarc Zyngier #include <asm/exception.h> 29021f6537SMarc Zyngier #include <asm/smp_plat.h> 300b6a3da9SMarc Zyngier #include <asm/virt.h> 31021f6537SMarc Zyngier 32021f6537SMarc Zyngier #include "irq-gic-common.h" 33021f6537SMarc Zyngier 34f32c9266SJulien Thierry #define GICD_INT_NMI_PRI (GICD_INT_DEF_PRI & ~0x80) 35f32c9266SJulien Thierry 369c8114c2SSrinivas Kandagatla #define FLAGS_WORKAROUND_GICR_WAKER_MSM8996 (1ULL << 0) 379c8114c2SSrinivas Kandagatla 38f5c1434cSMarc Zyngier struct redist_region { 39f5c1434cSMarc Zyngier void __iomem *redist_base; 40f5c1434cSMarc Zyngier phys_addr_t phys_base; 41b70fb7afSTomasz Nowicki bool single_redist; 42f5c1434cSMarc Zyngier }; 43f5c1434cSMarc Zyngier 44021f6537SMarc Zyngier struct gic_chip_data { 45e3825ba1SMarc Zyngier struct fwnode_handle *fwnode; 46021f6537SMarc Zyngier void __iomem *dist_base; 47f5c1434cSMarc Zyngier struct redist_region *redist_regions; 48f5c1434cSMarc Zyngier struct rdists rdists; 49021f6537SMarc Zyngier struct irq_domain *domain; 50021f6537SMarc Zyngier u64 redist_stride; 51f5c1434cSMarc Zyngier u32 nr_redist_regions; 529c8114c2SSrinivas Kandagatla u64 flags; 53eda0d04aSShanker Donthineni bool has_rss; 541a60e1e6SMarc Zyngier unsigned int ppi_nr; 5552085d3fSMarc Zyngier struct partition_desc **ppi_descs; 56021f6537SMarc Zyngier }; 57021f6537SMarc Zyngier 58021f6537SMarc Zyngier static struct gic_chip_data gic_data __read_mostly; 59d01d3274SDavidlohr Bueso static DEFINE_STATIC_KEY_TRUE(supports_deactivate_key); 60021f6537SMarc Zyngier 61211bddd2SMarc Zyngier #define GIC_ID_NR (1U << GICD_TYPER_ID_BITS(gic_data.rdists.gicd_typer)) 62c107d613SZenghui Yu #define GIC_LINE_NR min(GICD_TYPER_SPIS(gic_data.rdists.gicd_typer), 1020U) 63211bddd2SMarc Zyngier #define GIC_ESPI_NR GICD_TYPER_ESPIS(gic_data.rdists.gicd_typer) 64211bddd2SMarc Zyngier 65d98d0a99SJulien Thierry /* 66d98d0a99SJulien Thierry * The behaviours of RPR and PMR registers differ depending on the value of 67d98d0a99SJulien Thierry * SCR_EL3.FIQ, and the behaviour of non-secure priority registers of the 68d98d0a99SJulien Thierry * distributor and redistributors depends on whether security is enabled in the 69d98d0a99SJulien Thierry * GIC. 70d98d0a99SJulien Thierry * 71d98d0a99SJulien Thierry * When security is enabled, non-secure priority values from the (re)distributor 72d98d0a99SJulien Thierry * are presented to the GIC CPUIF as follow: 73d98d0a99SJulien Thierry * (GIC_(R)DIST_PRI[irq] >> 1) | 0x80; 74d98d0a99SJulien Thierry * 75d98d0a99SJulien Thierry * If SCR_EL3.FIQ == 1, the values writen to/read from PMR and RPR at non-secure 76d98d0a99SJulien Thierry * EL1 are subject to a similar operation thus matching the priorities presented 77d98d0a99SJulien Thierry * from the (re)distributor when security is enabled. 78d98d0a99SJulien Thierry * 79d98d0a99SJulien Thierry * see GICv3/GICv4 Architecture Specification (IHI0069D): 80d98d0a99SJulien Thierry * - section 4.8.1 Non-secure accesses to register fields for Secure interrupt 81d98d0a99SJulien Thierry * priorities. 82d98d0a99SJulien Thierry * - Figure 4-7 Secure read of the priority field for a Non-secure Group 1 83d98d0a99SJulien Thierry * interrupt. 84d98d0a99SJulien Thierry * 85d98d0a99SJulien Thierry * For now, we only support pseudo-NMIs if we have non-secure view of 86d98d0a99SJulien Thierry * priorities. 87d98d0a99SJulien Thierry */ 88d98d0a99SJulien Thierry static DEFINE_STATIC_KEY_FALSE(supports_pseudo_nmis); 89d98d0a99SJulien Thierry 90f2266504SMarc Zyngier /* 91f2266504SMarc Zyngier * Global static key controlling whether an update to PMR allowing more 92f2266504SMarc Zyngier * interrupts requires to be propagated to the redistributor (DSB SY). 93f2266504SMarc Zyngier * And this needs to be exported for modules to be able to enable 94f2266504SMarc Zyngier * interrupts... 95f2266504SMarc Zyngier */ 96f2266504SMarc Zyngier DEFINE_STATIC_KEY_FALSE(gic_pmr_sync); 97f2266504SMarc Zyngier EXPORT_SYMBOL(gic_pmr_sync); 98f2266504SMarc Zyngier 99101b35f7SJulien Thierry /* ppi_nmi_refs[n] == number of cpus having ppi[n + 16] set as NMI */ 10081a43273SMarc Zyngier static refcount_t *ppi_nmi_refs; 101101b35f7SJulien Thierry 1021839e576SJulien Grall static struct gic_kvm_info gic_v3_kvm_info; 103eda0d04aSShanker Donthineni static DEFINE_PER_CPU(bool, has_rss); 1041839e576SJulien Grall 105eda0d04aSShanker Donthineni #define MPIDR_RS(mpidr) (((mpidr) & 0xF0UL) >> 4) 106f5c1434cSMarc Zyngier #define gic_data_rdist() (this_cpu_ptr(gic_data.rdists.rdist)) 107f5c1434cSMarc Zyngier #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base) 108021f6537SMarc Zyngier #define gic_data_rdist_sgi_base() (gic_data_rdist_rd_base() + SZ_64K) 109021f6537SMarc Zyngier 110021f6537SMarc Zyngier /* Our default, arbitrary priority value. Linux only uses one anyway. */ 111021f6537SMarc Zyngier #define DEFAULT_PMR_VALUE 0xf0 112021f6537SMarc Zyngier 113e91b036eSMarc Zyngier enum gic_intid_range { 114e91b036eSMarc Zyngier PPI_RANGE, 115e91b036eSMarc Zyngier SPI_RANGE, 1165f51f803SMarc Zyngier EPPI_RANGE, 117211bddd2SMarc Zyngier ESPI_RANGE, 118e91b036eSMarc Zyngier LPI_RANGE, 119e91b036eSMarc Zyngier __INVALID_RANGE__ 120e91b036eSMarc Zyngier }; 121e91b036eSMarc Zyngier 122e91b036eSMarc Zyngier static enum gic_intid_range __get_intid_range(irq_hw_number_t hwirq) 123e91b036eSMarc Zyngier { 124e91b036eSMarc Zyngier switch (hwirq) { 125e91b036eSMarc Zyngier case 16 ... 31: 126e91b036eSMarc Zyngier return PPI_RANGE; 127e91b036eSMarc Zyngier case 32 ... 1019: 128e91b036eSMarc Zyngier return SPI_RANGE; 1295f51f803SMarc Zyngier case EPPI_BASE_INTID ... (EPPI_BASE_INTID + 63): 1305f51f803SMarc Zyngier return EPPI_RANGE; 131211bddd2SMarc Zyngier case ESPI_BASE_INTID ... (ESPI_BASE_INTID + 1023): 132211bddd2SMarc Zyngier return ESPI_RANGE; 133e91b036eSMarc Zyngier case 8192 ... GENMASK(23, 0): 134e91b036eSMarc Zyngier return LPI_RANGE; 135e91b036eSMarc Zyngier default: 136e91b036eSMarc Zyngier return __INVALID_RANGE__; 137e91b036eSMarc Zyngier } 138e91b036eSMarc Zyngier } 139e91b036eSMarc Zyngier 140e91b036eSMarc Zyngier static enum gic_intid_range get_intid_range(struct irq_data *d) 141e91b036eSMarc Zyngier { 142e91b036eSMarc Zyngier return __get_intid_range(d->hwirq); 143e91b036eSMarc Zyngier } 144e91b036eSMarc Zyngier 145021f6537SMarc Zyngier static inline unsigned int gic_irq(struct irq_data *d) 146021f6537SMarc Zyngier { 147021f6537SMarc Zyngier return d->hwirq; 148021f6537SMarc Zyngier } 149021f6537SMarc Zyngier 150021f6537SMarc Zyngier static inline int gic_irq_in_rdist(struct irq_data *d) 151021f6537SMarc Zyngier { 1525f51f803SMarc Zyngier enum gic_intid_range range = get_intid_range(d); 1535f51f803SMarc Zyngier return range == PPI_RANGE || range == EPPI_RANGE; 154021f6537SMarc Zyngier } 155021f6537SMarc Zyngier 156021f6537SMarc Zyngier static inline void __iomem *gic_dist_base(struct irq_data *d) 157021f6537SMarc Zyngier { 158e91b036eSMarc Zyngier switch (get_intid_range(d)) { 159e91b036eSMarc Zyngier case PPI_RANGE: 1605f51f803SMarc Zyngier case EPPI_RANGE: 161e91b036eSMarc Zyngier /* SGI+PPI -> SGI_base for this CPU */ 162021f6537SMarc Zyngier return gic_data_rdist_sgi_base(); 163021f6537SMarc Zyngier 164e91b036eSMarc Zyngier case SPI_RANGE: 165211bddd2SMarc Zyngier case ESPI_RANGE: 166e91b036eSMarc Zyngier /* SPI -> dist_base */ 167021f6537SMarc Zyngier return gic_data.dist_base; 168021f6537SMarc Zyngier 169e91b036eSMarc Zyngier default: 170021f6537SMarc Zyngier return NULL; 171021f6537SMarc Zyngier } 172e91b036eSMarc Zyngier } 173021f6537SMarc Zyngier 174021f6537SMarc Zyngier static void gic_do_wait_for_rwp(void __iomem *base) 175021f6537SMarc Zyngier { 176021f6537SMarc Zyngier u32 count = 1000000; /* 1s! */ 177021f6537SMarc Zyngier 178021f6537SMarc Zyngier while (readl_relaxed(base + GICD_CTLR) & GICD_CTLR_RWP) { 179021f6537SMarc Zyngier count--; 180021f6537SMarc Zyngier if (!count) { 181021f6537SMarc Zyngier pr_err_ratelimited("RWP timeout, gone fishing\n"); 182021f6537SMarc Zyngier return; 183021f6537SMarc Zyngier } 184021f6537SMarc Zyngier cpu_relax(); 185021f6537SMarc Zyngier udelay(1); 1862c542426SDaode Huang } 187021f6537SMarc Zyngier } 188021f6537SMarc Zyngier 189021f6537SMarc Zyngier /* Wait for completion of a distributor change */ 190021f6537SMarc Zyngier static void gic_dist_wait_for_rwp(void) 191021f6537SMarc Zyngier { 192021f6537SMarc Zyngier gic_do_wait_for_rwp(gic_data.dist_base); 193021f6537SMarc Zyngier } 194021f6537SMarc Zyngier 195021f6537SMarc Zyngier /* Wait for completion of a redistributor change */ 196021f6537SMarc Zyngier static void gic_redist_wait_for_rwp(void) 197021f6537SMarc Zyngier { 198021f6537SMarc Zyngier gic_do_wait_for_rwp(gic_data_rdist_rd_base()); 199021f6537SMarc Zyngier } 200021f6537SMarc Zyngier 2017936e914SJean-Philippe Brucker #ifdef CONFIG_ARM64 2026d4e11c5SRobert Richter 2036d4e11c5SRobert Richter static u64 __maybe_unused gic_read_iar(void) 2046d4e11c5SRobert Richter { 205a4023f68SSuzuki K Poulose if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_23154)) 2066d4e11c5SRobert Richter return gic_read_iar_cavium_thunderx(); 2076d4e11c5SRobert Richter else 2086d4e11c5SRobert Richter return gic_read_iar_common(); 2096d4e11c5SRobert Richter } 2107936e914SJean-Philippe Brucker #endif 211021f6537SMarc Zyngier 212a2c22510SSudeep Holla static void gic_enable_redist(bool enable) 213021f6537SMarc Zyngier { 214021f6537SMarc Zyngier void __iomem *rbase; 215021f6537SMarc Zyngier u32 count = 1000000; /* 1s! */ 216021f6537SMarc Zyngier u32 val; 217021f6537SMarc Zyngier 2189c8114c2SSrinivas Kandagatla if (gic_data.flags & FLAGS_WORKAROUND_GICR_WAKER_MSM8996) 2199c8114c2SSrinivas Kandagatla return; 2209c8114c2SSrinivas Kandagatla 221021f6537SMarc Zyngier rbase = gic_data_rdist_rd_base(); 222021f6537SMarc Zyngier 223021f6537SMarc Zyngier val = readl_relaxed(rbase + GICR_WAKER); 224a2c22510SSudeep Holla if (enable) 225a2c22510SSudeep Holla /* Wake up this CPU redistributor */ 226021f6537SMarc Zyngier val &= ~GICR_WAKER_ProcessorSleep; 227a2c22510SSudeep Holla else 228a2c22510SSudeep Holla val |= GICR_WAKER_ProcessorSleep; 229021f6537SMarc Zyngier writel_relaxed(val, rbase + GICR_WAKER); 230021f6537SMarc Zyngier 231a2c22510SSudeep Holla if (!enable) { /* Check that GICR_WAKER is writeable */ 232a2c22510SSudeep Holla val = readl_relaxed(rbase + GICR_WAKER); 233a2c22510SSudeep Holla if (!(val & GICR_WAKER_ProcessorSleep)) 234a2c22510SSudeep Holla return; /* No PM support in this redistributor */ 235021f6537SMarc Zyngier } 236a2c22510SSudeep Holla 237d102eb5cSDan Carpenter while (--count) { 238a2c22510SSudeep Holla val = readl_relaxed(rbase + GICR_WAKER); 239cf1d9d11SAndrew Jones if (enable ^ (bool)(val & GICR_WAKER_ChildrenAsleep)) 240a2c22510SSudeep Holla break; 241021f6537SMarc Zyngier cpu_relax(); 242021f6537SMarc Zyngier udelay(1); 2432c542426SDaode Huang } 244a2c22510SSudeep Holla if (!count) 245a2c22510SSudeep Holla pr_err_ratelimited("redistributor failed to %s...\n", 246a2c22510SSudeep Holla enable ? "wakeup" : "sleep"); 247021f6537SMarc Zyngier } 248021f6537SMarc Zyngier 249021f6537SMarc Zyngier /* 250021f6537SMarc Zyngier * Routines to disable, enable, EOI and route interrupts 251021f6537SMarc Zyngier */ 252e91b036eSMarc Zyngier static u32 convert_offset_index(struct irq_data *d, u32 offset, u32 *index) 253e91b036eSMarc Zyngier { 254e91b036eSMarc Zyngier switch (get_intid_range(d)) { 255e91b036eSMarc Zyngier case PPI_RANGE: 256e91b036eSMarc Zyngier case SPI_RANGE: 257e91b036eSMarc Zyngier *index = d->hwirq; 258e91b036eSMarc Zyngier return offset; 2595f51f803SMarc Zyngier case EPPI_RANGE: 2605f51f803SMarc Zyngier /* 2615f51f803SMarc Zyngier * Contrary to the ESPI range, the EPPI range is contiguous 2625f51f803SMarc Zyngier * to the PPI range in the registers, so let's adjust the 2635f51f803SMarc Zyngier * displacement accordingly. Consistency is overrated. 2645f51f803SMarc Zyngier */ 2655f51f803SMarc Zyngier *index = d->hwirq - EPPI_BASE_INTID + 32; 2665f51f803SMarc Zyngier return offset; 267211bddd2SMarc Zyngier case ESPI_RANGE: 268211bddd2SMarc Zyngier *index = d->hwirq - ESPI_BASE_INTID; 269211bddd2SMarc Zyngier switch (offset) { 270211bddd2SMarc Zyngier case GICD_ISENABLER: 271211bddd2SMarc Zyngier return GICD_ISENABLERnE; 272211bddd2SMarc Zyngier case GICD_ICENABLER: 273211bddd2SMarc Zyngier return GICD_ICENABLERnE; 274211bddd2SMarc Zyngier case GICD_ISPENDR: 275211bddd2SMarc Zyngier return GICD_ISPENDRnE; 276211bddd2SMarc Zyngier case GICD_ICPENDR: 277211bddd2SMarc Zyngier return GICD_ICPENDRnE; 278211bddd2SMarc Zyngier case GICD_ISACTIVER: 279211bddd2SMarc Zyngier return GICD_ISACTIVERnE; 280211bddd2SMarc Zyngier case GICD_ICACTIVER: 281211bddd2SMarc Zyngier return GICD_ICACTIVERnE; 282211bddd2SMarc Zyngier case GICD_IPRIORITYR: 283211bddd2SMarc Zyngier return GICD_IPRIORITYRnE; 284211bddd2SMarc Zyngier case GICD_ICFGR: 285211bddd2SMarc Zyngier return GICD_ICFGRnE; 286211bddd2SMarc Zyngier case GICD_IROUTER: 287211bddd2SMarc Zyngier return GICD_IROUTERnE; 288211bddd2SMarc Zyngier default: 289211bddd2SMarc Zyngier break; 290211bddd2SMarc Zyngier } 291211bddd2SMarc Zyngier break; 292e91b036eSMarc Zyngier default: 293e91b036eSMarc Zyngier break; 294e91b036eSMarc Zyngier } 295e91b036eSMarc Zyngier 296e91b036eSMarc Zyngier WARN_ON(1); 297e91b036eSMarc Zyngier *index = d->hwirq; 298e91b036eSMarc Zyngier return offset; 299e91b036eSMarc Zyngier } 300e91b036eSMarc Zyngier 301b594c6e2SMarc Zyngier static int gic_peek_irq(struct irq_data *d, u32 offset) 302b594c6e2SMarc Zyngier { 303b594c6e2SMarc Zyngier void __iomem *base; 304e91b036eSMarc Zyngier u32 index, mask; 305e91b036eSMarc Zyngier 306e91b036eSMarc Zyngier offset = convert_offset_index(d, offset, &index); 307e91b036eSMarc Zyngier mask = 1 << (index % 32); 308b594c6e2SMarc Zyngier 309b594c6e2SMarc Zyngier if (gic_irq_in_rdist(d)) 310b594c6e2SMarc Zyngier base = gic_data_rdist_sgi_base(); 311b594c6e2SMarc Zyngier else 312b594c6e2SMarc Zyngier base = gic_data.dist_base; 313b594c6e2SMarc Zyngier 314e91b036eSMarc Zyngier return !!(readl_relaxed(base + offset + (index / 32) * 4) & mask); 315b594c6e2SMarc Zyngier } 316b594c6e2SMarc Zyngier 317021f6537SMarc Zyngier static void gic_poke_irq(struct irq_data *d, u32 offset) 318021f6537SMarc Zyngier { 319021f6537SMarc Zyngier void (*rwp_wait)(void); 320021f6537SMarc Zyngier void __iomem *base; 321e91b036eSMarc Zyngier u32 index, mask; 322e91b036eSMarc Zyngier 323e91b036eSMarc Zyngier offset = convert_offset_index(d, offset, &index); 324e91b036eSMarc Zyngier mask = 1 << (index % 32); 325021f6537SMarc Zyngier 326021f6537SMarc Zyngier if (gic_irq_in_rdist(d)) { 327021f6537SMarc Zyngier base = gic_data_rdist_sgi_base(); 328021f6537SMarc Zyngier rwp_wait = gic_redist_wait_for_rwp; 329021f6537SMarc Zyngier } else { 330021f6537SMarc Zyngier base = gic_data.dist_base; 331021f6537SMarc Zyngier rwp_wait = gic_dist_wait_for_rwp; 332021f6537SMarc Zyngier } 333021f6537SMarc Zyngier 334e91b036eSMarc Zyngier writel_relaxed(mask, base + offset + (index / 32) * 4); 335021f6537SMarc Zyngier rwp_wait(); 336021f6537SMarc Zyngier } 337021f6537SMarc Zyngier 338021f6537SMarc Zyngier static void gic_mask_irq(struct irq_data *d) 339021f6537SMarc Zyngier { 340021f6537SMarc Zyngier gic_poke_irq(d, GICD_ICENABLER); 341021f6537SMarc Zyngier } 342021f6537SMarc Zyngier 3430b6a3da9SMarc Zyngier static void gic_eoimode1_mask_irq(struct irq_data *d) 3440b6a3da9SMarc Zyngier { 3450b6a3da9SMarc Zyngier gic_mask_irq(d); 346530bf353SMarc Zyngier /* 347530bf353SMarc Zyngier * When masking a forwarded interrupt, make sure it is 348530bf353SMarc Zyngier * deactivated as well. 349530bf353SMarc Zyngier * 350530bf353SMarc Zyngier * This ensures that an interrupt that is getting 351530bf353SMarc Zyngier * disabled/masked will not get "stuck", because there is 352530bf353SMarc Zyngier * noone to deactivate it (guest is being terminated). 353530bf353SMarc Zyngier */ 3544df7f54dSThomas Gleixner if (irqd_is_forwarded_to_vcpu(d)) 355530bf353SMarc Zyngier gic_poke_irq(d, GICD_ICACTIVER); 3560b6a3da9SMarc Zyngier } 3570b6a3da9SMarc Zyngier 358021f6537SMarc Zyngier static void gic_unmask_irq(struct irq_data *d) 359021f6537SMarc Zyngier { 360021f6537SMarc Zyngier gic_poke_irq(d, GICD_ISENABLER); 361021f6537SMarc Zyngier } 362021f6537SMarc Zyngier 363d98d0a99SJulien Thierry static inline bool gic_supports_nmi(void) 364d98d0a99SJulien Thierry { 365d98d0a99SJulien Thierry return IS_ENABLED(CONFIG_ARM64_PSEUDO_NMI) && 366d98d0a99SJulien Thierry static_branch_likely(&supports_pseudo_nmis); 367d98d0a99SJulien Thierry } 368d98d0a99SJulien Thierry 369b594c6e2SMarc Zyngier static int gic_irq_set_irqchip_state(struct irq_data *d, 370b594c6e2SMarc Zyngier enum irqchip_irq_state which, bool val) 371b594c6e2SMarc Zyngier { 372b594c6e2SMarc Zyngier u32 reg; 373b594c6e2SMarc Zyngier 374211bddd2SMarc Zyngier if (d->hwirq >= 8192) /* PPI/SPI only */ 375b594c6e2SMarc Zyngier return -EINVAL; 376b594c6e2SMarc Zyngier 377b594c6e2SMarc Zyngier switch (which) { 378b594c6e2SMarc Zyngier case IRQCHIP_STATE_PENDING: 379b594c6e2SMarc Zyngier reg = val ? GICD_ISPENDR : GICD_ICPENDR; 380b594c6e2SMarc Zyngier break; 381b594c6e2SMarc Zyngier 382b594c6e2SMarc Zyngier case IRQCHIP_STATE_ACTIVE: 383b594c6e2SMarc Zyngier reg = val ? GICD_ISACTIVER : GICD_ICACTIVER; 384b594c6e2SMarc Zyngier break; 385b594c6e2SMarc Zyngier 386b594c6e2SMarc Zyngier case IRQCHIP_STATE_MASKED: 387b594c6e2SMarc Zyngier reg = val ? GICD_ICENABLER : GICD_ISENABLER; 388b594c6e2SMarc Zyngier break; 389b594c6e2SMarc Zyngier 390b594c6e2SMarc Zyngier default: 391b594c6e2SMarc Zyngier return -EINVAL; 392b594c6e2SMarc Zyngier } 393b594c6e2SMarc Zyngier 394b594c6e2SMarc Zyngier gic_poke_irq(d, reg); 395b594c6e2SMarc Zyngier return 0; 396b594c6e2SMarc Zyngier } 397b594c6e2SMarc Zyngier 398b594c6e2SMarc Zyngier static int gic_irq_get_irqchip_state(struct irq_data *d, 399b594c6e2SMarc Zyngier enum irqchip_irq_state which, bool *val) 400b594c6e2SMarc Zyngier { 401211bddd2SMarc Zyngier if (d->hwirq >= 8192) /* PPI/SPI only */ 402b594c6e2SMarc Zyngier return -EINVAL; 403b594c6e2SMarc Zyngier 404b594c6e2SMarc Zyngier switch (which) { 405b594c6e2SMarc Zyngier case IRQCHIP_STATE_PENDING: 406b594c6e2SMarc Zyngier *val = gic_peek_irq(d, GICD_ISPENDR); 407b594c6e2SMarc Zyngier break; 408b594c6e2SMarc Zyngier 409b594c6e2SMarc Zyngier case IRQCHIP_STATE_ACTIVE: 410b594c6e2SMarc Zyngier *val = gic_peek_irq(d, GICD_ISACTIVER); 411b594c6e2SMarc Zyngier break; 412b594c6e2SMarc Zyngier 413b594c6e2SMarc Zyngier case IRQCHIP_STATE_MASKED: 414b594c6e2SMarc Zyngier *val = !gic_peek_irq(d, GICD_ISENABLER); 415b594c6e2SMarc Zyngier break; 416b594c6e2SMarc Zyngier 417b594c6e2SMarc Zyngier default: 418b594c6e2SMarc Zyngier return -EINVAL; 419b594c6e2SMarc Zyngier } 420b594c6e2SMarc Zyngier 421b594c6e2SMarc Zyngier return 0; 422b594c6e2SMarc Zyngier } 423b594c6e2SMarc Zyngier 424101b35f7SJulien Thierry static void gic_irq_set_prio(struct irq_data *d, u8 prio) 425101b35f7SJulien Thierry { 426101b35f7SJulien Thierry void __iomem *base = gic_dist_base(d); 427e91b036eSMarc Zyngier u32 offset, index; 428101b35f7SJulien Thierry 429e91b036eSMarc Zyngier offset = convert_offset_index(d, GICD_IPRIORITYR, &index); 430e91b036eSMarc Zyngier 431e91b036eSMarc Zyngier writeb_relaxed(prio, base + offset + index); 432101b35f7SJulien Thierry } 433101b35f7SJulien Thierry 43481a43273SMarc Zyngier static u32 gic_get_ppi_index(struct irq_data *d) 43581a43273SMarc Zyngier { 43681a43273SMarc Zyngier switch (get_intid_range(d)) { 43781a43273SMarc Zyngier case PPI_RANGE: 43881a43273SMarc Zyngier return d->hwirq - 16; 4395f51f803SMarc Zyngier case EPPI_RANGE: 4405f51f803SMarc Zyngier return d->hwirq - EPPI_BASE_INTID + 16; 44181a43273SMarc Zyngier default: 44281a43273SMarc Zyngier unreachable(); 44381a43273SMarc Zyngier } 44481a43273SMarc Zyngier } 44581a43273SMarc Zyngier 446101b35f7SJulien Thierry static int gic_irq_nmi_setup(struct irq_data *d) 447101b35f7SJulien Thierry { 448101b35f7SJulien Thierry struct irq_desc *desc = irq_to_desc(d->irq); 449101b35f7SJulien Thierry 450101b35f7SJulien Thierry if (!gic_supports_nmi()) 451101b35f7SJulien Thierry return -EINVAL; 452101b35f7SJulien Thierry 453101b35f7SJulien Thierry if (gic_peek_irq(d, GICD_ISENABLER)) { 454101b35f7SJulien Thierry pr_err("Cannot set NMI property of enabled IRQ %u\n", d->irq); 455101b35f7SJulien Thierry return -EINVAL; 456101b35f7SJulien Thierry } 457101b35f7SJulien Thierry 458101b35f7SJulien Thierry /* 459101b35f7SJulien Thierry * A secondary irq_chip should be in charge of LPI request, 460101b35f7SJulien Thierry * it should not be possible to get there 461101b35f7SJulien Thierry */ 462101b35f7SJulien Thierry if (WARN_ON(gic_irq(d) >= 8192)) 463101b35f7SJulien Thierry return -EINVAL; 464101b35f7SJulien Thierry 465101b35f7SJulien Thierry /* desc lock should already be held */ 46681a43273SMarc Zyngier if (gic_irq_in_rdist(d)) { 46781a43273SMarc Zyngier u32 idx = gic_get_ppi_index(d); 46881a43273SMarc Zyngier 469101b35f7SJulien Thierry /* Setting up PPI as NMI, only switch handler for first NMI */ 47081a43273SMarc Zyngier if (!refcount_inc_not_zero(&ppi_nmi_refs[idx])) { 47181a43273SMarc Zyngier refcount_set(&ppi_nmi_refs[idx], 1); 472101b35f7SJulien Thierry desc->handle_irq = handle_percpu_devid_fasteoi_nmi; 473101b35f7SJulien Thierry } 474101b35f7SJulien Thierry } else { 475101b35f7SJulien Thierry desc->handle_irq = handle_fasteoi_nmi; 476101b35f7SJulien Thierry } 477101b35f7SJulien Thierry 478101b35f7SJulien Thierry gic_irq_set_prio(d, GICD_INT_NMI_PRI); 479101b35f7SJulien Thierry 480101b35f7SJulien Thierry return 0; 481101b35f7SJulien Thierry } 482101b35f7SJulien Thierry 483101b35f7SJulien Thierry static void gic_irq_nmi_teardown(struct irq_data *d) 484101b35f7SJulien Thierry { 485101b35f7SJulien Thierry struct irq_desc *desc = irq_to_desc(d->irq); 486101b35f7SJulien Thierry 487101b35f7SJulien Thierry if (WARN_ON(!gic_supports_nmi())) 488101b35f7SJulien Thierry return; 489101b35f7SJulien Thierry 490101b35f7SJulien Thierry if (gic_peek_irq(d, GICD_ISENABLER)) { 491101b35f7SJulien Thierry pr_err("Cannot set NMI property of enabled IRQ %u\n", d->irq); 492101b35f7SJulien Thierry return; 493101b35f7SJulien Thierry } 494101b35f7SJulien Thierry 495101b35f7SJulien Thierry /* 496101b35f7SJulien Thierry * A secondary irq_chip should be in charge of LPI request, 497101b35f7SJulien Thierry * it should not be possible to get there 498101b35f7SJulien Thierry */ 499101b35f7SJulien Thierry if (WARN_ON(gic_irq(d) >= 8192)) 500101b35f7SJulien Thierry return; 501101b35f7SJulien Thierry 502101b35f7SJulien Thierry /* desc lock should already be held */ 50381a43273SMarc Zyngier if (gic_irq_in_rdist(d)) { 50481a43273SMarc Zyngier u32 idx = gic_get_ppi_index(d); 50581a43273SMarc Zyngier 506101b35f7SJulien Thierry /* Tearing down NMI, only switch handler for last NMI */ 50781a43273SMarc Zyngier if (refcount_dec_and_test(&ppi_nmi_refs[idx])) 508101b35f7SJulien Thierry desc->handle_irq = handle_percpu_devid_irq; 509101b35f7SJulien Thierry } else { 510101b35f7SJulien Thierry desc->handle_irq = handle_fasteoi_irq; 511101b35f7SJulien Thierry } 512101b35f7SJulien Thierry 513101b35f7SJulien Thierry gic_irq_set_prio(d, GICD_INT_DEF_PRI); 514101b35f7SJulien Thierry } 515101b35f7SJulien Thierry 516021f6537SMarc Zyngier static void gic_eoi_irq(struct irq_data *d) 517021f6537SMarc Zyngier { 518021f6537SMarc Zyngier gic_write_eoir(gic_irq(d)); 519021f6537SMarc Zyngier } 520021f6537SMarc Zyngier 5210b6a3da9SMarc Zyngier static void gic_eoimode1_eoi_irq(struct irq_data *d) 5220b6a3da9SMarc Zyngier { 5230b6a3da9SMarc Zyngier /* 524530bf353SMarc Zyngier * No need to deactivate an LPI, or an interrupt that 525530bf353SMarc Zyngier * is is getting forwarded to a vcpu. 5260b6a3da9SMarc Zyngier */ 5274df7f54dSThomas Gleixner if (gic_irq(d) >= 8192 || irqd_is_forwarded_to_vcpu(d)) 5280b6a3da9SMarc Zyngier return; 5290b6a3da9SMarc Zyngier gic_write_dir(gic_irq(d)); 5300b6a3da9SMarc Zyngier } 5310b6a3da9SMarc Zyngier 532021f6537SMarc Zyngier static int gic_set_type(struct irq_data *d, unsigned int type) 533021f6537SMarc Zyngier { 5345f51f803SMarc Zyngier enum gic_intid_range range; 535021f6537SMarc Zyngier unsigned int irq = gic_irq(d); 536021f6537SMarc Zyngier void (*rwp_wait)(void); 537021f6537SMarc Zyngier void __iomem *base; 538e91b036eSMarc Zyngier u32 offset, index; 53913d22e2eSMarc Zyngier int ret; 540021f6537SMarc Zyngier 541021f6537SMarc Zyngier /* Interrupt configuration for SGIs can't be changed */ 542021f6537SMarc Zyngier if (irq < 16) 543021f6537SMarc Zyngier return -EINVAL; 544021f6537SMarc Zyngier 5455f51f803SMarc Zyngier range = get_intid_range(d); 5465f51f803SMarc Zyngier 547fb7e7debSLiviu Dudau /* SPIs have restrictions on the supported types */ 5485f51f803SMarc Zyngier if ((range == SPI_RANGE || range == ESPI_RANGE) && 5495f51f803SMarc Zyngier type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING) 550021f6537SMarc Zyngier return -EINVAL; 551021f6537SMarc Zyngier 552021f6537SMarc Zyngier if (gic_irq_in_rdist(d)) { 553021f6537SMarc Zyngier base = gic_data_rdist_sgi_base(); 554021f6537SMarc Zyngier rwp_wait = gic_redist_wait_for_rwp; 555021f6537SMarc Zyngier } else { 556021f6537SMarc Zyngier base = gic_data.dist_base; 557021f6537SMarc Zyngier rwp_wait = gic_dist_wait_for_rwp; 558021f6537SMarc Zyngier } 559021f6537SMarc Zyngier 560e91b036eSMarc Zyngier offset = convert_offset_index(d, GICD_ICFGR, &index); 56113d22e2eSMarc Zyngier 562e91b036eSMarc Zyngier ret = gic_configure_irq(index, type, base + offset, rwp_wait); 5635f51f803SMarc Zyngier if (ret && (range == PPI_RANGE || range == EPPI_RANGE)) { 56413d22e2eSMarc Zyngier /* Misconfigured PPIs are usually not fatal */ 5655f51f803SMarc Zyngier pr_warn("GIC: PPI INTID%d is secure or misconfigured\n", irq); 56613d22e2eSMarc Zyngier ret = 0; 56713d22e2eSMarc Zyngier } 56813d22e2eSMarc Zyngier 56913d22e2eSMarc Zyngier return ret; 570021f6537SMarc Zyngier } 571021f6537SMarc Zyngier 572530bf353SMarc Zyngier static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu) 573530bf353SMarc Zyngier { 5744df7f54dSThomas Gleixner if (vcpu) 5754df7f54dSThomas Gleixner irqd_set_forwarded_to_vcpu(d); 5764df7f54dSThomas Gleixner else 5774df7f54dSThomas Gleixner irqd_clr_forwarded_to_vcpu(d); 578530bf353SMarc Zyngier return 0; 579530bf353SMarc Zyngier } 580530bf353SMarc Zyngier 581f6c86a41SJean-Philippe Brucker static u64 gic_mpidr_to_affinity(unsigned long mpidr) 582021f6537SMarc Zyngier { 583021f6537SMarc Zyngier u64 aff; 584021f6537SMarc Zyngier 585f6c86a41SJean-Philippe Brucker aff = ((u64)MPIDR_AFFINITY_LEVEL(mpidr, 3) << 32 | 586021f6537SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 | 587021f6537SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | 588021f6537SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 0)); 589021f6537SMarc Zyngier 590021f6537SMarc Zyngier return aff; 591021f6537SMarc Zyngier } 592021f6537SMarc Zyngier 593f32c9266SJulien Thierry static void gic_deactivate_unhandled(u32 irqnr) 594f32c9266SJulien Thierry { 595f32c9266SJulien Thierry if (static_branch_likely(&supports_deactivate_key)) { 596f32c9266SJulien Thierry if (irqnr < 8192) 597f32c9266SJulien Thierry gic_write_dir(irqnr); 598f32c9266SJulien Thierry } else { 599f32c9266SJulien Thierry gic_write_eoir(irqnr); 600f32c9266SJulien Thierry } 601f32c9266SJulien Thierry } 602f32c9266SJulien Thierry 603f32c9266SJulien Thierry static inline void gic_handle_nmi(u32 irqnr, struct pt_regs *regs) 604f32c9266SJulien Thierry { 60517ce302fSJulien Thierry bool irqs_enabled = interrupts_enabled(regs); 606f32c9266SJulien Thierry int err; 607f32c9266SJulien Thierry 60817ce302fSJulien Thierry if (irqs_enabled) 60917ce302fSJulien Thierry nmi_enter(); 61017ce302fSJulien Thierry 611f32c9266SJulien Thierry if (static_branch_likely(&supports_deactivate_key)) 612f32c9266SJulien Thierry gic_write_eoir(irqnr); 613f32c9266SJulien Thierry /* 614f32c9266SJulien Thierry * Leave the PSR.I bit set to prevent other NMIs to be 615f32c9266SJulien Thierry * received while handling this one. 616f32c9266SJulien Thierry * PSR.I will be restored when we ERET to the 617f32c9266SJulien Thierry * interrupted context. 618f32c9266SJulien Thierry */ 619f32c9266SJulien Thierry err = handle_domain_nmi(gic_data.domain, irqnr, regs); 620f32c9266SJulien Thierry if (err) 621f32c9266SJulien Thierry gic_deactivate_unhandled(irqnr); 62217ce302fSJulien Thierry 62317ce302fSJulien Thierry if (irqs_enabled) 62417ce302fSJulien Thierry nmi_exit(); 625f32c9266SJulien Thierry } 626f32c9266SJulien Thierry 627021f6537SMarc Zyngier static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) 628021f6537SMarc Zyngier { 629f6c86a41SJean-Philippe Brucker u32 irqnr; 630021f6537SMarc Zyngier 631021f6537SMarc Zyngier irqnr = gic_read_iar(); 632021f6537SMarc Zyngier 633f32c9266SJulien Thierry if (gic_supports_nmi() && 634f32c9266SJulien Thierry unlikely(gic_read_rpr() == GICD_INT_NMI_PRI)) { 635f32c9266SJulien Thierry gic_handle_nmi(irqnr, regs); 636f32c9266SJulien Thierry return; 637f32c9266SJulien Thierry } 638f32c9266SJulien Thierry 6393f1f3234SJulien Thierry if (gic_prio_masking_enabled()) { 6403f1f3234SJulien Thierry gic_pmr_mask_irqs(); 6413f1f3234SJulien Thierry gic_arch_enable_irqs(); 6423f1f3234SJulien Thierry } 6433f1f3234SJulien Thierry 644211bddd2SMarc Zyngier /* Check for special IDs first */ 645211bddd2SMarc Zyngier if ((irqnr >= 1020 && irqnr <= 1023)) 646211bddd2SMarc Zyngier return; 647211bddd2SMarc Zyngier 648211bddd2SMarc Zyngier /* Treat anything but SGIs in a uniform way */ 649211bddd2SMarc Zyngier if (likely(irqnr > 15)) { 650ebc6de00SMarc Zyngier int err; 6510b6a3da9SMarc Zyngier 652d01d3274SDavidlohr Bueso if (static_branch_likely(&supports_deactivate_key)) 6530b6a3da9SMarc Zyngier gic_write_eoir(irqnr); 65439a06b67SWill Deacon else 65539a06b67SWill Deacon isb(); 6560b6a3da9SMarc Zyngier 657ebc6de00SMarc Zyngier err = handle_domain_irq(gic_data.domain, irqnr, regs); 658ebc6de00SMarc Zyngier if (err) { 659da33f31dSMarc Zyngier WARN_ONCE(true, "Unexpected interrupt received!\n"); 660f32c9266SJulien Thierry gic_deactivate_unhandled(irqnr); 6610b6a3da9SMarc Zyngier } 662342677d7SJulien Thierry return; 663ebc6de00SMarc Zyngier } 664021f6537SMarc Zyngier if (irqnr < 16) { 665021f6537SMarc Zyngier gic_write_eoir(irqnr); 666d01d3274SDavidlohr Bueso if (static_branch_likely(&supports_deactivate_key)) 6670b6a3da9SMarc Zyngier gic_write_dir(irqnr); 668021f6537SMarc Zyngier #ifdef CONFIG_SMP 669f86c4fbdSWill Deacon /* 670f86c4fbdSWill Deacon * Unlike GICv2, we don't need an smp_rmb() here. 671f86c4fbdSWill Deacon * The control dependency from gic_read_iar to 672f86c4fbdSWill Deacon * the ISB in gic_write_eoir is enough to ensure 673f86c4fbdSWill Deacon * that any shared data read by handle_IPI will 674f86c4fbdSWill Deacon * be read after the ACK. 675f86c4fbdSWill Deacon */ 676021f6537SMarc Zyngier handle_IPI(irqnr, regs); 677021f6537SMarc Zyngier #else 678021f6537SMarc Zyngier WARN_ONCE(true, "Unexpected SGI received!\n"); 679021f6537SMarc Zyngier #endif 680021f6537SMarc Zyngier } 681021f6537SMarc Zyngier } 682021f6537SMarc Zyngier 683b5cf6073SJulien Thierry static u32 gic_get_pribits(void) 684b5cf6073SJulien Thierry { 685b5cf6073SJulien Thierry u32 pribits; 686b5cf6073SJulien Thierry 687b5cf6073SJulien Thierry pribits = gic_read_ctlr(); 688b5cf6073SJulien Thierry pribits &= ICC_CTLR_EL1_PRI_BITS_MASK; 689b5cf6073SJulien Thierry pribits >>= ICC_CTLR_EL1_PRI_BITS_SHIFT; 690b5cf6073SJulien Thierry pribits++; 691b5cf6073SJulien Thierry 692b5cf6073SJulien Thierry return pribits; 693b5cf6073SJulien Thierry } 694b5cf6073SJulien Thierry 695b5cf6073SJulien Thierry static bool gic_has_group0(void) 696b5cf6073SJulien Thierry { 697b5cf6073SJulien Thierry u32 val; 698e7932188SJulien Thierry u32 old_pmr; 699e7932188SJulien Thierry 700e7932188SJulien Thierry old_pmr = gic_read_pmr(); 701b5cf6073SJulien Thierry 702b5cf6073SJulien Thierry /* 703b5cf6073SJulien Thierry * Let's find out if Group0 is under control of EL3 or not by 704b5cf6073SJulien Thierry * setting the highest possible, non-zero priority in PMR. 705b5cf6073SJulien Thierry * 706b5cf6073SJulien Thierry * If SCR_EL3.FIQ is set, the priority gets shifted down in 707b5cf6073SJulien Thierry * order for the CPU interface to set bit 7, and keep the 708b5cf6073SJulien Thierry * actual priority in the non-secure range. In the process, it 709b5cf6073SJulien Thierry * looses the least significant bit and the actual priority 710b5cf6073SJulien Thierry * becomes 0x80. Reading it back returns 0, indicating that 711b5cf6073SJulien Thierry * we're don't have access to Group0. 712b5cf6073SJulien Thierry */ 713b5cf6073SJulien Thierry gic_write_pmr(BIT(8 - gic_get_pribits())); 714b5cf6073SJulien Thierry val = gic_read_pmr(); 715b5cf6073SJulien Thierry 716e7932188SJulien Thierry gic_write_pmr(old_pmr); 717e7932188SJulien Thierry 718b5cf6073SJulien Thierry return val != 0; 719b5cf6073SJulien Thierry } 720b5cf6073SJulien Thierry 721021f6537SMarc Zyngier static void __init gic_dist_init(void) 722021f6537SMarc Zyngier { 723021f6537SMarc Zyngier unsigned int i; 724021f6537SMarc Zyngier u64 affinity; 725021f6537SMarc Zyngier void __iomem *base = gic_data.dist_base; 7260b04758bSMarc Zyngier u32 val; 727021f6537SMarc Zyngier 728021f6537SMarc Zyngier /* Disable the distributor */ 729021f6537SMarc Zyngier writel_relaxed(0, base + GICD_CTLR); 730021f6537SMarc Zyngier gic_dist_wait_for_rwp(); 731021f6537SMarc Zyngier 7327c9b9730SMarc Zyngier /* 7337c9b9730SMarc Zyngier * Configure SPIs as non-secure Group-1. This will only matter 7347c9b9730SMarc Zyngier * if the GIC only has a single security state. This will not 7357c9b9730SMarc Zyngier * do the right thing if the kernel is running in secure mode, 7367c9b9730SMarc Zyngier * but that's not the intended use case anyway. 7377c9b9730SMarc Zyngier */ 738211bddd2SMarc Zyngier for (i = 32; i < GIC_LINE_NR; i += 32) 7397c9b9730SMarc Zyngier writel_relaxed(~0, base + GICD_IGROUPR + i / 8); 7407c9b9730SMarc Zyngier 741211bddd2SMarc Zyngier /* Extended SPI range, not handled by the GICv2/GICv3 common code */ 742211bddd2SMarc Zyngier for (i = 0; i < GIC_ESPI_NR; i += 32) { 743211bddd2SMarc Zyngier writel_relaxed(~0U, base + GICD_ICENABLERnE + i / 8); 744211bddd2SMarc Zyngier writel_relaxed(~0U, base + GICD_ICACTIVERnE + i / 8); 745211bddd2SMarc Zyngier } 746211bddd2SMarc Zyngier 747211bddd2SMarc Zyngier for (i = 0; i < GIC_ESPI_NR; i += 32) 748211bddd2SMarc Zyngier writel_relaxed(~0U, base + GICD_IGROUPRnE + i / 8); 749211bddd2SMarc Zyngier 750211bddd2SMarc Zyngier for (i = 0; i < GIC_ESPI_NR; i += 16) 751211bddd2SMarc Zyngier writel_relaxed(0, base + GICD_ICFGRnE + i / 4); 752211bddd2SMarc Zyngier 753211bddd2SMarc Zyngier for (i = 0; i < GIC_ESPI_NR; i += 4) 754211bddd2SMarc Zyngier writel_relaxed(GICD_INT_DEF_PRI_X4, base + GICD_IPRIORITYRnE + i); 755211bddd2SMarc Zyngier 756211bddd2SMarc Zyngier /* Now do the common stuff, and wait for the distributor to drain */ 757211bddd2SMarc Zyngier gic_dist_config(base, GIC_LINE_NR, gic_dist_wait_for_rwp); 758021f6537SMarc Zyngier 7590b04758bSMarc Zyngier val = GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G1A | GICD_CTLR_ENABLE_G1; 7600b04758bSMarc Zyngier if (gic_data.rdists.gicd_typer2 & GICD_TYPER2_nASSGIcap) { 7610b04758bSMarc Zyngier pr_info("Enabling SGIs without active state\n"); 7620b04758bSMarc Zyngier val |= GICD_CTLR_nASSGIreq; 7630b04758bSMarc Zyngier } 7640b04758bSMarc Zyngier 765021f6537SMarc Zyngier /* Enable distributor with ARE, Group1 */ 7660b04758bSMarc Zyngier writel_relaxed(val, base + GICD_CTLR); 767021f6537SMarc Zyngier 768021f6537SMarc Zyngier /* 769021f6537SMarc Zyngier * Set all global interrupts to the boot CPU only. ARE must be 770021f6537SMarc Zyngier * enabled. 771021f6537SMarc Zyngier */ 772021f6537SMarc Zyngier affinity = gic_mpidr_to_affinity(cpu_logical_map(smp_processor_id())); 773211bddd2SMarc Zyngier for (i = 32; i < GIC_LINE_NR; i++) 77472c97126SJean-Philippe Brucker gic_write_irouter(affinity, base + GICD_IROUTER + i * 8); 775211bddd2SMarc Zyngier 776211bddd2SMarc Zyngier for (i = 0; i < GIC_ESPI_NR; i++) 777211bddd2SMarc Zyngier gic_write_irouter(affinity, base + GICD_IROUTERnE + i * 8); 778021f6537SMarc Zyngier } 779021f6537SMarc Zyngier 7800d94ded2SMarc Zyngier static int gic_iterate_rdists(int (*fn)(struct redist_region *, void __iomem *)) 781021f6537SMarc Zyngier { 7820d94ded2SMarc Zyngier int ret = -ENODEV; 783021f6537SMarc Zyngier int i; 784021f6537SMarc Zyngier 785f5c1434cSMarc Zyngier for (i = 0; i < gic_data.nr_redist_regions; i++) { 786f5c1434cSMarc Zyngier void __iomem *ptr = gic_data.redist_regions[i].redist_base; 7870d94ded2SMarc Zyngier u64 typer; 788021f6537SMarc Zyngier u32 reg; 789021f6537SMarc Zyngier 790021f6537SMarc Zyngier reg = readl_relaxed(ptr + GICR_PIDR2) & GIC_PIDR2_ARCH_MASK; 791021f6537SMarc Zyngier if (reg != GIC_PIDR2_ARCH_GICv3 && 792021f6537SMarc Zyngier reg != GIC_PIDR2_ARCH_GICv4) { /* We're in trouble... */ 793021f6537SMarc Zyngier pr_warn("No redistributor present @%p\n", ptr); 794021f6537SMarc Zyngier break; 795021f6537SMarc Zyngier } 796021f6537SMarc Zyngier 797021f6537SMarc Zyngier do { 79872c97126SJean-Philippe Brucker typer = gic_read_typer(ptr + GICR_TYPER); 7990d94ded2SMarc Zyngier ret = fn(gic_data.redist_regions + i, ptr); 8000d94ded2SMarc Zyngier if (!ret) 801021f6537SMarc Zyngier return 0; 802021f6537SMarc Zyngier 803b70fb7afSTomasz Nowicki if (gic_data.redist_regions[i].single_redist) 804b70fb7afSTomasz Nowicki break; 805b70fb7afSTomasz Nowicki 806021f6537SMarc Zyngier if (gic_data.redist_stride) { 807021f6537SMarc Zyngier ptr += gic_data.redist_stride; 808021f6537SMarc Zyngier } else { 809021f6537SMarc Zyngier ptr += SZ_64K * 2; /* Skip RD_base + SGI_base */ 810021f6537SMarc Zyngier if (typer & GICR_TYPER_VLPIS) 811021f6537SMarc Zyngier ptr += SZ_64K * 2; /* Skip VLPI_base + reserved page */ 812021f6537SMarc Zyngier } 813021f6537SMarc Zyngier } while (!(typer & GICR_TYPER_LAST)); 814021f6537SMarc Zyngier } 815021f6537SMarc Zyngier 8160d94ded2SMarc Zyngier return ret ? -ENODEV : 0; 8170d94ded2SMarc Zyngier } 8180d94ded2SMarc Zyngier 8190d94ded2SMarc Zyngier static int __gic_populate_rdist(struct redist_region *region, void __iomem *ptr) 8200d94ded2SMarc Zyngier { 8210d94ded2SMarc Zyngier unsigned long mpidr = cpu_logical_map(smp_processor_id()); 8220d94ded2SMarc Zyngier u64 typer; 8230d94ded2SMarc Zyngier u32 aff; 8240d94ded2SMarc Zyngier 8250d94ded2SMarc Zyngier /* 8260d94ded2SMarc Zyngier * Convert affinity to a 32bit value that can be matched to 8270d94ded2SMarc Zyngier * GICR_TYPER bits [63:32]. 8280d94ded2SMarc Zyngier */ 8290d94ded2SMarc Zyngier aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 24 | 8300d94ded2SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 | 8310d94ded2SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | 8320d94ded2SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 0)); 8330d94ded2SMarc Zyngier 8340d94ded2SMarc Zyngier typer = gic_read_typer(ptr + GICR_TYPER); 8350d94ded2SMarc Zyngier if ((typer >> 32) == aff) { 8360d94ded2SMarc Zyngier u64 offset = ptr - region->redist_base; 8379058a4e9SMarc Zyngier raw_spin_lock_init(&gic_data_rdist()->rd_lock); 8380d94ded2SMarc Zyngier gic_data_rdist_rd_base() = ptr; 8390d94ded2SMarc Zyngier gic_data_rdist()->phys_base = region->phys_base + offset; 8400d94ded2SMarc Zyngier 8410d94ded2SMarc Zyngier pr_info("CPU%d: found redistributor %lx region %d:%pa\n", 8420d94ded2SMarc Zyngier smp_processor_id(), mpidr, 8430d94ded2SMarc Zyngier (int)(region - gic_data.redist_regions), 8440d94ded2SMarc Zyngier &gic_data_rdist()->phys_base); 8450d94ded2SMarc Zyngier return 0; 8460d94ded2SMarc Zyngier } 8470d94ded2SMarc Zyngier 8480d94ded2SMarc Zyngier /* Try next one */ 8490d94ded2SMarc Zyngier return 1; 8500d94ded2SMarc Zyngier } 8510d94ded2SMarc Zyngier 8520d94ded2SMarc Zyngier static int gic_populate_rdist(void) 8530d94ded2SMarc Zyngier { 8540d94ded2SMarc Zyngier if (gic_iterate_rdists(__gic_populate_rdist) == 0) 8550d94ded2SMarc Zyngier return 0; 8560d94ded2SMarc Zyngier 857021f6537SMarc Zyngier /* We couldn't even deal with ourselves... */ 858f6c86a41SJean-Philippe Brucker WARN(true, "CPU%d: mpidr %lx has no re-distributor!\n", 8590d94ded2SMarc Zyngier smp_processor_id(), 8600d94ded2SMarc Zyngier (unsigned long)cpu_logical_map(smp_processor_id())); 861021f6537SMarc Zyngier return -ENODEV; 862021f6537SMarc Zyngier } 863021f6537SMarc Zyngier 8641a60e1e6SMarc Zyngier static int __gic_update_rdist_properties(struct redist_region *region, 8650edc23eaSMarc Zyngier void __iomem *ptr) 8660edc23eaSMarc Zyngier { 8670edc23eaSMarc Zyngier u64 typer = gic_read_typer(ptr + GICR_TYPER); 868b25319d2SMarc Zyngier 8690edc23eaSMarc Zyngier gic_data.rdists.has_vlpis &= !!(typer & GICR_TYPER_VLPIS); 870b25319d2SMarc Zyngier 871b25319d2SMarc Zyngier /* RVPEID implies some form of DirectLPI, no matter what the doc says... :-/ */ 872b25319d2SMarc Zyngier gic_data.rdists.has_rvpeid &= !!(typer & GICR_TYPER_RVPEID); 873b25319d2SMarc Zyngier gic_data.rdists.has_direct_lpi &= (!!(typer & GICR_TYPER_DirectLPIS) | 874b25319d2SMarc Zyngier gic_data.rdists.has_rvpeid); 875b25319d2SMarc Zyngier 876b25319d2SMarc Zyngier /* Detect non-sensical configurations */ 877b25319d2SMarc Zyngier if (WARN_ON_ONCE(gic_data.rdists.has_rvpeid && !gic_data.rdists.has_vlpis)) { 878b25319d2SMarc Zyngier gic_data.rdists.has_direct_lpi = false; 879b25319d2SMarc Zyngier gic_data.rdists.has_vlpis = false; 880b25319d2SMarc Zyngier gic_data.rdists.has_rvpeid = false; 881b25319d2SMarc Zyngier } 882b25319d2SMarc Zyngier 8835f51f803SMarc Zyngier gic_data.ppi_nr = min(GICR_TYPER_NR_PPIS(typer), gic_data.ppi_nr); 8840edc23eaSMarc Zyngier 8850edc23eaSMarc Zyngier return 1; 8860edc23eaSMarc Zyngier } 8870edc23eaSMarc Zyngier 8881a60e1e6SMarc Zyngier static void gic_update_rdist_properties(void) 8890edc23eaSMarc Zyngier { 8901a60e1e6SMarc Zyngier gic_data.ppi_nr = UINT_MAX; 8911a60e1e6SMarc Zyngier gic_iterate_rdists(__gic_update_rdist_properties); 8921a60e1e6SMarc Zyngier if (WARN_ON(gic_data.ppi_nr == UINT_MAX)) 8931a60e1e6SMarc Zyngier gic_data.ppi_nr = 0; 8941a60e1e6SMarc Zyngier pr_info("%d PPIs implemented\n", gic_data.ppi_nr); 895b25319d2SMarc Zyngier pr_info("%sVLPI support, %sdirect LPI support, %sRVPEID support\n", 8960edc23eaSMarc Zyngier !gic_data.rdists.has_vlpis ? "no " : "", 897b25319d2SMarc Zyngier !gic_data.rdists.has_direct_lpi ? "no " : "", 898b25319d2SMarc Zyngier !gic_data.rdists.has_rvpeid ? "no " : ""); 8990edc23eaSMarc Zyngier } 9000edc23eaSMarc Zyngier 901d98d0a99SJulien Thierry /* Check whether it's single security state view */ 902d98d0a99SJulien Thierry static inline bool gic_dist_security_disabled(void) 903d98d0a99SJulien Thierry { 904d98d0a99SJulien Thierry return readl_relaxed(gic_data.dist_base + GICD_CTLR) & GICD_CTLR_DS; 905d98d0a99SJulien Thierry } 906d98d0a99SJulien Thierry 9073708d52fSSudeep Holla static void gic_cpu_sys_reg_init(void) 908021f6537SMarc Zyngier { 909eda0d04aSShanker Donthineni int i, cpu = smp_processor_id(); 910eda0d04aSShanker Donthineni u64 mpidr = cpu_logical_map(cpu); 911eda0d04aSShanker Donthineni u64 need_rss = MPIDR_RS(mpidr); 91233625282SMarc Zyngier bool group0; 913b5cf6073SJulien Thierry u32 pribits; 914eda0d04aSShanker Donthineni 9157cabd008SMarc Zyngier /* 9167cabd008SMarc Zyngier * Need to check that the SRE bit has actually been set. If 9177cabd008SMarc Zyngier * not, it means that SRE is disabled at EL2. We're going to 9187cabd008SMarc Zyngier * die painfully, and there is nothing we can do about it. 9197cabd008SMarc Zyngier * 9207cabd008SMarc Zyngier * Kindly inform the luser. 9217cabd008SMarc Zyngier */ 9227cabd008SMarc Zyngier if (!gic_enable_sre()) 9237cabd008SMarc Zyngier pr_err("GIC: unable to set SRE (disabled at EL2), panic ahead\n"); 924021f6537SMarc Zyngier 925b5cf6073SJulien Thierry pribits = gic_get_pribits(); 92633625282SMarc Zyngier 927b5cf6073SJulien Thierry group0 = gic_has_group0(); 92833625282SMarc Zyngier 929021f6537SMarc Zyngier /* Set priority mask register */ 930d98d0a99SJulien Thierry if (!gic_prio_masking_enabled()) { 93133625282SMarc Zyngier write_gicreg(DEFAULT_PMR_VALUE, ICC_PMR_EL1); 932d98d0a99SJulien Thierry } else { 933d98d0a99SJulien Thierry /* 934d98d0a99SJulien Thierry * Mismatch configuration with boot CPU, the system is likely 935d98d0a99SJulien Thierry * to die as interrupt masking will not work properly on all 936d98d0a99SJulien Thierry * CPUs 937d98d0a99SJulien Thierry */ 938d98d0a99SJulien Thierry WARN_ON(gic_supports_nmi() && group0 && 939d98d0a99SJulien Thierry !gic_dist_security_disabled()); 940d98d0a99SJulien Thierry } 941021f6537SMarc Zyngier 94291ef8442SDaniel Thompson /* 94391ef8442SDaniel Thompson * Some firmwares hand over to the kernel with the BPR changed from 94491ef8442SDaniel Thompson * its reset value (and with a value large enough to prevent 94591ef8442SDaniel Thompson * any pre-emptive interrupts from working at all). Writing a zero 94691ef8442SDaniel Thompson * to BPR restores is reset value. 94791ef8442SDaniel Thompson */ 94891ef8442SDaniel Thompson gic_write_bpr1(0); 94991ef8442SDaniel Thompson 950d01d3274SDavidlohr Bueso if (static_branch_likely(&supports_deactivate_key)) { 9510b6a3da9SMarc Zyngier /* EOI drops priority only (mode 1) */ 9520b6a3da9SMarc Zyngier gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop); 9530b6a3da9SMarc Zyngier } else { 954021f6537SMarc Zyngier /* EOI deactivates interrupt too (mode 0) */ 955021f6537SMarc Zyngier gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop_dir); 9560b6a3da9SMarc Zyngier } 957021f6537SMarc Zyngier 95833625282SMarc Zyngier /* Always whack Group0 before Group1 */ 95933625282SMarc Zyngier if (group0) { 96033625282SMarc Zyngier switch(pribits) { 96133625282SMarc Zyngier case 8: 96233625282SMarc Zyngier case 7: 96333625282SMarc Zyngier write_gicreg(0, ICC_AP0R3_EL1); 96433625282SMarc Zyngier write_gicreg(0, ICC_AP0R2_EL1); 96552f8c8b3SAnders Roxell /* Fall through */ 96633625282SMarc Zyngier case 6: 96733625282SMarc Zyngier write_gicreg(0, ICC_AP0R1_EL1); 96852f8c8b3SAnders Roxell /* Fall through */ 96933625282SMarc Zyngier case 5: 97033625282SMarc Zyngier case 4: 97133625282SMarc Zyngier write_gicreg(0, ICC_AP0R0_EL1); 97233625282SMarc Zyngier } 973d6062a6dSMarc Zyngier 97433625282SMarc Zyngier isb(); 97533625282SMarc Zyngier } 97633625282SMarc Zyngier 97733625282SMarc Zyngier switch(pribits) { 978d6062a6dSMarc Zyngier case 8: 979d6062a6dSMarc Zyngier case 7: 980d6062a6dSMarc Zyngier write_gicreg(0, ICC_AP1R3_EL1); 981d6062a6dSMarc Zyngier write_gicreg(0, ICC_AP1R2_EL1); 98252f8c8b3SAnders Roxell /* Fall through */ 983d6062a6dSMarc Zyngier case 6: 984d6062a6dSMarc Zyngier write_gicreg(0, ICC_AP1R1_EL1); 98552f8c8b3SAnders Roxell /* Fall through */ 986d6062a6dSMarc Zyngier case 5: 987d6062a6dSMarc Zyngier case 4: 988d6062a6dSMarc Zyngier write_gicreg(0, ICC_AP1R0_EL1); 989d6062a6dSMarc Zyngier } 990d6062a6dSMarc Zyngier 991d6062a6dSMarc Zyngier isb(); 992d6062a6dSMarc Zyngier 993021f6537SMarc Zyngier /* ... and let's hit the road... */ 994021f6537SMarc Zyngier gic_write_grpen1(1); 995eda0d04aSShanker Donthineni 996eda0d04aSShanker Donthineni /* Keep the RSS capability status in per_cpu variable */ 997eda0d04aSShanker Donthineni per_cpu(has_rss, cpu) = !!(gic_read_ctlr() & ICC_CTLR_EL1_RSS); 998eda0d04aSShanker Donthineni 999eda0d04aSShanker Donthineni /* Check all the CPUs have capable of sending SGIs to other CPUs */ 1000eda0d04aSShanker Donthineni for_each_online_cpu(i) { 1001eda0d04aSShanker Donthineni bool have_rss = per_cpu(has_rss, i) && per_cpu(has_rss, cpu); 1002eda0d04aSShanker Donthineni 1003eda0d04aSShanker Donthineni need_rss |= MPIDR_RS(cpu_logical_map(i)); 1004eda0d04aSShanker Donthineni if (need_rss && (!have_rss)) 1005eda0d04aSShanker Donthineni pr_crit("CPU%d (%lx) can't SGI CPU%d (%lx), no RSS\n", 1006eda0d04aSShanker Donthineni cpu, (unsigned long)mpidr, 1007eda0d04aSShanker Donthineni i, (unsigned long)cpu_logical_map(i)); 1008eda0d04aSShanker Donthineni } 1009eda0d04aSShanker Donthineni 1010eda0d04aSShanker Donthineni /** 1011eda0d04aSShanker Donthineni * GIC spec says, when ICC_CTLR_EL1.RSS==1 and GICD_TYPER.RSS==0, 1012eda0d04aSShanker Donthineni * writing ICC_ASGI1R_EL1 register with RS != 0 is a CONSTRAINED 1013eda0d04aSShanker Donthineni * UNPREDICTABLE choice of : 1014eda0d04aSShanker Donthineni * - The write is ignored. 1015eda0d04aSShanker Donthineni * - The RS field is treated as 0. 1016eda0d04aSShanker Donthineni */ 1017eda0d04aSShanker Donthineni if (need_rss && (!gic_data.has_rss)) 1018eda0d04aSShanker Donthineni pr_crit_once("RSS is required but GICD doesn't support it\n"); 1019021f6537SMarc Zyngier } 1020021f6537SMarc Zyngier 1021f736d65dSMarc Zyngier static bool gicv3_nolpi; 1022f736d65dSMarc Zyngier 1023f736d65dSMarc Zyngier static int __init gicv3_nolpi_cfg(char *buf) 1024f736d65dSMarc Zyngier { 1025f736d65dSMarc Zyngier return strtobool(buf, &gicv3_nolpi); 1026f736d65dSMarc Zyngier } 1027f736d65dSMarc Zyngier early_param("irqchip.gicv3_nolpi", gicv3_nolpi_cfg); 1028f736d65dSMarc Zyngier 1029da33f31dSMarc Zyngier static int gic_dist_supports_lpis(void) 1030da33f31dSMarc Zyngier { 1031d38a71c5SMarc Zyngier return (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && 1032d38a71c5SMarc Zyngier !!(readl_relaxed(gic_data.dist_base + GICD_TYPER) & GICD_TYPER_LPIS) && 1033d38a71c5SMarc Zyngier !gicv3_nolpi); 1034da33f31dSMarc Zyngier } 1035da33f31dSMarc Zyngier 1036021f6537SMarc Zyngier static void gic_cpu_init(void) 1037021f6537SMarc Zyngier { 1038021f6537SMarc Zyngier void __iomem *rbase; 10391a60e1e6SMarc Zyngier int i; 1040021f6537SMarc Zyngier 1041021f6537SMarc Zyngier /* Register ourselves with the rest of the world */ 1042021f6537SMarc Zyngier if (gic_populate_rdist()) 1043021f6537SMarc Zyngier return; 1044021f6537SMarc Zyngier 1045a2c22510SSudeep Holla gic_enable_redist(true); 1046021f6537SMarc Zyngier 1047ad5a78d3SMarc Zyngier WARN((gic_data.ppi_nr > 16 || GIC_ESPI_NR != 0) && 1048ad5a78d3SMarc Zyngier !(gic_read_ctlr() & ICC_CTLR_EL1_ExtRange), 1049ad5a78d3SMarc Zyngier "Distributor has extended ranges, but CPU%d doesn't\n", 1050ad5a78d3SMarc Zyngier smp_processor_id()); 1051ad5a78d3SMarc Zyngier 1052021f6537SMarc Zyngier rbase = gic_data_rdist_sgi_base(); 1053021f6537SMarc Zyngier 10547c9b9730SMarc Zyngier /* Configure SGIs/PPIs as non-secure Group-1 */ 10551a60e1e6SMarc Zyngier for (i = 0; i < gic_data.ppi_nr + 16; i += 32) 10561a60e1e6SMarc Zyngier writel_relaxed(~0, rbase + GICR_IGROUPR0 + i / 8); 10577c9b9730SMarc Zyngier 10581a60e1e6SMarc Zyngier gic_cpu_config(rbase, gic_data.ppi_nr + 16, gic_redist_wait_for_rwp); 1059021f6537SMarc Zyngier 10603708d52fSSudeep Holla /* initialise system registers */ 10613708d52fSSudeep Holla gic_cpu_sys_reg_init(); 1062021f6537SMarc Zyngier } 1063021f6537SMarc Zyngier 1064021f6537SMarc Zyngier #ifdef CONFIG_SMP 1065021f6537SMarc Zyngier 1066eda0d04aSShanker Donthineni #define MPIDR_TO_SGI_RS(mpidr) (MPIDR_RS(mpidr) << ICC_SGI1R_RS_SHIFT) 1067eda0d04aSShanker Donthineni #define MPIDR_TO_SGI_CLUSTER_ID(mpidr) ((mpidr) & ~0xFUL) 1068eda0d04aSShanker Donthineni 10696670a6d8SRichard Cochran static int gic_starting_cpu(unsigned int cpu) 10706670a6d8SRichard Cochran { 10716670a6d8SRichard Cochran gic_cpu_init(); 1072d38a71c5SMarc Zyngier 1073d38a71c5SMarc Zyngier if (gic_dist_supports_lpis()) 1074d38a71c5SMarc Zyngier its_cpu_init(); 1075d38a71c5SMarc Zyngier 10766670a6d8SRichard Cochran return 0; 10776670a6d8SRichard Cochran } 1078021f6537SMarc Zyngier 1079021f6537SMarc Zyngier static u16 gic_compute_target_list(int *base_cpu, const struct cpumask *mask, 1080f6c86a41SJean-Philippe Brucker unsigned long cluster_id) 1081021f6537SMarc Zyngier { 1082727653d6SJames Morse int next_cpu, cpu = *base_cpu; 1083f6c86a41SJean-Philippe Brucker unsigned long mpidr = cpu_logical_map(cpu); 1084021f6537SMarc Zyngier u16 tlist = 0; 1085021f6537SMarc Zyngier 1086021f6537SMarc Zyngier while (cpu < nr_cpu_ids) { 1087021f6537SMarc Zyngier tlist |= 1 << (mpidr & 0xf); 1088021f6537SMarc Zyngier 1089727653d6SJames Morse next_cpu = cpumask_next(cpu, mask); 1090727653d6SJames Morse if (next_cpu >= nr_cpu_ids) 1091021f6537SMarc Zyngier goto out; 1092727653d6SJames Morse cpu = next_cpu; 1093021f6537SMarc Zyngier 1094021f6537SMarc Zyngier mpidr = cpu_logical_map(cpu); 1095021f6537SMarc Zyngier 1096eda0d04aSShanker Donthineni if (cluster_id != MPIDR_TO_SGI_CLUSTER_ID(mpidr)) { 1097021f6537SMarc Zyngier cpu--; 1098021f6537SMarc Zyngier goto out; 1099021f6537SMarc Zyngier } 1100021f6537SMarc Zyngier } 1101021f6537SMarc Zyngier out: 1102021f6537SMarc Zyngier *base_cpu = cpu; 1103021f6537SMarc Zyngier return tlist; 1104021f6537SMarc Zyngier } 1105021f6537SMarc Zyngier 11067e580278SAndre Przywara #define MPIDR_TO_SGI_AFFINITY(cluster_id, level) \ 11077e580278SAndre Przywara (MPIDR_AFFINITY_LEVEL(cluster_id, level) \ 11087e580278SAndre Przywara << ICC_SGI1R_AFFINITY_## level ##_SHIFT) 11097e580278SAndre Przywara 1110021f6537SMarc Zyngier static void gic_send_sgi(u64 cluster_id, u16 tlist, unsigned int irq) 1111021f6537SMarc Zyngier { 1112021f6537SMarc Zyngier u64 val; 1113021f6537SMarc Zyngier 11147e580278SAndre Przywara val = (MPIDR_TO_SGI_AFFINITY(cluster_id, 3) | 11157e580278SAndre Przywara MPIDR_TO_SGI_AFFINITY(cluster_id, 2) | 11167e580278SAndre Przywara irq << ICC_SGI1R_SGI_ID_SHIFT | 11177e580278SAndre Przywara MPIDR_TO_SGI_AFFINITY(cluster_id, 1) | 1118eda0d04aSShanker Donthineni MPIDR_TO_SGI_RS(cluster_id) | 11197e580278SAndre Przywara tlist << ICC_SGI1R_TARGET_LIST_SHIFT); 1120021f6537SMarc Zyngier 1121b6dd4d83SMark Salter pr_devel("CPU%d: ICC_SGI1R_EL1 %llx\n", smp_processor_id(), val); 1122021f6537SMarc Zyngier gic_write_sgi1r(val); 1123021f6537SMarc Zyngier } 1124021f6537SMarc Zyngier 1125021f6537SMarc Zyngier static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) 1126021f6537SMarc Zyngier { 1127021f6537SMarc Zyngier int cpu; 1128021f6537SMarc Zyngier 1129021f6537SMarc Zyngier if (WARN_ON(irq >= 16)) 1130021f6537SMarc Zyngier return; 1131021f6537SMarc Zyngier 1132021f6537SMarc Zyngier /* 1133021f6537SMarc Zyngier * Ensure that stores to Normal memory are visible to the 1134021f6537SMarc Zyngier * other CPUs before issuing the IPI. 1135021f6537SMarc Zyngier */ 113621ec30c0SShanker Donthineni wmb(); 1137021f6537SMarc Zyngier 1138f9b531feSRusty Russell for_each_cpu(cpu, mask) { 1139eda0d04aSShanker Donthineni u64 cluster_id = MPIDR_TO_SGI_CLUSTER_ID(cpu_logical_map(cpu)); 1140021f6537SMarc Zyngier u16 tlist; 1141021f6537SMarc Zyngier 1142021f6537SMarc Zyngier tlist = gic_compute_target_list(&cpu, mask, cluster_id); 1143021f6537SMarc Zyngier gic_send_sgi(cluster_id, tlist, irq); 1144021f6537SMarc Zyngier } 1145021f6537SMarc Zyngier 1146021f6537SMarc Zyngier /* Force the above writes to ICC_SGI1R_EL1 to be executed */ 1147021f6537SMarc Zyngier isb(); 1148021f6537SMarc Zyngier } 1149021f6537SMarc Zyngier 1150021f6537SMarc Zyngier static void gic_smp_init(void) 1151021f6537SMarc Zyngier { 1152021f6537SMarc Zyngier set_smp_cross_call(gic_raise_softirq); 11536896bcd1SThomas Gleixner cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_GIC_STARTING, 115473c1b41eSThomas Gleixner "irqchip/arm/gicv3:starting", 115573c1b41eSThomas Gleixner gic_starting_cpu, NULL); 1156021f6537SMarc Zyngier } 1157021f6537SMarc Zyngier 1158021f6537SMarc Zyngier static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, 1159021f6537SMarc Zyngier bool force) 1160021f6537SMarc Zyngier { 116165a30f8bSSuzuki K Poulose unsigned int cpu; 1162e91b036eSMarc Zyngier u32 offset, index; 1163021f6537SMarc Zyngier void __iomem *reg; 1164021f6537SMarc Zyngier int enabled; 1165021f6537SMarc Zyngier u64 val; 1166021f6537SMarc Zyngier 116765a30f8bSSuzuki K Poulose if (force) 116865a30f8bSSuzuki K Poulose cpu = cpumask_first(mask_val); 116965a30f8bSSuzuki K Poulose else 117065a30f8bSSuzuki K Poulose cpu = cpumask_any_and(mask_val, cpu_online_mask); 117165a30f8bSSuzuki K Poulose 1172866d7c1bSSuzuki K Poulose if (cpu >= nr_cpu_ids) 1173866d7c1bSSuzuki K Poulose return -EINVAL; 1174866d7c1bSSuzuki K Poulose 1175021f6537SMarc Zyngier if (gic_irq_in_rdist(d)) 1176021f6537SMarc Zyngier return -EINVAL; 1177021f6537SMarc Zyngier 1178021f6537SMarc Zyngier /* If interrupt was enabled, disable it first */ 1179021f6537SMarc Zyngier enabled = gic_peek_irq(d, GICD_ISENABLER); 1180021f6537SMarc Zyngier if (enabled) 1181021f6537SMarc Zyngier gic_mask_irq(d); 1182021f6537SMarc Zyngier 1183e91b036eSMarc Zyngier offset = convert_offset_index(d, GICD_IROUTER, &index); 1184e91b036eSMarc Zyngier reg = gic_dist_base(d) + offset + (index * 8); 1185021f6537SMarc Zyngier val = gic_mpidr_to_affinity(cpu_logical_map(cpu)); 1186021f6537SMarc Zyngier 118772c97126SJean-Philippe Brucker gic_write_irouter(val, reg); 1188021f6537SMarc Zyngier 1189021f6537SMarc Zyngier /* 1190021f6537SMarc Zyngier * If the interrupt was enabled, enabled it again. Otherwise, 1191021f6537SMarc Zyngier * just wait for the distributor to have digested our changes. 1192021f6537SMarc Zyngier */ 1193021f6537SMarc Zyngier if (enabled) 1194021f6537SMarc Zyngier gic_unmask_irq(d); 1195021f6537SMarc Zyngier else 1196021f6537SMarc Zyngier gic_dist_wait_for_rwp(); 1197021f6537SMarc Zyngier 1198956ae91aSMarc Zyngier irq_data_update_effective_affinity(d, cpumask_of(cpu)); 1199956ae91aSMarc Zyngier 12000fc6fa29SAntoine Tenart return IRQ_SET_MASK_OK_DONE; 1201021f6537SMarc Zyngier } 1202021f6537SMarc Zyngier #else 1203021f6537SMarc Zyngier #define gic_set_affinity NULL 1204021f6537SMarc Zyngier #define gic_smp_init() do { } while(0) 1205021f6537SMarc Zyngier #endif 1206021f6537SMarc Zyngier 12073708d52fSSudeep Holla #ifdef CONFIG_CPU_PM 12083708d52fSSudeep Holla static int gic_cpu_pm_notifier(struct notifier_block *self, 12093708d52fSSudeep Holla unsigned long cmd, void *v) 12103708d52fSSudeep Holla { 12113708d52fSSudeep Holla if (cmd == CPU_PM_EXIT) { 1212ccd9432aSSudeep Holla if (gic_dist_security_disabled()) 12133708d52fSSudeep Holla gic_enable_redist(true); 12143708d52fSSudeep Holla gic_cpu_sys_reg_init(); 1215ccd9432aSSudeep Holla } else if (cmd == CPU_PM_ENTER && gic_dist_security_disabled()) { 12163708d52fSSudeep Holla gic_write_grpen1(0); 12173708d52fSSudeep Holla gic_enable_redist(false); 12183708d52fSSudeep Holla } 12193708d52fSSudeep Holla return NOTIFY_OK; 12203708d52fSSudeep Holla } 12213708d52fSSudeep Holla 12223708d52fSSudeep Holla static struct notifier_block gic_cpu_pm_notifier_block = { 12233708d52fSSudeep Holla .notifier_call = gic_cpu_pm_notifier, 12243708d52fSSudeep Holla }; 12253708d52fSSudeep Holla 12263708d52fSSudeep Holla static void gic_cpu_pm_init(void) 12273708d52fSSudeep Holla { 12283708d52fSSudeep Holla cpu_pm_register_notifier(&gic_cpu_pm_notifier_block); 12293708d52fSSudeep Holla } 12303708d52fSSudeep Holla 12313708d52fSSudeep Holla #else 12323708d52fSSudeep Holla static inline void gic_cpu_pm_init(void) { } 12333708d52fSSudeep Holla #endif /* CONFIG_CPU_PM */ 12343708d52fSSudeep Holla 1235021f6537SMarc Zyngier static struct irq_chip gic_chip = { 1236021f6537SMarc Zyngier .name = "GICv3", 1237021f6537SMarc Zyngier .irq_mask = gic_mask_irq, 1238021f6537SMarc Zyngier .irq_unmask = gic_unmask_irq, 1239021f6537SMarc Zyngier .irq_eoi = gic_eoi_irq, 1240021f6537SMarc Zyngier .irq_set_type = gic_set_type, 1241021f6537SMarc Zyngier .irq_set_affinity = gic_set_affinity, 1242b594c6e2SMarc Zyngier .irq_get_irqchip_state = gic_irq_get_irqchip_state, 1243b594c6e2SMarc Zyngier .irq_set_irqchip_state = gic_irq_set_irqchip_state, 1244101b35f7SJulien Thierry .irq_nmi_setup = gic_irq_nmi_setup, 1245101b35f7SJulien Thierry .irq_nmi_teardown = gic_irq_nmi_teardown, 12464110b5cbSMarc Zyngier .flags = IRQCHIP_SET_TYPE_MASKED | 12474110b5cbSMarc Zyngier IRQCHIP_SKIP_SET_WAKE | 12484110b5cbSMarc Zyngier IRQCHIP_MASK_ON_SUSPEND, 1249021f6537SMarc Zyngier }; 1250021f6537SMarc Zyngier 12510b6a3da9SMarc Zyngier static struct irq_chip gic_eoimode1_chip = { 12520b6a3da9SMarc Zyngier .name = "GICv3", 12530b6a3da9SMarc Zyngier .irq_mask = gic_eoimode1_mask_irq, 12540b6a3da9SMarc Zyngier .irq_unmask = gic_unmask_irq, 12550b6a3da9SMarc Zyngier .irq_eoi = gic_eoimode1_eoi_irq, 12560b6a3da9SMarc Zyngier .irq_set_type = gic_set_type, 12570b6a3da9SMarc Zyngier .irq_set_affinity = gic_set_affinity, 12580b6a3da9SMarc Zyngier .irq_get_irqchip_state = gic_irq_get_irqchip_state, 12590b6a3da9SMarc Zyngier .irq_set_irqchip_state = gic_irq_set_irqchip_state, 1260530bf353SMarc Zyngier .irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity, 1261101b35f7SJulien Thierry .irq_nmi_setup = gic_irq_nmi_setup, 1262101b35f7SJulien Thierry .irq_nmi_teardown = gic_irq_nmi_teardown, 12634110b5cbSMarc Zyngier .flags = IRQCHIP_SET_TYPE_MASKED | 12644110b5cbSMarc Zyngier IRQCHIP_SKIP_SET_WAKE | 12654110b5cbSMarc Zyngier IRQCHIP_MASK_ON_SUSPEND, 12660b6a3da9SMarc Zyngier }; 12670b6a3da9SMarc Zyngier 1268021f6537SMarc Zyngier static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq, 1269021f6537SMarc Zyngier irq_hw_number_t hw) 1270021f6537SMarc Zyngier { 12710b6a3da9SMarc Zyngier struct irq_chip *chip = &gic_chip; 12720b6a3da9SMarc Zyngier 1273d01d3274SDavidlohr Bueso if (static_branch_likely(&supports_deactivate_key)) 12740b6a3da9SMarc Zyngier chip = &gic_eoimode1_chip; 12750b6a3da9SMarc Zyngier 1276e91b036eSMarc Zyngier switch (__get_intid_range(hw)) { 1277e91b036eSMarc Zyngier case PPI_RANGE: 12785f51f803SMarc Zyngier case EPPI_RANGE: 1279021f6537SMarc Zyngier irq_set_percpu_devid(irq); 12800b6a3da9SMarc Zyngier irq_domain_set_info(d, irq, hw, chip, d->host_data, 1281443acc4fSMarc Zyngier handle_percpu_devid_irq, NULL, NULL); 1282d17cab44SRob Herring irq_set_status_flags(irq, IRQ_NOAUTOEN); 1283e91b036eSMarc Zyngier break; 1284e91b036eSMarc Zyngier 1285e91b036eSMarc Zyngier case SPI_RANGE: 1286211bddd2SMarc Zyngier case ESPI_RANGE: 12870b6a3da9SMarc Zyngier irq_domain_set_info(d, irq, hw, chip, d->host_data, 1288443acc4fSMarc Zyngier handle_fasteoi_irq, NULL, NULL); 1289d17cab44SRob Herring irq_set_probe(irq); 1290956ae91aSMarc Zyngier irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(irq))); 1291e91b036eSMarc Zyngier break; 1292e91b036eSMarc Zyngier 1293e91b036eSMarc Zyngier case LPI_RANGE: 1294da33f31dSMarc Zyngier if (!gic_dist_supports_lpis()) 1295da33f31dSMarc Zyngier return -EPERM; 12960b6a3da9SMarc Zyngier irq_domain_set_info(d, irq, hw, chip, d->host_data, 1297da33f31dSMarc Zyngier handle_fasteoi_irq, NULL, NULL); 1298e91b036eSMarc Zyngier break; 1299e91b036eSMarc Zyngier 1300e91b036eSMarc Zyngier default: 1301e91b036eSMarc Zyngier return -EPERM; 1302da33f31dSMarc Zyngier } 1303da33f31dSMarc Zyngier 1304021f6537SMarc Zyngier return 0; 1305021f6537SMarc Zyngier } 1306021f6537SMarc Zyngier 130765da7d19SMarc Zyngier #define GIC_IRQ_TYPE_PARTITION (GIC_IRQ_TYPE_LPI + 1) 130865da7d19SMarc Zyngier 1309f833f57fSMarc Zyngier static int gic_irq_domain_translate(struct irq_domain *d, 1310f833f57fSMarc Zyngier struct irq_fwspec *fwspec, 1311f833f57fSMarc Zyngier unsigned long *hwirq, 1312f833f57fSMarc Zyngier unsigned int *type) 1313021f6537SMarc Zyngier { 1314f833f57fSMarc Zyngier if (is_of_node(fwspec->fwnode)) { 1315f833f57fSMarc Zyngier if (fwspec->param_count < 3) 1316021f6537SMarc Zyngier return -EINVAL; 1317021f6537SMarc Zyngier 1318db8c70ecSMarc Zyngier switch (fwspec->param[0]) { 1319db8c70ecSMarc Zyngier case 0: /* SPI */ 1320db8c70ecSMarc Zyngier *hwirq = fwspec->param[1] + 32; 1321db8c70ecSMarc Zyngier break; 1322db8c70ecSMarc Zyngier case 1: /* PPI */ 1323f833f57fSMarc Zyngier *hwirq = fwspec->param[1] + 16; 1324db8c70ecSMarc Zyngier break; 1325211bddd2SMarc Zyngier case 2: /* ESPI */ 1326211bddd2SMarc Zyngier *hwirq = fwspec->param[1] + ESPI_BASE_INTID; 1327211bddd2SMarc Zyngier break; 13285f51f803SMarc Zyngier case 3: /* EPPI */ 13295f51f803SMarc Zyngier *hwirq = fwspec->param[1] + EPPI_BASE_INTID; 13305f51f803SMarc Zyngier break; 1331db8c70ecSMarc Zyngier case GIC_IRQ_TYPE_LPI: /* LPI */ 1332db8c70ecSMarc Zyngier *hwirq = fwspec->param[1]; 1333db8c70ecSMarc Zyngier break; 13345f51f803SMarc Zyngier case GIC_IRQ_TYPE_PARTITION: 13355f51f803SMarc Zyngier *hwirq = fwspec->param[1]; 13365f51f803SMarc Zyngier if (fwspec->param[1] >= 16) 13375f51f803SMarc Zyngier *hwirq += EPPI_BASE_INTID - 16; 13385f51f803SMarc Zyngier else 13395f51f803SMarc Zyngier *hwirq += 16; 13405f51f803SMarc Zyngier break; 1341db8c70ecSMarc Zyngier default: 1342db8c70ecSMarc Zyngier return -EINVAL; 1343db8c70ecSMarc Zyngier } 1344f833f57fSMarc Zyngier 1345f833f57fSMarc Zyngier *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; 13466ef6386eSMarc Zyngier 134765da7d19SMarc Zyngier /* 134865da7d19SMarc Zyngier * Make it clear that broken DTs are... broken. 134965da7d19SMarc Zyngier * Partitionned PPIs are an unfortunate exception. 135065da7d19SMarc Zyngier */ 135165da7d19SMarc Zyngier WARN_ON(*type == IRQ_TYPE_NONE && 135265da7d19SMarc Zyngier fwspec->param[0] != GIC_IRQ_TYPE_PARTITION); 1353f833f57fSMarc Zyngier return 0; 1354021f6537SMarc Zyngier } 1355021f6537SMarc Zyngier 1356ffa7d616STomasz Nowicki if (is_fwnode_irqchip(fwspec->fwnode)) { 1357ffa7d616STomasz Nowicki if(fwspec->param_count != 2) 1358ffa7d616STomasz Nowicki return -EINVAL; 1359ffa7d616STomasz Nowicki 1360ffa7d616STomasz Nowicki *hwirq = fwspec->param[0]; 1361ffa7d616STomasz Nowicki *type = fwspec->param[1]; 13626ef6386eSMarc Zyngier 13636ef6386eSMarc Zyngier WARN_ON(*type == IRQ_TYPE_NONE); 1364ffa7d616STomasz Nowicki return 0; 1365ffa7d616STomasz Nowicki } 1366ffa7d616STomasz Nowicki 1367f833f57fSMarc Zyngier return -EINVAL; 1368021f6537SMarc Zyngier } 1369021f6537SMarc Zyngier 1370443acc4fSMarc Zyngier static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, 1371443acc4fSMarc Zyngier unsigned int nr_irqs, void *arg) 1372443acc4fSMarc Zyngier { 1373443acc4fSMarc Zyngier int i, ret; 1374443acc4fSMarc Zyngier irq_hw_number_t hwirq; 1375443acc4fSMarc Zyngier unsigned int type = IRQ_TYPE_NONE; 1376f833f57fSMarc Zyngier struct irq_fwspec *fwspec = arg; 1377443acc4fSMarc Zyngier 1378f833f57fSMarc Zyngier ret = gic_irq_domain_translate(domain, fwspec, &hwirq, &type); 1379443acc4fSMarc Zyngier if (ret) 1380443acc4fSMarc Zyngier return ret; 1381443acc4fSMarc Zyngier 138263c16c6eSSuzuki K Poulose for (i = 0; i < nr_irqs; i++) { 138363c16c6eSSuzuki K Poulose ret = gic_irq_domain_map(domain, virq + i, hwirq + i); 138463c16c6eSSuzuki K Poulose if (ret) 138563c16c6eSSuzuki K Poulose return ret; 138663c16c6eSSuzuki K Poulose } 1387443acc4fSMarc Zyngier 1388443acc4fSMarc Zyngier return 0; 1389443acc4fSMarc Zyngier } 1390443acc4fSMarc Zyngier 1391443acc4fSMarc Zyngier static void gic_irq_domain_free(struct irq_domain *domain, unsigned int virq, 1392443acc4fSMarc Zyngier unsigned int nr_irqs) 1393443acc4fSMarc Zyngier { 1394443acc4fSMarc Zyngier int i; 1395443acc4fSMarc Zyngier 1396443acc4fSMarc Zyngier for (i = 0; i < nr_irqs; i++) { 1397443acc4fSMarc Zyngier struct irq_data *d = irq_domain_get_irq_data(domain, virq + i); 1398443acc4fSMarc Zyngier irq_set_handler(virq + i, NULL); 1399443acc4fSMarc Zyngier irq_domain_reset_irq_data(d); 1400443acc4fSMarc Zyngier } 1401443acc4fSMarc Zyngier } 1402443acc4fSMarc Zyngier 1403e3825ba1SMarc Zyngier static int gic_irq_domain_select(struct irq_domain *d, 1404e3825ba1SMarc Zyngier struct irq_fwspec *fwspec, 1405e3825ba1SMarc Zyngier enum irq_domain_bus_token bus_token) 1406e3825ba1SMarc Zyngier { 1407e3825ba1SMarc Zyngier /* Not for us */ 1408e3825ba1SMarc Zyngier if (fwspec->fwnode != d->fwnode) 1409e3825ba1SMarc Zyngier return 0; 1410e3825ba1SMarc Zyngier 1411e3825ba1SMarc Zyngier /* If this is not DT, then we have a single domain */ 1412e3825ba1SMarc Zyngier if (!is_of_node(fwspec->fwnode)) 1413e3825ba1SMarc Zyngier return 1; 1414e3825ba1SMarc Zyngier 1415e3825ba1SMarc Zyngier /* 1416e3825ba1SMarc Zyngier * If this is a PPI and we have a 4th (non-null) parameter, 1417e3825ba1SMarc Zyngier * then we need to match the partition domain. 1418e3825ba1SMarc Zyngier */ 1419e3825ba1SMarc Zyngier if (fwspec->param_count >= 4 && 142052085d3fSMarc Zyngier fwspec->param[0] == 1 && fwspec->param[3] != 0 && 142152085d3fSMarc Zyngier gic_data.ppi_descs) 1422e3825ba1SMarc Zyngier return d == partition_get_domain(gic_data.ppi_descs[fwspec->param[1]]); 1423e3825ba1SMarc Zyngier 1424e3825ba1SMarc Zyngier return d == gic_data.domain; 1425e3825ba1SMarc Zyngier } 1426e3825ba1SMarc Zyngier 1427021f6537SMarc Zyngier static const struct irq_domain_ops gic_irq_domain_ops = { 1428f833f57fSMarc Zyngier .translate = gic_irq_domain_translate, 1429443acc4fSMarc Zyngier .alloc = gic_irq_domain_alloc, 1430443acc4fSMarc Zyngier .free = gic_irq_domain_free, 1431e3825ba1SMarc Zyngier .select = gic_irq_domain_select, 1432e3825ba1SMarc Zyngier }; 1433e3825ba1SMarc Zyngier 1434e3825ba1SMarc Zyngier static int partition_domain_translate(struct irq_domain *d, 1435e3825ba1SMarc Zyngier struct irq_fwspec *fwspec, 1436e3825ba1SMarc Zyngier unsigned long *hwirq, 1437e3825ba1SMarc Zyngier unsigned int *type) 1438e3825ba1SMarc Zyngier { 1439e3825ba1SMarc Zyngier struct device_node *np; 1440e3825ba1SMarc Zyngier int ret; 1441e3825ba1SMarc Zyngier 144252085d3fSMarc Zyngier if (!gic_data.ppi_descs) 144352085d3fSMarc Zyngier return -ENOMEM; 144452085d3fSMarc Zyngier 1445e3825ba1SMarc Zyngier np = of_find_node_by_phandle(fwspec->param[3]); 1446e3825ba1SMarc Zyngier if (WARN_ON(!np)) 1447e3825ba1SMarc Zyngier return -EINVAL; 1448e3825ba1SMarc Zyngier 1449e3825ba1SMarc Zyngier ret = partition_translate_id(gic_data.ppi_descs[fwspec->param[1]], 1450e3825ba1SMarc Zyngier of_node_to_fwnode(np)); 1451e3825ba1SMarc Zyngier if (ret < 0) 1452e3825ba1SMarc Zyngier return ret; 1453e3825ba1SMarc Zyngier 1454e3825ba1SMarc Zyngier *hwirq = ret; 1455e3825ba1SMarc Zyngier *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; 1456e3825ba1SMarc Zyngier 1457e3825ba1SMarc Zyngier return 0; 1458e3825ba1SMarc Zyngier } 1459e3825ba1SMarc Zyngier 1460e3825ba1SMarc Zyngier static const struct irq_domain_ops partition_domain_ops = { 1461e3825ba1SMarc Zyngier .translate = partition_domain_translate, 1462e3825ba1SMarc Zyngier .select = gic_irq_domain_select, 1463021f6537SMarc Zyngier }; 1464021f6537SMarc Zyngier 14659c8114c2SSrinivas Kandagatla static bool gic_enable_quirk_msm8996(void *data) 14669c8114c2SSrinivas Kandagatla { 14679c8114c2SSrinivas Kandagatla struct gic_chip_data *d = data; 14689c8114c2SSrinivas Kandagatla 14699c8114c2SSrinivas Kandagatla d->flags |= FLAGS_WORKAROUND_GICR_WAKER_MSM8996; 14709c8114c2SSrinivas Kandagatla 14719c8114c2SSrinivas Kandagatla return true; 14729c8114c2SSrinivas Kandagatla } 14739c8114c2SSrinivas Kandagatla 14747f2481b3SMarc Zyngier static bool gic_enable_quirk_hip06_07(void *data) 14757f2481b3SMarc Zyngier { 14767f2481b3SMarc Zyngier struct gic_chip_data *d = data; 14777f2481b3SMarc Zyngier 14787f2481b3SMarc Zyngier /* 14797f2481b3SMarc Zyngier * HIP06 GICD_IIDR clashes with GIC-600 product number (despite 14807f2481b3SMarc Zyngier * not being an actual ARM implementation). The saving grace is 14817f2481b3SMarc Zyngier * that GIC-600 doesn't have ESPI, so nothing to do in that case. 14827f2481b3SMarc Zyngier * HIP07 doesn't even have a proper IIDR, and still pretends to 14837f2481b3SMarc Zyngier * have ESPI. In both cases, put them right. 14847f2481b3SMarc Zyngier */ 14857f2481b3SMarc Zyngier if (d->rdists.gicd_typer & GICD_TYPER_ESPI) { 14867f2481b3SMarc Zyngier /* Zero both ESPI and the RES0 field next to it... */ 14877f2481b3SMarc Zyngier d->rdists.gicd_typer &= ~GENMASK(9, 8); 14887f2481b3SMarc Zyngier return true; 14897f2481b3SMarc Zyngier } 14907f2481b3SMarc Zyngier 14917f2481b3SMarc Zyngier return false; 14927f2481b3SMarc Zyngier } 14937f2481b3SMarc Zyngier 14947f2481b3SMarc Zyngier static const struct gic_quirk gic_quirks[] = { 14957f2481b3SMarc Zyngier { 14967f2481b3SMarc Zyngier .desc = "GICv3: Qualcomm MSM8996 broken firmware", 14977f2481b3SMarc Zyngier .compatible = "qcom,msm8996-gic-v3", 14987f2481b3SMarc Zyngier .init = gic_enable_quirk_msm8996, 14997f2481b3SMarc Zyngier }, 15007f2481b3SMarc Zyngier { 15017f2481b3SMarc Zyngier .desc = "GICv3: HIP06 erratum 161010803", 15027f2481b3SMarc Zyngier .iidr = 0x0204043b, 15037f2481b3SMarc Zyngier .mask = 0xffffffff, 15047f2481b3SMarc Zyngier .init = gic_enable_quirk_hip06_07, 15057f2481b3SMarc Zyngier }, 15067f2481b3SMarc Zyngier { 15077f2481b3SMarc Zyngier .desc = "GICv3: HIP07 erratum 161010803", 15087f2481b3SMarc Zyngier .iidr = 0x00000000, 15097f2481b3SMarc Zyngier .mask = 0xffffffff, 15107f2481b3SMarc Zyngier .init = gic_enable_quirk_hip06_07, 15117f2481b3SMarc Zyngier }, 15127f2481b3SMarc Zyngier { 15137f2481b3SMarc Zyngier } 15147f2481b3SMarc Zyngier }; 15157f2481b3SMarc Zyngier 1516d98d0a99SJulien Thierry static void gic_enable_nmi_support(void) 1517d98d0a99SJulien Thierry { 1518101b35f7SJulien Thierry int i; 1519101b35f7SJulien Thierry 152081a43273SMarc Zyngier if (!gic_prio_masking_enabled()) 152181a43273SMarc Zyngier return; 152281a43273SMarc Zyngier 152381a43273SMarc Zyngier if (gic_has_group0() && !gic_dist_security_disabled()) { 152481a43273SMarc Zyngier pr_warn("SCR_EL3.FIQ is cleared, cannot enable use of pseudo-NMIs\n"); 152581a43273SMarc Zyngier return; 152681a43273SMarc Zyngier } 152781a43273SMarc Zyngier 152881a43273SMarc Zyngier ppi_nmi_refs = kcalloc(gic_data.ppi_nr, sizeof(*ppi_nmi_refs), GFP_KERNEL); 152981a43273SMarc Zyngier if (!ppi_nmi_refs) 153081a43273SMarc Zyngier return; 153181a43273SMarc Zyngier 153281a43273SMarc Zyngier for (i = 0; i < gic_data.ppi_nr; i++) 1533101b35f7SJulien Thierry refcount_set(&ppi_nmi_refs[i], 0); 1534101b35f7SJulien Thierry 1535f2266504SMarc Zyngier /* 1536f2266504SMarc Zyngier * Linux itself doesn't use 1:N distribution, so has no need to 1537f2266504SMarc Zyngier * set PMHE. The only reason to have it set is if EL3 requires it 1538f2266504SMarc Zyngier * (and we can't change it). 1539f2266504SMarc Zyngier */ 1540f2266504SMarc Zyngier if (gic_read_ctlr() & ICC_CTLR_EL1_PMHE_MASK) 1541f2266504SMarc Zyngier static_branch_enable(&gic_pmr_sync); 1542f2266504SMarc Zyngier 1543f2266504SMarc Zyngier pr_info("%s ICC_PMR_EL1 synchronisation\n", 1544f2266504SMarc Zyngier static_branch_unlikely(&gic_pmr_sync) ? "Forcing" : "Relaxing"); 1545f2266504SMarc Zyngier 1546d98d0a99SJulien Thierry static_branch_enable(&supports_pseudo_nmis); 1547101b35f7SJulien Thierry 1548101b35f7SJulien Thierry if (static_branch_likely(&supports_deactivate_key)) 1549101b35f7SJulien Thierry gic_eoimode1_chip.flags |= IRQCHIP_SUPPORTS_NMI; 1550101b35f7SJulien Thierry else 1551101b35f7SJulien Thierry gic_chip.flags |= IRQCHIP_SUPPORTS_NMI; 1552d98d0a99SJulien Thierry } 1553d98d0a99SJulien Thierry 1554db57d746STomasz Nowicki static int __init gic_init_bases(void __iomem *dist_base, 1555db57d746STomasz Nowicki struct redist_region *rdist_regs, 1556db57d746STomasz Nowicki u32 nr_redist_regions, 1557db57d746STomasz Nowicki u64 redist_stride, 1558db57d746STomasz Nowicki struct fwnode_handle *handle) 1559db57d746STomasz Nowicki { 1560db57d746STomasz Nowicki u32 typer; 1561db57d746STomasz Nowicki int err; 1562db57d746STomasz Nowicki 1563db57d746STomasz Nowicki if (!is_hyp_mode_available()) 1564d01d3274SDavidlohr Bueso static_branch_disable(&supports_deactivate_key); 1565db57d746STomasz Nowicki 1566d01d3274SDavidlohr Bueso if (static_branch_likely(&supports_deactivate_key)) 1567db57d746STomasz Nowicki pr_info("GIC: Using split EOI/Deactivate mode\n"); 1568db57d746STomasz Nowicki 1569e3825ba1SMarc Zyngier gic_data.fwnode = handle; 1570db57d746STomasz Nowicki gic_data.dist_base = dist_base; 1571db57d746STomasz Nowicki gic_data.redist_regions = rdist_regs; 1572db57d746STomasz Nowicki gic_data.nr_redist_regions = nr_redist_regions; 1573db57d746STomasz Nowicki gic_data.redist_stride = redist_stride; 1574db57d746STomasz Nowicki 1575db57d746STomasz Nowicki /* 1576db57d746STomasz Nowicki * Find out how many interrupts are supported. 1577db57d746STomasz Nowicki */ 1578db57d746STomasz Nowicki typer = readl_relaxed(gic_data.dist_base + GICD_TYPER); 1579a4f9edb2SMarc Zyngier gic_data.rdists.gicd_typer = typer; 15807f2481b3SMarc Zyngier 15817f2481b3SMarc Zyngier gic_enable_quirks(readl_relaxed(gic_data.dist_base + GICD_IIDR), 15827f2481b3SMarc Zyngier gic_quirks, &gic_data); 15837f2481b3SMarc Zyngier 1584211bddd2SMarc Zyngier pr_info("%d SPIs implemented\n", GIC_LINE_NR - 32); 1585211bddd2SMarc Zyngier pr_info("%d Extended SPIs implemented\n", GIC_ESPI_NR); 1586f2d83409SMarc Zyngier 1587f2d83409SMarc Zyngier gic_data.rdists.gicd_typer2 = readl_relaxed(gic_data.dist_base + GICD_TYPER2); 1588f2d83409SMarc Zyngier 1589db57d746STomasz Nowicki gic_data.domain = irq_domain_create_tree(handle, &gic_irq_domain_ops, 1590db57d746STomasz Nowicki &gic_data); 1591b2425b51SMarc Zyngier irq_domain_update_bus_token(gic_data.domain, DOMAIN_BUS_WIRED); 1592db57d746STomasz Nowicki gic_data.rdists.rdist = alloc_percpu(typeof(*gic_data.rdists.rdist)); 1593b25319d2SMarc Zyngier gic_data.rdists.has_rvpeid = true; 15940edc23eaSMarc Zyngier gic_data.rdists.has_vlpis = true; 15950edc23eaSMarc Zyngier gic_data.rdists.has_direct_lpi = true; 1596db57d746STomasz Nowicki 1597db57d746STomasz Nowicki if (WARN_ON(!gic_data.domain) || WARN_ON(!gic_data.rdists.rdist)) { 1598db57d746STomasz Nowicki err = -ENOMEM; 1599db57d746STomasz Nowicki goto out_free; 1600db57d746STomasz Nowicki } 1601db57d746STomasz Nowicki 1602eda0d04aSShanker Donthineni gic_data.has_rss = !!(typer & GICD_TYPER_RSS); 1603eda0d04aSShanker Donthineni pr_info("Distributor has %sRange Selector support\n", 1604eda0d04aSShanker Donthineni gic_data.has_rss ? "" : "no "); 1605eda0d04aSShanker Donthineni 160650528752SMarc Zyngier if (typer & GICD_TYPER_MBIS) { 160750528752SMarc Zyngier err = mbi_init(handle, gic_data.domain); 160850528752SMarc Zyngier if (err) 160950528752SMarc Zyngier pr_err("Failed to initialize MBIs\n"); 161050528752SMarc Zyngier } 161150528752SMarc Zyngier 1612db57d746STomasz Nowicki set_handle_irq(gic_handle_irq); 1613db57d746STomasz Nowicki 16141a60e1e6SMarc Zyngier gic_update_rdist_properties(); 16150edc23eaSMarc Zyngier 1616db57d746STomasz Nowicki gic_smp_init(); 1617db57d746STomasz Nowicki gic_dist_init(); 1618db57d746STomasz Nowicki gic_cpu_init(); 1619db57d746STomasz Nowicki gic_cpu_pm_init(); 1620db57d746STomasz Nowicki 1621d38a71c5SMarc Zyngier if (gic_dist_supports_lpis()) { 1622d38a71c5SMarc Zyngier its_init(handle, &gic_data.rdists, gic_data.domain); 1623d38a71c5SMarc Zyngier its_cpu_init(); 162490b4c555SZeev Zilberman } else { 162590b4c555SZeev Zilberman if (IS_ENABLED(CONFIG_ARM_GIC_V2M)) 162690b4c555SZeev Zilberman gicv2m_init(handle, gic_data.domain); 1627d38a71c5SMarc Zyngier } 1628d38a71c5SMarc Zyngier 1629d98d0a99SJulien Thierry gic_enable_nmi_support(); 1630d98d0a99SJulien Thierry 1631db57d746STomasz Nowicki return 0; 1632db57d746STomasz Nowicki 1633db57d746STomasz Nowicki out_free: 1634db57d746STomasz Nowicki if (gic_data.domain) 1635db57d746STomasz Nowicki irq_domain_remove(gic_data.domain); 1636db57d746STomasz Nowicki free_percpu(gic_data.rdists.rdist); 1637db57d746STomasz Nowicki return err; 1638db57d746STomasz Nowicki } 1639db57d746STomasz Nowicki 1640db57d746STomasz Nowicki static int __init gic_validate_dist_version(void __iomem *dist_base) 1641db57d746STomasz Nowicki { 1642db57d746STomasz Nowicki u32 reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK; 1643db57d746STomasz Nowicki 1644db57d746STomasz Nowicki if (reg != GIC_PIDR2_ARCH_GICv3 && reg != GIC_PIDR2_ARCH_GICv4) 1645db57d746STomasz Nowicki return -ENODEV; 1646db57d746STomasz Nowicki 1647db57d746STomasz Nowicki return 0; 1648db57d746STomasz Nowicki } 1649db57d746STomasz Nowicki 1650e3825ba1SMarc Zyngier /* Create all possible partitions at boot time */ 16517beaa24bSLinus Torvalds static void __init gic_populate_ppi_partitions(struct device_node *gic_node) 1652e3825ba1SMarc Zyngier { 1653e3825ba1SMarc Zyngier struct device_node *parts_node, *child_part; 1654e3825ba1SMarc Zyngier int part_idx = 0, i; 1655e3825ba1SMarc Zyngier int nr_parts; 1656e3825ba1SMarc Zyngier struct partition_affinity *parts; 1657e3825ba1SMarc Zyngier 165800ee9a1cSJohan Hovold parts_node = of_get_child_by_name(gic_node, "ppi-partitions"); 1659e3825ba1SMarc Zyngier if (!parts_node) 1660e3825ba1SMarc Zyngier return; 1661e3825ba1SMarc Zyngier 166252085d3fSMarc Zyngier gic_data.ppi_descs = kcalloc(gic_data.ppi_nr, sizeof(*gic_data.ppi_descs), GFP_KERNEL); 166352085d3fSMarc Zyngier if (!gic_data.ppi_descs) 166452085d3fSMarc Zyngier return; 166552085d3fSMarc Zyngier 1666e3825ba1SMarc Zyngier nr_parts = of_get_child_count(parts_node); 1667e3825ba1SMarc Zyngier 1668e3825ba1SMarc Zyngier if (!nr_parts) 166900ee9a1cSJohan Hovold goto out_put_node; 1670e3825ba1SMarc Zyngier 16716396bb22SKees Cook parts = kcalloc(nr_parts, sizeof(*parts), GFP_KERNEL); 1672e3825ba1SMarc Zyngier if (WARN_ON(!parts)) 167300ee9a1cSJohan Hovold goto out_put_node; 1674e3825ba1SMarc Zyngier 1675e3825ba1SMarc Zyngier for_each_child_of_node(parts_node, child_part) { 1676e3825ba1SMarc Zyngier struct partition_affinity *part; 1677e3825ba1SMarc Zyngier int n; 1678e3825ba1SMarc Zyngier 1679e3825ba1SMarc Zyngier part = &parts[part_idx]; 1680e3825ba1SMarc Zyngier 1681e3825ba1SMarc Zyngier part->partition_id = of_node_to_fwnode(child_part); 1682e3825ba1SMarc Zyngier 16832ef790dcSRob Herring pr_info("GIC: PPI partition %pOFn[%d] { ", 16842ef790dcSRob Herring child_part, part_idx); 1685e3825ba1SMarc Zyngier 1686e3825ba1SMarc Zyngier n = of_property_count_elems_of_size(child_part, "affinity", 1687e3825ba1SMarc Zyngier sizeof(u32)); 1688e3825ba1SMarc Zyngier WARN_ON(n <= 0); 1689e3825ba1SMarc Zyngier 1690e3825ba1SMarc Zyngier for (i = 0; i < n; i++) { 1691e3825ba1SMarc Zyngier int err, cpu; 1692e3825ba1SMarc Zyngier u32 cpu_phandle; 1693e3825ba1SMarc Zyngier struct device_node *cpu_node; 1694e3825ba1SMarc Zyngier 1695e3825ba1SMarc Zyngier err = of_property_read_u32_index(child_part, "affinity", 1696e3825ba1SMarc Zyngier i, &cpu_phandle); 1697e3825ba1SMarc Zyngier if (WARN_ON(err)) 1698e3825ba1SMarc Zyngier continue; 1699e3825ba1SMarc Zyngier 1700e3825ba1SMarc Zyngier cpu_node = of_find_node_by_phandle(cpu_phandle); 1701e3825ba1SMarc Zyngier if (WARN_ON(!cpu_node)) 1702e3825ba1SMarc Zyngier continue; 1703e3825ba1SMarc Zyngier 1704c08ec7daSSuzuki K Poulose cpu = of_cpu_node_to_id(cpu_node); 1705c08ec7daSSuzuki K Poulose if (WARN_ON(cpu < 0)) 1706e3825ba1SMarc Zyngier continue; 1707e3825ba1SMarc Zyngier 1708e81f54c6SRob Herring pr_cont("%pOF[%d] ", cpu_node, cpu); 1709e3825ba1SMarc Zyngier 1710e3825ba1SMarc Zyngier cpumask_set_cpu(cpu, &part->mask); 1711e3825ba1SMarc Zyngier } 1712e3825ba1SMarc Zyngier 1713e3825ba1SMarc Zyngier pr_cont("}\n"); 1714e3825ba1SMarc Zyngier part_idx++; 1715e3825ba1SMarc Zyngier } 1716e3825ba1SMarc Zyngier 171752085d3fSMarc Zyngier for (i = 0; i < gic_data.ppi_nr; i++) { 1718e3825ba1SMarc Zyngier unsigned int irq; 1719e3825ba1SMarc Zyngier struct partition_desc *desc; 1720e3825ba1SMarc Zyngier struct irq_fwspec ppi_fwspec = { 1721e3825ba1SMarc Zyngier .fwnode = gic_data.fwnode, 1722e3825ba1SMarc Zyngier .param_count = 3, 1723e3825ba1SMarc Zyngier .param = { 172465da7d19SMarc Zyngier [0] = GIC_IRQ_TYPE_PARTITION, 1725e3825ba1SMarc Zyngier [1] = i, 1726e3825ba1SMarc Zyngier [2] = IRQ_TYPE_NONE, 1727e3825ba1SMarc Zyngier }, 1728e3825ba1SMarc Zyngier }; 1729e3825ba1SMarc Zyngier 1730e3825ba1SMarc Zyngier irq = irq_create_fwspec_mapping(&ppi_fwspec); 1731e3825ba1SMarc Zyngier if (WARN_ON(!irq)) 1732e3825ba1SMarc Zyngier continue; 1733e3825ba1SMarc Zyngier desc = partition_create_desc(gic_data.fwnode, parts, nr_parts, 1734e3825ba1SMarc Zyngier irq, &partition_domain_ops); 1735e3825ba1SMarc Zyngier if (WARN_ON(!desc)) 1736e3825ba1SMarc Zyngier continue; 1737e3825ba1SMarc Zyngier 1738e3825ba1SMarc Zyngier gic_data.ppi_descs[i] = desc; 1739e3825ba1SMarc Zyngier } 174000ee9a1cSJohan Hovold 174100ee9a1cSJohan Hovold out_put_node: 174200ee9a1cSJohan Hovold of_node_put(parts_node); 1743e3825ba1SMarc Zyngier } 1744e3825ba1SMarc Zyngier 17451839e576SJulien Grall static void __init gic_of_setup_kvm_info(struct device_node *node) 17461839e576SJulien Grall { 17471839e576SJulien Grall int ret; 17481839e576SJulien Grall struct resource r; 17491839e576SJulien Grall u32 gicv_idx; 17501839e576SJulien Grall 17511839e576SJulien Grall gic_v3_kvm_info.type = GIC_V3; 17521839e576SJulien Grall 17531839e576SJulien Grall gic_v3_kvm_info.maint_irq = irq_of_parse_and_map(node, 0); 17541839e576SJulien Grall if (!gic_v3_kvm_info.maint_irq) 17551839e576SJulien Grall return; 17561839e576SJulien Grall 17571839e576SJulien Grall if (of_property_read_u32(node, "#redistributor-regions", 17581839e576SJulien Grall &gicv_idx)) 17591839e576SJulien Grall gicv_idx = 1; 17601839e576SJulien Grall 17611839e576SJulien Grall gicv_idx += 3; /* Also skip GICD, GICC, GICH */ 17621839e576SJulien Grall ret = of_address_to_resource(node, gicv_idx, &r); 17631839e576SJulien Grall if (!ret) 17641839e576SJulien Grall gic_v3_kvm_info.vcpu = r; 17651839e576SJulien Grall 17664bdf5025SMarc Zyngier gic_v3_kvm_info.has_v4 = gic_data.rdists.has_vlpis; 17671839e576SJulien Grall gic_set_kvm_info(&gic_v3_kvm_info); 17681839e576SJulien Grall } 17691839e576SJulien Grall 1770021f6537SMarc Zyngier static int __init gic_of_init(struct device_node *node, struct device_node *parent) 1771021f6537SMarc Zyngier { 1772021f6537SMarc Zyngier void __iomem *dist_base; 1773f5c1434cSMarc Zyngier struct redist_region *rdist_regs; 1774021f6537SMarc Zyngier u64 redist_stride; 1775f5c1434cSMarc Zyngier u32 nr_redist_regions; 1776db57d746STomasz Nowicki int err, i; 1777021f6537SMarc Zyngier 1778021f6537SMarc Zyngier dist_base = of_iomap(node, 0); 1779021f6537SMarc Zyngier if (!dist_base) { 1780e81f54c6SRob Herring pr_err("%pOF: unable to map gic dist registers\n", node); 1781021f6537SMarc Zyngier return -ENXIO; 1782021f6537SMarc Zyngier } 1783021f6537SMarc Zyngier 1784db57d746STomasz Nowicki err = gic_validate_dist_version(dist_base); 1785db57d746STomasz Nowicki if (err) { 1786e81f54c6SRob Herring pr_err("%pOF: no distributor detected, giving up\n", node); 1787021f6537SMarc Zyngier goto out_unmap_dist; 1788021f6537SMarc Zyngier } 1789021f6537SMarc Zyngier 1790f5c1434cSMarc Zyngier if (of_property_read_u32(node, "#redistributor-regions", &nr_redist_regions)) 1791f5c1434cSMarc Zyngier nr_redist_regions = 1; 1792021f6537SMarc Zyngier 17936396bb22SKees Cook rdist_regs = kcalloc(nr_redist_regions, sizeof(*rdist_regs), 17946396bb22SKees Cook GFP_KERNEL); 1795f5c1434cSMarc Zyngier if (!rdist_regs) { 1796021f6537SMarc Zyngier err = -ENOMEM; 1797021f6537SMarc Zyngier goto out_unmap_dist; 1798021f6537SMarc Zyngier } 1799021f6537SMarc Zyngier 1800f5c1434cSMarc Zyngier for (i = 0; i < nr_redist_regions; i++) { 1801f5c1434cSMarc Zyngier struct resource res; 1802f5c1434cSMarc Zyngier int ret; 1803f5c1434cSMarc Zyngier 1804f5c1434cSMarc Zyngier ret = of_address_to_resource(node, 1 + i, &res); 1805f5c1434cSMarc Zyngier rdist_regs[i].redist_base = of_iomap(node, 1 + i); 1806f5c1434cSMarc Zyngier if (ret || !rdist_regs[i].redist_base) { 1807e81f54c6SRob Herring pr_err("%pOF: couldn't map region %d\n", node, i); 1808021f6537SMarc Zyngier err = -ENODEV; 1809021f6537SMarc Zyngier goto out_unmap_rdist; 1810021f6537SMarc Zyngier } 1811f5c1434cSMarc Zyngier rdist_regs[i].phys_base = res.start; 1812021f6537SMarc Zyngier } 1813021f6537SMarc Zyngier 1814021f6537SMarc Zyngier if (of_property_read_u64(node, "redistributor-stride", &redist_stride)) 1815021f6537SMarc Zyngier redist_stride = 0; 1816021f6537SMarc Zyngier 1817f70fdb42SSrinivas Kandagatla gic_enable_of_quirks(node, gic_quirks, &gic_data); 1818f70fdb42SSrinivas Kandagatla 1819db57d746STomasz Nowicki err = gic_init_bases(dist_base, rdist_regs, nr_redist_regions, 1820db57d746STomasz Nowicki redist_stride, &node->fwnode); 1821e3825ba1SMarc Zyngier if (err) 1822e3825ba1SMarc Zyngier goto out_unmap_rdist; 1823e3825ba1SMarc Zyngier 1824e3825ba1SMarc Zyngier gic_populate_ppi_partitions(node); 1825d33a3c8cSChristoffer Dall 1826d01d3274SDavidlohr Bueso if (static_branch_likely(&supports_deactivate_key)) 18271839e576SJulien Grall gic_of_setup_kvm_info(node); 1828021f6537SMarc Zyngier return 0; 1829021f6537SMarc Zyngier 1830021f6537SMarc Zyngier out_unmap_rdist: 1831f5c1434cSMarc Zyngier for (i = 0; i < nr_redist_regions; i++) 1832f5c1434cSMarc Zyngier if (rdist_regs[i].redist_base) 1833f5c1434cSMarc Zyngier iounmap(rdist_regs[i].redist_base); 1834f5c1434cSMarc Zyngier kfree(rdist_regs); 1835021f6537SMarc Zyngier out_unmap_dist: 1836021f6537SMarc Zyngier iounmap(dist_base); 1837021f6537SMarc Zyngier return err; 1838021f6537SMarc Zyngier } 1839021f6537SMarc Zyngier 1840021f6537SMarc Zyngier IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init); 1841ffa7d616STomasz Nowicki 1842ffa7d616STomasz Nowicki #ifdef CONFIG_ACPI 1843611f039fSJulien Grall static struct 1844611f039fSJulien Grall { 1845611f039fSJulien Grall void __iomem *dist_base; 1846611f039fSJulien Grall struct redist_region *redist_regs; 1847611f039fSJulien Grall u32 nr_redist_regions; 1848611f039fSJulien Grall bool single_redist; 1849926b5dfaSMarc Zyngier int enabled_rdists; 18501839e576SJulien Grall u32 maint_irq; 18511839e576SJulien Grall int maint_irq_mode; 18521839e576SJulien Grall phys_addr_t vcpu_base; 1853611f039fSJulien Grall } acpi_data __initdata; 1854b70fb7afSTomasz Nowicki 1855b70fb7afSTomasz Nowicki static void __init 1856b70fb7afSTomasz Nowicki gic_acpi_register_redist(phys_addr_t phys_base, void __iomem *redist_base) 1857b70fb7afSTomasz Nowicki { 1858b70fb7afSTomasz Nowicki static int count = 0; 1859b70fb7afSTomasz Nowicki 1860611f039fSJulien Grall acpi_data.redist_regs[count].phys_base = phys_base; 1861611f039fSJulien Grall acpi_data.redist_regs[count].redist_base = redist_base; 1862611f039fSJulien Grall acpi_data.redist_regs[count].single_redist = acpi_data.single_redist; 1863b70fb7afSTomasz Nowicki count++; 1864b70fb7afSTomasz Nowicki } 1865ffa7d616STomasz Nowicki 1866ffa7d616STomasz Nowicki static int __init 186760574d1eSKeith Busch gic_acpi_parse_madt_redist(union acpi_subtable_headers *header, 1868ffa7d616STomasz Nowicki const unsigned long end) 1869ffa7d616STomasz Nowicki { 1870ffa7d616STomasz Nowicki struct acpi_madt_generic_redistributor *redist = 1871ffa7d616STomasz Nowicki (struct acpi_madt_generic_redistributor *)header; 1872ffa7d616STomasz Nowicki void __iomem *redist_base; 1873ffa7d616STomasz Nowicki 1874ffa7d616STomasz Nowicki redist_base = ioremap(redist->base_address, redist->length); 1875ffa7d616STomasz Nowicki if (!redist_base) { 1876ffa7d616STomasz Nowicki pr_err("Couldn't map GICR region @%llx\n", redist->base_address); 1877ffa7d616STomasz Nowicki return -ENOMEM; 1878ffa7d616STomasz Nowicki } 1879ffa7d616STomasz Nowicki 1880b70fb7afSTomasz Nowicki gic_acpi_register_redist(redist->base_address, redist_base); 1881ffa7d616STomasz Nowicki return 0; 1882ffa7d616STomasz Nowicki } 1883ffa7d616STomasz Nowicki 1884b70fb7afSTomasz Nowicki static int __init 188560574d1eSKeith Busch gic_acpi_parse_madt_gicc(union acpi_subtable_headers *header, 1886b70fb7afSTomasz Nowicki const unsigned long end) 1887b70fb7afSTomasz Nowicki { 1888b70fb7afSTomasz Nowicki struct acpi_madt_generic_interrupt *gicc = 1889b70fb7afSTomasz Nowicki (struct acpi_madt_generic_interrupt *)header; 1890611f039fSJulien Grall u32 reg = readl_relaxed(acpi_data.dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK; 1891b70fb7afSTomasz Nowicki u32 size = reg == GIC_PIDR2_ARCH_GICv4 ? SZ_64K * 4 : SZ_64K * 2; 1892b70fb7afSTomasz Nowicki void __iomem *redist_base; 1893b70fb7afSTomasz Nowicki 1894ebe2f871SShanker Donthineni /* GICC entry which has !ACPI_MADT_ENABLED is not unusable so skip */ 1895ebe2f871SShanker Donthineni if (!(gicc->flags & ACPI_MADT_ENABLED)) 1896ebe2f871SShanker Donthineni return 0; 1897ebe2f871SShanker Donthineni 1898b70fb7afSTomasz Nowicki redist_base = ioremap(gicc->gicr_base_address, size); 1899b70fb7afSTomasz Nowicki if (!redist_base) 1900b70fb7afSTomasz Nowicki return -ENOMEM; 1901b70fb7afSTomasz Nowicki 1902b70fb7afSTomasz Nowicki gic_acpi_register_redist(gicc->gicr_base_address, redist_base); 1903b70fb7afSTomasz Nowicki return 0; 1904b70fb7afSTomasz Nowicki } 1905b70fb7afSTomasz Nowicki 1906b70fb7afSTomasz Nowicki static int __init gic_acpi_collect_gicr_base(void) 1907b70fb7afSTomasz Nowicki { 1908b70fb7afSTomasz Nowicki acpi_tbl_entry_handler redist_parser; 1909b70fb7afSTomasz Nowicki enum acpi_madt_type type; 1910b70fb7afSTomasz Nowicki 1911611f039fSJulien Grall if (acpi_data.single_redist) { 1912b70fb7afSTomasz Nowicki type = ACPI_MADT_TYPE_GENERIC_INTERRUPT; 1913b70fb7afSTomasz Nowicki redist_parser = gic_acpi_parse_madt_gicc; 1914b70fb7afSTomasz Nowicki } else { 1915b70fb7afSTomasz Nowicki type = ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR; 1916b70fb7afSTomasz Nowicki redist_parser = gic_acpi_parse_madt_redist; 1917b70fb7afSTomasz Nowicki } 1918b70fb7afSTomasz Nowicki 1919b70fb7afSTomasz Nowicki /* Collect redistributor base addresses in GICR entries */ 1920b70fb7afSTomasz Nowicki if (acpi_table_parse_madt(type, redist_parser, 0) > 0) 1921b70fb7afSTomasz Nowicki return 0; 1922b70fb7afSTomasz Nowicki 1923b70fb7afSTomasz Nowicki pr_info("No valid GICR entries exist\n"); 1924b70fb7afSTomasz Nowicki return -ENODEV; 1925b70fb7afSTomasz Nowicki } 1926b70fb7afSTomasz Nowicki 192760574d1eSKeith Busch static int __init gic_acpi_match_gicr(union acpi_subtable_headers *header, 1928ffa7d616STomasz Nowicki const unsigned long end) 1929ffa7d616STomasz Nowicki { 1930ffa7d616STomasz Nowicki /* Subtable presence means that redist exists, that's it */ 1931ffa7d616STomasz Nowicki return 0; 1932ffa7d616STomasz Nowicki } 1933ffa7d616STomasz Nowicki 193460574d1eSKeith Busch static int __init gic_acpi_match_gicc(union acpi_subtable_headers *header, 1935b70fb7afSTomasz Nowicki const unsigned long end) 1936b70fb7afSTomasz Nowicki { 1937b70fb7afSTomasz Nowicki struct acpi_madt_generic_interrupt *gicc = 1938b70fb7afSTomasz Nowicki (struct acpi_madt_generic_interrupt *)header; 1939b70fb7afSTomasz Nowicki 1940b70fb7afSTomasz Nowicki /* 1941b70fb7afSTomasz Nowicki * If GICC is enabled and has valid gicr base address, then it means 1942b70fb7afSTomasz Nowicki * GICR base is presented via GICC 1943b70fb7afSTomasz Nowicki */ 1944926b5dfaSMarc Zyngier if ((gicc->flags & ACPI_MADT_ENABLED) && gicc->gicr_base_address) { 1945926b5dfaSMarc Zyngier acpi_data.enabled_rdists++; 1946b70fb7afSTomasz Nowicki return 0; 1947926b5dfaSMarc Zyngier } 1948b70fb7afSTomasz Nowicki 1949ebe2f871SShanker Donthineni /* 1950ebe2f871SShanker Donthineni * It's perfectly valid firmware can pass disabled GICC entry, driver 1951ebe2f871SShanker Donthineni * should not treat as errors, skip the entry instead of probe fail. 1952ebe2f871SShanker Donthineni */ 1953ebe2f871SShanker Donthineni if (!(gicc->flags & ACPI_MADT_ENABLED)) 1954ebe2f871SShanker Donthineni return 0; 1955ebe2f871SShanker Donthineni 1956b70fb7afSTomasz Nowicki return -ENODEV; 1957b70fb7afSTomasz Nowicki } 1958b70fb7afSTomasz Nowicki 1959b70fb7afSTomasz Nowicki static int __init gic_acpi_count_gicr_regions(void) 1960b70fb7afSTomasz Nowicki { 1961b70fb7afSTomasz Nowicki int count; 1962b70fb7afSTomasz Nowicki 1963b70fb7afSTomasz Nowicki /* 1964b70fb7afSTomasz Nowicki * Count how many redistributor regions we have. It is not allowed 1965b70fb7afSTomasz Nowicki * to mix redistributor description, GICR and GICC subtables have to be 1966b70fb7afSTomasz Nowicki * mutually exclusive. 1967b70fb7afSTomasz Nowicki */ 1968b70fb7afSTomasz Nowicki count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR, 1969b70fb7afSTomasz Nowicki gic_acpi_match_gicr, 0); 1970b70fb7afSTomasz Nowicki if (count > 0) { 1971611f039fSJulien Grall acpi_data.single_redist = false; 1972b70fb7afSTomasz Nowicki return count; 1973b70fb7afSTomasz Nowicki } 1974b70fb7afSTomasz Nowicki 1975b70fb7afSTomasz Nowicki count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT, 1976b70fb7afSTomasz Nowicki gic_acpi_match_gicc, 0); 1977926b5dfaSMarc Zyngier if (count > 0) { 1978611f039fSJulien Grall acpi_data.single_redist = true; 1979926b5dfaSMarc Zyngier count = acpi_data.enabled_rdists; 1980926b5dfaSMarc Zyngier } 1981b70fb7afSTomasz Nowicki 1982b70fb7afSTomasz Nowicki return count; 1983b70fb7afSTomasz Nowicki } 1984b70fb7afSTomasz Nowicki 1985ffa7d616STomasz Nowicki static bool __init acpi_validate_gic_table(struct acpi_subtable_header *header, 1986ffa7d616STomasz Nowicki struct acpi_probe_entry *ape) 1987ffa7d616STomasz Nowicki { 1988ffa7d616STomasz Nowicki struct acpi_madt_generic_distributor *dist; 1989ffa7d616STomasz Nowicki int count; 1990ffa7d616STomasz Nowicki 1991ffa7d616STomasz Nowicki dist = (struct acpi_madt_generic_distributor *)header; 1992ffa7d616STomasz Nowicki if (dist->version != ape->driver_data) 1993ffa7d616STomasz Nowicki return false; 1994ffa7d616STomasz Nowicki 1995ffa7d616STomasz Nowicki /* We need to do that exercise anyway, the sooner the better */ 1996b70fb7afSTomasz Nowicki count = gic_acpi_count_gicr_regions(); 1997ffa7d616STomasz Nowicki if (count <= 0) 1998ffa7d616STomasz Nowicki return false; 1999ffa7d616STomasz Nowicki 2000611f039fSJulien Grall acpi_data.nr_redist_regions = count; 2001ffa7d616STomasz Nowicki return true; 2002ffa7d616STomasz Nowicki } 2003ffa7d616STomasz Nowicki 200460574d1eSKeith Busch static int __init gic_acpi_parse_virt_madt_gicc(union acpi_subtable_headers *header, 20051839e576SJulien Grall const unsigned long end) 20061839e576SJulien Grall { 20071839e576SJulien Grall struct acpi_madt_generic_interrupt *gicc = 20081839e576SJulien Grall (struct acpi_madt_generic_interrupt *)header; 20091839e576SJulien Grall int maint_irq_mode; 20101839e576SJulien Grall static int first_madt = true; 20111839e576SJulien Grall 20121839e576SJulien Grall /* Skip unusable CPUs */ 20131839e576SJulien Grall if (!(gicc->flags & ACPI_MADT_ENABLED)) 20141839e576SJulien Grall return 0; 20151839e576SJulien Grall 20161839e576SJulien Grall maint_irq_mode = (gicc->flags & ACPI_MADT_VGIC_IRQ_MODE) ? 20171839e576SJulien Grall ACPI_EDGE_SENSITIVE : ACPI_LEVEL_SENSITIVE; 20181839e576SJulien Grall 20191839e576SJulien Grall if (first_madt) { 20201839e576SJulien Grall first_madt = false; 20211839e576SJulien Grall 20221839e576SJulien Grall acpi_data.maint_irq = gicc->vgic_interrupt; 20231839e576SJulien Grall acpi_data.maint_irq_mode = maint_irq_mode; 20241839e576SJulien Grall acpi_data.vcpu_base = gicc->gicv_base_address; 20251839e576SJulien Grall 20261839e576SJulien Grall return 0; 20271839e576SJulien Grall } 20281839e576SJulien Grall 20291839e576SJulien Grall /* 20301839e576SJulien Grall * The maintenance interrupt and GICV should be the same for every CPU 20311839e576SJulien Grall */ 20321839e576SJulien Grall if ((acpi_data.maint_irq != gicc->vgic_interrupt) || 20331839e576SJulien Grall (acpi_data.maint_irq_mode != maint_irq_mode) || 20341839e576SJulien Grall (acpi_data.vcpu_base != gicc->gicv_base_address)) 20351839e576SJulien Grall return -EINVAL; 20361839e576SJulien Grall 20371839e576SJulien Grall return 0; 20381839e576SJulien Grall } 20391839e576SJulien Grall 20401839e576SJulien Grall static bool __init gic_acpi_collect_virt_info(void) 20411839e576SJulien Grall { 20421839e576SJulien Grall int count; 20431839e576SJulien Grall 20441839e576SJulien Grall count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT, 20451839e576SJulien Grall gic_acpi_parse_virt_madt_gicc, 0); 20461839e576SJulien Grall 20471839e576SJulien Grall return (count > 0); 20481839e576SJulien Grall } 20491839e576SJulien Grall 2050ffa7d616STomasz Nowicki #define ACPI_GICV3_DIST_MEM_SIZE (SZ_64K) 20511839e576SJulien Grall #define ACPI_GICV2_VCTRL_MEM_SIZE (SZ_4K) 20521839e576SJulien Grall #define ACPI_GICV2_VCPU_MEM_SIZE (SZ_8K) 20531839e576SJulien Grall 20541839e576SJulien Grall static void __init gic_acpi_setup_kvm_info(void) 20551839e576SJulien Grall { 20561839e576SJulien Grall int irq; 20571839e576SJulien Grall 20581839e576SJulien Grall if (!gic_acpi_collect_virt_info()) { 20591839e576SJulien Grall pr_warn("Unable to get hardware information used for virtualization\n"); 20601839e576SJulien Grall return; 20611839e576SJulien Grall } 20621839e576SJulien Grall 20631839e576SJulien Grall gic_v3_kvm_info.type = GIC_V3; 20641839e576SJulien Grall 20651839e576SJulien Grall irq = acpi_register_gsi(NULL, acpi_data.maint_irq, 20661839e576SJulien Grall acpi_data.maint_irq_mode, 20671839e576SJulien Grall ACPI_ACTIVE_HIGH); 20681839e576SJulien Grall if (irq <= 0) 20691839e576SJulien Grall return; 20701839e576SJulien Grall 20711839e576SJulien Grall gic_v3_kvm_info.maint_irq = irq; 20721839e576SJulien Grall 20731839e576SJulien Grall if (acpi_data.vcpu_base) { 20741839e576SJulien Grall struct resource *vcpu = &gic_v3_kvm_info.vcpu; 20751839e576SJulien Grall 20761839e576SJulien Grall vcpu->flags = IORESOURCE_MEM; 20771839e576SJulien Grall vcpu->start = acpi_data.vcpu_base; 20781839e576SJulien Grall vcpu->end = vcpu->start + ACPI_GICV2_VCPU_MEM_SIZE - 1; 20791839e576SJulien Grall } 20801839e576SJulien Grall 20814bdf5025SMarc Zyngier gic_v3_kvm_info.has_v4 = gic_data.rdists.has_vlpis; 20821839e576SJulien Grall gic_set_kvm_info(&gic_v3_kvm_info); 20831839e576SJulien Grall } 2084ffa7d616STomasz Nowicki 2085ffa7d616STomasz Nowicki static int __init 2086ffa7d616STomasz Nowicki gic_acpi_init(struct acpi_subtable_header *header, const unsigned long end) 2087ffa7d616STomasz Nowicki { 2088ffa7d616STomasz Nowicki struct acpi_madt_generic_distributor *dist; 2089ffa7d616STomasz Nowicki struct fwnode_handle *domain_handle; 2090611f039fSJulien Grall size_t size; 2091b70fb7afSTomasz Nowicki int i, err; 2092ffa7d616STomasz Nowicki 2093ffa7d616STomasz Nowicki /* Get distributor base address */ 2094ffa7d616STomasz Nowicki dist = (struct acpi_madt_generic_distributor *)header; 2095611f039fSJulien Grall acpi_data.dist_base = ioremap(dist->base_address, 2096611f039fSJulien Grall ACPI_GICV3_DIST_MEM_SIZE); 2097611f039fSJulien Grall if (!acpi_data.dist_base) { 2098ffa7d616STomasz Nowicki pr_err("Unable to map GICD registers\n"); 2099ffa7d616STomasz Nowicki return -ENOMEM; 2100ffa7d616STomasz Nowicki } 2101ffa7d616STomasz Nowicki 2102611f039fSJulien Grall err = gic_validate_dist_version(acpi_data.dist_base); 2103ffa7d616STomasz Nowicki if (err) { 210471192a68SArvind Yadav pr_err("No distributor detected at @%p, giving up\n", 2105611f039fSJulien Grall acpi_data.dist_base); 2106ffa7d616STomasz Nowicki goto out_dist_unmap; 2107ffa7d616STomasz Nowicki } 2108ffa7d616STomasz Nowicki 2109611f039fSJulien Grall size = sizeof(*acpi_data.redist_regs) * acpi_data.nr_redist_regions; 2110611f039fSJulien Grall acpi_data.redist_regs = kzalloc(size, GFP_KERNEL); 2111611f039fSJulien Grall if (!acpi_data.redist_regs) { 2112ffa7d616STomasz Nowicki err = -ENOMEM; 2113ffa7d616STomasz Nowicki goto out_dist_unmap; 2114ffa7d616STomasz Nowicki } 2115ffa7d616STomasz Nowicki 2116b70fb7afSTomasz Nowicki err = gic_acpi_collect_gicr_base(); 2117b70fb7afSTomasz Nowicki if (err) 2118ffa7d616STomasz Nowicki goto out_redist_unmap; 2119ffa7d616STomasz Nowicki 2120eeee0d09SMarc Zyngier domain_handle = irq_domain_alloc_fwnode(&dist->base_address); 2121ffa7d616STomasz Nowicki if (!domain_handle) { 2122ffa7d616STomasz Nowicki err = -ENOMEM; 2123ffa7d616STomasz Nowicki goto out_redist_unmap; 2124ffa7d616STomasz Nowicki } 2125ffa7d616STomasz Nowicki 2126611f039fSJulien Grall err = gic_init_bases(acpi_data.dist_base, acpi_data.redist_regs, 2127611f039fSJulien Grall acpi_data.nr_redist_regions, 0, domain_handle); 2128ffa7d616STomasz Nowicki if (err) 2129ffa7d616STomasz Nowicki goto out_fwhandle_free; 2130ffa7d616STomasz Nowicki 2131ffa7d616STomasz Nowicki acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, domain_handle); 2132d33a3c8cSChristoffer Dall 2133d01d3274SDavidlohr Bueso if (static_branch_likely(&supports_deactivate_key)) 21341839e576SJulien Grall gic_acpi_setup_kvm_info(); 21351839e576SJulien Grall 2136ffa7d616STomasz Nowicki return 0; 2137ffa7d616STomasz Nowicki 2138ffa7d616STomasz Nowicki out_fwhandle_free: 2139ffa7d616STomasz Nowicki irq_domain_free_fwnode(domain_handle); 2140ffa7d616STomasz Nowicki out_redist_unmap: 2141611f039fSJulien Grall for (i = 0; i < acpi_data.nr_redist_regions; i++) 2142611f039fSJulien Grall if (acpi_data.redist_regs[i].redist_base) 2143611f039fSJulien Grall iounmap(acpi_data.redist_regs[i].redist_base); 2144611f039fSJulien Grall kfree(acpi_data.redist_regs); 2145ffa7d616STomasz Nowicki out_dist_unmap: 2146611f039fSJulien Grall iounmap(acpi_data.dist_base); 2147ffa7d616STomasz Nowicki return err; 2148ffa7d616STomasz Nowicki } 2149ffa7d616STomasz Nowicki IRQCHIP_ACPI_DECLARE(gic_v3, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 2150ffa7d616STomasz Nowicki acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V3, 2151ffa7d616STomasz Nowicki gic_acpi_init); 2152ffa7d616STomasz Nowicki IRQCHIP_ACPI_DECLARE(gic_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 2153ffa7d616STomasz Nowicki acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V4, 2154ffa7d616STomasz Nowicki gic_acpi_init); 2155ffa7d616STomasz Nowicki IRQCHIP_ACPI_DECLARE(gic_v3_or_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 2156ffa7d616STomasz Nowicki acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_NONE, 2157ffa7d616STomasz Nowicki gic_acpi_init); 2158ffa7d616STomasz Nowicki #endif 2159