1021f6537SMarc Zyngier /* 2021f6537SMarc Zyngier * Copyright (C) 2013, 2014 ARM Limited, All Rights Reserved. 3021f6537SMarc Zyngier * Author: Marc Zyngier <marc.zyngier@arm.com> 4021f6537SMarc Zyngier * 5021f6537SMarc Zyngier * This program is free software; you can redistribute it and/or modify 6021f6537SMarc Zyngier * it under the terms of the GNU General Public License version 2 as 7021f6537SMarc Zyngier * published by the Free Software Foundation. 8021f6537SMarc Zyngier * 9021f6537SMarc Zyngier * This program is distributed in the hope that it will be useful, 10021f6537SMarc Zyngier * but WITHOUT ANY WARRANTY; without even the implied warranty of 11021f6537SMarc Zyngier * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12021f6537SMarc Zyngier * GNU General Public License for more details. 13021f6537SMarc Zyngier * 14021f6537SMarc Zyngier * You should have received a copy of the GNU General Public License 15021f6537SMarc Zyngier * along with this program. If not, see <http://www.gnu.org/licenses/>. 16021f6537SMarc Zyngier */ 17021f6537SMarc Zyngier 18021f6537SMarc Zyngier #include <linux/cpu.h> 193708d52fSSudeep Holla #include <linux/cpu_pm.h> 20021f6537SMarc Zyngier #include <linux/delay.h> 21021f6537SMarc Zyngier #include <linux/interrupt.h> 22021f6537SMarc Zyngier #include <linux/of.h> 23021f6537SMarc Zyngier #include <linux/of_address.h> 24021f6537SMarc Zyngier #include <linux/of_irq.h> 25021f6537SMarc Zyngier #include <linux/percpu.h> 26021f6537SMarc Zyngier #include <linux/slab.h> 27021f6537SMarc Zyngier 28021f6537SMarc Zyngier #include <linux/irqchip/arm-gic-v3.h> 29021f6537SMarc Zyngier 30021f6537SMarc Zyngier #include <asm/cputype.h> 31021f6537SMarc Zyngier #include <asm/exception.h> 32021f6537SMarc Zyngier #include <asm/smp_plat.h> 33021f6537SMarc Zyngier 34021f6537SMarc Zyngier #include "irq-gic-common.h" 35021f6537SMarc Zyngier #include "irqchip.h" 36021f6537SMarc Zyngier 37f5c1434cSMarc Zyngier struct redist_region { 38f5c1434cSMarc Zyngier void __iomem *redist_base; 39f5c1434cSMarc Zyngier phys_addr_t phys_base; 40f5c1434cSMarc Zyngier }; 41f5c1434cSMarc Zyngier 42021f6537SMarc Zyngier struct gic_chip_data { 43021f6537SMarc Zyngier void __iomem *dist_base; 44f5c1434cSMarc Zyngier struct redist_region *redist_regions; 45f5c1434cSMarc Zyngier struct rdists rdists; 46021f6537SMarc Zyngier struct irq_domain *domain; 47021f6537SMarc Zyngier u64 redist_stride; 48f5c1434cSMarc Zyngier u32 nr_redist_regions; 49021f6537SMarc Zyngier unsigned int irq_nr; 50021f6537SMarc Zyngier }; 51021f6537SMarc Zyngier 52021f6537SMarc Zyngier static struct gic_chip_data gic_data __read_mostly; 53021f6537SMarc Zyngier 54f5c1434cSMarc Zyngier #define gic_data_rdist() (this_cpu_ptr(gic_data.rdists.rdist)) 55f5c1434cSMarc Zyngier #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base) 56021f6537SMarc Zyngier #define gic_data_rdist_sgi_base() (gic_data_rdist_rd_base() + SZ_64K) 57021f6537SMarc Zyngier 58021f6537SMarc Zyngier /* Our default, arbitrary priority value. Linux only uses one anyway. */ 59021f6537SMarc Zyngier #define DEFAULT_PMR_VALUE 0xf0 60021f6537SMarc Zyngier 61021f6537SMarc Zyngier static inline unsigned int gic_irq(struct irq_data *d) 62021f6537SMarc Zyngier { 63021f6537SMarc Zyngier return d->hwirq; 64021f6537SMarc Zyngier } 65021f6537SMarc Zyngier 66021f6537SMarc Zyngier static inline int gic_irq_in_rdist(struct irq_data *d) 67021f6537SMarc Zyngier { 68021f6537SMarc Zyngier return gic_irq(d) < 32; 69021f6537SMarc Zyngier } 70021f6537SMarc Zyngier 71021f6537SMarc Zyngier static inline void __iomem *gic_dist_base(struct irq_data *d) 72021f6537SMarc Zyngier { 73021f6537SMarc Zyngier if (gic_irq_in_rdist(d)) /* SGI+PPI -> SGI_base for this CPU */ 74021f6537SMarc Zyngier return gic_data_rdist_sgi_base(); 75021f6537SMarc Zyngier 76021f6537SMarc Zyngier if (d->hwirq <= 1023) /* SPI -> dist_base */ 77021f6537SMarc Zyngier return gic_data.dist_base; 78021f6537SMarc Zyngier 79021f6537SMarc Zyngier return NULL; 80021f6537SMarc Zyngier } 81021f6537SMarc Zyngier 82021f6537SMarc Zyngier static void gic_do_wait_for_rwp(void __iomem *base) 83021f6537SMarc Zyngier { 84021f6537SMarc Zyngier u32 count = 1000000; /* 1s! */ 85021f6537SMarc Zyngier 86021f6537SMarc Zyngier while (readl_relaxed(base + GICD_CTLR) & GICD_CTLR_RWP) { 87021f6537SMarc Zyngier count--; 88021f6537SMarc Zyngier if (!count) { 89021f6537SMarc Zyngier pr_err_ratelimited("RWP timeout, gone fishing\n"); 90021f6537SMarc Zyngier return; 91021f6537SMarc Zyngier } 92021f6537SMarc Zyngier cpu_relax(); 93021f6537SMarc Zyngier udelay(1); 94021f6537SMarc Zyngier }; 95021f6537SMarc Zyngier } 96021f6537SMarc Zyngier 97021f6537SMarc Zyngier /* Wait for completion of a distributor change */ 98021f6537SMarc Zyngier static void gic_dist_wait_for_rwp(void) 99021f6537SMarc Zyngier { 100021f6537SMarc Zyngier gic_do_wait_for_rwp(gic_data.dist_base); 101021f6537SMarc Zyngier } 102021f6537SMarc Zyngier 103021f6537SMarc Zyngier /* Wait for completion of a redistributor change */ 104021f6537SMarc Zyngier static void gic_redist_wait_for_rwp(void) 105021f6537SMarc Zyngier { 106021f6537SMarc Zyngier gic_do_wait_for_rwp(gic_data_rdist_rd_base()); 107021f6537SMarc Zyngier } 108021f6537SMarc Zyngier 109021f6537SMarc Zyngier /* Low level accessors */ 110c44e9d77SMark Brown static u64 __maybe_unused gic_read_iar(void) 111021f6537SMarc Zyngier { 112021f6537SMarc Zyngier u64 irqstat; 113021f6537SMarc Zyngier 11472c58395SCatalin Marinas asm volatile("mrs_s %0, " __stringify(ICC_IAR1_EL1) : "=r" (irqstat)); 115021f6537SMarc Zyngier return irqstat; 116021f6537SMarc Zyngier } 117021f6537SMarc Zyngier 118c44e9d77SMark Brown static void __maybe_unused gic_write_pmr(u64 val) 119021f6537SMarc Zyngier { 12072c58395SCatalin Marinas asm volatile("msr_s " __stringify(ICC_PMR_EL1) ", %0" : : "r" (val)); 121021f6537SMarc Zyngier } 122021f6537SMarc Zyngier 123c44e9d77SMark Brown static void __maybe_unused gic_write_ctlr(u64 val) 124021f6537SMarc Zyngier { 12572c58395SCatalin Marinas asm volatile("msr_s " __stringify(ICC_CTLR_EL1) ", %0" : : "r" (val)); 126021f6537SMarc Zyngier isb(); 127021f6537SMarc Zyngier } 128021f6537SMarc Zyngier 129c44e9d77SMark Brown static void __maybe_unused gic_write_grpen1(u64 val) 130021f6537SMarc Zyngier { 13172c58395SCatalin Marinas asm volatile("msr_s " __stringify(ICC_GRPEN1_EL1) ", %0" : : "r" (val)); 132021f6537SMarc Zyngier isb(); 133021f6537SMarc Zyngier } 134021f6537SMarc Zyngier 135c44e9d77SMark Brown static void __maybe_unused gic_write_sgi1r(u64 val) 136021f6537SMarc Zyngier { 13772c58395SCatalin Marinas asm volatile("msr_s " __stringify(ICC_SGI1R_EL1) ", %0" : : "r" (val)); 138021f6537SMarc Zyngier } 139021f6537SMarc Zyngier 140021f6537SMarc Zyngier static void gic_enable_sre(void) 141021f6537SMarc Zyngier { 142021f6537SMarc Zyngier u64 val; 143021f6537SMarc Zyngier 14472c58395SCatalin Marinas asm volatile("mrs_s %0, " __stringify(ICC_SRE_EL1) : "=r" (val)); 145021f6537SMarc Zyngier val |= ICC_SRE_EL1_SRE; 14672c58395SCatalin Marinas asm volatile("msr_s " __stringify(ICC_SRE_EL1) ", %0" : : "r" (val)); 147021f6537SMarc Zyngier isb(); 148021f6537SMarc Zyngier 149021f6537SMarc Zyngier /* 150021f6537SMarc Zyngier * Need to check that the SRE bit has actually been set. If 151021f6537SMarc Zyngier * not, it means that SRE is disabled at EL2. We're going to 152021f6537SMarc Zyngier * die painfully, and there is nothing we can do about it. 153021f6537SMarc Zyngier * 154021f6537SMarc Zyngier * Kindly inform the luser. 155021f6537SMarc Zyngier */ 15672c58395SCatalin Marinas asm volatile("mrs_s %0, " __stringify(ICC_SRE_EL1) : "=r" (val)); 157021f6537SMarc Zyngier if (!(val & ICC_SRE_EL1_SRE)) 158021f6537SMarc Zyngier pr_err("GIC: unable to set SRE (disabled at EL2), panic ahead\n"); 159021f6537SMarc Zyngier } 160021f6537SMarc Zyngier 161a2c22510SSudeep Holla static void gic_enable_redist(bool enable) 162021f6537SMarc Zyngier { 163021f6537SMarc Zyngier void __iomem *rbase; 164021f6537SMarc Zyngier u32 count = 1000000; /* 1s! */ 165021f6537SMarc Zyngier u32 val; 166021f6537SMarc Zyngier 167021f6537SMarc Zyngier rbase = gic_data_rdist_rd_base(); 168021f6537SMarc Zyngier 169021f6537SMarc Zyngier val = readl_relaxed(rbase + GICR_WAKER); 170a2c22510SSudeep Holla if (enable) 171a2c22510SSudeep Holla /* Wake up this CPU redistributor */ 172021f6537SMarc Zyngier val &= ~GICR_WAKER_ProcessorSleep; 173a2c22510SSudeep Holla else 174a2c22510SSudeep Holla val |= GICR_WAKER_ProcessorSleep; 175021f6537SMarc Zyngier writel_relaxed(val, rbase + GICR_WAKER); 176021f6537SMarc Zyngier 177a2c22510SSudeep Holla if (!enable) { /* Check that GICR_WAKER is writeable */ 178a2c22510SSudeep Holla val = readl_relaxed(rbase + GICR_WAKER); 179a2c22510SSudeep Holla if (!(val & GICR_WAKER_ProcessorSleep)) 180a2c22510SSudeep Holla return; /* No PM support in this redistributor */ 181021f6537SMarc Zyngier } 182a2c22510SSudeep Holla 183a2c22510SSudeep Holla while (count--) { 184a2c22510SSudeep Holla val = readl_relaxed(rbase + GICR_WAKER); 185a2c22510SSudeep Holla if (enable ^ (val & GICR_WAKER_ChildrenAsleep)) 186a2c22510SSudeep Holla break; 187021f6537SMarc Zyngier cpu_relax(); 188021f6537SMarc Zyngier udelay(1); 189021f6537SMarc Zyngier }; 190a2c22510SSudeep Holla if (!count) 191a2c22510SSudeep Holla pr_err_ratelimited("redistributor failed to %s...\n", 192a2c22510SSudeep Holla enable ? "wakeup" : "sleep"); 193021f6537SMarc Zyngier } 194021f6537SMarc Zyngier 195021f6537SMarc Zyngier /* 196021f6537SMarc Zyngier * Routines to disable, enable, EOI and route interrupts 197021f6537SMarc Zyngier */ 198021f6537SMarc Zyngier static void gic_poke_irq(struct irq_data *d, u32 offset) 199021f6537SMarc Zyngier { 200021f6537SMarc Zyngier u32 mask = 1 << (gic_irq(d) % 32); 201021f6537SMarc Zyngier void (*rwp_wait)(void); 202021f6537SMarc Zyngier void __iomem *base; 203021f6537SMarc Zyngier 204021f6537SMarc Zyngier if (gic_irq_in_rdist(d)) { 205021f6537SMarc Zyngier base = gic_data_rdist_sgi_base(); 206021f6537SMarc Zyngier rwp_wait = gic_redist_wait_for_rwp; 207021f6537SMarc Zyngier } else { 208021f6537SMarc Zyngier base = gic_data.dist_base; 209021f6537SMarc Zyngier rwp_wait = gic_dist_wait_for_rwp; 210021f6537SMarc Zyngier } 211021f6537SMarc Zyngier 212021f6537SMarc Zyngier writel_relaxed(mask, base + offset + (gic_irq(d) / 32) * 4); 213021f6537SMarc Zyngier rwp_wait(); 214021f6537SMarc Zyngier } 215021f6537SMarc Zyngier 216021f6537SMarc Zyngier static void gic_mask_irq(struct irq_data *d) 217021f6537SMarc Zyngier { 218021f6537SMarc Zyngier gic_poke_irq(d, GICD_ICENABLER); 219021f6537SMarc Zyngier } 220021f6537SMarc Zyngier 221021f6537SMarc Zyngier static void gic_unmask_irq(struct irq_data *d) 222021f6537SMarc Zyngier { 223021f6537SMarc Zyngier gic_poke_irq(d, GICD_ISENABLER); 224021f6537SMarc Zyngier } 225021f6537SMarc Zyngier 226021f6537SMarc Zyngier static void gic_eoi_irq(struct irq_data *d) 227021f6537SMarc Zyngier { 228021f6537SMarc Zyngier gic_write_eoir(gic_irq(d)); 229021f6537SMarc Zyngier } 230021f6537SMarc Zyngier 231021f6537SMarc Zyngier static int gic_set_type(struct irq_data *d, unsigned int type) 232021f6537SMarc Zyngier { 233021f6537SMarc Zyngier unsigned int irq = gic_irq(d); 234021f6537SMarc Zyngier void (*rwp_wait)(void); 235021f6537SMarc Zyngier void __iomem *base; 236021f6537SMarc Zyngier 237021f6537SMarc Zyngier /* Interrupt configuration for SGIs can't be changed */ 238021f6537SMarc Zyngier if (irq < 16) 239021f6537SMarc Zyngier return -EINVAL; 240021f6537SMarc Zyngier 241021f6537SMarc Zyngier if (type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING) 242021f6537SMarc Zyngier return -EINVAL; 243021f6537SMarc Zyngier 244021f6537SMarc Zyngier if (gic_irq_in_rdist(d)) { 245021f6537SMarc Zyngier base = gic_data_rdist_sgi_base(); 246021f6537SMarc Zyngier rwp_wait = gic_redist_wait_for_rwp; 247021f6537SMarc Zyngier } else { 248021f6537SMarc Zyngier base = gic_data.dist_base; 249021f6537SMarc Zyngier rwp_wait = gic_dist_wait_for_rwp; 250021f6537SMarc Zyngier } 251021f6537SMarc Zyngier 252021f6537SMarc Zyngier gic_configure_irq(irq, type, base, rwp_wait); 253021f6537SMarc Zyngier 254021f6537SMarc Zyngier return 0; 255021f6537SMarc Zyngier } 256021f6537SMarc Zyngier 257021f6537SMarc Zyngier static u64 gic_mpidr_to_affinity(u64 mpidr) 258021f6537SMarc Zyngier { 259021f6537SMarc Zyngier u64 aff; 260021f6537SMarc Zyngier 261021f6537SMarc Zyngier aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 32 | 262021f6537SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 | 263021f6537SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | 264021f6537SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 0)); 265021f6537SMarc Zyngier 266021f6537SMarc Zyngier return aff; 267021f6537SMarc Zyngier } 268021f6537SMarc Zyngier 269021f6537SMarc Zyngier static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) 270021f6537SMarc Zyngier { 271021f6537SMarc Zyngier u64 irqnr; 272021f6537SMarc Zyngier 273021f6537SMarc Zyngier do { 274021f6537SMarc Zyngier irqnr = gic_read_iar(); 275021f6537SMarc Zyngier 276da33f31dSMarc Zyngier if (likely(irqnr > 15 && irqnr < 1020) || irqnr >= 8192) { 277ebc6de00SMarc Zyngier int err; 278ebc6de00SMarc Zyngier err = handle_domain_irq(gic_data.domain, irqnr, regs); 279ebc6de00SMarc Zyngier if (err) { 280da33f31dSMarc Zyngier WARN_ONCE(true, "Unexpected interrupt received!\n"); 281021f6537SMarc Zyngier gic_write_eoir(irqnr); 282021f6537SMarc Zyngier } 283ebc6de00SMarc Zyngier continue; 284ebc6de00SMarc Zyngier } 285021f6537SMarc Zyngier if (irqnr < 16) { 286021f6537SMarc Zyngier gic_write_eoir(irqnr); 287021f6537SMarc Zyngier #ifdef CONFIG_SMP 288021f6537SMarc Zyngier handle_IPI(irqnr, regs); 289021f6537SMarc Zyngier #else 290021f6537SMarc Zyngier WARN_ONCE(true, "Unexpected SGI received!\n"); 291021f6537SMarc Zyngier #endif 292021f6537SMarc Zyngier continue; 293021f6537SMarc Zyngier } 294021f6537SMarc Zyngier } while (irqnr != ICC_IAR1_EL1_SPURIOUS); 295021f6537SMarc Zyngier } 296021f6537SMarc Zyngier 297021f6537SMarc Zyngier static void __init gic_dist_init(void) 298021f6537SMarc Zyngier { 299021f6537SMarc Zyngier unsigned int i; 300021f6537SMarc Zyngier u64 affinity; 301021f6537SMarc Zyngier void __iomem *base = gic_data.dist_base; 302021f6537SMarc Zyngier 303021f6537SMarc Zyngier /* Disable the distributor */ 304021f6537SMarc Zyngier writel_relaxed(0, base + GICD_CTLR); 305021f6537SMarc Zyngier gic_dist_wait_for_rwp(); 306021f6537SMarc Zyngier 307021f6537SMarc Zyngier gic_dist_config(base, gic_data.irq_nr, gic_dist_wait_for_rwp); 308021f6537SMarc Zyngier 309021f6537SMarc Zyngier /* Enable distributor with ARE, Group1 */ 310021f6537SMarc Zyngier writel_relaxed(GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G1A | GICD_CTLR_ENABLE_G1, 311021f6537SMarc Zyngier base + GICD_CTLR); 312021f6537SMarc Zyngier 313021f6537SMarc Zyngier /* 314021f6537SMarc Zyngier * Set all global interrupts to the boot CPU only. ARE must be 315021f6537SMarc Zyngier * enabled. 316021f6537SMarc Zyngier */ 317021f6537SMarc Zyngier affinity = gic_mpidr_to_affinity(cpu_logical_map(smp_processor_id())); 318021f6537SMarc Zyngier for (i = 32; i < gic_data.irq_nr; i++) 319021f6537SMarc Zyngier writeq_relaxed(affinity, base + GICD_IROUTER + i * 8); 320021f6537SMarc Zyngier } 321021f6537SMarc Zyngier 322021f6537SMarc Zyngier static int gic_populate_rdist(void) 323021f6537SMarc Zyngier { 324021f6537SMarc Zyngier u64 mpidr = cpu_logical_map(smp_processor_id()); 325021f6537SMarc Zyngier u64 typer; 326021f6537SMarc Zyngier u32 aff; 327021f6537SMarc Zyngier int i; 328021f6537SMarc Zyngier 329021f6537SMarc Zyngier /* 330021f6537SMarc Zyngier * Convert affinity to a 32bit value that can be matched to 331021f6537SMarc Zyngier * GICR_TYPER bits [63:32]. 332021f6537SMarc Zyngier */ 333021f6537SMarc Zyngier aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 24 | 334021f6537SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 | 335021f6537SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | 336021f6537SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 0)); 337021f6537SMarc Zyngier 338f5c1434cSMarc Zyngier for (i = 0; i < gic_data.nr_redist_regions; i++) { 339f5c1434cSMarc Zyngier void __iomem *ptr = gic_data.redist_regions[i].redist_base; 340021f6537SMarc Zyngier u32 reg; 341021f6537SMarc Zyngier 342021f6537SMarc Zyngier reg = readl_relaxed(ptr + GICR_PIDR2) & GIC_PIDR2_ARCH_MASK; 343021f6537SMarc Zyngier if (reg != GIC_PIDR2_ARCH_GICv3 && 344021f6537SMarc Zyngier reg != GIC_PIDR2_ARCH_GICv4) { /* We're in trouble... */ 345021f6537SMarc Zyngier pr_warn("No redistributor present @%p\n", ptr); 346021f6537SMarc Zyngier break; 347021f6537SMarc Zyngier } 348021f6537SMarc Zyngier 349021f6537SMarc Zyngier do { 350021f6537SMarc Zyngier typer = readq_relaxed(ptr + GICR_TYPER); 351021f6537SMarc Zyngier if ((typer >> 32) == aff) { 352f5c1434cSMarc Zyngier u64 offset = ptr - gic_data.redist_regions[i].redist_base; 353021f6537SMarc Zyngier gic_data_rdist_rd_base() = ptr; 354f5c1434cSMarc Zyngier gic_data_rdist()->phys_base = gic_data.redist_regions[i].phys_base + offset; 355f5c1434cSMarc Zyngier pr_info("CPU%d: found redistributor %llx region %d:%pa\n", 356021f6537SMarc Zyngier smp_processor_id(), 357f5c1434cSMarc Zyngier (unsigned long long)mpidr, 358f5c1434cSMarc Zyngier i, &gic_data_rdist()->phys_base); 359021f6537SMarc Zyngier return 0; 360021f6537SMarc Zyngier } 361021f6537SMarc Zyngier 362021f6537SMarc Zyngier if (gic_data.redist_stride) { 363021f6537SMarc Zyngier ptr += gic_data.redist_stride; 364021f6537SMarc Zyngier } else { 365021f6537SMarc Zyngier ptr += SZ_64K * 2; /* Skip RD_base + SGI_base */ 366021f6537SMarc Zyngier if (typer & GICR_TYPER_VLPIS) 367021f6537SMarc Zyngier ptr += SZ_64K * 2; /* Skip VLPI_base + reserved page */ 368021f6537SMarc Zyngier } 369021f6537SMarc Zyngier } while (!(typer & GICR_TYPER_LAST)); 370021f6537SMarc Zyngier } 371021f6537SMarc Zyngier 372021f6537SMarc Zyngier /* We couldn't even deal with ourselves... */ 373021f6537SMarc Zyngier WARN(true, "CPU%d: mpidr %llx has no re-distributor!\n", 374021f6537SMarc Zyngier smp_processor_id(), (unsigned long long)mpidr); 375021f6537SMarc Zyngier return -ENODEV; 376021f6537SMarc Zyngier } 377021f6537SMarc Zyngier 3783708d52fSSudeep Holla static void gic_cpu_sys_reg_init(void) 379021f6537SMarc Zyngier { 380021f6537SMarc Zyngier /* Enable system registers */ 381021f6537SMarc Zyngier gic_enable_sre(); 382021f6537SMarc Zyngier 383021f6537SMarc Zyngier /* Set priority mask register */ 384021f6537SMarc Zyngier gic_write_pmr(DEFAULT_PMR_VALUE); 385021f6537SMarc Zyngier 386021f6537SMarc Zyngier /* EOI deactivates interrupt too (mode 0) */ 387021f6537SMarc Zyngier gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop_dir); 388021f6537SMarc Zyngier 389021f6537SMarc Zyngier /* ... and let's hit the road... */ 390021f6537SMarc Zyngier gic_write_grpen1(1); 391021f6537SMarc Zyngier } 392021f6537SMarc Zyngier 393da33f31dSMarc Zyngier static int gic_dist_supports_lpis(void) 394da33f31dSMarc Zyngier { 395da33f31dSMarc Zyngier return !!(readl_relaxed(gic_data.dist_base + GICD_TYPER) & GICD_TYPER_LPIS); 396da33f31dSMarc Zyngier } 397da33f31dSMarc Zyngier 398021f6537SMarc Zyngier static void gic_cpu_init(void) 399021f6537SMarc Zyngier { 400021f6537SMarc Zyngier void __iomem *rbase; 401021f6537SMarc Zyngier 402021f6537SMarc Zyngier /* Register ourselves with the rest of the world */ 403021f6537SMarc Zyngier if (gic_populate_rdist()) 404021f6537SMarc Zyngier return; 405021f6537SMarc Zyngier 406a2c22510SSudeep Holla gic_enable_redist(true); 407021f6537SMarc Zyngier 408021f6537SMarc Zyngier rbase = gic_data_rdist_sgi_base(); 409021f6537SMarc Zyngier 410021f6537SMarc Zyngier gic_cpu_config(rbase, gic_redist_wait_for_rwp); 411021f6537SMarc Zyngier 412da33f31dSMarc Zyngier /* Give LPIs a spin */ 413da33f31dSMarc Zyngier if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis()) 414da33f31dSMarc Zyngier its_cpu_init(); 415da33f31dSMarc Zyngier 4163708d52fSSudeep Holla /* initialise system registers */ 4173708d52fSSudeep Holla gic_cpu_sys_reg_init(); 418021f6537SMarc Zyngier } 419021f6537SMarc Zyngier 420021f6537SMarc Zyngier #ifdef CONFIG_SMP 421ddc86821SMark Brown static int gic_peek_irq(struct irq_data *d, u32 offset) 422ddc86821SMark Brown { 423ddc86821SMark Brown u32 mask = 1 << (gic_irq(d) % 32); 424ddc86821SMark Brown void __iomem *base; 425ddc86821SMark Brown 426ddc86821SMark Brown if (gic_irq_in_rdist(d)) 427ddc86821SMark Brown base = gic_data_rdist_sgi_base(); 428ddc86821SMark Brown else 429ddc86821SMark Brown base = gic_data.dist_base; 430ddc86821SMark Brown 431ddc86821SMark Brown return !!(readl_relaxed(base + offset + (gic_irq(d) / 32) * 4) & mask); 432ddc86821SMark Brown } 433ddc86821SMark Brown 434021f6537SMarc Zyngier static int gic_secondary_init(struct notifier_block *nfb, 435021f6537SMarc Zyngier unsigned long action, void *hcpu) 436021f6537SMarc Zyngier { 437021f6537SMarc Zyngier if (action == CPU_STARTING || action == CPU_STARTING_FROZEN) 438021f6537SMarc Zyngier gic_cpu_init(); 439021f6537SMarc Zyngier return NOTIFY_OK; 440021f6537SMarc Zyngier } 441021f6537SMarc Zyngier 442021f6537SMarc Zyngier /* 443021f6537SMarc Zyngier * Notifier for enabling the GIC CPU interface. Set an arbitrarily high 444021f6537SMarc Zyngier * priority because the GIC needs to be up before the ARM generic timers. 445021f6537SMarc Zyngier */ 446021f6537SMarc Zyngier static struct notifier_block gic_cpu_notifier = { 447021f6537SMarc Zyngier .notifier_call = gic_secondary_init, 448021f6537SMarc Zyngier .priority = 100, 449021f6537SMarc Zyngier }; 450021f6537SMarc Zyngier 451021f6537SMarc Zyngier static u16 gic_compute_target_list(int *base_cpu, const struct cpumask *mask, 452021f6537SMarc Zyngier u64 cluster_id) 453021f6537SMarc Zyngier { 454021f6537SMarc Zyngier int cpu = *base_cpu; 455021f6537SMarc Zyngier u64 mpidr = cpu_logical_map(cpu); 456021f6537SMarc Zyngier u16 tlist = 0; 457021f6537SMarc Zyngier 458021f6537SMarc Zyngier while (cpu < nr_cpu_ids) { 459021f6537SMarc Zyngier /* 460021f6537SMarc Zyngier * If we ever get a cluster of more than 16 CPUs, just 461021f6537SMarc Zyngier * scream and skip that CPU. 462021f6537SMarc Zyngier */ 463021f6537SMarc Zyngier if (WARN_ON((mpidr & 0xff) >= 16)) 464021f6537SMarc Zyngier goto out; 465021f6537SMarc Zyngier 466021f6537SMarc Zyngier tlist |= 1 << (mpidr & 0xf); 467021f6537SMarc Zyngier 468021f6537SMarc Zyngier cpu = cpumask_next(cpu, mask); 469021f6537SMarc Zyngier if (cpu == nr_cpu_ids) 470021f6537SMarc Zyngier goto out; 471021f6537SMarc Zyngier 472021f6537SMarc Zyngier mpidr = cpu_logical_map(cpu); 473021f6537SMarc Zyngier 474021f6537SMarc Zyngier if (cluster_id != (mpidr & ~0xffUL)) { 475021f6537SMarc Zyngier cpu--; 476021f6537SMarc Zyngier goto out; 477021f6537SMarc Zyngier } 478021f6537SMarc Zyngier } 479021f6537SMarc Zyngier out: 480021f6537SMarc Zyngier *base_cpu = cpu; 481021f6537SMarc Zyngier return tlist; 482021f6537SMarc Zyngier } 483021f6537SMarc Zyngier 4847e580278SAndre Przywara #define MPIDR_TO_SGI_AFFINITY(cluster_id, level) \ 4857e580278SAndre Przywara (MPIDR_AFFINITY_LEVEL(cluster_id, level) \ 4867e580278SAndre Przywara << ICC_SGI1R_AFFINITY_## level ##_SHIFT) 4877e580278SAndre Przywara 488021f6537SMarc Zyngier static void gic_send_sgi(u64 cluster_id, u16 tlist, unsigned int irq) 489021f6537SMarc Zyngier { 490021f6537SMarc Zyngier u64 val; 491021f6537SMarc Zyngier 4927e580278SAndre Przywara val = (MPIDR_TO_SGI_AFFINITY(cluster_id, 3) | 4937e580278SAndre Przywara MPIDR_TO_SGI_AFFINITY(cluster_id, 2) | 4947e580278SAndre Przywara irq << ICC_SGI1R_SGI_ID_SHIFT | 4957e580278SAndre Przywara MPIDR_TO_SGI_AFFINITY(cluster_id, 1) | 4967e580278SAndre Przywara tlist << ICC_SGI1R_TARGET_LIST_SHIFT); 497021f6537SMarc Zyngier 498021f6537SMarc Zyngier pr_debug("CPU%d: ICC_SGI1R_EL1 %llx\n", smp_processor_id(), val); 499021f6537SMarc Zyngier gic_write_sgi1r(val); 500021f6537SMarc Zyngier } 501021f6537SMarc Zyngier 502021f6537SMarc Zyngier static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) 503021f6537SMarc Zyngier { 504021f6537SMarc Zyngier int cpu; 505021f6537SMarc Zyngier 506021f6537SMarc Zyngier if (WARN_ON(irq >= 16)) 507021f6537SMarc Zyngier return; 508021f6537SMarc Zyngier 509021f6537SMarc Zyngier /* 510021f6537SMarc Zyngier * Ensure that stores to Normal memory are visible to the 511021f6537SMarc Zyngier * other CPUs before issuing the IPI. 512021f6537SMarc Zyngier */ 513021f6537SMarc Zyngier smp_wmb(); 514021f6537SMarc Zyngier 515021f6537SMarc Zyngier for_each_cpu_mask(cpu, *mask) { 516021f6537SMarc Zyngier u64 cluster_id = cpu_logical_map(cpu) & ~0xffUL; 517021f6537SMarc Zyngier u16 tlist; 518021f6537SMarc Zyngier 519021f6537SMarc Zyngier tlist = gic_compute_target_list(&cpu, mask, cluster_id); 520021f6537SMarc Zyngier gic_send_sgi(cluster_id, tlist, irq); 521021f6537SMarc Zyngier } 522021f6537SMarc Zyngier 523021f6537SMarc Zyngier /* Force the above writes to ICC_SGI1R_EL1 to be executed */ 524021f6537SMarc Zyngier isb(); 525021f6537SMarc Zyngier } 526021f6537SMarc Zyngier 527021f6537SMarc Zyngier static void gic_smp_init(void) 528021f6537SMarc Zyngier { 529021f6537SMarc Zyngier set_smp_cross_call(gic_raise_softirq); 530021f6537SMarc Zyngier register_cpu_notifier(&gic_cpu_notifier); 531021f6537SMarc Zyngier } 532021f6537SMarc Zyngier 533021f6537SMarc Zyngier static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, 534021f6537SMarc Zyngier bool force) 535021f6537SMarc Zyngier { 536021f6537SMarc Zyngier unsigned int cpu = cpumask_any_and(mask_val, cpu_online_mask); 537021f6537SMarc Zyngier void __iomem *reg; 538021f6537SMarc Zyngier int enabled; 539021f6537SMarc Zyngier u64 val; 540021f6537SMarc Zyngier 541021f6537SMarc Zyngier if (gic_irq_in_rdist(d)) 542021f6537SMarc Zyngier return -EINVAL; 543021f6537SMarc Zyngier 544021f6537SMarc Zyngier /* If interrupt was enabled, disable it first */ 545021f6537SMarc Zyngier enabled = gic_peek_irq(d, GICD_ISENABLER); 546021f6537SMarc Zyngier if (enabled) 547021f6537SMarc Zyngier gic_mask_irq(d); 548021f6537SMarc Zyngier 549021f6537SMarc Zyngier reg = gic_dist_base(d) + GICD_IROUTER + (gic_irq(d) * 8); 550021f6537SMarc Zyngier val = gic_mpidr_to_affinity(cpu_logical_map(cpu)); 551021f6537SMarc Zyngier 552021f6537SMarc Zyngier writeq_relaxed(val, reg); 553021f6537SMarc Zyngier 554021f6537SMarc Zyngier /* 555021f6537SMarc Zyngier * If the interrupt was enabled, enabled it again. Otherwise, 556021f6537SMarc Zyngier * just wait for the distributor to have digested our changes. 557021f6537SMarc Zyngier */ 558021f6537SMarc Zyngier if (enabled) 559021f6537SMarc Zyngier gic_unmask_irq(d); 560021f6537SMarc Zyngier else 561021f6537SMarc Zyngier gic_dist_wait_for_rwp(); 562021f6537SMarc Zyngier 563021f6537SMarc Zyngier return IRQ_SET_MASK_OK; 564021f6537SMarc Zyngier } 565021f6537SMarc Zyngier #else 566021f6537SMarc Zyngier #define gic_set_affinity NULL 567021f6537SMarc Zyngier #define gic_smp_init() do { } while(0) 568021f6537SMarc Zyngier #endif 569021f6537SMarc Zyngier 5703708d52fSSudeep Holla #ifdef CONFIG_CPU_PM 5713708d52fSSudeep Holla static int gic_cpu_pm_notifier(struct notifier_block *self, 5723708d52fSSudeep Holla unsigned long cmd, void *v) 5733708d52fSSudeep Holla { 5743708d52fSSudeep Holla if (cmd == CPU_PM_EXIT) { 5753708d52fSSudeep Holla gic_enable_redist(true); 5763708d52fSSudeep Holla gic_cpu_sys_reg_init(); 5773708d52fSSudeep Holla } else if (cmd == CPU_PM_ENTER) { 5783708d52fSSudeep Holla gic_write_grpen1(0); 5793708d52fSSudeep Holla gic_enable_redist(false); 5803708d52fSSudeep Holla } 5813708d52fSSudeep Holla return NOTIFY_OK; 5823708d52fSSudeep Holla } 5833708d52fSSudeep Holla 5843708d52fSSudeep Holla static struct notifier_block gic_cpu_pm_notifier_block = { 5853708d52fSSudeep Holla .notifier_call = gic_cpu_pm_notifier, 5863708d52fSSudeep Holla }; 5873708d52fSSudeep Holla 5883708d52fSSudeep Holla static void gic_cpu_pm_init(void) 5893708d52fSSudeep Holla { 5903708d52fSSudeep Holla cpu_pm_register_notifier(&gic_cpu_pm_notifier_block); 5913708d52fSSudeep Holla } 5923708d52fSSudeep Holla 5933708d52fSSudeep Holla #else 5943708d52fSSudeep Holla static inline void gic_cpu_pm_init(void) { } 5953708d52fSSudeep Holla #endif /* CONFIG_CPU_PM */ 5963708d52fSSudeep Holla 597021f6537SMarc Zyngier static struct irq_chip gic_chip = { 598021f6537SMarc Zyngier .name = "GICv3", 599021f6537SMarc Zyngier .irq_mask = gic_mask_irq, 600021f6537SMarc Zyngier .irq_unmask = gic_unmask_irq, 601021f6537SMarc Zyngier .irq_eoi = gic_eoi_irq, 602021f6537SMarc Zyngier .irq_set_type = gic_set_type, 603021f6537SMarc Zyngier .irq_set_affinity = gic_set_affinity, 604021f6537SMarc Zyngier }; 605021f6537SMarc Zyngier 606da33f31dSMarc Zyngier #define GIC_ID_NR (1U << gic_data.rdists.id_bits) 607da33f31dSMarc Zyngier 608021f6537SMarc Zyngier static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq, 609021f6537SMarc Zyngier irq_hw_number_t hw) 610021f6537SMarc Zyngier { 611021f6537SMarc Zyngier /* SGIs are private to the core kernel */ 612021f6537SMarc Zyngier if (hw < 16) 613021f6537SMarc Zyngier return -EPERM; 614da33f31dSMarc Zyngier /* Nothing here */ 615da33f31dSMarc Zyngier if (hw >= gic_data.irq_nr && hw < 8192) 616da33f31dSMarc Zyngier return -EPERM; 617da33f31dSMarc Zyngier /* Off limits */ 618da33f31dSMarc Zyngier if (hw >= GIC_ID_NR) 619da33f31dSMarc Zyngier return -EPERM; 620da33f31dSMarc Zyngier 621021f6537SMarc Zyngier /* PPIs */ 622021f6537SMarc Zyngier if (hw < 32) { 623021f6537SMarc Zyngier irq_set_percpu_devid(irq); 624443acc4fSMarc Zyngier irq_domain_set_info(d, irq, hw, &gic_chip, d->host_data, 625443acc4fSMarc Zyngier handle_percpu_devid_irq, NULL, NULL); 626021f6537SMarc Zyngier set_irq_flags(irq, IRQF_VALID | IRQF_NOAUTOEN); 627021f6537SMarc Zyngier } 628021f6537SMarc Zyngier /* SPIs */ 629021f6537SMarc Zyngier if (hw >= 32 && hw < gic_data.irq_nr) { 630443acc4fSMarc Zyngier irq_domain_set_info(d, irq, hw, &gic_chip, d->host_data, 631443acc4fSMarc Zyngier handle_fasteoi_irq, NULL, NULL); 632021f6537SMarc Zyngier set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 633021f6537SMarc Zyngier } 634da33f31dSMarc Zyngier /* LPIs */ 635da33f31dSMarc Zyngier if (hw >= 8192 && hw < GIC_ID_NR) { 636da33f31dSMarc Zyngier if (!gic_dist_supports_lpis()) 637da33f31dSMarc Zyngier return -EPERM; 638da33f31dSMarc Zyngier irq_domain_set_info(d, irq, hw, &gic_chip, d->host_data, 639da33f31dSMarc Zyngier handle_fasteoi_irq, NULL, NULL); 640da33f31dSMarc Zyngier set_irq_flags(irq, IRQF_VALID); 641da33f31dSMarc Zyngier } 642da33f31dSMarc Zyngier 643021f6537SMarc Zyngier return 0; 644021f6537SMarc Zyngier } 645021f6537SMarc Zyngier 646021f6537SMarc Zyngier static int gic_irq_domain_xlate(struct irq_domain *d, 647021f6537SMarc Zyngier struct device_node *controller, 648021f6537SMarc Zyngier const u32 *intspec, unsigned int intsize, 649021f6537SMarc Zyngier unsigned long *out_hwirq, unsigned int *out_type) 650021f6537SMarc Zyngier { 651021f6537SMarc Zyngier if (d->of_node != controller) 652021f6537SMarc Zyngier return -EINVAL; 653021f6537SMarc Zyngier if (intsize < 3) 654021f6537SMarc Zyngier return -EINVAL; 655021f6537SMarc Zyngier 656021f6537SMarc Zyngier switch(intspec[0]) { 657021f6537SMarc Zyngier case 0: /* SPI */ 658021f6537SMarc Zyngier *out_hwirq = intspec[1] + 32; 659021f6537SMarc Zyngier break; 660021f6537SMarc Zyngier case 1: /* PPI */ 661021f6537SMarc Zyngier *out_hwirq = intspec[1] + 16; 662021f6537SMarc Zyngier break; 663da33f31dSMarc Zyngier case GIC_IRQ_TYPE_LPI: /* LPI */ 664da33f31dSMarc Zyngier *out_hwirq = intspec[1]; 665da33f31dSMarc Zyngier break; 666021f6537SMarc Zyngier default: 667021f6537SMarc Zyngier return -EINVAL; 668021f6537SMarc Zyngier } 669021f6537SMarc Zyngier 670021f6537SMarc Zyngier *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK; 671021f6537SMarc Zyngier return 0; 672021f6537SMarc Zyngier } 673021f6537SMarc Zyngier 674443acc4fSMarc Zyngier static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, 675443acc4fSMarc Zyngier unsigned int nr_irqs, void *arg) 676443acc4fSMarc Zyngier { 677443acc4fSMarc Zyngier int i, ret; 678443acc4fSMarc Zyngier irq_hw_number_t hwirq; 679443acc4fSMarc Zyngier unsigned int type = IRQ_TYPE_NONE; 680443acc4fSMarc Zyngier struct of_phandle_args *irq_data = arg; 681443acc4fSMarc Zyngier 682443acc4fSMarc Zyngier ret = gic_irq_domain_xlate(domain, irq_data->np, irq_data->args, 683443acc4fSMarc Zyngier irq_data->args_count, &hwirq, &type); 684443acc4fSMarc Zyngier if (ret) 685443acc4fSMarc Zyngier return ret; 686443acc4fSMarc Zyngier 687443acc4fSMarc Zyngier for (i = 0; i < nr_irqs; i++) 688443acc4fSMarc Zyngier gic_irq_domain_map(domain, virq + i, hwirq + i); 689443acc4fSMarc Zyngier 690443acc4fSMarc Zyngier return 0; 691443acc4fSMarc Zyngier } 692443acc4fSMarc Zyngier 693443acc4fSMarc Zyngier static void gic_irq_domain_free(struct irq_domain *domain, unsigned int virq, 694443acc4fSMarc Zyngier unsigned int nr_irqs) 695443acc4fSMarc Zyngier { 696443acc4fSMarc Zyngier int i; 697443acc4fSMarc Zyngier 698443acc4fSMarc Zyngier for (i = 0; i < nr_irqs; i++) { 699443acc4fSMarc Zyngier struct irq_data *d = irq_domain_get_irq_data(domain, virq + i); 700443acc4fSMarc Zyngier irq_set_handler(virq + i, NULL); 701443acc4fSMarc Zyngier irq_domain_reset_irq_data(d); 702443acc4fSMarc Zyngier } 703443acc4fSMarc Zyngier } 704443acc4fSMarc Zyngier 705021f6537SMarc Zyngier static const struct irq_domain_ops gic_irq_domain_ops = { 706021f6537SMarc Zyngier .xlate = gic_irq_domain_xlate, 707443acc4fSMarc Zyngier .alloc = gic_irq_domain_alloc, 708443acc4fSMarc Zyngier .free = gic_irq_domain_free, 709021f6537SMarc Zyngier }; 710021f6537SMarc Zyngier 711021f6537SMarc Zyngier static int __init gic_of_init(struct device_node *node, struct device_node *parent) 712021f6537SMarc Zyngier { 713021f6537SMarc Zyngier void __iomem *dist_base; 714f5c1434cSMarc Zyngier struct redist_region *rdist_regs; 715021f6537SMarc Zyngier u64 redist_stride; 716f5c1434cSMarc Zyngier u32 nr_redist_regions; 717f5c1434cSMarc Zyngier u32 typer; 718021f6537SMarc Zyngier u32 reg; 719021f6537SMarc Zyngier int gic_irqs; 720021f6537SMarc Zyngier int err; 721021f6537SMarc Zyngier int i; 722021f6537SMarc Zyngier 723021f6537SMarc Zyngier dist_base = of_iomap(node, 0); 724021f6537SMarc Zyngier if (!dist_base) { 725021f6537SMarc Zyngier pr_err("%s: unable to map gic dist registers\n", 726021f6537SMarc Zyngier node->full_name); 727021f6537SMarc Zyngier return -ENXIO; 728021f6537SMarc Zyngier } 729021f6537SMarc Zyngier 730021f6537SMarc Zyngier reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK; 731021f6537SMarc Zyngier if (reg != GIC_PIDR2_ARCH_GICv3 && reg != GIC_PIDR2_ARCH_GICv4) { 732021f6537SMarc Zyngier pr_err("%s: no distributor detected, giving up\n", 733021f6537SMarc Zyngier node->full_name); 734021f6537SMarc Zyngier err = -ENODEV; 735021f6537SMarc Zyngier goto out_unmap_dist; 736021f6537SMarc Zyngier } 737021f6537SMarc Zyngier 738f5c1434cSMarc Zyngier if (of_property_read_u32(node, "#redistributor-regions", &nr_redist_regions)) 739f5c1434cSMarc Zyngier nr_redist_regions = 1; 740021f6537SMarc Zyngier 741f5c1434cSMarc Zyngier rdist_regs = kzalloc(sizeof(*rdist_regs) * nr_redist_regions, GFP_KERNEL); 742f5c1434cSMarc Zyngier if (!rdist_regs) { 743021f6537SMarc Zyngier err = -ENOMEM; 744021f6537SMarc Zyngier goto out_unmap_dist; 745021f6537SMarc Zyngier } 746021f6537SMarc Zyngier 747f5c1434cSMarc Zyngier for (i = 0; i < nr_redist_regions; i++) { 748f5c1434cSMarc Zyngier struct resource res; 749f5c1434cSMarc Zyngier int ret; 750f5c1434cSMarc Zyngier 751f5c1434cSMarc Zyngier ret = of_address_to_resource(node, 1 + i, &res); 752f5c1434cSMarc Zyngier rdist_regs[i].redist_base = of_iomap(node, 1 + i); 753f5c1434cSMarc Zyngier if (ret || !rdist_regs[i].redist_base) { 754021f6537SMarc Zyngier pr_err("%s: couldn't map region %d\n", 755021f6537SMarc Zyngier node->full_name, i); 756021f6537SMarc Zyngier err = -ENODEV; 757021f6537SMarc Zyngier goto out_unmap_rdist; 758021f6537SMarc Zyngier } 759f5c1434cSMarc Zyngier rdist_regs[i].phys_base = res.start; 760021f6537SMarc Zyngier } 761021f6537SMarc Zyngier 762021f6537SMarc Zyngier if (of_property_read_u64(node, "redistributor-stride", &redist_stride)) 763021f6537SMarc Zyngier redist_stride = 0; 764021f6537SMarc Zyngier 765021f6537SMarc Zyngier gic_data.dist_base = dist_base; 766f5c1434cSMarc Zyngier gic_data.redist_regions = rdist_regs; 767f5c1434cSMarc Zyngier gic_data.nr_redist_regions = nr_redist_regions; 768021f6537SMarc Zyngier gic_data.redist_stride = redist_stride; 769021f6537SMarc Zyngier 770021f6537SMarc Zyngier /* 771021f6537SMarc Zyngier * Find out how many interrupts are supported. 772021f6537SMarc Zyngier * The GIC only supports up to 1020 interrupt sources (SGI+PPI+SPI) 773021f6537SMarc Zyngier */ 774f5c1434cSMarc Zyngier typer = readl_relaxed(gic_data.dist_base + GICD_TYPER); 775f5c1434cSMarc Zyngier gic_data.rdists.id_bits = GICD_TYPER_ID_BITS(typer); 776f5c1434cSMarc Zyngier gic_irqs = GICD_TYPER_IRQS(typer); 777021f6537SMarc Zyngier if (gic_irqs > 1020) 778021f6537SMarc Zyngier gic_irqs = 1020; 779021f6537SMarc Zyngier gic_data.irq_nr = gic_irqs; 780021f6537SMarc Zyngier 781021f6537SMarc Zyngier gic_data.domain = irq_domain_add_tree(node, &gic_irq_domain_ops, 782021f6537SMarc Zyngier &gic_data); 783f5c1434cSMarc Zyngier gic_data.rdists.rdist = alloc_percpu(typeof(*gic_data.rdists.rdist)); 784021f6537SMarc Zyngier 785f5c1434cSMarc Zyngier if (WARN_ON(!gic_data.domain) || WARN_ON(!gic_data.rdists.rdist)) { 786021f6537SMarc Zyngier err = -ENOMEM; 787021f6537SMarc Zyngier goto out_free; 788021f6537SMarc Zyngier } 789021f6537SMarc Zyngier 790021f6537SMarc Zyngier set_handle_irq(gic_handle_irq); 791021f6537SMarc Zyngier 792da33f31dSMarc Zyngier if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis()) 793da33f31dSMarc Zyngier its_init(node, &gic_data.rdists, gic_data.domain); 794da33f31dSMarc Zyngier 795021f6537SMarc Zyngier gic_smp_init(); 796021f6537SMarc Zyngier gic_dist_init(); 797021f6537SMarc Zyngier gic_cpu_init(); 7983708d52fSSudeep Holla gic_cpu_pm_init(); 799021f6537SMarc Zyngier 800021f6537SMarc Zyngier return 0; 801021f6537SMarc Zyngier 802021f6537SMarc Zyngier out_free: 803021f6537SMarc Zyngier if (gic_data.domain) 804021f6537SMarc Zyngier irq_domain_remove(gic_data.domain); 805f5c1434cSMarc Zyngier free_percpu(gic_data.rdists.rdist); 806021f6537SMarc Zyngier out_unmap_rdist: 807f5c1434cSMarc Zyngier for (i = 0; i < nr_redist_regions; i++) 808f5c1434cSMarc Zyngier if (rdist_regs[i].redist_base) 809f5c1434cSMarc Zyngier iounmap(rdist_regs[i].redist_base); 810f5c1434cSMarc Zyngier kfree(rdist_regs); 811021f6537SMarc Zyngier out_unmap_dist: 812021f6537SMarc Zyngier iounmap(dist_base); 813021f6537SMarc Zyngier return err; 814021f6537SMarc Zyngier } 815021f6537SMarc Zyngier 816021f6537SMarc Zyngier IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init); 817