1021f6537SMarc Zyngier /* 2021f6537SMarc Zyngier * Copyright (C) 2013, 2014 ARM Limited, All Rights Reserved. 3021f6537SMarc Zyngier * Author: Marc Zyngier <marc.zyngier@arm.com> 4021f6537SMarc Zyngier * 5021f6537SMarc Zyngier * This program is free software; you can redistribute it and/or modify 6021f6537SMarc Zyngier * it under the terms of the GNU General Public License version 2 as 7021f6537SMarc Zyngier * published by the Free Software Foundation. 8021f6537SMarc Zyngier * 9021f6537SMarc Zyngier * This program is distributed in the hope that it will be useful, 10021f6537SMarc Zyngier * but WITHOUT ANY WARRANTY; without even the implied warranty of 11021f6537SMarc Zyngier * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12021f6537SMarc Zyngier * GNU General Public License for more details. 13021f6537SMarc Zyngier * 14021f6537SMarc Zyngier * You should have received a copy of the GNU General Public License 15021f6537SMarc Zyngier * along with this program. If not, see <http://www.gnu.org/licenses/>. 16021f6537SMarc Zyngier */ 17021f6537SMarc Zyngier 1868628bb8SJulien Grall #define pr_fmt(fmt) "GICv3: " fmt 1968628bb8SJulien Grall 20ffa7d616STomasz Nowicki #include <linux/acpi.h> 21021f6537SMarc Zyngier #include <linux/cpu.h> 223708d52fSSudeep Holla #include <linux/cpu_pm.h> 23021f6537SMarc Zyngier #include <linux/delay.h> 24021f6537SMarc Zyngier #include <linux/interrupt.h> 25ffa7d616STomasz Nowicki #include <linux/irqdomain.h> 26021f6537SMarc Zyngier #include <linux/of.h> 27021f6537SMarc Zyngier #include <linux/of_address.h> 28021f6537SMarc Zyngier #include <linux/of_irq.h> 29021f6537SMarc Zyngier #include <linux/percpu.h> 30021f6537SMarc Zyngier #include <linux/slab.h> 31021f6537SMarc Zyngier 3241a83e06SJoel Porquet #include <linux/irqchip.h> 331839e576SJulien Grall #include <linux/irqchip/arm-gic-common.h> 34021f6537SMarc Zyngier #include <linux/irqchip/arm-gic-v3.h> 35e3825ba1SMarc Zyngier #include <linux/irqchip/irq-partition-percpu.h> 36021f6537SMarc Zyngier 37021f6537SMarc Zyngier #include <asm/cputype.h> 38021f6537SMarc Zyngier #include <asm/exception.h> 39021f6537SMarc Zyngier #include <asm/smp_plat.h> 400b6a3da9SMarc Zyngier #include <asm/virt.h> 41021f6537SMarc Zyngier 42021f6537SMarc Zyngier #include "irq-gic-common.h" 43021f6537SMarc Zyngier 44f5c1434cSMarc Zyngier struct redist_region { 45f5c1434cSMarc Zyngier void __iomem *redist_base; 46f5c1434cSMarc Zyngier phys_addr_t phys_base; 47b70fb7afSTomasz Nowicki bool single_redist; 48f5c1434cSMarc Zyngier }; 49f5c1434cSMarc Zyngier 50021f6537SMarc Zyngier struct gic_chip_data { 51e3825ba1SMarc Zyngier struct fwnode_handle *fwnode; 52021f6537SMarc Zyngier void __iomem *dist_base; 53f5c1434cSMarc Zyngier struct redist_region *redist_regions; 54f5c1434cSMarc Zyngier struct rdists rdists; 55021f6537SMarc Zyngier struct irq_domain *domain; 56021f6537SMarc Zyngier u64 redist_stride; 57f5c1434cSMarc Zyngier u32 nr_redist_regions; 58021f6537SMarc Zyngier unsigned int irq_nr; 59e3825ba1SMarc Zyngier struct partition_desc *ppi_descs[16]; 60021f6537SMarc Zyngier }; 61021f6537SMarc Zyngier 62021f6537SMarc Zyngier static struct gic_chip_data gic_data __read_mostly; 630b6a3da9SMarc Zyngier static struct static_key supports_deactivate = STATIC_KEY_INIT_TRUE; 64021f6537SMarc Zyngier 651839e576SJulien Grall static struct gic_kvm_info gic_v3_kvm_info; 661839e576SJulien Grall 67f5c1434cSMarc Zyngier #define gic_data_rdist() (this_cpu_ptr(gic_data.rdists.rdist)) 68f5c1434cSMarc Zyngier #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base) 69021f6537SMarc Zyngier #define gic_data_rdist_sgi_base() (gic_data_rdist_rd_base() + SZ_64K) 70021f6537SMarc Zyngier 71021f6537SMarc Zyngier /* Our default, arbitrary priority value. Linux only uses one anyway. */ 72021f6537SMarc Zyngier #define DEFAULT_PMR_VALUE 0xf0 73021f6537SMarc Zyngier 74021f6537SMarc Zyngier static inline unsigned int gic_irq(struct irq_data *d) 75021f6537SMarc Zyngier { 76021f6537SMarc Zyngier return d->hwirq; 77021f6537SMarc Zyngier } 78021f6537SMarc Zyngier 79021f6537SMarc Zyngier static inline int gic_irq_in_rdist(struct irq_data *d) 80021f6537SMarc Zyngier { 81021f6537SMarc Zyngier return gic_irq(d) < 32; 82021f6537SMarc Zyngier } 83021f6537SMarc Zyngier 84021f6537SMarc Zyngier static inline void __iomem *gic_dist_base(struct irq_data *d) 85021f6537SMarc Zyngier { 86021f6537SMarc Zyngier if (gic_irq_in_rdist(d)) /* SGI+PPI -> SGI_base for this CPU */ 87021f6537SMarc Zyngier return gic_data_rdist_sgi_base(); 88021f6537SMarc Zyngier 89021f6537SMarc Zyngier if (d->hwirq <= 1023) /* SPI -> dist_base */ 90021f6537SMarc Zyngier return gic_data.dist_base; 91021f6537SMarc Zyngier 92021f6537SMarc Zyngier return NULL; 93021f6537SMarc Zyngier } 94021f6537SMarc Zyngier 95021f6537SMarc Zyngier static void gic_do_wait_for_rwp(void __iomem *base) 96021f6537SMarc Zyngier { 97021f6537SMarc Zyngier u32 count = 1000000; /* 1s! */ 98021f6537SMarc Zyngier 99021f6537SMarc Zyngier while (readl_relaxed(base + GICD_CTLR) & GICD_CTLR_RWP) { 100021f6537SMarc Zyngier count--; 101021f6537SMarc Zyngier if (!count) { 102021f6537SMarc Zyngier pr_err_ratelimited("RWP timeout, gone fishing\n"); 103021f6537SMarc Zyngier return; 104021f6537SMarc Zyngier } 105021f6537SMarc Zyngier cpu_relax(); 106021f6537SMarc Zyngier udelay(1); 107021f6537SMarc Zyngier }; 108021f6537SMarc Zyngier } 109021f6537SMarc Zyngier 110021f6537SMarc Zyngier /* Wait for completion of a distributor change */ 111021f6537SMarc Zyngier static void gic_dist_wait_for_rwp(void) 112021f6537SMarc Zyngier { 113021f6537SMarc Zyngier gic_do_wait_for_rwp(gic_data.dist_base); 114021f6537SMarc Zyngier } 115021f6537SMarc Zyngier 116021f6537SMarc Zyngier /* Wait for completion of a redistributor change */ 117021f6537SMarc Zyngier static void gic_redist_wait_for_rwp(void) 118021f6537SMarc Zyngier { 119021f6537SMarc Zyngier gic_do_wait_for_rwp(gic_data_rdist_rd_base()); 120021f6537SMarc Zyngier } 121021f6537SMarc Zyngier 1227936e914SJean-Philippe Brucker #ifdef CONFIG_ARM64 1238ac2a170SRobert Richter static DEFINE_STATIC_KEY_FALSE(is_cavium_thunderx); 1246d4e11c5SRobert Richter 1256d4e11c5SRobert Richter static u64 __maybe_unused gic_read_iar(void) 1266d4e11c5SRobert Richter { 1278ac2a170SRobert Richter if (static_branch_unlikely(&is_cavium_thunderx)) 1286d4e11c5SRobert Richter return gic_read_iar_cavium_thunderx(); 1296d4e11c5SRobert Richter else 1306d4e11c5SRobert Richter return gic_read_iar_common(); 1316d4e11c5SRobert Richter } 1327936e914SJean-Philippe Brucker #endif 133021f6537SMarc Zyngier 134a2c22510SSudeep Holla static void gic_enable_redist(bool enable) 135021f6537SMarc Zyngier { 136021f6537SMarc Zyngier void __iomem *rbase; 137021f6537SMarc Zyngier u32 count = 1000000; /* 1s! */ 138021f6537SMarc Zyngier u32 val; 139021f6537SMarc Zyngier 140021f6537SMarc Zyngier rbase = gic_data_rdist_rd_base(); 141021f6537SMarc Zyngier 142021f6537SMarc Zyngier val = readl_relaxed(rbase + GICR_WAKER); 143a2c22510SSudeep Holla if (enable) 144a2c22510SSudeep Holla /* Wake up this CPU redistributor */ 145021f6537SMarc Zyngier val &= ~GICR_WAKER_ProcessorSleep; 146a2c22510SSudeep Holla else 147a2c22510SSudeep Holla val |= GICR_WAKER_ProcessorSleep; 148021f6537SMarc Zyngier writel_relaxed(val, rbase + GICR_WAKER); 149021f6537SMarc Zyngier 150a2c22510SSudeep Holla if (!enable) { /* Check that GICR_WAKER is writeable */ 151a2c22510SSudeep Holla val = readl_relaxed(rbase + GICR_WAKER); 152a2c22510SSudeep Holla if (!(val & GICR_WAKER_ProcessorSleep)) 153a2c22510SSudeep Holla return; /* No PM support in this redistributor */ 154021f6537SMarc Zyngier } 155a2c22510SSudeep Holla 156a2c22510SSudeep Holla while (count--) { 157a2c22510SSudeep Holla val = readl_relaxed(rbase + GICR_WAKER); 158cf1d9d11SAndrew Jones if (enable ^ (bool)(val & GICR_WAKER_ChildrenAsleep)) 159a2c22510SSudeep Holla break; 160021f6537SMarc Zyngier cpu_relax(); 161021f6537SMarc Zyngier udelay(1); 162021f6537SMarc Zyngier }; 163a2c22510SSudeep Holla if (!count) 164a2c22510SSudeep Holla pr_err_ratelimited("redistributor failed to %s...\n", 165a2c22510SSudeep Holla enable ? "wakeup" : "sleep"); 166021f6537SMarc Zyngier } 167021f6537SMarc Zyngier 168021f6537SMarc Zyngier /* 169021f6537SMarc Zyngier * Routines to disable, enable, EOI and route interrupts 170021f6537SMarc Zyngier */ 171b594c6e2SMarc Zyngier static int gic_peek_irq(struct irq_data *d, u32 offset) 172b594c6e2SMarc Zyngier { 173b594c6e2SMarc Zyngier u32 mask = 1 << (gic_irq(d) % 32); 174b594c6e2SMarc Zyngier void __iomem *base; 175b594c6e2SMarc Zyngier 176b594c6e2SMarc Zyngier if (gic_irq_in_rdist(d)) 177b594c6e2SMarc Zyngier base = gic_data_rdist_sgi_base(); 178b594c6e2SMarc Zyngier else 179b594c6e2SMarc Zyngier base = gic_data.dist_base; 180b594c6e2SMarc Zyngier 181b594c6e2SMarc Zyngier return !!(readl_relaxed(base + offset + (gic_irq(d) / 32) * 4) & mask); 182b594c6e2SMarc Zyngier } 183b594c6e2SMarc Zyngier 184021f6537SMarc Zyngier static void gic_poke_irq(struct irq_data *d, u32 offset) 185021f6537SMarc Zyngier { 186021f6537SMarc Zyngier u32 mask = 1 << (gic_irq(d) % 32); 187021f6537SMarc Zyngier void (*rwp_wait)(void); 188021f6537SMarc Zyngier void __iomem *base; 189021f6537SMarc Zyngier 190021f6537SMarc Zyngier if (gic_irq_in_rdist(d)) { 191021f6537SMarc Zyngier base = gic_data_rdist_sgi_base(); 192021f6537SMarc Zyngier rwp_wait = gic_redist_wait_for_rwp; 193021f6537SMarc Zyngier } else { 194021f6537SMarc Zyngier base = gic_data.dist_base; 195021f6537SMarc Zyngier rwp_wait = gic_dist_wait_for_rwp; 196021f6537SMarc Zyngier } 197021f6537SMarc Zyngier 198021f6537SMarc Zyngier writel_relaxed(mask, base + offset + (gic_irq(d) / 32) * 4); 199021f6537SMarc Zyngier rwp_wait(); 200021f6537SMarc Zyngier } 201021f6537SMarc Zyngier 202021f6537SMarc Zyngier static void gic_mask_irq(struct irq_data *d) 203021f6537SMarc Zyngier { 204021f6537SMarc Zyngier gic_poke_irq(d, GICD_ICENABLER); 205021f6537SMarc Zyngier } 206021f6537SMarc Zyngier 2070b6a3da9SMarc Zyngier static void gic_eoimode1_mask_irq(struct irq_data *d) 2080b6a3da9SMarc Zyngier { 2090b6a3da9SMarc Zyngier gic_mask_irq(d); 210530bf353SMarc Zyngier /* 211530bf353SMarc Zyngier * When masking a forwarded interrupt, make sure it is 212530bf353SMarc Zyngier * deactivated as well. 213530bf353SMarc Zyngier * 214530bf353SMarc Zyngier * This ensures that an interrupt that is getting 215530bf353SMarc Zyngier * disabled/masked will not get "stuck", because there is 216530bf353SMarc Zyngier * noone to deactivate it (guest is being terminated). 217530bf353SMarc Zyngier */ 2184df7f54dSThomas Gleixner if (irqd_is_forwarded_to_vcpu(d)) 219530bf353SMarc Zyngier gic_poke_irq(d, GICD_ICACTIVER); 2200b6a3da9SMarc Zyngier } 2210b6a3da9SMarc Zyngier 222021f6537SMarc Zyngier static void gic_unmask_irq(struct irq_data *d) 223021f6537SMarc Zyngier { 224021f6537SMarc Zyngier gic_poke_irq(d, GICD_ISENABLER); 225021f6537SMarc Zyngier } 226021f6537SMarc Zyngier 227b594c6e2SMarc Zyngier static int gic_irq_set_irqchip_state(struct irq_data *d, 228b594c6e2SMarc Zyngier enum irqchip_irq_state which, bool val) 229b594c6e2SMarc Zyngier { 230b594c6e2SMarc Zyngier u32 reg; 231b594c6e2SMarc Zyngier 232b594c6e2SMarc Zyngier if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */ 233b594c6e2SMarc Zyngier return -EINVAL; 234b594c6e2SMarc Zyngier 235b594c6e2SMarc Zyngier switch (which) { 236b594c6e2SMarc Zyngier case IRQCHIP_STATE_PENDING: 237b594c6e2SMarc Zyngier reg = val ? GICD_ISPENDR : GICD_ICPENDR; 238b594c6e2SMarc Zyngier break; 239b594c6e2SMarc Zyngier 240b594c6e2SMarc Zyngier case IRQCHIP_STATE_ACTIVE: 241b594c6e2SMarc Zyngier reg = val ? GICD_ISACTIVER : GICD_ICACTIVER; 242b594c6e2SMarc Zyngier break; 243b594c6e2SMarc Zyngier 244b594c6e2SMarc Zyngier case IRQCHIP_STATE_MASKED: 245b594c6e2SMarc Zyngier reg = val ? GICD_ICENABLER : GICD_ISENABLER; 246b594c6e2SMarc Zyngier break; 247b594c6e2SMarc Zyngier 248b594c6e2SMarc Zyngier default: 249b594c6e2SMarc Zyngier return -EINVAL; 250b594c6e2SMarc Zyngier } 251b594c6e2SMarc Zyngier 252b594c6e2SMarc Zyngier gic_poke_irq(d, reg); 253b594c6e2SMarc Zyngier return 0; 254b594c6e2SMarc Zyngier } 255b594c6e2SMarc Zyngier 256b594c6e2SMarc Zyngier static int gic_irq_get_irqchip_state(struct irq_data *d, 257b594c6e2SMarc Zyngier enum irqchip_irq_state which, bool *val) 258b594c6e2SMarc Zyngier { 259b594c6e2SMarc Zyngier if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */ 260b594c6e2SMarc Zyngier return -EINVAL; 261b594c6e2SMarc Zyngier 262b594c6e2SMarc Zyngier switch (which) { 263b594c6e2SMarc Zyngier case IRQCHIP_STATE_PENDING: 264b594c6e2SMarc Zyngier *val = gic_peek_irq(d, GICD_ISPENDR); 265b594c6e2SMarc Zyngier break; 266b594c6e2SMarc Zyngier 267b594c6e2SMarc Zyngier case IRQCHIP_STATE_ACTIVE: 268b594c6e2SMarc Zyngier *val = gic_peek_irq(d, GICD_ISACTIVER); 269b594c6e2SMarc Zyngier break; 270b594c6e2SMarc Zyngier 271b594c6e2SMarc Zyngier case IRQCHIP_STATE_MASKED: 272b594c6e2SMarc Zyngier *val = !gic_peek_irq(d, GICD_ISENABLER); 273b594c6e2SMarc Zyngier break; 274b594c6e2SMarc Zyngier 275b594c6e2SMarc Zyngier default: 276b594c6e2SMarc Zyngier return -EINVAL; 277b594c6e2SMarc Zyngier } 278b594c6e2SMarc Zyngier 279b594c6e2SMarc Zyngier return 0; 280b594c6e2SMarc Zyngier } 281b594c6e2SMarc Zyngier 282021f6537SMarc Zyngier static void gic_eoi_irq(struct irq_data *d) 283021f6537SMarc Zyngier { 284021f6537SMarc Zyngier gic_write_eoir(gic_irq(d)); 285021f6537SMarc Zyngier } 286021f6537SMarc Zyngier 2870b6a3da9SMarc Zyngier static void gic_eoimode1_eoi_irq(struct irq_data *d) 2880b6a3da9SMarc Zyngier { 2890b6a3da9SMarc Zyngier /* 290530bf353SMarc Zyngier * No need to deactivate an LPI, or an interrupt that 291530bf353SMarc Zyngier * is is getting forwarded to a vcpu. 2920b6a3da9SMarc Zyngier */ 2934df7f54dSThomas Gleixner if (gic_irq(d) >= 8192 || irqd_is_forwarded_to_vcpu(d)) 2940b6a3da9SMarc Zyngier return; 2950b6a3da9SMarc Zyngier gic_write_dir(gic_irq(d)); 2960b6a3da9SMarc Zyngier } 2970b6a3da9SMarc Zyngier 298021f6537SMarc Zyngier static int gic_set_type(struct irq_data *d, unsigned int type) 299021f6537SMarc Zyngier { 300021f6537SMarc Zyngier unsigned int irq = gic_irq(d); 301021f6537SMarc Zyngier void (*rwp_wait)(void); 302021f6537SMarc Zyngier void __iomem *base; 303021f6537SMarc Zyngier 304021f6537SMarc Zyngier /* Interrupt configuration for SGIs can't be changed */ 305021f6537SMarc Zyngier if (irq < 16) 306021f6537SMarc Zyngier return -EINVAL; 307021f6537SMarc Zyngier 308fb7e7debSLiviu Dudau /* SPIs have restrictions on the supported types */ 309fb7e7debSLiviu Dudau if (irq >= 32 && type != IRQ_TYPE_LEVEL_HIGH && 310fb7e7debSLiviu Dudau type != IRQ_TYPE_EDGE_RISING) 311021f6537SMarc Zyngier return -EINVAL; 312021f6537SMarc Zyngier 313021f6537SMarc Zyngier if (gic_irq_in_rdist(d)) { 314021f6537SMarc Zyngier base = gic_data_rdist_sgi_base(); 315021f6537SMarc Zyngier rwp_wait = gic_redist_wait_for_rwp; 316021f6537SMarc Zyngier } else { 317021f6537SMarc Zyngier base = gic_data.dist_base; 318021f6537SMarc Zyngier rwp_wait = gic_dist_wait_for_rwp; 319021f6537SMarc Zyngier } 320021f6537SMarc Zyngier 321fb7e7debSLiviu Dudau return gic_configure_irq(irq, type, base, rwp_wait); 322021f6537SMarc Zyngier } 323021f6537SMarc Zyngier 324530bf353SMarc Zyngier static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu) 325530bf353SMarc Zyngier { 3264df7f54dSThomas Gleixner if (vcpu) 3274df7f54dSThomas Gleixner irqd_set_forwarded_to_vcpu(d); 3284df7f54dSThomas Gleixner else 3294df7f54dSThomas Gleixner irqd_clr_forwarded_to_vcpu(d); 330530bf353SMarc Zyngier return 0; 331530bf353SMarc Zyngier } 332530bf353SMarc Zyngier 333f6c86a41SJean-Philippe Brucker static u64 gic_mpidr_to_affinity(unsigned long mpidr) 334021f6537SMarc Zyngier { 335021f6537SMarc Zyngier u64 aff; 336021f6537SMarc Zyngier 337f6c86a41SJean-Philippe Brucker aff = ((u64)MPIDR_AFFINITY_LEVEL(mpidr, 3) << 32 | 338021f6537SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 | 339021f6537SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | 340021f6537SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 0)); 341021f6537SMarc Zyngier 342021f6537SMarc Zyngier return aff; 343021f6537SMarc Zyngier } 344021f6537SMarc Zyngier 345021f6537SMarc Zyngier static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) 346021f6537SMarc Zyngier { 347f6c86a41SJean-Philippe Brucker u32 irqnr; 348021f6537SMarc Zyngier 349021f6537SMarc Zyngier do { 350021f6537SMarc Zyngier irqnr = gic_read_iar(); 351021f6537SMarc Zyngier 352da33f31dSMarc Zyngier if (likely(irqnr > 15 && irqnr < 1020) || irqnr >= 8192) { 353ebc6de00SMarc Zyngier int err; 3540b6a3da9SMarc Zyngier 3550b6a3da9SMarc Zyngier if (static_key_true(&supports_deactivate)) 3560b6a3da9SMarc Zyngier gic_write_eoir(irqnr); 3570b6a3da9SMarc Zyngier 358ebc6de00SMarc Zyngier err = handle_domain_irq(gic_data.domain, irqnr, regs); 359ebc6de00SMarc Zyngier if (err) { 360da33f31dSMarc Zyngier WARN_ONCE(true, "Unexpected interrupt received!\n"); 3610b6a3da9SMarc Zyngier if (static_key_true(&supports_deactivate)) { 3620b6a3da9SMarc Zyngier if (irqnr < 8192) 3630b6a3da9SMarc Zyngier gic_write_dir(irqnr); 3640b6a3da9SMarc Zyngier } else { 365021f6537SMarc Zyngier gic_write_eoir(irqnr); 366021f6537SMarc Zyngier } 3670b6a3da9SMarc Zyngier } 368ebc6de00SMarc Zyngier continue; 369ebc6de00SMarc Zyngier } 370021f6537SMarc Zyngier if (irqnr < 16) { 371021f6537SMarc Zyngier gic_write_eoir(irqnr); 3720b6a3da9SMarc Zyngier if (static_key_true(&supports_deactivate)) 3730b6a3da9SMarc Zyngier gic_write_dir(irqnr); 374021f6537SMarc Zyngier #ifdef CONFIG_SMP 375f86c4fbdSWill Deacon /* 376f86c4fbdSWill Deacon * Unlike GICv2, we don't need an smp_rmb() here. 377f86c4fbdSWill Deacon * The control dependency from gic_read_iar to 378f86c4fbdSWill Deacon * the ISB in gic_write_eoir is enough to ensure 379f86c4fbdSWill Deacon * that any shared data read by handle_IPI will 380f86c4fbdSWill Deacon * be read after the ACK. 381f86c4fbdSWill Deacon */ 382021f6537SMarc Zyngier handle_IPI(irqnr, regs); 383021f6537SMarc Zyngier #else 384021f6537SMarc Zyngier WARN_ONCE(true, "Unexpected SGI received!\n"); 385021f6537SMarc Zyngier #endif 386021f6537SMarc Zyngier continue; 387021f6537SMarc Zyngier } 388021f6537SMarc Zyngier } while (irqnr != ICC_IAR1_EL1_SPURIOUS); 389021f6537SMarc Zyngier } 390021f6537SMarc Zyngier 391021f6537SMarc Zyngier static void __init gic_dist_init(void) 392021f6537SMarc Zyngier { 393021f6537SMarc Zyngier unsigned int i; 394021f6537SMarc Zyngier u64 affinity; 395021f6537SMarc Zyngier void __iomem *base = gic_data.dist_base; 396021f6537SMarc Zyngier 397021f6537SMarc Zyngier /* Disable the distributor */ 398021f6537SMarc Zyngier writel_relaxed(0, base + GICD_CTLR); 399021f6537SMarc Zyngier gic_dist_wait_for_rwp(); 400021f6537SMarc Zyngier 4017c9b9730SMarc Zyngier /* 4027c9b9730SMarc Zyngier * Configure SPIs as non-secure Group-1. This will only matter 4037c9b9730SMarc Zyngier * if the GIC only has a single security state. This will not 4047c9b9730SMarc Zyngier * do the right thing if the kernel is running in secure mode, 4057c9b9730SMarc Zyngier * but that's not the intended use case anyway. 4067c9b9730SMarc Zyngier */ 4077c9b9730SMarc Zyngier for (i = 32; i < gic_data.irq_nr; i += 32) 4087c9b9730SMarc Zyngier writel_relaxed(~0, base + GICD_IGROUPR + i / 8); 4097c9b9730SMarc Zyngier 410021f6537SMarc Zyngier gic_dist_config(base, gic_data.irq_nr, gic_dist_wait_for_rwp); 411021f6537SMarc Zyngier 412021f6537SMarc Zyngier /* Enable distributor with ARE, Group1 */ 413021f6537SMarc Zyngier writel_relaxed(GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G1A | GICD_CTLR_ENABLE_G1, 414021f6537SMarc Zyngier base + GICD_CTLR); 415021f6537SMarc Zyngier 416021f6537SMarc Zyngier /* 417021f6537SMarc Zyngier * Set all global interrupts to the boot CPU only. ARE must be 418021f6537SMarc Zyngier * enabled. 419021f6537SMarc Zyngier */ 420021f6537SMarc Zyngier affinity = gic_mpidr_to_affinity(cpu_logical_map(smp_processor_id())); 421021f6537SMarc Zyngier for (i = 32; i < gic_data.irq_nr; i++) 42272c97126SJean-Philippe Brucker gic_write_irouter(affinity, base + GICD_IROUTER + i * 8); 423021f6537SMarc Zyngier } 424021f6537SMarc Zyngier 425021f6537SMarc Zyngier static int gic_populate_rdist(void) 426021f6537SMarc Zyngier { 427f6c86a41SJean-Philippe Brucker unsigned long mpidr = cpu_logical_map(smp_processor_id()); 428021f6537SMarc Zyngier u64 typer; 429021f6537SMarc Zyngier u32 aff; 430021f6537SMarc Zyngier int i; 431021f6537SMarc Zyngier 432021f6537SMarc Zyngier /* 433021f6537SMarc Zyngier * Convert affinity to a 32bit value that can be matched to 434021f6537SMarc Zyngier * GICR_TYPER bits [63:32]. 435021f6537SMarc Zyngier */ 436021f6537SMarc Zyngier aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 24 | 437021f6537SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 | 438021f6537SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | 439021f6537SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 0)); 440021f6537SMarc Zyngier 441f5c1434cSMarc Zyngier for (i = 0; i < gic_data.nr_redist_regions; i++) { 442f5c1434cSMarc Zyngier void __iomem *ptr = gic_data.redist_regions[i].redist_base; 443021f6537SMarc Zyngier u32 reg; 444021f6537SMarc Zyngier 445021f6537SMarc Zyngier reg = readl_relaxed(ptr + GICR_PIDR2) & GIC_PIDR2_ARCH_MASK; 446021f6537SMarc Zyngier if (reg != GIC_PIDR2_ARCH_GICv3 && 447021f6537SMarc Zyngier reg != GIC_PIDR2_ARCH_GICv4) { /* We're in trouble... */ 448021f6537SMarc Zyngier pr_warn("No redistributor present @%p\n", ptr); 449021f6537SMarc Zyngier break; 450021f6537SMarc Zyngier } 451021f6537SMarc Zyngier 452021f6537SMarc Zyngier do { 45372c97126SJean-Philippe Brucker typer = gic_read_typer(ptr + GICR_TYPER); 454021f6537SMarc Zyngier if ((typer >> 32) == aff) { 455f5c1434cSMarc Zyngier u64 offset = ptr - gic_data.redist_regions[i].redist_base; 456021f6537SMarc Zyngier gic_data_rdist_rd_base() = ptr; 457f5c1434cSMarc Zyngier gic_data_rdist()->phys_base = gic_data.redist_regions[i].phys_base + offset; 458f6c86a41SJean-Philippe Brucker pr_info("CPU%d: found redistributor %lx region %d:%pa\n", 459f6c86a41SJean-Philippe Brucker smp_processor_id(), mpidr, i, 460f6c86a41SJean-Philippe Brucker &gic_data_rdist()->phys_base); 461021f6537SMarc Zyngier return 0; 462021f6537SMarc Zyngier } 463021f6537SMarc Zyngier 464b70fb7afSTomasz Nowicki if (gic_data.redist_regions[i].single_redist) 465b70fb7afSTomasz Nowicki break; 466b70fb7afSTomasz Nowicki 467021f6537SMarc Zyngier if (gic_data.redist_stride) { 468021f6537SMarc Zyngier ptr += gic_data.redist_stride; 469021f6537SMarc Zyngier } else { 470021f6537SMarc Zyngier ptr += SZ_64K * 2; /* Skip RD_base + SGI_base */ 471021f6537SMarc Zyngier if (typer & GICR_TYPER_VLPIS) 472021f6537SMarc Zyngier ptr += SZ_64K * 2; /* Skip VLPI_base + reserved page */ 473021f6537SMarc Zyngier } 474021f6537SMarc Zyngier } while (!(typer & GICR_TYPER_LAST)); 475021f6537SMarc Zyngier } 476021f6537SMarc Zyngier 477021f6537SMarc Zyngier /* We couldn't even deal with ourselves... */ 478f6c86a41SJean-Philippe Brucker WARN(true, "CPU%d: mpidr %lx has no re-distributor!\n", 479f6c86a41SJean-Philippe Brucker smp_processor_id(), mpidr); 480021f6537SMarc Zyngier return -ENODEV; 481021f6537SMarc Zyngier } 482021f6537SMarc Zyngier 4833708d52fSSudeep Holla static void gic_cpu_sys_reg_init(void) 484021f6537SMarc Zyngier { 4857cabd008SMarc Zyngier /* 4867cabd008SMarc Zyngier * Need to check that the SRE bit has actually been set. If 4877cabd008SMarc Zyngier * not, it means that SRE is disabled at EL2. We're going to 4887cabd008SMarc Zyngier * die painfully, and there is nothing we can do about it. 4897cabd008SMarc Zyngier * 4907cabd008SMarc Zyngier * Kindly inform the luser. 4917cabd008SMarc Zyngier */ 4927cabd008SMarc Zyngier if (!gic_enable_sre()) 4937cabd008SMarc Zyngier pr_err("GIC: unable to set SRE (disabled at EL2), panic ahead\n"); 494021f6537SMarc Zyngier 495021f6537SMarc Zyngier /* Set priority mask register */ 496021f6537SMarc Zyngier gic_write_pmr(DEFAULT_PMR_VALUE); 497021f6537SMarc Zyngier 4980b6a3da9SMarc Zyngier if (static_key_true(&supports_deactivate)) { 4990b6a3da9SMarc Zyngier /* EOI drops priority only (mode 1) */ 5000b6a3da9SMarc Zyngier gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop); 5010b6a3da9SMarc Zyngier } else { 502021f6537SMarc Zyngier /* EOI deactivates interrupt too (mode 0) */ 503021f6537SMarc Zyngier gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop_dir); 5040b6a3da9SMarc Zyngier } 505021f6537SMarc Zyngier 506021f6537SMarc Zyngier /* ... and let's hit the road... */ 507021f6537SMarc Zyngier gic_write_grpen1(1); 508021f6537SMarc Zyngier } 509021f6537SMarc Zyngier 510da33f31dSMarc Zyngier static int gic_dist_supports_lpis(void) 511da33f31dSMarc Zyngier { 512da33f31dSMarc Zyngier return !!(readl_relaxed(gic_data.dist_base + GICD_TYPER) & GICD_TYPER_LPIS); 513da33f31dSMarc Zyngier } 514da33f31dSMarc Zyngier 515021f6537SMarc Zyngier static void gic_cpu_init(void) 516021f6537SMarc Zyngier { 517021f6537SMarc Zyngier void __iomem *rbase; 518021f6537SMarc Zyngier 519021f6537SMarc Zyngier /* Register ourselves with the rest of the world */ 520021f6537SMarc Zyngier if (gic_populate_rdist()) 521021f6537SMarc Zyngier return; 522021f6537SMarc Zyngier 523a2c22510SSudeep Holla gic_enable_redist(true); 524021f6537SMarc Zyngier 525021f6537SMarc Zyngier rbase = gic_data_rdist_sgi_base(); 526021f6537SMarc Zyngier 5277c9b9730SMarc Zyngier /* Configure SGIs/PPIs as non-secure Group-1 */ 5287c9b9730SMarc Zyngier writel_relaxed(~0, rbase + GICR_IGROUPR0); 5297c9b9730SMarc Zyngier 530021f6537SMarc Zyngier gic_cpu_config(rbase, gic_redist_wait_for_rwp); 531021f6537SMarc Zyngier 532da33f31dSMarc Zyngier /* Give LPIs a spin */ 533da33f31dSMarc Zyngier if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis()) 534da33f31dSMarc Zyngier its_cpu_init(); 535da33f31dSMarc Zyngier 5363708d52fSSudeep Holla /* initialise system registers */ 5373708d52fSSudeep Holla gic_cpu_sys_reg_init(); 538021f6537SMarc Zyngier } 539021f6537SMarc Zyngier 540021f6537SMarc Zyngier #ifdef CONFIG_SMP 541021f6537SMarc Zyngier 5426670a6d8SRichard Cochran static int gic_starting_cpu(unsigned int cpu) 5436670a6d8SRichard Cochran { 5446670a6d8SRichard Cochran gic_cpu_init(); 5456670a6d8SRichard Cochran return 0; 5466670a6d8SRichard Cochran } 547021f6537SMarc Zyngier 548021f6537SMarc Zyngier static u16 gic_compute_target_list(int *base_cpu, const struct cpumask *mask, 549f6c86a41SJean-Philippe Brucker unsigned long cluster_id) 550021f6537SMarc Zyngier { 551727653d6SJames Morse int next_cpu, cpu = *base_cpu; 552f6c86a41SJean-Philippe Brucker unsigned long mpidr = cpu_logical_map(cpu); 553021f6537SMarc Zyngier u16 tlist = 0; 554021f6537SMarc Zyngier 555021f6537SMarc Zyngier while (cpu < nr_cpu_ids) { 556021f6537SMarc Zyngier /* 557021f6537SMarc Zyngier * If we ever get a cluster of more than 16 CPUs, just 558021f6537SMarc Zyngier * scream and skip that CPU. 559021f6537SMarc Zyngier */ 560021f6537SMarc Zyngier if (WARN_ON((mpidr & 0xff) >= 16)) 561021f6537SMarc Zyngier goto out; 562021f6537SMarc Zyngier 563021f6537SMarc Zyngier tlist |= 1 << (mpidr & 0xf); 564021f6537SMarc Zyngier 565727653d6SJames Morse next_cpu = cpumask_next(cpu, mask); 566727653d6SJames Morse if (next_cpu >= nr_cpu_ids) 567021f6537SMarc Zyngier goto out; 568727653d6SJames Morse cpu = next_cpu; 569021f6537SMarc Zyngier 570021f6537SMarc Zyngier mpidr = cpu_logical_map(cpu); 571021f6537SMarc Zyngier 572021f6537SMarc Zyngier if (cluster_id != (mpidr & ~0xffUL)) { 573021f6537SMarc Zyngier cpu--; 574021f6537SMarc Zyngier goto out; 575021f6537SMarc Zyngier } 576021f6537SMarc Zyngier } 577021f6537SMarc Zyngier out: 578021f6537SMarc Zyngier *base_cpu = cpu; 579021f6537SMarc Zyngier return tlist; 580021f6537SMarc Zyngier } 581021f6537SMarc Zyngier 5827e580278SAndre Przywara #define MPIDR_TO_SGI_AFFINITY(cluster_id, level) \ 5837e580278SAndre Przywara (MPIDR_AFFINITY_LEVEL(cluster_id, level) \ 5847e580278SAndre Przywara << ICC_SGI1R_AFFINITY_## level ##_SHIFT) 5857e580278SAndre Przywara 586021f6537SMarc Zyngier static void gic_send_sgi(u64 cluster_id, u16 tlist, unsigned int irq) 587021f6537SMarc Zyngier { 588021f6537SMarc Zyngier u64 val; 589021f6537SMarc Zyngier 5907e580278SAndre Przywara val = (MPIDR_TO_SGI_AFFINITY(cluster_id, 3) | 5917e580278SAndre Przywara MPIDR_TO_SGI_AFFINITY(cluster_id, 2) | 5927e580278SAndre Przywara irq << ICC_SGI1R_SGI_ID_SHIFT | 5937e580278SAndre Przywara MPIDR_TO_SGI_AFFINITY(cluster_id, 1) | 5947e580278SAndre Przywara tlist << ICC_SGI1R_TARGET_LIST_SHIFT); 595021f6537SMarc Zyngier 596021f6537SMarc Zyngier pr_debug("CPU%d: ICC_SGI1R_EL1 %llx\n", smp_processor_id(), val); 597021f6537SMarc Zyngier gic_write_sgi1r(val); 598021f6537SMarc Zyngier } 599021f6537SMarc Zyngier 600021f6537SMarc Zyngier static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) 601021f6537SMarc Zyngier { 602021f6537SMarc Zyngier int cpu; 603021f6537SMarc Zyngier 604021f6537SMarc Zyngier if (WARN_ON(irq >= 16)) 605021f6537SMarc Zyngier return; 606021f6537SMarc Zyngier 607021f6537SMarc Zyngier /* 608021f6537SMarc Zyngier * Ensure that stores to Normal memory are visible to the 609021f6537SMarc Zyngier * other CPUs before issuing the IPI. 610021f6537SMarc Zyngier */ 611021f6537SMarc Zyngier smp_wmb(); 612021f6537SMarc Zyngier 613f9b531feSRusty Russell for_each_cpu(cpu, mask) { 614f6c86a41SJean-Philippe Brucker unsigned long cluster_id = cpu_logical_map(cpu) & ~0xffUL; 615021f6537SMarc Zyngier u16 tlist; 616021f6537SMarc Zyngier 617021f6537SMarc Zyngier tlist = gic_compute_target_list(&cpu, mask, cluster_id); 618021f6537SMarc Zyngier gic_send_sgi(cluster_id, tlist, irq); 619021f6537SMarc Zyngier } 620021f6537SMarc Zyngier 621021f6537SMarc Zyngier /* Force the above writes to ICC_SGI1R_EL1 to be executed */ 622021f6537SMarc Zyngier isb(); 623021f6537SMarc Zyngier } 624021f6537SMarc Zyngier 625021f6537SMarc Zyngier static void gic_smp_init(void) 626021f6537SMarc Zyngier { 627021f6537SMarc Zyngier set_smp_cross_call(gic_raise_softirq); 6286670a6d8SRichard Cochran cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_GICV3_STARTING, 6296670a6d8SRichard Cochran "AP_IRQ_GICV3_STARTING", gic_starting_cpu, 6306670a6d8SRichard Cochran NULL); 631021f6537SMarc Zyngier } 632021f6537SMarc Zyngier 633021f6537SMarc Zyngier static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, 634021f6537SMarc Zyngier bool force) 635021f6537SMarc Zyngier { 636021f6537SMarc Zyngier unsigned int cpu = cpumask_any_and(mask_val, cpu_online_mask); 637021f6537SMarc Zyngier void __iomem *reg; 638021f6537SMarc Zyngier int enabled; 639021f6537SMarc Zyngier u64 val; 640021f6537SMarc Zyngier 641021f6537SMarc Zyngier if (gic_irq_in_rdist(d)) 642021f6537SMarc Zyngier return -EINVAL; 643021f6537SMarc Zyngier 644021f6537SMarc Zyngier /* If interrupt was enabled, disable it first */ 645021f6537SMarc Zyngier enabled = gic_peek_irq(d, GICD_ISENABLER); 646021f6537SMarc Zyngier if (enabled) 647021f6537SMarc Zyngier gic_mask_irq(d); 648021f6537SMarc Zyngier 649021f6537SMarc Zyngier reg = gic_dist_base(d) + GICD_IROUTER + (gic_irq(d) * 8); 650021f6537SMarc Zyngier val = gic_mpidr_to_affinity(cpu_logical_map(cpu)); 651021f6537SMarc Zyngier 65272c97126SJean-Philippe Brucker gic_write_irouter(val, reg); 653021f6537SMarc Zyngier 654021f6537SMarc Zyngier /* 655021f6537SMarc Zyngier * If the interrupt was enabled, enabled it again. Otherwise, 656021f6537SMarc Zyngier * just wait for the distributor to have digested our changes. 657021f6537SMarc Zyngier */ 658021f6537SMarc Zyngier if (enabled) 659021f6537SMarc Zyngier gic_unmask_irq(d); 660021f6537SMarc Zyngier else 661021f6537SMarc Zyngier gic_dist_wait_for_rwp(); 662021f6537SMarc Zyngier 6630fc6fa29SAntoine Tenart return IRQ_SET_MASK_OK_DONE; 664021f6537SMarc Zyngier } 665021f6537SMarc Zyngier #else 666021f6537SMarc Zyngier #define gic_set_affinity NULL 667021f6537SMarc Zyngier #define gic_smp_init() do { } while(0) 668021f6537SMarc Zyngier #endif 669021f6537SMarc Zyngier 6703708d52fSSudeep Holla #ifdef CONFIG_CPU_PM 671ccd9432aSSudeep Holla /* Check whether it's single security state view */ 672ccd9432aSSudeep Holla static bool gic_dist_security_disabled(void) 673ccd9432aSSudeep Holla { 674ccd9432aSSudeep Holla return readl_relaxed(gic_data.dist_base + GICD_CTLR) & GICD_CTLR_DS; 675ccd9432aSSudeep Holla } 676ccd9432aSSudeep Holla 6773708d52fSSudeep Holla static int gic_cpu_pm_notifier(struct notifier_block *self, 6783708d52fSSudeep Holla unsigned long cmd, void *v) 6793708d52fSSudeep Holla { 6803708d52fSSudeep Holla if (cmd == CPU_PM_EXIT) { 681ccd9432aSSudeep Holla if (gic_dist_security_disabled()) 6823708d52fSSudeep Holla gic_enable_redist(true); 6833708d52fSSudeep Holla gic_cpu_sys_reg_init(); 684ccd9432aSSudeep Holla } else if (cmd == CPU_PM_ENTER && gic_dist_security_disabled()) { 6853708d52fSSudeep Holla gic_write_grpen1(0); 6863708d52fSSudeep Holla gic_enable_redist(false); 6873708d52fSSudeep Holla } 6883708d52fSSudeep Holla return NOTIFY_OK; 6893708d52fSSudeep Holla } 6903708d52fSSudeep Holla 6913708d52fSSudeep Holla static struct notifier_block gic_cpu_pm_notifier_block = { 6923708d52fSSudeep Holla .notifier_call = gic_cpu_pm_notifier, 6933708d52fSSudeep Holla }; 6943708d52fSSudeep Holla 6953708d52fSSudeep Holla static void gic_cpu_pm_init(void) 6963708d52fSSudeep Holla { 6973708d52fSSudeep Holla cpu_pm_register_notifier(&gic_cpu_pm_notifier_block); 6983708d52fSSudeep Holla } 6993708d52fSSudeep Holla 7003708d52fSSudeep Holla #else 7013708d52fSSudeep Holla static inline void gic_cpu_pm_init(void) { } 7023708d52fSSudeep Holla #endif /* CONFIG_CPU_PM */ 7033708d52fSSudeep Holla 704021f6537SMarc Zyngier static struct irq_chip gic_chip = { 705021f6537SMarc Zyngier .name = "GICv3", 706021f6537SMarc Zyngier .irq_mask = gic_mask_irq, 707021f6537SMarc Zyngier .irq_unmask = gic_unmask_irq, 708021f6537SMarc Zyngier .irq_eoi = gic_eoi_irq, 709021f6537SMarc Zyngier .irq_set_type = gic_set_type, 710021f6537SMarc Zyngier .irq_set_affinity = gic_set_affinity, 711b594c6e2SMarc Zyngier .irq_get_irqchip_state = gic_irq_get_irqchip_state, 712b594c6e2SMarc Zyngier .irq_set_irqchip_state = gic_irq_set_irqchip_state, 71355963c9fSSudeep Holla .flags = IRQCHIP_SET_TYPE_MASKED, 714021f6537SMarc Zyngier }; 715021f6537SMarc Zyngier 7160b6a3da9SMarc Zyngier static struct irq_chip gic_eoimode1_chip = { 7170b6a3da9SMarc Zyngier .name = "GICv3", 7180b6a3da9SMarc Zyngier .irq_mask = gic_eoimode1_mask_irq, 7190b6a3da9SMarc Zyngier .irq_unmask = gic_unmask_irq, 7200b6a3da9SMarc Zyngier .irq_eoi = gic_eoimode1_eoi_irq, 7210b6a3da9SMarc Zyngier .irq_set_type = gic_set_type, 7220b6a3da9SMarc Zyngier .irq_set_affinity = gic_set_affinity, 7230b6a3da9SMarc Zyngier .irq_get_irqchip_state = gic_irq_get_irqchip_state, 7240b6a3da9SMarc Zyngier .irq_set_irqchip_state = gic_irq_set_irqchip_state, 725530bf353SMarc Zyngier .irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity, 7260b6a3da9SMarc Zyngier .flags = IRQCHIP_SET_TYPE_MASKED, 7270b6a3da9SMarc Zyngier }; 7280b6a3da9SMarc Zyngier 729da33f31dSMarc Zyngier #define GIC_ID_NR (1U << gic_data.rdists.id_bits) 730da33f31dSMarc Zyngier 731021f6537SMarc Zyngier static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq, 732021f6537SMarc Zyngier irq_hw_number_t hw) 733021f6537SMarc Zyngier { 7340b6a3da9SMarc Zyngier struct irq_chip *chip = &gic_chip; 7350b6a3da9SMarc Zyngier 7360b6a3da9SMarc Zyngier if (static_key_true(&supports_deactivate)) 7370b6a3da9SMarc Zyngier chip = &gic_eoimode1_chip; 7380b6a3da9SMarc Zyngier 739021f6537SMarc Zyngier /* SGIs are private to the core kernel */ 740021f6537SMarc Zyngier if (hw < 16) 741021f6537SMarc Zyngier return -EPERM; 742da33f31dSMarc Zyngier /* Nothing here */ 743da33f31dSMarc Zyngier if (hw >= gic_data.irq_nr && hw < 8192) 744da33f31dSMarc Zyngier return -EPERM; 745da33f31dSMarc Zyngier /* Off limits */ 746da33f31dSMarc Zyngier if (hw >= GIC_ID_NR) 747da33f31dSMarc Zyngier return -EPERM; 748da33f31dSMarc Zyngier 749021f6537SMarc Zyngier /* PPIs */ 750021f6537SMarc Zyngier if (hw < 32) { 751021f6537SMarc Zyngier irq_set_percpu_devid(irq); 7520b6a3da9SMarc Zyngier irq_domain_set_info(d, irq, hw, chip, d->host_data, 753443acc4fSMarc Zyngier handle_percpu_devid_irq, NULL, NULL); 754d17cab44SRob Herring irq_set_status_flags(irq, IRQ_NOAUTOEN); 755021f6537SMarc Zyngier } 756021f6537SMarc Zyngier /* SPIs */ 757021f6537SMarc Zyngier if (hw >= 32 && hw < gic_data.irq_nr) { 7580b6a3da9SMarc Zyngier irq_domain_set_info(d, irq, hw, chip, d->host_data, 759443acc4fSMarc Zyngier handle_fasteoi_irq, NULL, NULL); 760d17cab44SRob Herring irq_set_probe(irq); 761021f6537SMarc Zyngier } 762da33f31dSMarc Zyngier /* LPIs */ 763da33f31dSMarc Zyngier if (hw >= 8192 && hw < GIC_ID_NR) { 764da33f31dSMarc Zyngier if (!gic_dist_supports_lpis()) 765da33f31dSMarc Zyngier return -EPERM; 7660b6a3da9SMarc Zyngier irq_domain_set_info(d, irq, hw, chip, d->host_data, 767da33f31dSMarc Zyngier handle_fasteoi_irq, NULL, NULL); 768da33f31dSMarc Zyngier } 769da33f31dSMarc Zyngier 770021f6537SMarc Zyngier return 0; 771021f6537SMarc Zyngier } 772021f6537SMarc Zyngier 773f833f57fSMarc Zyngier static int gic_irq_domain_translate(struct irq_domain *d, 774f833f57fSMarc Zyngier struct irq_fwspec *fwspec, 775f833f57fSMarc Zyngier unsigned long *hwirq, 776f833f57fSMarc Zyngier unsigned int *type) 777021f6537SMarc Zyngier { 778f833f57fSMarc Zyngier if (is_of_node(fwspec->fwnode)) { 779f833f57fSMarc Zyngier if (fwspec->param_count < 3) 780021f6537SMarc Zyngier return -EINVAL; 781021f6537SMarc Zyngier 782db8c70ecSMarc Zyngier switch (fwspec->param[0]) { 783db8c70ecSMarc Zyngier case 0: /* SPI */ 784db8c70ecSMarc Zyngier *hwirq = fwspec->param[1] + 32; 785db8c70ecSMarc Zyngier break; 786db8c70ecSMarc Zyngier case 1: /* PPI */ 787f833f57fSMarc Zyngier *hwirq = fwspec->param[1] + 16; 788db8c70ecSMarc Zyngier break; 789db8c70ecSMarc Zyngier case GIC_IRQ_TYPE_LPI: /* LPI */ 790db8c70ecSMarc Zyngier *hwirq = fwspec->param[1]; 791db8c70ecSMarc Zyngier break; 792db8c70ecSMarc Zyngier default: 793db8c70ecSMarc Zyngier return -EINVAL; 794db8c70ecSMarc Zyngier } 795f833f57fSMarc Zyngier 796f833f57fSMarc Zyngier *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; 797f833f57fSMarc Zyngier return 0; 798021f6537SMarc Zyngier } 799021f6537SMarc Zyngier 800ffa7d616STomasz Nowicki if (is_fwnode_irqchip(fwspec->fwnode)) { 801ffa7d616STomasz Nowicki if(fwspec->param_count != 2) 802ffa7d616STomasz Nowicki return -EINVAL; 803ffa7d616STomasz Nowicki 804ffa7d616STomasz Nowicki *hwirq = fwspec->param[0]; 805ffa7d616STomasz Nowicki *type = fwspec->param[1]; 806ffa7d616STomasz Nowicki return 0; 807ffa7d616STomasz Nowicki } 808ffa7d616STomasz Nowicki 809f833f57fSMarc Zyngier return -EINVAL; 810021f6537SMarc Zyngier } 811021f6537SMarc Zyngier 812443acc4fSMarc Zyngier static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, 813443acc4fSMarc Zyngier unsigned int nr_irqs, void *arg) 814443acc4fSMarc Zyngier { 815443acc4fSMarc Zyngier int i, ret; 816443acc4fSMarc Zyngier irq_hw_number_t hwirq; 817443acc4fSMarc Zyngier unsigned int type = IRQ_TYPE_NONE; 818f833f57fSMarc Zyngier struct irq_fwspec *fwspec = arg; 819443acc4fSMarc Zyngier 820f833f57fSMarc Zyngier ret = gic_irq_domain_translate(domain, fwspec, &hwirq, &type); 821443acc4fSMarc Zyngier if (ret) 822443acc4fSMarc Zyngier return ret; 823443acc4fSMarc Zyngier 824443acc4fSMarc Zyngier for (i = 0; i < nr_irqs; i++) 825443acc4fSMarc Zyngier gic_irq_domain_map(domain, virq + i, hwirq + i); 826443acc4fSMarc Zyngier 827443acc4fSMarc Zyngier return 0; 828443acc4fSMarc Zyngier } 829443acc4fSMarc Zyngier 830443acc4fSMarc Zyngier static void gic_irq_domain_free(struct irq_domain *domain, unsigned int virq, 831443acc4fSMarc Zyngier unsigned int nr_irqs) 832443acc4fSMarc Zyngier { 833443acc4fSMarc Zyngier int i; 834443acc4fSMarc Zyngier 835443acc4fSMarc Zyngier for (i = 0; i < nr_irqs; i++) { 836443acc4fSMarc Zyngier struct irq_data *d = irq_domain_get_irq_data(domain, virq + i); 837443acc4fSMarc Zyngier irq_set_handler(virq + i, NULL); 838443acc4fSMarc Zyngier irq_domain_reset_irq_data(d); 839443acc4fSMarc Zyngier } 840443acc4fSMarc Zyngier } 841443acc4fSMarc Zyngier 842e3825ba1SMarc Zyngier static int gic_irq_domain_select(struct irq_domain *d, 843e3825ba1SMarc Zyngier struct irq_fwspec *fwspec, 844e3825ba1SMarc Zyngier enum irq_domain_bus_token bus_token) 845e3825ba1SMarc Zyngier { 846e3825ba1SMarc Zyngier /* Not for us */ 847e3825ba1SMarc Zyngier if (fwspec->fwnode != d->fwnode) 848e3825ba1SMarc Zyngier return 0; 849e3825ba1SMarc Zyngier 850e3825ba1SMarc Zyngier /* If this is not DT, then we have a single domain */ 851e3825ba1SMarc Zyngier if (!is_of_node(fwspec->fwnode)) 852e3825ba1SMarc Zyngier return 1; 853e3825ba1SMarc Zyngier 854e3825ba1SMarc Zyngier /* 855e3825ba1SMarc Zyngier * If this is a PPI and we have a 4th (non-null) parameter, 856e3825ba1SMarc Zyngier * then we need to match the partition domain. 857e3825ba1SMarc Zyngier */ 858e3825ba1SMarc Zyngier if (fwspec->param_count >= 4 && 859e3825ba1SMarc Zyngier fwspec->param[0] == 1 && fwspec->param[3] != 0) 860e3825ba1SMarc Zyngier return d == partition_get_domain(gic_data.ppi_descs[fwspec->param[1]]); 861e3825ba1SMarc Zyngier 862e3825ba1SMarc Zyngier return d == gic_data.domain; 863e3825ba1SMarc Zyngier } 864e3825ba1SMarc Zyngier 865021f6537SMarc Zyngier static const struct irq_domain_ops gic_irq_domain_ops = { 866f833f57fSMarc Zyngier .translate = gic_irq_domain_translate, 867443acc4fSMarc Zyngier .alloc = gic_irq_domain_alloc, 868443acc4fSMarc Zyngier .free = gic_irq_domain_free, 869e3825ba1SMarc Zyngier .select = gic_irq_domain_select, 870e3825ba1SMarc Zyngier }; 871e3825ba1SMarc Zyngier 872e3825ba1SMarc Zyngier static int partition_domain_translate(struct irq_domain *d, 873e3825ba1SMarc Zyngier struct irq_fwspec *fwspec, 874e3825ba1SMarc Zyngier unsigned long *hwirq, 875e3825ba1SMarc Zyngier unsigned int *type) 876e3825ba1SMarc Zyngier { 877e3825ba1SMarc Zyngier struct device_node *np; 878e3825ba1SMarc Zyngier int ret; 879e3825ba1SMarc Zyngier 880e3825ba1SMarc Zyngier np = of_find_node_by_phandle(fwspec->param[3]); 881e3825ba1SMarc Zyngier if (WARN_ON(!np)) 882e3825ba1SMarc Zyngier return -EINVAL; 883e3825ba1SMarc Zyngier 884e3825ba1SMarc Zyngier ret = partition_translate_id(gic_data.ppi_descs[fwspec->param[1]], 885e3825ba1SMarc Zyngier of_node_to_fwnode(np)); 886e3825ba1SMarc Zyngier if (ret < 0) 887e3825ba1SMarc Zyngier return ret; 888e3825ba1SMarc Zyngier 889e3825ba1SMarc Zyngier *hwirq = ret; 890e3825ba1SMarc Zyngier *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; 891e3825ba1SMarc Zyngier 892e3825ba1SMarc Zyngier return 0; 893e3825ba1SMarc Zyngier } 894e3825ba1SMarc Zyngier 895e3825ba1SMarc Zyngier static const struct irq_domain_ops partition_domain_ops = { 896e3825ba1SMarc Zyngier .translate = partition_domain_translate, 897e3825ba1SMarc Zyngier .select = gic_irq_domain_select, 898021f6537SMarc Zyngier }; 899021f6537SMarc Zyngier 9006d4e11c5SRobert Richter static void gicv3_enable_quirks(void) 9016d4e11c5SRobert Richter { 9027936e914SJean-Philippe Brucker #ifdef CONFIG_ARM64 9036d4e11c5SRobert Richter if (cpus_have_cap(ARM64_WORKAROUND_CAVIUM_23154)) 9048ac2a170SRobert Richter static_branch_enable(&is_cavium_thunderx); 9057936e914SJean-Philippe Brucker #endif 9066d4e11c5SRobert Richter } 9076d4e11c5SRobert Richter 908db57d746STomasz Nowicki static int __init gic_init_bases(void __iomem *dist_base, 909db57d746STomasz Nowicki struct redist_region *rdist_regs, 910db57d746STomasz Nowicki u32 nr_redist_regions, 911db57d746STomasz Nowicki u64 redist_stride, 912db57d746STomasz Nowicki struct fwnode_handle *handle) 913db57d746STomasz Nowicki { 914db57d746STomasz Nowicki struct device_node *node; 915db57d746STomasz Nowicki u32 typer; 916db57d746STomasz Nowicki int gic_irqs; 917db57d746STomasz Nowicki int err; 918db57d746STomasz Nowicki 919db57d746STomasz Nowicki if (!is_hyp_mode_available()) 920db57d746STomasz Nowicki static_key_slow_dec(&supports_deactivate); 921db57d746STomasz Nowicki 922db57d746STomasz Nowicki if (static_key_true(&supports_deactivate)) 923db57d746STomasz Nowicki pr_info("GIC: Using split EOI/Deactivate mode\n"); 924db57d746STomasz Nowicki 925e3825ba1SMarc Zyngier gic_data.fwnode = handle; 926db57d746STomasz Nowicki gic_data.dist_base = dist_base; 927db57d746STomasz Nowicki gic_data.redist_regions = rdist_regs; 928db57d746STomasz Nowicki gic_data.nr_redist_regions = nr_redist_regions; 929db57d746STomasz Nowicki gic_data.redist_stride = redist_stride; 930db57d746STomasz Nowicki 931db57d746STomasz Nowicki gicv3_enable_quirks(); 932db57d746STomasz Nowicki 933db57d746STomasz Nowicki /* 934db57d746STomasz Nowicki * Find out how many interrupts are supported. 935db57d746STomasz Nowicki * The GIC only supports up to 1020 interrupt sources (SGI+PPI+SPI) 936db57d746STomasz Nowicki */ 937db57d746STomasz Nowicki typer = readl_relaxed(gic_data.dist_base + GICD_TYPER); 938db57d746STomasz Nowicki gic_data.rdists.id_bits = GICD_TYPER_ID_BITS(typer); 939db57d746STomasz Nowicki gic_irqs = GICD_TYPER_IRQS(typer); 940db57d746STomasz Nowicki if (gic_irqs > 1020) 941db57d746STomasz Nowicki gic_irqs = 1020; 942db57d746STomasz Nowicki gic_data.irq_nr = gic_irqs; 943db57d746STomasz Nowicki 944db57d746STomasz Nowicki gic_data.domain = irq_domain_create_tree(handle, &gic_irq_domain_ops, 945db57d746STomasz Nowicki &gic_data); 946db57d746STomasz Nowicki gic_data.rdists.rdist = alloc_percpu(typeof(*gic_data.rdists.rdist)); 947db57d746STomasz Nowicki 948db57d746STomasz Nowicki if (WARN_ON(!gic_data.domain) || WARN_ON(!gic_data.rdists.rdist)) { 949db57d746STomasz Nowicki err = -ENOMEM; 950db57d746STomasz Nowicki goto out_free; 951db57d746STomasz Nowicki } 952db57d746STomasz Nowicki 953db57d746STomasz Nowicki set_handle_irq(gic_handle_irq); 954db57d746STomasz Nowicki 955db57d746STomasz Nowicki node = to_of_node(handle); 956db57d746STomasz Nowicki if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis() && 957db57d746STomasz Nowicki node) /* Temp hack to prevent ITS init for ACPI */ 958db57d746STomasz Nowicki its_init(node, &gic_data.rdists, gic_data.domain); 959db57d746STomasz Nowicki 960db57d746STomasz Nowicki gic_smp_init(); 961db57d746STomasz Nowicki gic_dist_init(); 962db57d746STomasz Nowicki gic_cpu_init(); 963db57d746STomasz Nowicki gic_cpu_pm_init(); 964db57d746STomasz Nowicki 965db57d746STomasz Nowicki return 0; 966db57d746STomasz Nowicki 967db57d746STomasz Nowicki out_free: 968db57d746STomasz Nowicki if (gic_data.domain) 969db57d746STomasz Nowicki irq_domain_remove(gic_data.domain); 970db57d746STomasz Nowicki free_percpu(gic_data.rdists.rdist); 971db57d746STomasz Nowicki return err; 972db57d746STomasz Nowicki } 973db57d746STomasz Nowicki 974db57d746STomasz Nowicki static int __init gic_validate_dist_version(void __iomem *dist_base) 975db57d746STomasz Nowicki { 976db57d746STomasz Nowicki u32 reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK; 977db57d746STomasz Nowicki 978db57d746STomasz Nowicki if (reg != GIC_PIDR2_ARCH_GICv3 && reg != GIC_PIDR2_ARCH_GICv4) 979db57d746STomasz Nowicki return -ENODEV; 980db57d746STomasz Nowicki 981db57d746STomasz Nowicki return 0; 982db57d746STomasz Nowicki } 983db57d746STomasz Nowicki 984e3825ba1SMarc Zyngier static int get_cpu_number(struct device_node *dn) 985e3825ba1SMarc Zyngier { 986e3825ba1SMarc Zyngier const __be32 *cell; 987e3825ba1SMarc Zyngier u64 hwid; 988e3825ba1SMarc Zyngier int i; 989e3825ba1SMarc Zyngier 990e3825ba1SMarc Zyngier cell = of_get_property(dn, "reg", NULL); 991e3825ba1SMarc Zyngier if (!cell) 992e3825ba1SMarc Zyngier return -1; 993e3825ba1SMarc Zyngier 994e3825ba1SMarc Zyngier hwid = of_read_number(cell, of_n_addr_cells(dn)); 995e3825ba1SMarc Zyngier 996e3825ba1SMarc Zyngier /* 997e3825ba1SMarc Zyngier * Non affinity bits must be set to 0 in the DT 998e3825ba1SMarc Zyngier */ 999e3825ba1SMarc Zyngier if (hwid & ~MPIDR_HWID_BITMASK) 1000e3825ba1SMarc Zyngier return -1; 1001e3825ba1SMarc Zyngier 1002e3825ba1SMarc Zyngier for (i = 0; i < num_possible_cpus(); i++) 1003e3825ba1SMarc Zyngier if (cpu_logical_map(i) == hwid) 1004e3825ba1SMarc Zyngier return i; 1005e3825ba1SMarc Zyngier 1006e3825ba1SMarc Zyngier return -1; 1007e3825ba1SMarc Zyngier } 1008e3825ba1SMarc Zyngier 1009e3825ba1SMarc Zyngier /* Create all possible partitions at boot time */ 10107beaa24bSLinus Torvalds static void __init gic_populate_ppi_partitions(struct device_node *gic_node) 1011e3825ba1SMarc Zyngier { 1012e3825ba1SMarc Zyngier struct device_node *parts_node, *child_part; 1013e3825ba1SMarc Zyngier int part_idx = 0, i; 1014e3825ba1SMarc Zyngier int nr_parts; 1015e3825ba1SMarc Zyngier struct partition_affinity *parts; 1016e3825ba1SMarc Zyngier 1017e3825ba1SMarc Zyngier parts_node = of_find_node_by_name(gic_node, "ppi-partitions"); 1018e3825ba1SMarc Zyngier if (!parts_node) 1019e3825ba1SMarc Zyngier return; 1020e3825ba1SMarc Zyngier 1021e3825ba1SMarc Zyngier nr_parts = of_get_child_count(parts_node); 1022e3825ba1SMarc Zyngier 1023e3825ba1SMarc Zyngier if (!nr_parts) 1024e3825ba1SMarc Zyngier return; 1025e3825ba1SMarc Zyngier 1026e3825ba1SMarc Zyngier parts = kzalloc(sizeof(*parts) * nr_parts, GFP_KERNEL); 1027e3825ba1SMarc Zyngier if (WARN_ON(!parts)) 1028e3825ba1SMarc Zyngier return; 1029e3825ba1SMarc Zyngier 1030e3825ba1SMarc Zyngier for_each_child_of_node(parts_node, child_part) { 1031e3825ba1SMarc Zyngier struct partition_affinity *part; 1032e3825ba1SMarc Zyngier int n; 1033e3825ba1SMarc Zyngier 1034e3825ba1SMarc Zyngier part = &parts[part_idx]; 1035e3825ba1SMarc Zyngier 1036e3825ba1SMarc Zyngier part->partition_id = of_node_to_fwnode(child_part); 1037e3825ba1SMarc Zyngier 1038e3825ba1SMarc Zyngier pr_info("GIC: PPI partition %s[%d] { ", 1039e3825ba1SMarc Zyngier child_part->name, part_idx); 1040e3825ba1SMarc Zyngier 1041e3825ba1SMarc Zyngier n = of_property_count_elems_of_size(child_part, "affinity", 1042e3825ba1SMarc Zyngier sizeof(u32)); 1043e3825ba1SMarc Zyngier WARN_ON(n <= 0); 1044e3825ba1SMarc Zyngier 1045e3825ba1SMarc Zyngier for (i = 0; i < n; i++) { 1046e3825ba1SMarc Zyngier int err, cpu; 1047e3825ba1SMarc Zyngier u32 cpu_phandle; 1048e3825ba1SMarc Zyngier struct device_node *cpu_node; 1049e3825ba1SMarc Zyngier 1050e3825ba1SMarc Zyngier err = of_property_read_u32_index(child_part, "affinity", 1051e3825ba1SMarc Zyngier i, &cpu_phandle); 1052e3825ba1SMarc Zyngier if (WARN_ON(err)) 1053e3825ba1SMarc Zyngier continue; 1054e3825ba1SMarc Zyngier 1055e3825ba1SMarc Zyngier cpu_node = of_find_node_by_phandle(cpu_phandle); 1056e3825ba1SMarc Zyngier if (WARN_ON(!cpu_node)) 1057e3825ba1SMarc Zyngier continue; 1058e3825ba1SMarc Zyngier 1059e3825ba1SMarc Zyngier cpu = get_cpu_number(cpu_node); 1060e3825ba1SMarc Zyngier if (WARN_ON(cpu == -1)) 1061e3825ba1SMarc Zyngier continue; 1062e3825ba1SMarc Zyngier 1063e3825ba1SMarc Zyngier pr_cont("%s[%d] ", cpu_node->full_name, cpu); 1064e3825ba1SMarc Zyngier 1065e3825ba1SMarc Zyngier cpumask_set_cpu(cpu, &part->mask); 1066e3825ba1SMarc Zyngier } 1067e3825ba1SMarc Zyngier 1068e3825ba1SMarc Zyngier pr_cont("}\n"); 1069e3825ba1SMarc Zyngier part_idx++; 1070e3825ba1SMarc Zyngier } 1071e3825ba1SMarc Zyngier 1072e3825ba1SMarc Zyngier for (i = 0; i < 16; i++) { 1073e3825ba1SMarc Zyngier unsigned int irq; 1074e3825ba1SMarc Zyngier struct partition_desc *desc; 1075e3825ba1SMarc Zyngier struct irq_fwspec ppi_fwspec = { 1076e3825ba1SMarc Zyngier .fwnode = gic_data.fwnode, 1077e3825ba1SMarc Zyngier .param_count = 3, 1078e3825ba1SMarc Zyngier .param = { 1079e3825ba1SMarc Zyngier [0] = 1, 1080e3825ba1SMarc Zyngier [1] = i, 1081e3825ba1SMarc Zyngier [2] = IRQ_TYPE_NONE, 1082e3825ba1SMarc Zyngier }, 1083e3825ba1SMarc Zyngier }; 1084e3825ba1SMarc Zyngier 1085e3825ba1SMarc Zyngier irq = irq_create_fwspec_mapping(&ppi_fwspec); 1086e3825ba1SMarc Zyngier if (WARN_ON(!irq)) 1087e3825ba1SMarc Zyngier continue; 1088e3825ba1SMarc Zyngier desc = partition_create_desc(gic_data.fwnode, parts, nr_parts, 1089e3825ba1SMarc Zyngier irq, &partition_domain_ops); 1090e3825ba1SMarc Zyngier if (WARN_ON(!desc)) 1091e3825ba1SMarc Zyngier continue; 1092e3825ba1SMarc Zyngier 1093e3825ba1SMarc Zyngier gic_data.ppi_descs[i] = desc; 1094e3825ba1SMarc Zyngier } 1095e3825ba1SMarc Zyngier } 1096e3825ba1SMarc Zyngier 10971839e576SJulien Grall static void __init gic_of_setup_kvm_info(struct device_node *node) 10981839e576SJulien Grall { 10991839e576SJulien Grall int ret; 11001839e576SJulien Grall struct resource r; 11011839e576SJulien Grall u32 gicv_idx; 11021839e576SJulien Grall 11031839e576SJulien Grall gic_v3_kvm_info.type = GIC_V3; 11041839e576SJulien Grall 11051839e576SJulien Grall gic_v3_kvm_info.maint_irq = irq_of_parse_and_map(node, 0); 11061839e576SJulien Grall if (!gic_v3_kvm_info.maint_irq) 11071839e576SJulien Grall return; 11081839e576SJulien Grall 11091839e576SJulien Grall if (of_property_read_u32(node, "#redistributor-regions", 11101839e576SJulien Grall &gicv_idx)) 11111839e576SJulien Grall gicv_idx = 1; 11121839e576SJulien Grall 11131839e576SJulien Grall gicv_idx += 3; /* Also skip GICD, GICC, GICH */ 11141839e576SJulien Grall ret = of_address_to_resource(node, gicv_idx, &r); 11151839e576SJulien Grall if (!ret) 11161839e576SJulien Grall gic_v3_kvm_info.vcpu = r; 11171839e576SJulien Grall 11181839e576SJulien Grall gic_set_kvm_info(&gic_v3_kvm_info); 11191839e576SJulien Grall } 11201839e576SJulien Grall 1121021f6537SMarc Zyngier static int __init gic_of_init(struct device_node *node, struct device_node *parent) 1122021f6537SMarc Zyngier { 1123021f6537SMarc Zyngier void __iomem *dist_base; 1124f5c1434cSMarc Zyngier struct redist_region *rdist_regs; 1125021f6537SMarc Zyngier u64 redist_stride; 1126f5c1434cSMarc Zyngier u32 nr_redist_regions; 1127db57d746STomasz Nowicki int err, i; 1128021f6537SMarc Zyngier 1129021f6537SMarc Zyngier dist_base = of_iomap(node, 0); 1130021f6537SMarc Zyngier if (!dist_base) { 1131021f6537SMarc Zyngier pr_err("%s: unable to map gic dist registers\n", 1132021f6537SMarc Zyngier node->full_name); 1133021f6537SMarc Zyngier return -ENXIO; 1134021f6537SMarc Zyngier } 1135021f6537SMarc Zyngier 1136db57d746STomasz Nowicki err = gic_validate_dist_version(dist_base); 1137db57d746STomasz Nowicki if (err) { 1138021f6537SMarc Zyngier pr_err("%s: no distributor detected, giving up\n", 1139021f6537SMarc Zyngier node->full_name); 1140021f6537SMarc Zyngier goto out_unmap_dist; 1141021f6537SMarc Zyngier } 1142021f6537SMarc Zyngier 1143f5c1434cSMarc Zyngier if (of_property_read_u32(node, "#redistributor-regions", &nr_redist_regions)) 1144f5c1434cSMarc Zyngier nr_redist_regions = 1; 1145021f6537SMarc Zyngier 1146f5c1434cSMarc Zyngier rdist_regs = kzalloc(sizeof(*rdist_regs) * nr_redist_regions, GFP_KERNEL); 1147f5c1434cSMarc Zyngier if (!rdist_regs) { 1148021f6537SMarc Zyngier err = -ENOMEM; 1149021f6537SMarc Zyngier goto out_unmap_dist; 1150021f6537SMarc Zyngier } 1151021f6537SMarc Zyngier 1152f5c1434cSMarc Zyngier for (i = 0; i < nr_redist_regions; i++) { 1153f5c1434cSMarc Zyngier struct resource res; 1154f5c1434cSMarc Zyngier int ret; 1155f5c1434cSMarc Zyngier 1156f5c1434cSMarc Zyngier ret = of_address_to_resource(node, 1 + i, &res); 1157f5c1434cSMarc Zyngier rdist_regs[i].redist_base = of_iomap(node, 1 + i); 1158f5c1434cSMarc Zyngier if (ret || !rdist_regs[i].redist_base) { 1159021f6537SMarc Zyngier pr_err("%s: couldn't map region %d\n", 1160021f6537SMarc Zyngier node->full_name, i); 1161021f6537SMarc Zyngier err = -ENODEV; 1162021f6537SMarc Zyngier goto out_unmap_rdist; 1163021f6537SMarc Zyngier } 1164f5c1434cSMarc Zyngier rdist_regs[i].phys_base = res.start; 1165021f6537SMarc Zyngier } 1166021f6537SMarc Zyngier 1167021f6537SMarc Zyngier if (of_property_read_u64(node, "redistributor-stride", &redist_stride)) 1168021f6537SMarc Zyngier redist_stride = 0; 1169021f6537SMarc Zyngier 1170db57d746STomasz Nowicki err = gic_init_bases(dist_base, rdist_regs, nr_redist_regions, 1171db57d746STomasz Nowicki redist_stride, &node->fwnode); 1172e3825ba1SMarc Zyngier if (err) 1173e3825ba1SMarc Zyngier goto out_unmap_rdist; 1174e3825ba1SMarc Zyngier 1175e3825ba1SMarc Zyngier gic_populate_ppi_partitions(node); 11761839e576SJulien Grall gic_of_setup_kvm_info(node); 1177021f6537SMarc Zyngier return 0; 1178021f6537SMarc Zyngier 1179021f6537SMarc Zyngier out_unmap_rdist: 1180f5c1434cSMarc Zyngier for (i = 0; i < nr_redist_regions; i++) 1181f5c1434cSMarc Zyngier if (rdist_regs[i].redist_base) 1182f5c1434cSMarc Zyngier iounmap(rdist_regs[i].redist_base); 1183f5c1434cSMarc Zyngier kfree(rdist_regs); 1184021f6537SMarc Zyngier out_unmap_dist: 1185021f6537SMarc Zyngier iounmap(dist_base); 1186021f6537SMarc Zyngier return err; 1187021f6537SMarc Zyngier } 1188021f6537SMarc Zyngier 1189021f6537SMarc Zyngier IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init); 1190ffa7d616STomasz Nowicki 1191ffa7d616STomasz Nowicki #ifdef CONFIG_ACPI 1192611f039fSJulien Grall static struct 1193611f039fSJulien Grall { 1194611f039fSJulien Grall void __iomem *dist_base; 1195611f039fSJulien Grall struct redist_region *redist_regs; 1196611f039fSJulien Grall u32 nr_redist_regions; 1197611f039fSJulien Grall bool single_redist; 11981839e576SJulien Grall u32 maint_irq; 11991839e576SJulien Grall int maint_irq_mode; 12001839e576SJulien Grall phys_addr_t vcpu_base; 1201611f039fSJulien Grall } acpi_data __initdata; 1202b70fb7afSTomasz Nowicki 1203b70fb7afSTomasz Nowicki static void __init 1204b70fb7afSTomasz Nowicki gic_acpi_register_redist(phys_addr_t phys_base, void __iomem *redist_base) 1205b70fb7afSTomasz Nowicki { 1206b70fb7afSTomasz Nowicki static int count = 0; 1207b70fb7afSTomasz Nowicki 1208611f039fSJulien Grall acpi_data.redist_regs[count].phys_base = phys_base; 1209611f039fSJulien Grall acpi_data.redist_regs[count].redist_base = redist_base; 1210611f039fSJulien Grall acpi_data.redist_regs[count].single_redist = acpi_data.single_redist; 1211b70fb7afSTomasz Nowicki count++; 1212b70fb7afSTomasz Nowicki } 1213ffa7d616STomasz Nowicki 1214ffa7d616STomasz Nowicki static int __init 1215ffa7d616STomasz Nowicki gic_acpi_parse_madt_redist(struct acpi_subtable_header *header, 1216ffa7d616STomasz Nowicki const unsigned long end) 1217ffa7d616STomasz Nowicki { 1218ffa7d616STomasz Nowicki struct acpi_madt_generic_redistributor *redist = 1219ffa7d616STomasz Nowicki (struct acpi_madt_generic_redistributor *)header; 1220ffa7d616STomasz Nowicki void __iomem *redist_base; 1221ffa7d616STomasz Nowicki 1222ffa7d616STomasz Nowicki redist_base = ioremap(redist->base_address, redist->length); 1223ffa7d616STomasz Nowicki if (!redist_base) { 1224ffa7d616STomasz Nowicki pr_err("Couldn't map GICR region @%llx\n", redist->base_address); 1225ffa7d616STomasz Nowicki return -ENOMEM; 1226ffa7d616STomasz Nowicki } 1227ffa7d616STomasz Nowicki 1228b70fb7afSTomasz Nowicki gic_acpi_register_redist(redist->base_address, redist_base); 1229ffa7d616STomasz Nowicki return 0; 1230ffa7d616STomasz Nowicki } 1231ffa7d616STomasz Nowicki 1232b70fb7afSTomasz Nowicki static int __init 1233b70fb7afSTomasz Nowicki gic_acpi_parse_madt_gicc(struct acpi_subtable_header *header, 1234b70fb7afSTomasz Nowicki const unsigned long end) 1235b70fb7afSTomasz Nowicki { 1236b70fb7afSTomasz Nowicki struct acpi_madt_generic_interrupt *gicc = 1237b70fb7afSTomasz Nowicki (struct acpi_madt_generic_interrupt *)header; 1238611f039fSJulien Grall u32 reg = readl_relaxed(acpi_data.dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK; 1239b70fb7afSTomasz Nowicki u32 size = reg == GIC_PIDR2_ARCH_GICv4 ? SZ_64K * 4 : SZ_64K * 2; 1240b70fb7afSTomasz Nowicki void __iomem *redist_base; 1241b70fb7afSTomasz Nowicki 1242b70fb7afSTomasz Nowicki redist_base = ioremap(gicc->gicr_base_address, size); 1243b70fb7afSTomasz Nowicki if (!redist_base) 1244b70fb7afSTomasz Nowicki return -ENOMEM; 1245b70fb7afSTomasz Nowicki 1246b70fb7afSTomasz Nowicki gic_acpi_register_redist(gicc->gicr_base_address, redist_base); 1247b70fb7afSTomasz Nowicki return 0; 1248b70fb7afSTomasz Nowicki } 1249b70fb7afSTomasz Nowicki 1250b70fb7afSTomasz Nowicki static int __init gic_acpi_collect_gicr_base(void) 1251b70fb7afSTomasz Nowicki { 1252b70fb7afSTomasz Nowicki acpi_tbl_entry_handler redist_parser; 1253b70fb7afSTomasz Nowicki enum acpi_madt_type type; 1254b70fb7afSTomasz Nowicki 1255611f039fSJulien Grall if (acpi_data.single_redist) { 1256b70fb7afSTomasz Nowicki type = ACPI_MADT_TYPE_GENERIC_INTERRUPT; 1257b70fb7afSTomasz Nowicki redist_parser = gic_acpi_parse_madt_gicc; 1258b70fb7afSTomasz Nowicki } else { 1259b70fb7afSTomasz Nowicki type = ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR; 1260b70fb7afSTomasz Nowicki redist_parser = gic_acpi_parse_madt_redist; 1261b70fb7afSTomasz Nowicki } 1262b70fb7afSTomasz Nowicki 1263b70fb7afSTomasz Nowicki /* Collect redistributor base addresses in GICR entries */ 1264b70fb7afSTomasz Nowicki if (acpi_table_parse_madt(type, redist_parser, 0) > 0) 1265b70fb7afSTomasz Nowicki return 0; 1266b70fb7afSTomasz Nowicki 1267b70fb7afSTomasz Nowicki pr_info("No valid GICR entries exist\n"); 1268b70fb7afSTomasz Nowicki return -ENODEV; 1269b70fb7afSTomasz Nowicki } 1270b70fb7afSTomasz Nowicki 1271ffa7d616STomasz Nowicki static int __init gic_acpi_match_gicr(struct acpi_subtable_header *header, 1272ffa7d616STomasz Nowicki const unsigned long end) 1273ffa7d616STomasz Nowicki { 1274ffa7d616STomasz Nowicki /* Subtable presence means that redist exists, that's it */ 1275ffa7d616STomasz Nowicki return 0; 1276ffa7d616STomasz Nowicki } 1277ffa7d616STomasz Nowicki 1278b70fb7afSTomasz Nowicki static int __init gic_acpi_match_gicc(struct acpi_subtable_header *header, 1279b70fb7afSTomasz Nowicki const unsigned long end) 1280b70fb7afSTomasz Nowicki { 1281b70fb7afSTomasz Nowicki struct acpi_madt_generic_interrupt *gicc = 1282b70fb7afSTomasz Nowicki (struct acpi_madt_generic_interrupt *)header; 1283b70fb7afSTomasz Nowicki 1284b70fb7afSTomasz Nowicki /* 1285b70fb7afSTomasz Nowicki * If GICC is enabled and has valid gicr base address, then it means 1286b70fb7afSTomasz Nowicki * GICR base is presented via GICC 1287b70fb7afSTomasz Nowicki */ 1288b70fb7afSTomasz Nowicki if ((gicc->flags & ACPI_MADT_ENABLED) && gicc->gicr_base_address) 1289b70fb7afSTomasz Nowicki return 0; 1290b70fb7afSTomasz Nowicki 1291b70fb7afSTomasz Nowicki return -ENODEV; 1292b70fb7afSTomasz Nowicki } 1293b70fb7afSTomasz Nowicki 1294b70fb7afSTomasz Nowicki static int __init gic_acpi_count_gicr_regions(void) 1295b70fb7afSTomasz Nowicki { 1296b70fb7afSTomasz Nowicki int count; 1297b70fb7afSTomasz Nowicki 1298b70fb7afSTomasz Nowicki /* 1299b70fb7afSTomasz Nowicki * Count how many redistributor regions we have. It is not allowed 1300b70fb7afSTomasz Nowicki * to mix redistributor description, GICR and GICC subtables have to be 1301b70fb7afSTomasz Nowicki * mutually exclusive. 1302b70fb7afSTomasz Nowicki */ 1303b70fb7afSTomasz Nowicki count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR, 1304b70fb7afSTomasz Nowicki gic_acpi_match_gicr, 0); 1305b70fb7afSTomasz Nowicki if (count > 0) { 1306611f039fSJulien Grall acpi_data.single_redist = false; 1307b70fb7afSTomasz Nowicki return count; 1308b70fb7afSTomasz Nowicki } 1309b70fb7afSTomasz Nowicki 1310b70fb7afSTomasz Nowicki count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT, 1311b70fb7afSTomasz Nowicki gic_acpi_match_gicc, 0); 1312b70fb7afSTomasz Nowicki if (count > 0) 1313611f039fSJulien Grall acpi_data.single_redist = true; 1314b70fb7afSTomasz Nowicki 1315b70fb7afSTomasz Nowicki return count; 1316b70fb7afSTomasz Nowicki } 1317b70fb7afSTomasz Nowicki 1318ffa7d616STomasz Nowicki static bool __init acpi_validate_gic_table(struct acpi_subtable_header *header, 1319ffa7d616STomasz Nowicki struct acpi_probe_entry *ape) 1320ffa7d616STomasz Nowicki { 1321ffa7d616STomasz Nowicki struct acpi_madt_generic_distributor *dist; 1322ffa7d616STomasz Nowicki int count; 1323ffa7d616STomasz Nowicki 1324ffa7d616STomasz Nowicki dist = (struct acpi_madt_generic_distributor *)header; 1325ffa7d616STomasz Nowicki if (dist->version != ape->driver_data) 1326ffa7d616STomasz Nowicki return false; 1327ffa7d616STomasz Nowicki 1328ffa7d616STomasz Nowicki /* We need to do that exercise anyway, the sooner the better */ 1329b70fb7afSTomasz Nowicki count = gic_acpi_count_gicr_regions(); 1330ffa7d616STomasz Nowicki if (count <= 0) 1331ffa7d616STomasz Nowicki return false; 1332ffa7d616STomasz Nowicki 1333611f039fSJulien Grall acpi_data.nr_redist_regions = count; 1334ffa7d616STomasz Nowicki return true; 1335ffa7d616STomasz Nowicki } 1336ffa7d616STomasz Nowicki 13371839e576SJulien Grall static int __init gic_acpi_parse_virt_madt_gicc(struct acpi_subtable_header *header, 13381839e576SJulien Grall const unsigned long end) 13391839e576SJulien Grall { 13401839e576SJulien Grall struct acpi_madt_generic_interrupt *gicc = 13411839e576SJulien Grall (struct acpi_madt_generic_interrupt *)header; 13421839e576SJulien Grall int maint_irq_mode; 13431839e576SJulien Grall static int first_madt = true; 13441839e576SJulien Grall 13451839e576SJulien Grall /* Skip unusable CPUs */ 13461839e576SJulien Grall if (!(gicc->flags & ACPI_MADT_ENABLED)) 13471839e576SJulien Grall return 0; 13481839e576SJulien Grall 13491839e576SJulien Grall maint_irq_mode = (gicc->flags & ACPI_MADT_VGIC_IRQ_MODE) ? 13501839e576SJulien Grall ACPI_EDGE_SENSITIVE : ACPI_LEVEL_SENSITIVE; 13511839e576SJulien Grall 13521839e576SJulien Grall if (first_madt) { 13531839e576SJulien Grall first_madt = false; 13541839e576SJulien Grall 13551839e576SJulien Grall acpi_data.maint_irq = gicc->vgic_interrupt; 13561839e576SJulien Grall acpi_data.maint_irq_mode = maint_irq_mode; 13571839e576SJulien Grall acpi_data.vcpu_base = gicc->gicv_base_address; 13581839e576SJulien Grall 13591839e576SJulien Grall return 0; 13601839e576SJulien Grall } 13611839e576SJulien Grall 13621839e576SJulien Grall /* 13631839e576SJulien Grall * The maintenance interrupt and GICV should be the same for every CPU 13641839e576SJulien Grall */ 13651839e576SJulien Grall if ((acpi_data.maint_irq != gicc->vgic_interrupt) || 13661839e576SJulien Grall (acpi_data.maint_irq_mode != maint_irq_mode) || 13671839e576SJulien Grall (acpi_data.vcpu_base != gicc->gicv_base_address)) 13681839e576SJulien Grall return -EINVAL; 13691839e576SJulien Grall 13701839e576SJulien Grall return 0; 13711839e576SJulien Grall } 13721839e576SJulien Grall 13731839e576SJulien Grall static bool __init gic_acpi_collect_virt_info(void) 13741839e576SJulien Grall { 13751839e576SJulien Grall int count; 13761839e576SJulien Grall 13771839e576SJulien Grall count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT, 13781839e576SJulien Grall gic_acpi_parse_virt_madt_gicc, 0); 13791839e576SJulien Grall 13801839e576SJulien Grall return (count > 0); 13811839e576SJulien Grall } 13821839e576SJulien Grall 1383ffa7d616STomasz Nowicki #define ACPI_GICV3_DIST_MEM_SIZE (SZ_64K) 13841839e576SJulien Grall #define ACPI_GICV2_VCTRL_MEM_SIZE (SZ_4K) 13851839e576SJulien Grall #define ACPI_GICV2_VCPU_MEM_SIZE (SZ_8K) 13861839e576SJulien Grall 13871839e576SJulien Grall static void __init gic_acpi_setup_kvm_info(void) 13881839e576SJulien Grall { 13891839e576SJulien Grall int irq; 13901839e576SJulien Grall 13911839e576SJulien Grall if (!gic_acpi_collect_virt_info()) { 13921839e576SJulien Grall pr_warn("Unable to get hardware information used for virtualization\n"); 13931839e576SJulien Grall return; 13941839e576SJulien Grall } 13951839e576SJulien Grall 13961839e576SJulien Grall gic_v3_kvm_info.type = GIC_V3; 13971839e576SJulien Grall 13981839e576SJulien Grall irq = acpi_register_gsi(NULL, acpi_data.maint_irq, 13991839e576SJulien Grall acpi_data.maint_irq_mode, 14001839e576SJulien Grall ACPI_ACTIVE_HIGH); 14011839e576SJulien Grall if (irq <= 0) 14021839e576SJulien Grall return; 14031839e576SJulien Grall 14041839e576SJulien Grall gic_v3_kvm_info.maint_irq = irq; 14051839e576SJulien Grall 14061839e576SJulien Grall if (acpi_data.vcpu_base) { 14071839e576SJulien Grall struct resource *vcpu = &gic_v3_kvm_info.vcpu; 14081839e576SJulien Grall 14091839e576SJulien Grall vcpu->flags = IORESOURCE_MEM; 14101839e576SJulien Grall vcpu->start = acpi_data.vcpu_base; 14111839e576SJulien Grall vcpu->end = vcpu->start + ACPI_GICV2_VCPU_MEM_SIZE - 1; 14121839e576SJulien Grall } 14131839e576SJulien Grall 14141839e576SJulien Grall gic_set_kvm_info(&gic_v3_kvm_info); 14151839e576SJulien Grall } 1416ffa7d616STomasz Nowicki 1417ffa7d616STomasz Nowicki static int __init 1418ffa7d616STomasz Nowicki gic_acpi_init(struct acpi_subtable_header *header, const unsigned long end) 1419ffa7d616STomasz Nowicki { 1420ffa7d616STomasz Nowicki struct acpi_madt_generic_distributor *dist; 1421ffa7d616STomasz Nowicki struct fwnode_handle *domain_handle; 1422611f039fSJulien Grall size_t size; 1423b70fb7afSTomasz Nowicki int i, err; 1424ffa7d616STomasz Nowicki 1425ffa7d616STomasz Nowicki /* Get distributor base address */ 1426ffa7d616STomasz Nowicki dist = (struct acpi_madt_generic_distributor *)header; 1427611f039fSJulien Grall acpi_data.dist_base = ioremap(dist->base_address, 1428611f039fSJulien Grall ACPI_GICV3_DIST_MEM_SIZE); 1429611f039fSJulien Grall if (!acpi_data.dist_base) { 1430ffa7d616STomasz Nowicki pr_err("Unable to map GICD registers\n"); 1431ffa7d616STomasz Nowicki return -ENOMEM; 1432ffa7d616STomasz Nowicki } 1433ffa7d616STomasz Nowicki 1434611f039fSJulien Grall err = gic_validate_dist_version(acpi_data.dist_base); 1435ffa7d616STomasz Nowicki if (err) { 1436611f039fSJulien Grall pr_err("No distributor detected at @%p, giving up", 1437611f039fSJulien Grall acpi_data.dist_base); 1438ffa7d616STomasz Nowicki goto out_dist_unmap; 1439ffa7d616STomasz Nowicki } 1440ffa7d616STomasz Nowicki 1441611f039fSJulien Grall size = sizeof(*acpi_data.redist_regs) * acpi_data.nr_redist_regions; 1442611f039fSJulien Grall acpi_data.redist_regs = kzalloc(size, GFP_KERNEL); 1443611f039fSJulien Grall if (!acpi_data.redist_regs) { 1444ffa7d616STomasz Nowicki err = -ENOMEM; 1445ffa7d616STomasz Nowicki goto out_dist_unmap; 1446ffa7d616STomasz Nowicki } 1447ffa7d616STomasz Nowicki 1448b70fb7afSTomasz Nowicki err = gic_acpi_collect_gicr_base(); 1449b70fb7afSTomasz Nowicki if (err) 1450ffa7d616STomasz Nowicki goto out_redist_unmap; 1451ffa7d616STomasz Nowicki 1452611f039fSJulien Grall domain_handle = irq_domain_alloc_fwnode(acpi_data.dist_base); 1453ffa7d616STomasz Nowicki if (!domain_handle) { 1454ffa7d616STomasz Nowicki err = -ENOMEM; 1455ffa7d616STomasz Nowicki goto out_redist_unmap; 1456ffa7d616STomasz Nowicki } 1457ffa7d616STomasz Nowicki 1458611f039fSJulien Grall err = gic_init_bases(acpi_data.dist_base, acpi_data.redist_regs, 1459611f039fSJulien Grall acpi_data.nr_redist_regions, 0, domain_handle); 1460ffa7d616STomasz Nowicki if (err) 1461ffa7d616STomasz Nowicki goto out_fwhandle_free; 1462ffa7d616STomasz Nowicki 1463ffa7d616STomasz Nowicki acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, domain_handle); 14641839e576SJulien Grall gic_acpi_setup_kvm_info(); 14651839e576SJulien Grall 1466ffa7d616STomasz Nowicki return 0; 1467ffa7d616STomasz Nowicki 1468ffa7d616STomasz Nowicki out_fwhandle_free: 1469ffa7d616STomasz Nowicki irq_domain_free_fwnode(domain_handle); 1470ffa7d616STomasz Nowicki out_redist_unmap: 1471611f039fSJulien Grall for (i = 0; i < acpi_data.nr_redist_regions; i++) 1472611f039fSJulien Grall if (acpi_data.redist_regs[i].redist_base) 1473611f039fSJulien Grall iounmap(acpi_data.redist_regs[i].redist_base); 1474611f039fSJulien Grall kfree(acpi_data.redist_regs); 1475ffa7d616STomasz Nowicki out_dist_unmap: 1476611f039fSJulien Grall iounmap(acpi_data.dist_base); 1477ffa7d616STomasz Nowicki return err; 1478ffa7d616STomasz Nowicki } 1479ffa7d616STomasz Nowicki IRQCHIP_ACPI_DECLARE(gic_v3, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 1480ffa7d616STomasz Nowicki acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V3, 1481ffa7d616STomasz Nowicki gic_acpi_init); 1482ffa7d616STomasz Nowicki IRQCHIP_ACPI_DECLARE(gic_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 1483ffa7d616STomasz Nowicki acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V4, 1484ffa7d616STomasz Nowicki gic_acpi_init); 1485ffa7d616STomasz Nowicki IRQCHIP_ACPI_DECLARE(gic_v3_or_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 1486ffa7d616STomasz Nowicki acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_NONE, 1487ffa7d616STomasz Nowicki gic_acpi_init); 1488ffa7d616STomasz Nowicki #endif 1489