1021f6537SMarc Zyngier /* 20edc23eaSMarc Zyngier * Copyright (C) 2013-2017 ARM Limited, All Rights Reserved. 3021f6537SMarc Zyngier * Author: Marc Zyngier <marc.zyngier@arm.com> 4021f6537SMarc Zyngier * 5021f6537SMarc Zyngier * This program is free software; you can redistribute it and/or modify 6021f6537SMarc Zyngier * it under the terms of the GNU General Public License version 2 as 7021f6537SMarc Zyngier * published by the Free Software Foundation. 8021f6537SMarc Zyngier * 9021f6537SMarc Zyngier * This program is distributed in the hope that it will be useful, 10021f6537SMarc Zyngier * but WITHOUT ANY WARRANTY; without even the implied warranty of 11021f6537SMarc Zyngier * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12021f6537SMarc Zyngier * GNU General Public License for more details. 13021f6537SMarc Zyngier * 14021f6537SMarc Zyngier * You should have received a copy of the GNU General Public License 15021f6537SMarc Zyngier * along with this program. If not, see <http://www.gnu.org/licenses/>. 16021f6537SMarc Zyngier */ 17021f6537SMarc Zyngier 1868628bb8SJulien Grall #define pr_fmt(fmt) "GICv3: " fmt 1968628bb8SJulien Grall 20ffa7d616STomasz Nowicki #include <linux/acpi.h> 21021f6537SMarc Zyngier #include <linux/cpu.h> 223708d52fSSudeep Holla #include <linux/cpu_pm.h> 23021f6537SMarc Zyngier #include <linux/delay.h> 24021f6537SMarc Zyngier #include <linux/interrupt.h> 25ffa7d616STomasz Nowicki #include <linux/irqdomain.h> 26021f6537SMarc Zyngier #include <linux/of.h> 27021f6537SMarc Zyngier #include <linux/of_address.h> 28021f6537SMarc Zyngier #include <linux/of_irq.h> 29021f6537SMarc Zyngier #include <linux/percpu.h> 30021f6537SMarc Zyngier #include <linux/slab.h> 31021f6537SMarc Zyngier 3241a83e06SJoel Porquet #include <linux/irqchip.h> 331839e576SJulien Grall #include <linux/irqchip/arm-gic-common.h> 34021f6537SMarc Zyngier #include <linux/irqchip/arm-gic-v3.h> 35e3825ba1SMarc Zyngier #include <linux/irqchip/irq-partition-percpu.h> 36021f6537SMarc Zyngier 37021f6537SMarc Zyngier #include <asm/cputype.h> 38021f6537SMarc Zyngier #include <asm/exception.h> 39021f6537SMarc Zyngier #include <asm/smp_plat.h> 400b6a3da9SMarc Zyngier #include <asm/virt.h> 41021f6537SMarc Zyngier 42021f6537SMarc Zyngier #include "irq-gic-common.h" 43021f6537SMarc Zyngier 44f5c1434cSMarc Zyngier struct redist_region { 45f5c1434cSMarc Zyngier void __iomem *redist_base; 46f5c1434cSMarc Zyngier phys_addr_t phys_base; 47b70fb7afSTomasz Nowicki bool single_redist; 48f5c1434cSMarc Zyngier }; 49f5c1434cSMarc Zyngier 50021f6537SMarc Zyngier struct gic_chip_data { 51e3825ba1SMarc Zyngier struct fwnode_handle *fwnode; 52021f6537SMarc Zyngier void __iomem *dist_base; 53f5c1434cSMarc Zyngier struct redist_region *redist_regions; 54f5c1434cSMarc Zyngier struct rdists rdists; 55021f6537SMarc Zyngier struct irq_domain *domain; 56021f6537SMarc Zyngier u64 redist_stride; 57f5c1434cSMarc Zyngier u32 nr_redist_regions; 58eda0d04aSShanker Donthineni bool has_rss; 59021f6537SMarc Zyngier unsigned int irq_nr; 60e3825ba1SMarc Zyngier struct partition_desc *ppi_descs[16]; 61021f6537SMarc Zyngier }; 62021f6537SMarc Zyngier 63021f6537SMarc Zyngier static struct gic_chip_data gic_data __read_mostly; 640b6a3da9SMarc Zyngier static struct static_key supports_deactivate = STATIC_KEY_INIT_TRUE; 65021f6537SMarc Zyngier 661839e576SJulien Grall static struct gic_kvm_info gic_v3_kvm_info; 67eda0d04aSShanker Donthineni static DEFINE_PER_CPU(bool, has_rss); 681839e576SJulien Grall 69eda0d04aSShanker Donthineni #define MPIDR_RS(mpidr) (((mpidr) & 0xF0UL) >> 4) 70f5c1434cSMarc Zyngier #define gic_data_rdist() (this_cpu_ptr(gic_data.rdists.rdist)) 71f5c1434cSMarc Zyngier #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base) 72021f6537SMarc Zyngier #define gic_data_rdist_sgi_base() (gic_data_rdist_rd_base() + SZ_64K) 73021f6537SMarc Zyngier 74021f6537SMarc Zyngier /* Our default, arbitrary priority value. Linux only uses one anyway. */ 75021f6537SMarc Zyngier #define DEFAULT_PMR_VALUE 0xf0 76021f6537SMarc Zyngier 77021f6537SMarc Zyngier static inline unsigned int gic_irq(struct irq_data *d) 78021f6537SMarc Zyngier { 79021f6537SMarc Zyngier return d->hwirq; 80021f6537SMarc Zyngier } 81021f6537SMarc Zyngier 82021f6537SMarc Zyngier static inline int gic_irq_in_rdist(struct irq_data *d) 83021f6537SMarc Zyngier { 84021f6537SMarc Zyngier return gic_irq(d) < 32; 85021f6537SMarc Zyngier } 86021f6537SMarc Zyngier 87021f6537SMarc Zyngier static inline void __iomem *gic_dist_base(struct irq_data *d) 88021f6537SMarc Zyngier { 89021f6537SMarc Zyngier if (gic_irq_in_rdist(d)) /* SGI+PPI -> SGI_base for this CPU */ 90021f6537SMarc Zyngier return gic_data_rdist_sgi_base(); 91021f6537SMarc Zyngier 92021f6537SMarc Zyngier if (d->hwirq <= 1023) /* SPI -> dist_base */ 93021f6537SMarc Zyngier return gic_data.dist_base; 94021f6537SMarc Zyngier 95021f6537SMarc Zyngier return NULL; 96021f6537SMarc Zyngier } 97021f6537SMarc Zyngier 98021f6537SMarc Zyngier static void gic_do_wait_for_rwp(void __iomem *base) 99021f6537SMarc Zyngier { 100021f6537SMarc Zyngier u32 count = 1000000; /* 1s! */ 101021f6537SMarc Zyngier 102021f6537SMarc Zyngier while (readl_relaxed(base + GICD_CTLR) & GICD_CTLR_RWP) { 103021f6537SMarc Zyngier count--; 104021f6537SMarc Zyngier if (!count) { 105021f6537SMarc Zyngier pr_err_ratelimited("RWP timeout, gone fishing\n"); 106021f6537SMarc Zyngier return; 107021f6537SMarc Zyngier } 108021f6537SMarc Zyngier cpu_relax(); 109021f6537SMarc Zyngier udelay(1); 110021f6537SMarc Zyngier }; 111021f6537SMarc Zyngier } 112021f6537SMarc Zyngier 113021f6537SMarc Zyngier /* Wait for completion of a distributor change */ 114021f6537SMarc Zyngier static void gic_dist_wait_for_rwp(void) 115021f6537SMarc Zyngier { 116021f6537SMarc Zyngier gic_do_wait_for_rwp(gic_data.dist_base); 117021f6537SMarc Zyngier } 118021f6537SMarc Zyngier 119021f6537SMarc Zyngier /* Wait for completion of a redistributor change */ 120021f6537SMarc Zyngier static void gic_redist_wait_for_rwp(void) 121021f6537SMarc Zyngier { 122021f6537SMarc Zyngier gic_do_wait_for_rwp(gic_data_rdist_rd_base()); 123021f6537SMarc Zyngier } 124021f6537SMarc Zyngier 1257936e914SJean-Philippe Brucker #ifdef CONFIG_ARM64 1266d4e11c5SRobert Richter 1276d4e11c5SRobert Richter static u64 __maybe_unused gic_read_iar(void) 1286d4e11c5SRobert Richter { 129a4023f68SSuzuki K Poulose if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_23154)) 1306d4e11c5SRobert Richter return gic_read_iar_cavium_thunderx(); 1316d4e11c5SRobert Richter else 1326d4e11c5SRobert Richter return gic_read_iar_common(); 1336d4e11c5SRobert Richter } 1347936e914SJean-Philippe Brucker #endif 135021f6537SMarc Zyngier 136a2c22510SSudeep Holla static void gic_enable_redist(bool enable) 137021f6537SMarc Zyngier { 138021f6537SMarc Zyngier void __iomem *rbase; 139021f6537SMarc Zyngier u32 count = 1000000; /* 1s! */ 140021f6537SMarc Zyngier u32 val; 141021f6537SMarc Zyngier 142021f6537SMarc Zyngier rbase = gic_data_rdist_rd_base(); 143021f6537SMarc Zyngier 144021f6537SMarc Zyngier val = readl_relaxed(rbase + GICR_WAKER); 145a2c22510SSudeep Holla if (enable) 146a2c22510SSudeep Holla /* Wake up this CPU redistributor */ 147021f6537SMarc Zyngier val &= ~GICR_WAKER_ProcessorSleep; 148a2c22510SSudeep Holla else 149a2c22510SSudeep Holla val |= GICR_WAKER_ProcessorSleep; 150021f6537SMarc Zyngier writel_relaxed(val, rbase + GICR_WAKER); 151021f6537SMarc Zyngier 152a2c22510SSudeep Holla if (!enable) { /* Check that GICR_WAKER is writeable */ 153a2c22510SSudeep Holla val = readl_relaxed(rbase + GICR_WAKER); 154a2c22510SSudeep Holla if (!(val & GICR_WAKER_ProcessorSleep)) 155a2c22510SSudeep Holla return; /* No PM support in this redistributor */ 156021f6537SMarc Zyngier } 157a2c22510SSudeep Holla 158d102eb5cSDan Carpenter while (--count) { 159a2c22510SSudeep Holla val = readl_relaxed(rbase + GICR_WAKER); 160cf1d9d11SAndrew Jones if (enable ^ (bool)(val & GICR_WAKER_ChildrenAsleep)) 161a2c22510SSudeep Holla break; 162021f6537SMarc Zyngier cpu_relax(); 163021f6537SMarc Zyngier udelay(1); 164021f6537SMarc Zyngier }; 165a2c22510SSudeep Holla if (!count) 166a2c22510SSudeep Holla pr_err_ratelimited("redistributor failed to %s...\n", 167a2c22510SSudeep Holla enable ? "wakeup" : "sleep"); 168021f6537SMarc Zyngier } 169021f6537SMarc Zyngier 170021f6537SMarc Zyngier /* 171021f6537SMarc Zyngier * Routines to disable, enable, EOI and route interrupts 172021f6537SMarc Zyngier */ 173b594c6e2SMarc Zyngier static int gic_peek_irq(struct irq_data *d, u32 offset) 174b594c6e2SMarc Zyngier { 175b594c6e2SMarc Zyngier u32 mask = 1 << (gic_irq(d) % 32); 176b594c6e2SMarc Zyngier void __iomem *base; 177b594c6e2SMarc Zyngier 178b594c6e2SMarc Zyngier if (gic_irq_in_rdist(d)) 179b594c6e2SMarc Zyngier base = gic_data_rdist_sgi_base(); 180b594c6e2SMarc Zyngier else 181b594c6e2SMarc Zyngier base = gic_data.dist_base; 182b594c6e2SMarc Zyngier 183b594c6e2SMarc Zyngier return !!(readl_relaxed(base + offset + (gic_irq(d) / 32) * 4) & mask); 184b594c6e2SMarc Zyngier } 185b594c6e2SMarc Zyngier 186021f6537SMarc Zyngier static void gic_poke_irq(struct irq_data *d, u32 offset) 187021f6537SMarc Zyngier { 188021f6537SMarc Zyngier u32 mask = 1 << (gic_irq(d) % 32); 189021f6537SMarc Zyngier void (*rwp_wait)(void); 190021f6537SMarc Zyngier void __iomem *base; 191021f6537SMarc Zyngier 192021f6537SMarc Zyngier if (gic_irq_in_rdist(d)) { 193021f6537SMarc Zyngier base = gic_data_rdist_sgi_base(); 194021f6537SMarc Zyngier rwp_wait = gic_redist_wait_for_rwp; 195021f6537SMarc Zyngier } else { 196021f6537SMarc Zyngier base = gic_data.dist_base; 197021f6537SMarc Zyngier rwp_wait = gic_dist_wait_for_rwp; 198021f6537SMarc Zyngier } 199021f6537SMarc Zyngier 200021f6537SMarc Zyngier writel_relaxed(mask, base + offset + (gic_irq(d) / 32) * 4); 201021f6537SMarc Zyngier rwp_wait(); 202021f6537SMarc Zyngier } 203021f6537SMarc Zyngier 204021f6537SMarc Zyngier static void gic_mask_irq(struct irq_data *d) 205021f6537SMarc Zyngier { 206021f6537SMarc Zyngier gic_poke_irq(d, GICD_ICENABLER); 207021f6537SMarc Zyngier } 208021f6537SMarc Zyngier 2090b6a3da9SMarc Zyngier static void gic_eoimode1_mask_irq(struct irq_data *d) 2100b6a3da9SMarc Zyngier { 2110b6a3da9SMarc Zyngier gic_mask_irq(d); 212530bf353SMarc Zyngier /* 213530bf353SMarc Zyngier * When masking a forwarded interrupt, make sure it is 214530bf353SMarc Zyngier * deactivated as well. 215530bf353SMarc Zyngier * 216530bf353SMarc Zyngier * This ensures that an interrupt that is getting 217530bf353SMarc Zyngier * disabled/masked will not get "stuck", because there is 218530bf353SMarc Zyngier * noone to deactivate it (guest is being terminated). 219530bf353SMarc Zyngier */ 2204df7f54dSThomas Gleixner if (irqd_is_forwarded_to_vcpu(d)) 221530bf353SMarc Zyngier gic_poke_irq(d, GICD_ICACTIVER); 2220b6a3da9SMarc Zyngier } 2230b6a3da9SMarc Zyngier 224021f6537SMarc Zyngier static void gic_unmask_irq(struct irq_data *d) 225021f6537SMarc Zyngier { 226021f6537SMarc Zyngier gic_poke_irq(d, GICD_ISENABLER); 227021f6537SMarc Zyngier } 228021f6537SMarc Zyngier 229b594c6e2SMarc Zyngier static int gic_irq_set_irqchip_state(struct irq_data *d, 230b594c6e2SMarc Zyngier enum irqchip_irq_state which, bool val) 231b594c6e2SMarc Zyngier { 232b594c6e2SMarc Zyngier u32 reg; 233b594c6e2SMarc Zyngier 234b594c6e2SMarc Zyngier if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */ 235b594c6e2SMarc Zyngier return -EINVAL; 236b594c6e2SMarc Zyngier 237b594c6e2SMarc Zyngier switch (which) { 238b594c6e2SMarc Zyngier case IRQCHIP_STATE_PENDING: 239b594c6e2SMarc Zyngier reg = val ? GICD_ISPENDR : GICD_ICPENDR; 240b594c6e2SMarc Zyngier break; 241b594c6e2SMarc Zyngier 242b594c6e2SMarc Zyngier case IRQCHIP_STATE_ACTIVE: 243b594c6e2SMarc Zyngier reg = val ? GICD_ISACTIVER : GICD_ICACTIVER; 244b594c6e2SMarc Zyngier break; 245b594c6e2SMarc Zyngier 246b594c6e2SMarc Zyngier case IRQCHIP_STATE_MASKED: 247b594c6e2SMarc Zyngier reg = val ? GICD_ICENABLER : GICD_ISENABLER; 248b594c6e2SMarc Zyngier break; 249b594c6e2SMarc Zyngier 250b594c6e2SMarc Zyngier default: 251b594c6e2SMarc Zyngier return -EINVAL; 252b594c6e2SMarc Zyngier } 253b594c6e2SMarc Zyngier 254b594c6e2SMarc Zyngier gic_poke_irq(d, reg); 255b594c6e2SMarc Zyngier return 0; 256b594c6e2SMarc Zyngier } 257b594c6e2SMarc Zyngier 258b594c6e2SMarc Zyngier static int gic_irq_get_irqchip_state(struct irq_data *d, 259b594c6e2SMarc Zyngier enum irqchip_irq_state which, bool *val) 260b594c6e2SMarc Zyngier { 261b594c6e2SMarc Zyngier if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */ 262b594c6e2SMarc Zyngier return -EINVAL; 263b594c6e2SMarc Zyngier 264b594c6e2SMarc Zyngier switch (which) { 265b594c6e2SMarc Zyngier case IRQCHIP_STATE_PENDING: 266b594c6e2SMarc Zyngier *val = gic_peek_irq(d, GICD_ISPENDR); 267b594c6e2SMarc Zyngier break; 268b594c6e2SMarc Zyngier 269b594c6e2SMarc Zyngier case IRQCHIP_STATE_ACTIVE: 270b594c6e2SMarc Zyngier *val = gic_peek_irq(d, GICD_ISACTIVER); 271b594c6e2SMarc Zyngier break; 272b594c6e2SMarc Zyngier 273b594c6e2SMarc Zyngier case IRQCHIP_STATE_MASKED: 274b594c6e2SMarc Zyngier *val = !gic_peek_irq(d, GICD_ISENABLER); 275b594c6e2SMarc Zyngier break; 276b594c6e2SMarc Zyngier 277b594c6e2SMarc Zyngier default: 278b594c6e2SMarc Zyngier return -EINVAL; 279b594c6e2SMarc Zyngier } 280b594c6e2SMarc Zyngier 281b594c6e2SMarc Zyngier return 0; 282b594c6e2SMarc Zyngier } 283b594c6e2SMarc Zyngier 284021f6537SMarc Zyngier static void gic_eoi_irq(struct irq_data *d) 285021f6537SMarc Zyngier { 286021f6537SMarc Zyngier gic_write_eoir(gic_irq(d)); 287021f6537SMarc Zyngier } 288021f6537SMarc Zyngier 2890b6a3da9SMarc Zyngier static void gic_eoimode1_eoi_irq(struct irq_data *d) 2900b6a3da9SMarc Zyngier { 2910b6a3da9SMarc Zyngier /* 292530bf353SMarc Zyngier * No need to deactivate an LPI, or an interrupt that 293530bf353SMarc Zyngier * is is getting forwarded to a vcpu. 2940b6a3da9SMarc Zyngier */ 2954df7f54dSThomas Gleixner if (gic_irq(d) >= 8192 || irqd_is_forwarded_to_vcpu(d)) 2960b6a3da9SMarc Zyngier return; 2970b6a3da9SMarc Zyngier gic_write_dir(gic_irq(d)); 2980b6a3da9SMarc Zyngier } 2990b6a3da9SMarc Zyngier 300021f6537SMarc Zyngier static int gic_set_type(struct irq_data *d, unsigned int type) 301021f6537SMarc Zyngier { 302021f6537SMarc Zyngier unsigned int irq = gic_irq(d); 303021f6537SMarc Zyngier void (*rwp_wait)(void); 304021f6537SMarc Zyngier void __iomem *base; 305021f6537SMarc Zyngier 306021f6537SMarc Zyngier /* Interrupt configuration for SGIs can't be changed */ 307021f6537SMarc Zyngier if (irq < 16) 308021f6537SMarc Zyngier return -EINVAL; 309021f6537SMarc Zyngier 310fb7e7debSLiviu Dudau /* SPIs have restrictions on the supported types */ 311fb7e7debSLiviu Dudau if (irq >= 32 && type != IRQ_TYPE_LEVEL_HIGH && 312fb7e7debSLiviu Dudau type != IRQ_TYPE_EDGE_RISING) 313021f6537SMarc Zyngier return -EINVAL; 314021f6537SMarc Zyngier 315021f6537SMarc Zyngier if (gic_irq_in_rdist(d)) { 316021f6537SMarc Zyngier base = gic_data_rdist_sgi_base(); 317021f6537SMarc Zyngier rwp_wait = gic_redist_wait_for_rwp; 318021f6537SMarc Zyngier } else { 319021f6537SMarc Zyngier base = gic_data.dist_base; 320021f6537SMarc Zyngier rwp_wait = gic_dist_wait_for_rwp; 321021f6537SMarc Zyngier } 322021f6537SMarc Zyngier 323fb7e7debSLiviu Dudau return gic_configure_irq(irq, type, base, rwp_wait); 324021f6537SMarc Zyngier } 325021f6537SMarc Zyngier 326530bf353SMarc Zyngier static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu) 327530bf353SMarc Zyngier { 3284df7f54dSThomas Gleixner if (vcpu) 3294df7f54dSThomas Gleixner irqd_set_forwarded_to_vcpu(d); 3304df7f54dSThomas Gleixner else 3314df7f54dSThomas Gleixner irqd_clr_forwarded_to_vcpu(d); 332530bf353SMarc Zyngier return 0; 333530bf353SMarc Zyngier } 334530bf353SMarc Zyngier 335f6c86a41SJean-Philippe Brucker static u64 gic_mpidr_to_affinity(unsigned long mpidr) 336021f6537SMarc Zyngier { 337021f6537SMarc Zyngier u64 aff; 338021f6537SMarc Zyngier 339f6c86a41SJean-Philippe Brucker aff = ((u64)MPIDR_AFFINITY_LEVEL(mpidr, 3) << 32 | 340021f6537SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 | 341021f6537SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | 342021f6537SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 0)); 343021f6537SMarc Zyngier 344021f6537SMarc Zyngier return aff; 345021f6537SMarc Zyngier } 346021f6537SMarc Zyngier 347021f6537SMarc Zyngier static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) 348021f6537SMarc Zyngier { 349f6c86a41SJean-Philippe Brucker u32 irqnr; 350021f6537SMarc Zyngier 351021f6537SMarc Zyngier do { 352021f6537SMarc Zyngier irqnr = gic_read_iar(); 353021f6537SMarc Zyngier 354da33f31dSMarc Zyngier if (likely(irqnr > 15 && irqnr < 1020) || irqnr >= 8192) { 355ebc6de00SMarc Zyngier int err; 3560b6a3da9SMarc Zyngier 3570b6a3da9SMarc Zyngier if (static_key_true(&supports_deactivate)) 3580b6a3da9SMarc Zyngier gic_write_eoir(irqnr); 35939a06b67SWill Deacon else 36039a06b67SWill Deacon isb(); 3610b6a3da9SMarc Zyngier 362ebc6de00SMarc Zyngier err = handle_domain_irq(gic_data.domain, irqnr, regs); 363ebc6de00SMarc Zyngier if (err) { 364da33f31dSMarc Zyngier WARN_ONCE(true, "Unexpected interrupt received!\n"); 3650b6a3da9SMarc Zyngier if (static_key_true(&supports_deactivate)) { 3660b6a3da9SMarc Zyngier if (irqnr < 8192) 3670b6a3da9SMarc Zyngier gic_write_dir(irqnr); 3680b6a3da9SMarc Zyngier } else { 369021f6537SMarc Zyngier gic_write_eoir(irqnr); 370021f6537SMarc Zyngier } 3710b6a3da9SMarc Zyngier } 372ebc6de00SMarc Zyngier continue; 373ebc6de00SMarc Zyngier } 374021f6537SMarc Zyngier if (irqnr < 16) { 375021f6537SMarc Zyngier gic_write_eoir(irqnr); 3760b6a3da9SMarc Zyngier if (static_key_true(&supports_deactivate)) 3770b6a3da9SMarc Zyngier gic_write_dir(irqnr); 378021f6537SMarc Zyngier #ifdef CONFIG_SMP 379f86c4fbdSWill Deacon /* 380f86c4fbdSWill Deacon * Unlike GICv2, we don't need an smp_rmb() here. 381f86c4fbdSWill Deacon * The control dependency from gic_read_iar to 382f86c4fbdSWill Deacon * the ISB in gic_write_eoir is enough to ensure 383f86c4fbdSWill Deacon * that any shared data read by handle_IPI will 384f86c4fbdSWill Deacon * be read after the ACK. 385f86c4fbdSWill Deacon */ 386021f6537SMarc Zyngier handle_IPI(irqnr, regs); 387021f6537SMarc Zyngier #else 388021f6537SMarc Zyngier WARN_ONCE(true, "Unexpected SGI received!\n"); 389021f6537SMarc Zyngier #endif 390021f6537SMarc Zyngier continue; 391021f6537SMarc Zyngier } 392021f6537SMarc Zyngier } while (irqnr != ICC_IAR1_EL1_SPURIOUS); 393021f6537SMarc Zyngier } 394021f6537SMarc Zyngier 395021f6537SMarc Zyngier static void __init gic_dist_init(void) 396021f6537SMarc Zyngier { 397021f6537SMarc Zyngier unsigned int i; 398021f6537SMarc Zyngier u64 affinity; 399021f6537SMarc Zyngier void __iomem *base = gic_data.dist_base; 400021f6537SMarc Zyngier 401021f6537SMarc Zyngier /* Disable the distributor */ 402021f6537SMarc Zyngier writel_relaxed(0, base + GICD_CTLR); 403021f6537SMarc Zyngier gic_dist_wait_for_rwp(); 404021f6537SMarc Zyngier 4057c9b9730SMarc Zyngier /* 4067c9b9730SMarc Zyngier * Configure SPIs as non-secure Group-1. This will only matter 4077c9b9730SMarc Zyngier * if the GIC only has a single security state. This will not 4087c9b9730SMarc Zyngier * do the right thing if the kernel is running in secure mode, 4097c9b9730SMarc Zyngier * but that's not the intended use case anyway. 4107c9b9730SMarc Zyngier */ 4117c9b9730SMarc Zyngier for (i = 32; i < gic_data.irq_nr; i += 32) 4127c9b9730SMarc Zyngier writel_relaxed(~0, base + GICD_IGROUPR + i / 8); 4137c9b9730SMarc Zyngier 414021f6537SMarc Zyngier gic_dist_config(base, gic_data.irq_nr, gic_dist_wait_for_rwp); 415021f6537SMarc Zyngier 416021f6537SMarc Zyngier /* Enable distributor with ARE, Group1 */ 417021f6537SMarc Zyngier writel_relaxed(GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G1A | GICD_CTLR_ENABLE_G1, 418021f6537SMarc Zyngier base + GICD_CTLR); 419021f6537SMarc Zyngier 420021f6537SMarc Zyngier /* 421021f6537SMarc Zyngier * Set all global interrupts to the boot CPU only. ARE must be 422021f6537SMarc Zyngier * enabled. 423021f6537SMarc Zyngier */ 424021f6537SMarc Zyngier affinity = gic_mpidr_to_affinity(cpu_logical_map(smp_processor_id())); 425021f6537SMarc Zyngier for (i = 32; i < gic_data.irq_nr; i++) 42672c97126SJean-Philippe Brucker gic_write_irouter(affinity, base + GICD_IROUTER + i * 8); 427021f6537SMarc Zyngier } 428021f6537SMarc Zyngier 4290d94ded2SMarc Zyngier static int gic_iterate_rdists(int (*fn)(struct redist_region *, void __iomem *)) 430021f6537SMarc Zyngier { 4310d94ded2SMarc Zyngier int ret = -ENODEV; 432021f6537SMarc Zyngier int i; 433021f6537SMarc Zyngier 434f5c1434cSMarc Zyngier for (i = 0; i < gic_data.nr_redist_regions; i++) { 435f5c1434cSMarc Zyngier void __iomem *ptr = gic_data.redist_regions[i].redist_base; 4360d94ded2SMarc Zyngier u64 typer; 437021f6537SMarc Zyngier u32 reg; 438021f6537SMarc Zyngier 439021f6537SMarc Zyngier reg = readl_relaxed(ptr + GICR_PIDR2) & GIC_PIDR2_ARCH_MASK; 440021f6537SMarc Zyngier if (reg != GIC_PIDR2_ARCH_GICv3 && 441021f6537SMarc Zyngier reg != GIC_PIDR2_ARCH_GICv4) { /* We're in trouble... */ 442021f6537SMarc Zyngier pr_warn("No redistributor present @%p\n", ptr); 443021f6537SMarc Zyngier break; 444021f6537SMarc Zyngier } 445021f6537SMarc Zyngier 446021f6537SMarc Zyngier do { 44772c97126SJean-Philippe Brucker typer = gic_read_typer(ptr + GICR_TYPER); 4480d94ded2SMarc Zyngier ret = fn(gic_data.redist_regions + i, ptr); 4490d94ded2SMarc Zyngier if (!ret) 450021f6537SMarc Zyngier return 0; 451021f6537SMarc Zyngier 452b70fb7afSTomasz Nowicki if (gic_data.redist_regions[i].single_redist) 453b70fb7afSTomasz Nowicki break; 454b70fb7afSTomasz Nowicki 455021f6537SMarc Zyngier if (gic_data.redist_stride) { 456021f6537SMarc Zyngier ptr += gic_data.redist_stride; 457021f6537SMarc Zyngier } else { 458021f6537SMarc Zyngier ptr += SZ_64K * 2; /* Skip RD_base + SGI_base */ 459021f6537SMarc Zyngier if (typer & GICR_TYPER_VLPIS) 460021f6537SMarc Zyngier ptr += SZ_64K * 2; /* Skip VLPI_base + reserved page */ 461021f6537SMarc Zyngier } 462021f6537SMarc Zyngier } while (!(typer & GICR_TYPER_LAST)); 463021f6537SMarc Zyngier } 464021f6537SMarc Zyngier 4650d94ded2SMarc Zyngier return ret ? -ENODEV : 0; 4660d94ded2SMarc Zyngier } 4670d94ded2SMarc Zyngier 4680d94ded2SMarc Zyngier static int __gic_populate_rdist(struct redist_region *region, void __iomem *ptr) 4690d94ded2SMarc Zyngier { 4700d94ded2SMarc Zyngier unsigned long mpidr = cpu_logical_map(smp_processor_id()); 4710d94ded2SMarc Zyngier u64 typer; 4720d94ded2SMarc Zyngier u32 aff; 4730d94ded2SMarc Zyngier 4740d94ded2SMarc Zyngier /* 4750d94ded2SMarc Zyngier * Convert affinity to a 32bit value that can be matched to 4760d94ded2SMarc Zyngier * GICR_TYPER bits [63:32]. 4770d94ded2SMarc Zyngier */ 4780d94ded2SMarc Zyngier aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 24 | 4790d94ded2SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 | 4800d94ded2SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | 4810d94ded2SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 0)); 4820d94ded2SMarc Zyngier 4830d94ded2SMarc Zyngier typer = gic_read_typer(ptr + GICR_TYPER); 4840d94ded2SMarc Zyngier if ((typer >> 32) == aff) { 4850d94ded2SMarc Zyngier u64 offset = ptr - region->redist_base; 4860d94ded2SMarc Zyngier gic_data_rdist_rd_base() = ptr; 4870d94ded2SMarc Zyngier gic_data_rdist()->phys_base = region->phys_base + offset; 4880d94ded2SMarc Zyngier 4890d94ded2SMarc Zyngier pr_info("CPU%d: found redistributor %lx region %d:%pa\n", 4900d94ded2SMarc Zyngier smp_processor_id(), mpidr, 4910d94ded2SMarc Zyngier (int)(region - gic_data.redist_regions), 4920d94ded2SMarc Zyngier &gic_data_rdist()->phys_base); 4930d94ded2SMarc Zyngier return 0; 4940d94ded2SMarc Zyngier } 4950d94ded2SMarc Zyngier 4960d94ded2SMarc Zyngier /* Try next one */ 4970d94ded2SMarc Zyngier return 1; 4980d94ded2SMarc Zyngier } 4990d94ded2SMarc Zyngier 5000d94ded2SMarc Zyngier static int gic_populate_rdist(void) 5010d94ded2SMarc Zyngier { 5020d94ded2SMarc Zyngier if (gic_iterate_rdists(__gic_populate_rdist) == 0) 5030d94ded2SMarc Zyngier return 0; 5040d94ded2SMarc Zyngier 505021f6537SMarc Zyngier /* We couldn't even deal with ourselves... */ 506f6c86a41SJean-Philippe Brucker WARN(true, "CPU%d: mpidr %lx has no re-distributor!\n", 5070d94ded2SMarc Zyngier smp_processor_id(), 5080d94ded2SMarc Zyngier (unsigned long)cpu_logical_map(smp_processor_id())); 509021f6537SMarc Zyngier return -ENODEV; 510021f6537SMarc Zyngier } 511021f6537SMarc Zyngier 5120edc23eaSMarc Zyngier static int __gic_update_vlpi_properties(struct redist_region *region, 5130edc23eaSMarc Zyngier void __iomem *ptr) 5140edc23eaSMarc Zyngier { 5150edc23eaSMarc Zyngier u64 typer = gic_read_typer(ptr + GICR_TYPER); 5160edc23eaSMarc Zyngier gic_data.rdists.has_vlpis &= !!(typer & GICR_TYPER_VLPIS); 5170edc23eaSMarc Zyngier gic_data.rdists.has_direct_lpi &= !!(typer & GICR_TYPER_DirectLPIS); 5180edc23eaSMarc Zyngier 5190edc23eaSMarc Zyngier return 1; 5200edc23eaSMarc Zyngier } 5210edc23eaSMarc Zyngier 5220edc23eaSMarc Zyngier static void gic_update_vlpi_properties(void) 5230edc23eaSMarc Zyngier { 5240edc23eaSMarc Zyngier gic_iterate_rdists(__gic_update_vlpi_properties); 5250edc23eaSMarc Zyngier pr_info("%sVLPI support, %sdirect LPI support\n", 5260edc23eaSMarc Zyngier !gic_data.rdists.has_vlpis ? "no " : "", 5270edc23eaSMarc Zyngier !gic_data.rdists.has_direct_lpi ? "no " : ""); 5280edc23eaSMarc Zyngier } 5290edc23eaSMarc Zyngier 5303708d52fSSudeep Holla static void gic_cpu_sys_reg_init(void) 531021f6537SMarc Zyngier { 532eda0d04aSShanker Donthineni int i, cpu = smp_processor_id(); 533eda0d04aSShanker Donthineni u64 mpidr = cpu_logical_map(cpu); 534eda0d04aSShanker Donthineni u64 need_rss = MPIDR_RS(mpidr); 535eda0d04aSShanker Donthineni 5367cabd008SMarc Zyngier /* 5377cabd008SMarc Zyngier * Need to check that the SRE bit has actually been set. If 5387cabd008SMarc Zyngier * not, it means that SRE is disabled at EL2. We're going to 5397cabd008SMarc Zyngier * die painfully, and there is nothing we can do about it. 5407cabd008SMarc Zyngier * 5417cabd008SMarc Zyngier * Kindly inform the luser. 5427cabd008SMarc Zyngier */ 5437cabd008SMarc Zyngier if (!gic_enable_sre()) 5447cabd008SMarc Zyngier pr_err("GIC: unable to set SRE (disabled at EL2), panic ahead\n"); 545021f6537SMarc Zyngier 546021f6537SMarc Zyngier /* Set priority mask register */ 547021f6537SMarc Zyngier gic_write_pmr(DEFAULT_PMR_VALUE); 548021f6537SMarc Zyngier 54991ef8442SDaniel Thompson /* 55091ef8442SDaniel Thompson * Some firmwares hand over to the kernel with the BPR changed from 55191ef8442SDaniel Thompson * its reset value (and with a value large enough to prevent 55291ef8442SDaniel Thompson * any pre-emptive interrupts from working at all). Writing a zero 55391ef8442SDaniel Thompson * to BPR restores is reset value. 55491ef8442SDaniel Thompson */ 55591ef8442SDaniel Thompson gic_write_bpr1(0); 55691ef8442SDaniel Thompson 5570b6a3da9SMarc Zyngier if (static_key_true(&supports_deactivate)) { 5580b6a3da9SMarc Zyngier /* EOI drops priority only (mode 1) */ 5590b6a3da9SMarc Zyngier gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop); 5600b6a3da9SMarc Zyngier } else { 561021f6537SMarc Zyngier /* EOI deactivates interrupt too (mode 0) */ 562021f6537SMarc Zyngier gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop_dir); 5630b6a3da9SMarc Zyngier } 564021f6537SMarc Zyngier 565021f6537SMarc Zyngier /* ... and let's hit the road... */ 566021f6537SMarc Zyngier gic_write_grpen1(1); 567eda0d04aSShanker Donthineni 568eda0d04aSShanker Donthineni /* Keep the RSS capability status in per_cpu variable */ 569eda0d04aSShanker Donthineni per_cpu(has_rss, cpu) = !!(gic_read_ctlr() & ICC_CTLR_EL1_RSS); 570eda0d04aSShanker Donthineni 571eda0d04aSShanker Donthineni /* Check all the CPUs have capable of sending SGIs to other CPUs */ 572eda0d04aSShanker Donthineni for_each_online_cpu(i) { 573eda0d04aSShanker Donthineni bool have_rss = per_cpu(has_rss, i) && per_cpu(has_rss, cpu); 574eda0d04aSShanker Donthineni 575eda0d04aSShanker Donthineni need_rss |= MPIDR_RS(cpu_logical_map(i)); 576eda0d04aSShanker Donthineni if (need_rss && (!have_rss)) 577eda0d04aSShanker Donthineni pr_crit("CPU%d (%lx) can't SGI CPU%d (%lx), no RSS\n", 578eda0d04aSShanker Donthineni cpu, (unsigned long)mpidr, 579eda0d04aSShanker Donthineni i, (unsigned long)cpu_logical_map(i)); 580eda0d04aSShanker Donthineni } 581eda0d04aSShanker Donthineni 582eda0d04aSShanker Donthineni /** 583eda0d04aSShanker Donthineni * GIC spec says, when ICC_CTLR_EL1.RSS==1 and GICD_TYPER.RSS==0, 584eda0d04aSShanker Donthineni * writing ICC_ASGI1R_EL1 register with RS != 0 is a CONSTRAINED 585eda0d04aSShanker Donthineni * UNPREDICTABLE choice of : 586eda0d04aSShanker Donthineni * - The write is ignored. 587eda0d04aSShanker Donthineni * - The RS field is treated as 0. 588eda0d04aSShanker Donthineni */ 589eda0d04aSShanker Donthineni if (need_rss && (!gic_data.has_rss)) 590eda0d04aSShanker Donthineni pr_crit_once("RSS is required but GICD doesn't support it\n"); 591021f6537SMarc Zyngier } 592021f6537SMarc Zyngier 593da33f31dSMarc Zyngier static int gic_dist_supports_lpis(void) 594da33f31dSMarc Zyngier { 595da33f31dSMarc Zyngier return !!(readl_relaxed(gic_data.dist_base + GICD_TYPER) & GICD_TYPER_LPIS); 596da33f31dSMarc Zyngier } 597da33f31dSMarc Zyngier 598021f6537SMarc Zyngier static void gic_cpu_init(void) 599021f6537SMarc Zyngier { 600021f6537SMarc Zyngier void __iomem *rbase; 601021f6537SMarc Zyngier 602021f6537SMarc Zyngier /* Register ourselves with the rest of the world */ 603021f6537SMarc Zyngier if (gic_populate_rdist()) 604021f6537SMarc Zyngier return; 605021f6537SMarc Zyngier 606a2c22510SSudeep Holla gic_enable_redist(true); 607021f6537SMarc Zyngier 608021f6537SMarc Zyngier rbase = gic_data_rdist_sgi_base(); 609021f6537SMarc Zyngier 6107c9b9730SMarc Zyngier /* Configure SGIs/PPIs as non-secure Group-1 */ 6117c9b9730SMarc Zyngier writel_relaxed(~0, rbase + GICR_IGROUPR0); 6127c9b9730SMarc Zyngier 613021f6537SMarc Zyngier gic_cpu_config(rbase, gic_redist_wait_for_rwp); 614021f6537SMarc Zyngier 615da33f31dSMarc Zyngier /* Give LPIs a spin */ 616da33f31dSMarc Zyngier if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis()) 617da33f31dSMarc Zyngier its_cpu_init(); 618da33f31dSMarc Zyngier 6193708d52fSSudeep Holla /* initialise system registers */ 6203708d52fSSudeep Holla gic_cpu_sys_reg_init(); 621021f6537SMarc Zyngier } 622021f6537SMarc Zyngier 623021f6537SMarc Zyngier #ifdef CONFIG_SMP 624021f6537SMarc Zyngier 625eda0d04aSShanker Donthineni #define MPIDR_TO_SGI_RS(mpidr) (MPIDR_RS(mpidr) << ICC_SGI1R_RS_SHIFT) 626eda0d04aSShanker Donthineni #define MPIDR_TO_SGI_CLUSTER_ID(mpidr) ((mpidr) & ~0xFUL) 627eda0d04aSShanker Donthineni 6286670a6d8SRichard Cochran static int gic_starting_cpu(unsigned int cpu) 6296670a6d8SRichard Cochran { 6306670a6d8SRichard Cochran gic_cpu_init(); 6316670a6d8SRichard Cochran return 0; 6326670a6d8SRichard Cochran } 633021f6537SMarc Zyngier 634021f6537SMarc Zyngier static u16 gic_compute_target_list(int *base_cpu, const struct cpumask *mask, 635f6c86a41SJean-Philippe Brucker unsigned long cluster_id) 636021f6537SMarc Zyngier { 637727653d6SJames Morse int next_cpu, cpu = *base_cpu; 638f6c86a41SJean-Philippe Brucker unsigned long mpidr = cpu_logical_map(cpu); 639021f6537SMarc Zyngier u16 tlist = 0; 640021f6537SMarc Zyngier 641021f6537SMarc Zyngier while (cpu < nr_cpu_ids) { 642021f6537SMarc Zyngier tlist |= 1 << (mpidr & 0xf); 643021f6537SMarc Zyngier 644727653d6SJames Morse next_cpu = cpumask_next(cpu, mask); 645727653d6SJames Morse if (next_cpu >= nr_cpu_ids) 646021f6537SMarc Zyngier goto out; 647727653d6SJames Morse cpu = next_cpu; 648021f6537SMarc Zyngier 649021f6537SMarc Zyngier mpidr = cpu_logical_map(cpu); 650021f6537SMarc Zyngier 651eda0d04aSShanker Donthineni if (cluster_id != MPIDR_TO_SGI_CLUSTER_ID(mpidr)) { 652021f6537SMarc Zyngier cpu--; 653021f6537SMarc Zyngier goto out; 654021f6537SMarc Zyngier } 655021f6537SMarc Zyngier } 656021f6537SMarc Zyngier out: 657021f6537SMarc Zyngier *base_cpu = cpu; 658021f6537SMarc Zyngier return tlist; 659021f6537SMarc Zyngier } 660021f6537SMarc Zyngier 6617e580278SAndre Przywara #define MPIDR_TO_SGI_AFFINITY(cluster_id, level) \ 6627e580278SAndre Przywara (MPIDR_AFFINITY_LEVEL(cluster_id, level) \ 6637e580278SAndre Przywara << ICC_SGI1R_AFFINITY_## level ##_SHIFT) 6647e580278SAndre Przywara 665021f6537SMarc Zyngier static void gic_send_sgi(u64 cluster_id, u16 tlist, unsigned int irq) 666021f6537SMarc Zyngier { 667021f6537SMarc Zyngier u64 val; 668021f6537SMarc Zyngier 6697e580278SAndre Przywara val = (MPIDR_TO_SGI_AFFINITY(cluster_id, 3) | 6707e580278SAndre Przywara MPIDR_TO_SGI_AFFINITY(cluster_id, 2) | 6717e580278SAndre Przywara irq << ICC_SGI1R_SGI_ID_SHIFT | 6727e580278SAndre Przywara MPIDR_TO_SGI_AFFINITY(cluster_id, 1) | 673eda0d04aSShanker Donthineni MPIDR_TO_SGI_RS(cluster_id) | 6747e580278SAndre Przywara tlist << ICC_SGI1R_TARGET_LIST_SHIFT); 675021f6537SMarc Zyngier 676021f6537SMarc Zyngier pr_debug("CPU%d: ICC_SGI1R_EL1 %llx\n", smp_processor_id(), val); 677021f6537SMarc Zyngier gic_write_sgi1r(val); 678021f6537SMarc Zyngier } 679021f6537SMarc Zyngier 680021f6537SMarc Zyngier static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) 681021f6537SMarc Zyngier { 682021f6537SMarc Zyngier int cpu; 683021f6537SMarc Zyngier 684021f6537SMarc Zyngier if (WARN_ON(irq >= 16)) 685021f6537SMarc Zyngier return; 686021f6537SMarc Zyngier 687021f6537SMarc Zyngier /* 688021f6537SMarc Zyngier * Ensure that stores to Normal memory are visible to the 689021f6537SMarc Zyngier * other CPUs before issuing the IPI. 690021f6537SMarc Zyngier */ 691021f6537SMarc Zyngier smp_wmb(); 692021f6537SMarc Zyngier 693f9b531feSRusty Russell for_each_cpu(cpu, mask) { 694eda0d04aSShanker Donthineni u64 cluster_id = MPIDR_TO_SGI_CLUSTER_ID(cpu_logical_map(cpu)); 695021f6537SMarc Zyngier u16 tlist; 696021f6537SMarc Zyngier 697021f6537SMarc Zyngier tlist = gic_compute_target_list(&cpu, mask, cluster_id); 698021f6537SMarc Zyngier gic_send_sgi(cluster_id, tlist, irq); 699021f6537SMarc Zyngier } 700021f6537SMarc Zyngier 701021f6537SMarc Zyngier /* Force the above writes to ICC_SGI1R_EL1 to be executed */ 702021f6537SMarc Zyngier isb(); 703021f6537SMarc Zyngier } 704021f6537SMarc Zyngier 705021f6537SMarc Zyngier static void gic_smp_init(void) 706021f6537SMarc Zyngier { 707021f6537SMarc Zyngier set_smp_cross_call(gic_raise_softirq); 7086896bcd1SThomas Gleixner cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_GIC_STARTING, 70973c1b41eSThomas Gleixner "irqchip/arm/gicv3:starting", 71073c1b41eSThomas Gleixner gic_starting_cpu, NULL); 711021f6537SMarc Zyngier } 712021f6537SMarc Zyngier 713021f6537SMarc Zyngier static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, 714021f6537SMarc Zyngier bool force) 715021f6537SMarc Zyngier { 71665a30f8bSSuzuki K Poulose unsigned int cpu; 717021f6537SMarc Zyngier void __iomem *reg; 718021f6537SMarc Zyngier int enabled; 719021f6537SMarc Zyngier u64 val; 720021f6537SMarc Zyngier 72165a30f8bSSuzuki K Poulose if (force) 72265a30f8bSSuzuki K Poulose cpu = cpumask_first(mask_val); 72365a30f8bSSuzuki K Poulose else 72465a30f8bSSuzuki K Poulose cpu = cpumask_any_and(mask_val, cpu_online_mask); 72565a30f8bSSuzuki K Poulose 726866d7c1bSSuzuki K Poulose if (cpu >= nr_cpu_ids) 727866d7c1bSSuzuki K Poulose return -EINVAL; 728866d7c1bSSuzuki K Poulose 729021f6537SMarc Zyngier if (gic_irq_in_rdist(d)) 730021f6537SMarc Zyngier return -EINVAL; 731021f6537SMarc Zyngier 732021f6537SMarc Zyngier /* If interrupt was enabled, disable it first */ 733021f6537SMarc Zyngier enabled = gic_peek_irq(d, GICD_ISENABLER); 734021f6537SMarc Zyngier if (enabled) 735021f6537SMarc Zyngier gic_mask_irq(d); 736021f6537SMarc Zyngier 737021f6537SMarc Zyngier reg = gic_dist_base(d) + GICD_IROUTER + (gic_irq(d) * 8); 738021f6537SMarc Zyngier val = gic_mpidr_to_affinity(cpu_logical_map(cpu)); 739021f6537SMarc Zyngier 74072c97126SJean-Philippe Brucker gic_write_irouter(val, reg); 741021f6537SMarc Zyngier 742021f6537SMarc Zyngier /* 743021f6537SMarc Zyngier * If the interrupt was enabled, enabled it again. Otherwise, 744021f6537SMarc Zyngier * just wait for the distributor to have digested our changes. 745021f6537SMarc Zyngier */ 746021f6537SMarc Zyngier if (enabled) 747021f6537SMarc Zyngier gic_unmask_irq(d); 748021f6537SMarc Zyngier else 749021f6537SMarc Zyngier gic_dist_wait_for_rwp(); 750021f6537SMarc Zyngier 751956ae91aSMarc Zyngier irq_data_update_effective_affinity(d, cpumask_of(cpu)); 752956ae91aSMarc Zyngier 7530fc6fa29SAntoine Tenart return IRQ_SET_MASK_OK_DONE; 754021f6537SMarc Zyngier } 755021f6537SMarc Zyngier #else 756021f6537SMarc Zyngier #define gic_set_affinity NULL 757021f6537SMarc Zyngier #define gic_smp_init() do { } while(0) 758021f6537SMarc Zyngier #endif 759021f6537SMarc Zyngier 7603708d52fSSudeep Holla #ifdef CONFIG_CPU_PM 761ccd9432aSSudeep Holla /* Check whether it's single security state view */ 762ccd9432aSSudeep Holla static bool gic_dist_security_disabled(void) 763ccd9432aSSudeep Holla { 764ccd9432aSSudeep Holla return readl_relaxed(gic_data.dist_base + GICD_CTLR) & GICD_CTLR_DS; 765ccd9432aSSudeep Holla } 766ccd9432aSSudeep Holla 7673708d52fSSudeep Holla static int gic_cpu_pm_notifier(struct notifier_block *self, 7683708d52fSSudeep Holla unsigned long cmd, void *v) 7693708d52fSSudeep Holla { 7703708d52fSSudeep Holla if (cmd == CPU_PM_EXIT) { 771ccd9432aSSudeep Holla if (gic_dist_security_disabled()) 7723708d52fSSudeep Holla gic_enable_redist(true); 7733708d52fSSudeep Holla gic_cpu_sys_reg_init(); 774ccd9432aSSudeep Holla } else if (cmd == CPU_PM_ENTER && gic_dist_security_disabled()) { 7753708d52fSSudeep Holla gic_write_grpen1(0); 7763708d52fSSudeep Holla gic_enable_redist(false); 7773708d52fSSudeep Holla } 7783708d52fSSudeep Holla return NOTIFY_OK; 7793708d52fSSudeep Holla } 7803708d52fSSudeep Holla 7813708d52fSSudeep Holla static struct notifier_block gic_cpu_pm_notifier_block = { 7823708d52fSSudeep Holla .notifier_call = gic_cpu_pm_notifier, 7833708d52fSSudeep Holla }; 7843708d52fSSudeep Holla 7853708d52fSSudeep Holla static void gic_cpu_pm_init(void) 7863708d52fSSudeep Holla { 7873708d52fSSudeep Holla cpu_pm_register_notifier(&gic_cpu_pm_notifier_block); 7883708d52fSSudeep Holla } 7893708d52fSSudeep Holla 7903708d52fSSudeep Holla #else 7913708d52fSSudeep Holla static inline void gic_cpu_pm_init(void) { } 7923708d52fSSudeep Holla #endif /* CONFIG_CPU_PM */ 7933708d52fSSudeep Holla 794021f6537SMarc Zyngier static struct irq_chip gic_chip = { 795021f6537SMarc Zyngier .name = "GICv3", 796021f6537SMarc Zyngier .irq_mask = gic_mask_irq, 797021f6537SMarc Zyngier .irq_unmask = gic_unmask_irq, 798021f6537SMarc Zyngier .irq_eoi = gic_eoi_irq, 799021f6537SMarc Zyngier .irq_set_type = gic_set_type, 800021f6537SMarc Zyngier .irq_set_affinity = gic_set_affinity, 801b594c6e2SMarc Zyngier .irq_get_irqchip_state = gic_irq_get_irqchip_state, 802b594c6e2SMarc Zyngier .irq_set_irqchip_state = gic_irq_set_irqchip_state, 80355963c9fSSudeep Holla .flags = IRQCHIP_SET_TYPE_MASKED, 804021f6537SMarc Zyngier }; 805021f6537SMarc Zyngier 8060b6a3da9SMarc Zyngier static struct irq_chip gic_eoimode1_chip = { 8070b6a3da9SMarc Zyngier .name = "GICv3", 8080b6a3da9SMarc Zyngier .irq_mask = gic_eoimode1_mask_irq, 8090b6a3da9SMarc Zyngier .irq_unmask = gic_unmask_irq, 8100b6a3da9SMarc Zyngier .irq_eoi = gic_eoimode1_eoi_irq, 8110b6a3da9SMarc Zyngier .irq_set_type = gic_set_type, 8120b6a3da9SMarc Zyngier .irq_set_affinity = gic_set_affinity, 8130b6a3da9SMarc Zyngier .irq_get_irqchip_state = gic_irq_get_irqchip_state, 8140b6a3da9SMarc Zyngier .irq_set_irqchip_state = gic_irq_set_irqchip_state, 815530bf353SMarc Zyngier .irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity, 8160b6a3da9SMarc Zyngier .flags = IRQCHIP_SET_TYPE_MASKED, 8170b6a3da9SMarc Zyngier }; 8180b6a3da9SMarc Zyngier 819da33f31dSMarc Zyngier #define GIC_ID_NR (1U << gic_data.rdists.id_bits) 820da33f31dSMarc Zyngier 821021f6537SMarc Zyngier static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq, 822021f6537SMarc Zyngier irq_hw_number_t hw) 823021f6537SMarc Zyngier { 8240b6a3da9SMarc Zyngier struct irq_chip *chip = &gic_chip; 8250b6a3da9SMarc Zyngier 8260b6a3da9SMarc Zyngier if (static_key_true(&supports_deactivate)) 8270b6a3da9SMarc Zyngier chip = &gic_eoimode1_chip; 8280b6a3da9SMarc Zyngier 829021f6537SMarc Zyngier /* SGIs are private to the core kernel */ 830021f6537SMarc Zyngier if (hw < 16) 831021f6537SMarc Zyngier return -EPERM; 832da33f31dSMarc Zyngier /* Nothing here */ 833da33f31dSMarc Zyngier if (hw >= gic_data.irq_nr && hw < 8192) 834da33f31dSMarc Zyngier return -EPERM; 835da33f31dSMarc Zyngier /* Off limits */ 836da33f31dSMarc Zyngier if (hw >= GIC_ID_NR) 837da33f31dSMarc Zyngier return -EPERM; 838da33f31dSMarc Zyngier 839021f6537SMarc Zyngier /* PPIs */ 840021f6537SMarc Zyngier if (hw < 32) { 841021f6537SMarc Zyngier irq_set_percpu_devid(irq); 8420b6a3da9SMarc Zyngier irq_domain_set_info(d, irq, hw, chip, d->host_data, 843443acc4fSMarc Zyngier handle_percpu_devid_irq, NULL, NULL); 844d17cab44SRob Herring irq_set_status_flags(irq, IRQ_NOAUTOEN); 845021f6537SMarc Zyngier } 846021f6537SMarc Zyngier /* SPIs */ 847021f6537SMarc Zyngier if (hw >= 32 && hw < gic_data.irq_nr) { 8480b6a3da9SMarc Zyngier irq_domain_set_info(d, irq, hw, chip, d->host_data, 849443acc4fSMarc Zyngier handle_fasteoi_irq, NULL, NULL); 850d17cab44SRob Herring irq_set_probe(irq); 851956ae91aSMarc Zyngier irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(irq))); 852021f6537SMarc Zyngier } 853da33f31dSMarc Zyngier /* LPIs */ 854da33f31dSMarc Zyngier if (hw >= 8192 && hw < GIC_ID_NR) { 855da33f31dSMarc Zyngier if (!gic_dist_supports_lpis()) 856da33f31dSMarc Zyngier return -EPERM; 8570b6a3da9SMarc Zyngier irq_domain_set_info(d, irq, hw, chip, d->host_data, 858da33f31dSMarc Zyngier handle_fasteoi_irq, NULL, NULL); 859da33f31dSMarc Zyngier } 860da33f31dSMarc Zyngier 861021f6537SMarc Zyngier return 0; 862021f6537SMarc Zyngier } 863021f6537SMarc Zyngier 864f833f57fSMarc Zyngier static int gic_irq_domain_translate(struct irq_domain *d, 865f833f57fSMarc Zyngier struct irq_fwspec *fwspec, 866f833f57fSMarc Zyngier unsigned long *hwirq, 867f833f57fSMarc Zyngier unsigned int *type) 868021f6537SMarc Zyngier { 869f833f57fSMarc Zyngier if (is_of_node(fwspec->fwnode)) { 870f833f57fSMarc Zyngier if (fwspec->param_count < 3) 871021f6537SMarc Zyngier return -EINVAL; 872021f6537SMarc Zyngier 873db8c70ecSMarc Zyngier switch (fwspec->param[0]) { 874db8c70ecSMarc Zyngier case 0: /* SPI */ 875db8c70ecSMarc Zyngier *hwirq = fwspec->param[1] + 32; 876db8c70ecSMarc Zyngier break; 877db8c70ecSMarc Zyngier case 1: /* PPI */ 878f833f57fSMarc Zyngier *hwirq = fwspec->param[1] + 16; 879db8c70ecSMarc Zyngier break; 880db8c70ecSMarc Zyngier case GIC_IRQ_TYPE_LPI: /* LPI */ 881db8c70ecSMarc Zyngier *hwirq = fwspec->param[1]; 882db8c70ecSMarc Zyngier break; 883db8c70ecSMarc Zyngier default: 884db8c70ecSMarc Zyngier return -EINVAL; 885db8c70ecSMarc Zyngier } 886f833f57fSMarc Zyngier 887f833f57fSMarc Zyngier *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; 888f833f57fSMarc Zyngier return 0; 889021f6537SMarc Zyngier } 890021f6537SMarc Zyngier 891ffa7d616STomasz Nowicki if (is_fwnode_irqchip(fwspec->fwnode)) { 892ffa7d616STomasz Nowicki if(fwspec->param_count != 2) 893ffa7d616STomasz Nowicki return -EINVAL; 894ffa7d616STomasz Nowicki 895ffa7d616STomasz Nowicki *hwirq = fwspec->param[0]; 896ffa7d616STomasz Nowicki *type = fwspec->param[1]; 897ffa7d616STomasz Nowicki return 0; 898ffa7d616STomasz Nowicki } 899ffa7d616STomasz Nowicki 900f833f57fSMarc Zyngier return -EINVAL; 901021f6537SMarc Zyngier } 902021f6537SMarc Zyngier 903443acc4fSMarc Zyngier static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, 904443acc4fSMarc Zyngier unsigned int nr_irqs, void *arg) 905443acc4fSMarc Zyngier { 906443acc4fSMarc Zyngier int i, ret; 907443acc4fSMarc Zyngier irq_hw_number_t hwirq; 908443acc4fSMarc Zyngier unsigned int type = IRQ_TYPE_NONE; 909f833f57fSMarc Zyngier struct irq_fwspec *fwspec = arg; 910443acc4fSMarc Zyngier 911f833f57fSMarc Zyngier ret = gic_irq_domain_translate(domain, fwspec, &hwirq, &type); 912443acc4fSMarc Zyngier if (ret) 913443acc4fSMarc Zyngier return ret; 914443acc4fSMarc Zyngier 91563c16c6eSSuzuki K Poulose for (i = 0; i < nr_irqs; i++) { 91663c16c6eSSuzuki K Poulose ret = gic_irq_domain_map(domain, virq + i, hwirq + i); 91763c16c6eSSuzuki K Poulose if (ret) 91863c16c6eSSuzuki K Poulose return ret; 91963c16c6eSSuzuki K Poulose } 920443acc4fSMarc Zyngier 921443acc4fSMarc Zyngier return 0; 922443acc4fSMarc Zyngier } 923443acc4fSMarc Zyngier 924443acc4fSMarc Zyngier static void gic_irq_domain_free(struct irq_domain *domain, unsigned int virq, 925443acc4fSMarc Zyngier unsigned int nr_irqs) 926443acc4fSMarc Zyngier { 927443acc4fSMarc Zyngier int i; 928443acc4fSMarc Zyngier 929443acc4fSMarc Zyngier for (i = 0; i < nr_irqs; i++) { 930443acc4fSMarc Zyngier struct irq_data *d = irq_domain_get_irq_data(domain, virq + i); 931443acc4fSMarc Zyngier irq_set_handler(virq + i, NULL); 932443acc4fSMarc Zyngier irq_domain_reset_irq_data(d); 933443acc4fSMarc Zyngier } 934443acc4fSMarc Zyngier } 935443acc4fSMarc Zyngier 936e3825ba1SMarc Zyngier static int gic_irq_domain_select(struct irq_domain *d, 937e3825ba1SMarc Zyngier struct irq_fwspec *fwspec, 938e3825ba1SMarc Zyngier enum irq_domain_bus_token bus_token) 939e3825ba1SMarc Zyngier { 940e3825ba1SMarc Zyngier /* Not for us */ 941e3825ba1SMarc Zyngier if (fwspec->fwnode != d->fwnode) 942e3825ba1SMarc Zyngier return 0; 943e3825ba1SMarc Zyngier 944e3825ba1SMarc Zyngier /* If this is not DT, then we have a single domain */ 945e3825ba1SMarc Zyngier if (!is_of_node(fwspec->fwnode)) 946e3825ba1SMarc Zyngier return 1; 947e3825ba1SMarc Zyngier 948e3825ba1SMarc Zyngier /* 949e3825ba1SMarc Zyngier * If this is a PPI and we have a 4th (non-null) parameter, 950e3825ba1SMarc Zyngier * then we need to match the partition domain. 951e3825ba1SMarc Zyngier */ 952e3825ba1SMarc Zyngier if (fwspec->param_count >= 4 && 953e3825ba1SMarc Zyngier fwspec->param[0] == 1 && fwspec->param[3] != 0) 954e3825ba1SMarc Zyngier return d == partition_get_domain(gic_data.ppi_descs[fwspec->param[1]]); 955e3825ba1SMarc Zyngier 956e3825ba1SMarc Zyngier return d == gic_data.domain; 957e3825ba1SMarc Zyngier } 958e3825ba1SMarc Zyngier 959021f6537SMarc Zyngier static const struct irq_domain_ops gic_irq_domain_ops = { 960f833f57fSMarc Zyngier .translate = gic_irq_domain_translate, 961443acc4fSMarc Zyngier .alloc = gic_irq_domain_alloc, 962443acc4fSMarc Zyngier .free = gic_irq_domain_free, 963e3825ba1SMarc Zyngier .select = gic_irq_domain_select, 964e3825ba1SMarc Zyngier }; 965e3825ba1SMarc Zyngier 966e3825ba1SMarc Zyngier static int partition_domain_translate(struct irq_domain *d, 967e3825ba1SMarc Zyngier struct irq_fwspec *fwspec, 968e3825ba1SMarc Zyngier unsigned long *hwirq, 969e3825ba1SMarc Zyngier unsigned int *type) 970e3825ba1SMarc Zyngier { 971e3825ba1SMarc Zyngier struct device_node *np; 972e3825ba1SMarc Zyngier int ret; 973e3825ba1SMarc Zyngier 974e3825ba1SMarc Zyngier np = of_find_node_by_phandle(fwspec->param[3]); 975e3825ba1SMarc Zyngier if (WARN_ON(!np)) 976e3825ba1SMarc Zyngier return -EINVAL; 977e3825ba1SMarc Zyngier 978e3825ba1SMarc Zyngier ret = partition_translate_id(gic_data.ppi_descs[fwspec->param[1]], 979e3825ba1SMarc Zyngier of_node_to_fwnode(np)); 980e3825ba1SMarc Zyngier if (ret < 0) 981e3825ba1SMarc Zyngier return ret; 982e3825ba1SMarc Zyngier 983e3825ba1SMarc Zyngier *hwirq = ret; 984e3825ba1SMarc Zyngier *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; 985e3825ba1SMarc Zyngier 986e3825ba1SMarc Zyngier return 0; 987e3825ba1SMarc Zyngier } 988e3825ba1SMarc Zyngier 989e3825ba1SMarc Zyngier static const struct irq_domain_ops partition_domain_ops = { 990e3825ba1SMarc Zyngier .translate = partition_domain_translate, 991e3825ba1SMarc Zyngier .select = gic_irq_domain_select, 992021f6537SMarc Zyngier }; 993021f6537SMarc Zyngier 994db57d746STomasz Nowicki static int __init gic_init_bases(void __iomem *dist_base, 995db57d746STomasz Nowicki struct redist_region *rdist_regs, 996db57d746STomasz Nowicki u32 nr_redist_regions, 997db57d746STomasz Nowicki u64 redist_stride, 998db57d746STomasz Nowicki struct fwnode_handle *handle) 999db57d746STomasz Nowicki { 1000db57d746STomasz Nowicki u32 typer; 1001db57d746STomasz Nowicki int gic_irqs; 1002db57d746STomasz Nowicki int err; 1003db57d746STomasz Nowicki 1004db57d746STomasz Nowicki if (!is_hyp_mode_available()) 1005db57d746STomasz Nowicki static_key_slow_dec(&supports_deactivate); 1006db57d746STomasz Nowicki 1007db57d746STomasz Nowicki if (static_key_true(&supports_deactivate)) 1008db57d746STomasz Nowicki pr_info("GIC: Using split EOI/Deactivate mode\n"); 1009db57d746STomasz Nowicki 1010e3825ba1SMarc Zyngier gic_data.fwnode = handle; 1011db57d746STomasz Nowicki gic_data.dist_base = dist_base; 1012db57d746STomasz Nowicki gic_data.redist_regions = rdist_regs; 1013db57d746STomasz Nowicki gic_data.nr_redist_regions = nr_redist_regions; 1014db57d746STomasz Nowicki gic_data.redist_stride = redist_stride; 1015db57d746STomasz Nowicki 1016db57d746STomasz Nowicki /* 1017db57d746STomasz Nowicki * Find out how many interrupts are supported. 1018db57d746STomasz Nowicki * The GIC only supports up to 1020 interrupt sources (SGI+PPI+SPI) 1019db57d746STomasz Nowicki */ 1020db57d746STomasz Nowicki typer = readl_relaxed(gic_data.dist_base + GICD_TYPER); 1021db57d746STomasz Nowicki gic_data.rdists.id_bits = GICD_TYPER_ID_BITS(typer); 1022db57d746STomasz Nowicki gic_irqs = GICD_TYPER_IRQS(typer); 1023db57d746STomasz Nowicki if (gic_irqs > 1020) 1024db57d746STomasz Nowicki gic_irqs = 1020; 1025db57d746STomasz Nowicki gic_data.irq_nr = gic_irqs; 1026db57d746STomasz Nowicki 1027db57d746STomasz Nowicki gic_data.domain = irq_domain_create_tree(handle, &gic_irq_domain_ops, 1028db57d746STomasz Nowicki &gic_data); 1029db57d746STomasz Nowicki gic_data.rdists.rdist = alloc_percpu(typeof(*gic_data.rdists.rdist)); 10300edc23eaSMarc Zyngier gic_data.rdists.has_vlpis = true; 10310edc23eaSMarc Zyngier gic_data.rdists.has_direct_lpi = true; 1032db57d746STomasz Nowicki 1033db57d746STomasz Nowicki if (WARN_ON(!gic_data.domain) || WARN_ON(!gic_data.rdists.rdist)) { 1034db57d746STomasz Nowicki err = -ENOMEM; 1035db57d746STomasz Nowicki goto out_free; 1036db57d746STomasz Nowicki } 1037db57d746STomasz Nowicki 1038eda0d04aSShanker Donthineni gic_data.has_rss = !!(typer & GICD_TYPER_RSS); 1039eda0d04aSShanker Donthineni pr_info("Distributor has %sRange Selector support\n", 1040eda0d04aSShanker Donthineni gic_data.has_rss ? "" : "no "); 1041eda0d04aSShanker Donthineni 1042db57d746STomasz Nowicki set_handle_irq(gic_handle_irq); 1043db57d746STomasz Nowicki 10440edc23eaSMarc Zyngier gic_update_vlpi_properties(); 10450edc23eaSMarc Zyngier 1046db40f0a7STomasz Nowicki if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis()) 1047db40f0a7STomasz Nowicki its_init(handle, &gic_data.rdists, gic_data.domain); 1048db57d746STomasz Nowicki 1049db57d746STomasz Nowicki gic_smp_init(); 1050db57d746STomasz Nowicki gic_dist_init(); 1051db57d746STomasz Nowicki gic_cpu_init(); 1052db57d746STomasz Nowicki gic_cpu_pm_init(); 1053db57d746STomasz Nowicki 1054db57d746STomasz Nowicki return 0; 1055db57d746STomasz Nowicki 1056db57d746STomasz Nowicki out_free: 1057db57d746STomasz Nowicki if (gic_data.domain) 1058db57d746STomasz Nowicki irq_domain_remove(gic_data.domain); 1059db57d746STomasz Nowicki free_percpu(gic_data.rdists.rdist); 1060db57d746STomasz Nowicki return err; 1061db57d746STomasz Nowicki } 1062db57d746STomasz Nowicki 1063db57d746STomasz Nowicki static int __init gic_validate_dist_version(void __iomem *dist_base) 1064db57d746STomasz Nowicki { 1065db57d746STomasz Nowicki u32 reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK; 1066db57d746STomasz Nowicki 1067db57d746STomasz Nowicki if (reg != GIC_PIDR2_ARCH_GICv3 && reg != GIC_PIDR2_ARCH_GICv4) 1068db57d746STomasz Nowicki return -ENODEV; 1069db57d746STomasz Nowicki 1070db57d746STomasz Nowicki return 0; 1071db57d746STomasz Nowicki } 1072db57d746STomasz Nowicki 1073e3825ba1SMarc Zyngier static int get_cpu_number(struct device_node *dn) 1074e3825ba1SMarc Zyngier { 1075e3825ba1SMarc Zyngier const __be32 *cell; 1076e3825ba1SMarc Zyngier u64 hwid; 10773fad4cdaSzijun_hu int cpu; 1078e3825ba1SMarc Zyngier 1079e3825ba1SMarc Zyngier cell = of_get_property(dn, "reg", NULL); 1080e3825ba1SMarc Zyngier if (!cell) 1081e3825ba1SMarc Zyngier return -1; 1082e3825ba1SMarc Zyngier 1083e3825ba1SMarc Zyngier hwid = of_read_number(cell, of_n_addr_cells(dn)); 1084e3825ba1SMarc Zyngier 1085e3825ba1SMarc Zyngier /* 1086e3825ba1SMarc Zyngier * Non affinity bits must be set to 0 in the DT 1087e3825ba1SMarc Zyngier */ 1088e3825ba1SMarc Zyngier if (hwid & ~MPIDR_HWID_BITMASK) 1089e3825ba1SMarc Zyngier return -1; 1090e3825ba1SMarc Zyngier 10913fad4cdaSzijun_hu for_each_possible_cpu(cpu) 10923fad4cdaSzijun_hu if (cpu_logical_map(cpu) == hwid) 10933fad4cdaSzijun_hu return cpu; 1094e3825ba1SMarc Zyngier 1095e3825ba1SMarc Zyngier return -1; 1096e3825ba1SMarc Zyngier } 1097e3825ba1SMarc Zyngier 1098e3825ba1SMarc Zyngier /* Create all possible partitions at boot time */ 10997beaa24bSLinus Torvalds static void __init gic_populate_ppi_partitions(struct device_node *gic_node) 1100e3825ba1SMarc Zyngier { 1101e3825ba1SMarc Zyngier struct device_node *parts_node, *child_part; 1102e3825ba1SMarc Zyngier int part_idx = 0, i; 1103e3825ba1SMarc Zyngier int nr_parts; 1104e3825ba1SMarc Zyngier struct partition_affinity *parts; 1105e3825ba1SMarc Zyngier 110600ee9a1cSJohan Hovold parts_node = of_get_child_by_name(gic_node, "ppi-partitions"); 1107e3825ba1SMarc Zyngier if (!parts_node) 1108e3825ba1SMarc Zyngier return; 1109e3825ba1SMarc Zyngier 1110e3825ba1SMarc Zyngier nr_parts = of_get_child_count(parts_node); 1111e3825ba1SMarc Zyngier 1112e3825ba1SMarc Zyngier if (!nr_parts) 111300ee9a1cSJohan Hovold goto out_put_node; 1114e3825ba1SMarc Zyngier 1115e3825ba1SMarc Zyngier parts = kzalloc(sizeof(*parts) * nr_parts, GFP_KERNEL); 1116e3825ba1SMarc Zyngier if (WARN_ON(!parts)) 111700ee9a1cSJohan Hovold goto out_put_node; 1118e3825ba1SMarc Zyngier 1119e3825ba1SMarc Zyngier for_each_child_of_node(parts_node, child_part) { 1120e3825ba1SMarc Zyngier struct partition_affinity *part; 1121e3825ba1SMarc Zyngier int n; 1122e3825ba1SMarc Zyngier 1123e3825ba1SMarc Zyngier part = &parts[part_idx]; 1124e3825ba1SMarc Zyngier 1125e3825ba1SMarc Zyngier part->partition_id = of_node_to_fwnode(child_part); 1126e3825ba1SMarc Zyngier 1127e3825ba1SMarc Zyngier pr_info("GIC: PPI partition %s[%d] { ", 1128e3825ba1SMarc Zyngier child_part->name, part_idx); 1129e3825ba1SMarc Zyngier 1130e3825ba1SMarc Zyngier n = of_property_count_elems_of_size(child_part, "affinity", 1131e3825ba1SMarc Zyngier sizeof(u32)); 1132e3825ba1SMarc Zyngier WARN_ON(n <= 0); 1133e3825ba1SMarc Zyngier 1134e3825ba1SMarc Zyngier for (i = 0; i < n; i++) { 1135e3825ba1SMarc Zyngier int err, cpu; 1136e3825ba1SMarc Zyngier u32 cpu_phandle; 1137e3825ba1SMarc Zyngier struct device_node *cpu_node; 1138e3825ba1SMarc Zyngier 1139e3825ba1SMarc Zyngier err = of_property_read_u32_index(child_part, "affinity", 1140e3825ba1SMarc Zyngier i, &cpu_phandle); 1141e3825ba1SMarc Zyngier if (WARN_ON(err)) 1142e3825ba1SMarc Zyngier continue; 1143e3825ba1SMarc Zyngier 1144e3825ba1SMarc Zyngier cpu_node = of_find_node_by_phandle(cpu_phandle); 1145e3825ba1SMarc Zyngier if (WARN_ON(!cpu_node)) 1146e3825ba1SMarc Zyngier continue; 1147e3825ba1SMarc Zyngier 1148e3825ba1SMarc Zyngier cpu = get_cpu_number(cpu_node); 1149e3825ba1SMarc Zyngier if (WARN_ON(cpu == -1)) 1150e3825ba1SMarc Zyngier continue; 1151e3825ba1SMarc Zyngier 1152e81f54c6SRob Herring pr_cont("%pOF[%d] ", cpu_node, cpu); 1153e3825ba1SMarc Zyngier 1154e3825ba1SMarc Zyngier cpumask_set_cpu(cpu, &part->mask); 1155e3825ba1SMarc Zyngier } 1156e3825ba1SMarc Zyngier 1157e3825ba1SMarc Zyngier pr_cont("}\n"); 1158e3825ba1SMarc Zyngier part_idx++; 1159e3825ba1SMarc Zyngier } 1160e3825ba1SMarc Zyngier 1161e3825ba1SMarc Zyngier for (i = 0; i < 16; i++) { 1162e3825ba1SMarc Zyngier unsigned int irq; 1163e3825ba1SMarc Zyngier struct partition_desc *desc; 1164e3825ba1SMarc Zyngier struct irq_fwspec ppi_fwspec = { 1165e3825ba1SMarc Zyngier .fwnode = gic_data.fwnode, 1166e3825ba1SMarc Zyngier .param_count = 3, 1167e3825ba1SMarc Zyngier .param = { 1168e3825ba1SMarc Zyngier [0] = 1, 1169e3825ba1SMarc Zyngier [1] = i, 1170e3825ba1SMarc Zyngier [2] = IRQ_TYPE_NONE, 1171e3825ba1SMarc Zyngier }, 1172e3825ba1SMarc Zyngier }; 1173e3825ba1SMarc Zyngier 1174e3825ba1SMarc Zyngier irq = irq_create_fwspec_mapping(&ppi_fwspec); 1175e3825ba1SMarc Zyngier if (WARN_ON(!irq)) 1176e3825ba1SMarc Zyngier continue; 1177e3825ba1SMarc Zyngier desc = partition_create_desc(gic_data.fwnode, parts, nr_parts, 1178e3825ba1SMarc Zyngier irq, &partition_domain_ops); 1179e3825ba1SMarc Zyngier if (WARN_ON(!desc)) 1180e3825ba1SMarc Zyngier continue; 1181e3825ba1SMarc Zyngier 1182e3825ba1SMarc Zyngier gic_data.ppi_descs[i] = desc; 1183e3825ba1SMarc Zyngier } 118400ee9a1cSJohan Hovold 118500ee9a1cSJohan Hovold out_put_node: 118600ee9a1cSJohan Hovold of_node_put(parts_node); 1187e3825ba1SMarc Zyngier } 1188e3825ba1SMarc Zyngier 11891839e576SJulien Grall static void __init gic_of_setup_kvm_info(struct device_node *node) 11901839e576SJulien Grall { 11911839e576SJulien Grall int ret; 11921839e576SJulien Grall struct resource r; 11931839e576SJulien Grall u32 gicv_idx; 11941839e576SJulien Grall 11951839e576SJulien Grall gic_v3_kvm_info.type = GIC_V3; 11961839e576SJulien Grall 11971839e576SJulien Grall gic_v3_kvm_info.maint_irq = irq_of_parse_and_map(node, 0); 11981839e576SJulien Grall if (!gic_v3_kvm_info.maint_irq) 11991839e576SJulien Grall return; 12001839e576SJulien Grall 12011839e576SJulien Grall if (of_property_read_u32(node, "#redistributor-regions", 12021839e576SJulien Grall &gicv_idx)) 12031839e576SJulien Grall gicv_idx = 1; 12041839e576SJulien Grall 12051839e576SJulien Grall gicv_idx += 3; /* Also skip GICD, GICC, GICH */ 12061839e576SJulien Grall ret = of_address_to_resource(node, gicv_idx, &r); 12071839e576SJulien Grall if (!ret) 12081839e576SJulien Grall gic_v3_kvm_info.vcpu = r; 12091839e576SJulien Grall 12104bdf5025SMarc Zyngier gic_v3_kvm_info.has_v4 = gic_data.rdists.has_vlpis; 12111839e576SJulien Grall gic_set_kvm_info(&gic_v3_kvm_info); 12121839e576SJulien Grall } 12131839e576SJulien Grall 1214021f6537SMarc Zyngier static int __init gic_of_init(struct device_node *node, struct device_node *parent) 1215021f6537SMarc Zyngier { 1216021f6537SMarc Zyngier void __iomem *dist_base; 1217f5c1434cSMarc Zyngier struct redist_region *rdist_regs; 1218021f6537SMarc Zyngier u64 redist_stride; 1219f5c1434cSMarc Zyngier u32 nr_redist_regions; 1220db57d746STomasz Nowicki int err, i; 1221021f6537SMarc Zyngier 1222021f6537SMarc Zyngier dist_base = of_iomap(node, 0); 1223021f6537SMarc Zyngier if (!dist_base) { 1224e81f54c6SRob Herring pr_err("%pOF: unable to map gic dist registers\n", node); 1225021f6537SMarc Zyngier return -ENXIO; 1226021f6537SMarc Zyngier } 1227021f6537SMarc Zyngier 1228db57d746STomasz Nowicki err = gic_validate_dist_version(dist_base); 1229db57d746STomasz Nowicki if (err) { 1230e81f54c6SRob Herring pr_err("%pOF: no distributor detected, giving up\n", node); 1231021f6537SMarc Zyngier goto out_unmap_dist; 1232021f6537SMarc Zyngier } 1233021f6537SMarc Zyngier 1234f5c1434cSMarc Zyngier if (of_property_read_u32(node, "#redistributor-regions", &nr_redist_regions)) 1235f5c1434cSMarc Zyngier nr_redist_regions = 1; 1236021f6537SMarc Zyngier 1237f5c1434cSMarc Zyngier rdist_regs = kzalloc(sizeof(*rdist_regs) * nr_redist_regions, GFP_KERNEL); 1238f5c1434cSMarc Zyngier if (!rdist_regs) { 1239021f6537SMarc Zyngier err = -ENOMEM; 1240021f6537SMarc Zyngier goto out_unmap_dist; 1241021f6537SMarc Zyngier } 1242021f6537SMarc Zyngier 1243f5c1434cSMarc Zyngier for (i = 0; i < nr_redist_regions; i++) { 1244f5c1434cSMarc Zyngier struct resource res; 1245f5c1434cSMarc Zyngier int ret; 1246f5c1434cSMarc Zyngier 1247f5c1434cSMarc Zyngier ret = of_address_to_resource(node, 1 + i, &res); 1248f5c1434cSMarc Zyngier rdist_regs[i].redist_base = of_iomap(node, 1 + i); 1249f5c1434cSMarc Zyngier if (ret || !rdist_regs[i].redist_base) { 1250e81f54c6SRob Herring pr_err("%pOF: couldn't map region %d\n", node, i); 1251021f6537SMarc Zyngier err = -ENODEV; 1252021f6537SMarc Zyngier goto out_unmap_rdist; 1253021f6537SMarc Zyngier } 1254f5c1434cSMarc Zyngier rdist_regs[i].phys_base = res.start; 1255021f6537SMarc Zyngier } 1256021f6537SMarc Zyngier 1257021f6537SMarc Zyngier if (of_property_read_u64(node, "redistributor-stride", &redist_stride)) 1258021f6537SMarc Zyngier redist_stride = 0; 1259021f6537SMarc Zyngier 1260db57d746STomasz Nowicki err = gic_init_bases(dist_base, rdist_regs, nr_redist_regions, 1261db57d746STomasz Nowicki redist_stride, &node->fwnode); 1262e3825ba1SMarc Zyngier if (err) 1263e3825ba1SMarc Zyngier goto out_unmap_rdist; 1264e3825ba1SMarc Zyngier 1265e3825ba1SMarc Zyngier gic_populate_ppi_partitions(node); 12661839e576SJulien Grall gic_of_setup_kvm_info(node); 1267021f6537SMarc Zyngier return 0; 1268021f6537SMarc Zyngier 1269021f6537SMarc Zyngier out_unmap_rdist: 1270f5c1434cSMarc Zyngier for (i = 0; i < nr_redist_regions; i++) 1271f5c1434cSMarc Zyngier if (rdist_regs[i].redist_base) 1272f5c1434cSMarc Zyngier iounmap(rdist_regs[i].redist_base); 1273f5c1434cSMarc Zyngier kfree(rdist_regs); 1274021f6537SMarc Zyngier out_unmap_dist: 1275021f6537SMarc Zyngier iounmap(dist_base); 1276021f6537SMarc Zyngier return err; 1277021f6537SMarc Zyngier } 1278021f6537SMarc Zyngier 1279021f6537SMarc Zyngier IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init); 1280ffa7d616STomasz Nowicki 1281ffa7d616STomasz Nowicki #ifdef CONFIG_ACPI 1282611f039fSJulien Grall static struct 1283611f039fSJulien Grall { 1284611f039fSJulien Grall void __iomem *dist_base; 1285611f039fSJulien Grall struct redist_region *redist_regs; 1286611f039fSJulien Grall u32 nr_redist_regions; 1287611f039fSJulien Grall bool single_redist; 12881839e576SJulien Grall u32 maint_irq; 12891839e576SJulien Grall int maint_irq_mode; 12901839e576SJulien Grall phys_addr_t vcpu_base; 1291611f039fSJulien Grall } acpi_data __initdata; 1292b70fb7afSTomasz Nowicki 1293b70fb7afSTomasz Nowicki static void __init 1294b70fb7afSTomasz Nowicki gic_acpi_register_redist(phys_addr_t phys_base, void __iomem *redist_base) 1295b70fb7afSTomasz Nowicki { 1296b70fb7afSTomasz Nowicki static int count = 0; 1297b70fb7afSTomasz Nowicki 1298611f039fSJulien Grall acpi_data.redist_regs[count].phys_base = phys_base; 1299611f039fSJulien Grall acpi_data.redist_regs[count].redist_base = redist_base; 1300611f039fSJulien Grall acpi_data.redist_regs[count].single_redist = acpi_data.single_redist; 1301b70fb7afSTomasz Nowicki count++; 1302b70fb7afSTomasz Nowicki } 1303ffa7d616STomasz Nowicki 1304ffa7d616STomasz Nowicki static int __init 1305ffa7d616STomasz Nowicki gic_acpi_parse_madt_redist(struct acpi_subtable_header *header, 1306ffa7d616STomasz Nowicki const unsigned long end) 1307ffa7d616STomasz Nowicki { 1308ffa7d616STomasz Nowicki struct acpi_madt_generic_redistributor *redist = 1309ffa7d616STomasz Nowicki (struct acpi_madt_generic_redistributor *)header; 1310ffa7d616STomasz Nowicki void __iomem *redist_base; 1311ffa7d616STomasz Nowicki 1312ffa7d616STomasz Nowicki redist_base = ioremap(redist->base_address, redist->length); 1313ffa7d616STomasz Nowicki if (!redist_base) { 1314ffa7d616STomasz Nowicki pr_err("Couldn't map GICR region @%llx\n", redist->base_address); 1315ffa7d616STomasz Nowicki return -ENOMEM; 1316ffa7d616STomasz Nowicki } 1317ffa7d616STomasz Nowicki 1318b70fb7afSTomasz Nowicki gic_acpi_register_redist(redist->base_address, redist_base); 1319ffa7d616STomasz Nowicki return 0; 1320ffa7d616STomasz Nowicki } 1321ffa7d616STomasz Nowicki 1322b70fb7afSTomasz Nowicki static int __init 1323b70fb7afSTomasz Nowicki gic_acpi_parse_madt_gicc(struct acpi_subtable_header *header, 1324b70fb7afSTomasz Nowicki const unsigned long end) 1325b70fb7afSTomasz Nowicki { 1326b70fb7afSTomasz Nowicki struct acpi_madt_generic_interrupt *gicc = 1327b70fb7afSTomasz Nowicki (struct acpi_madt_generic_interrupt *)header; 1328611f039fSJulien Grall u32 reg = readl_relaxed(acpi_data.dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK; 1329b70fb7afSTomasz Nowicki u32 size = reg == GIC_PIDR2_ARCH_GICv4 ? SZ_64K * 4 : SZ_64K * 2; 1330b70fb7afSTomasz Nowicki void __iomem *redist_base; 1331b70fb7afSTomasz Nowicki 1332b70fb7afSTomasz Nowicki redist_base = ioremap(gicc->gicr_base_address, size); 1333b70fb7afSTomasz Nowicki if (!redist_base) 1334b70fb7afSTomasz Nowicki return -ENOMEM; 1335b70fb7afSTomasz Nowicki 1336b70fb7afSTomasz Nowicki gic_acpi_register_redist(gicc->gicr_base_address, redist_base); 1337b70fb7afSTomasz Nowicki return 0; 1338b70fb7afSTomasz Nowicki } 1339b70fb7afSTomasz Nowicki 1340b70fb7afSTomasz Nowicki static int __init gic_acpi_collect_gicr_base(void) 1341b70fb7afSTomasz Nowicki { 1342b70fb7afSTomasz Nowicki acpi_tbl_entry_handler redist_parser; 1343b70fb7afSTomasz Nowicki enum acpi_madt_type type; 1344b70fb7afSTomasz Nowicki 1345611f039fSJulien Grall if (acpi_data.single_redist) { 1346b70fb7afSTomasz Nowicki type = ACPI_MADT_TYPE_GENERIC_INTERRUPT; 1347b70fb7afSTomasz Nowicki redist_parser = gic_acpi_parse_madt_gicc; 1348b70fb7afSTomasz Nowicki } else { 1349b70fb7afSTomasz Nowicki type = ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR; 1350b70fb7afSTomasz Nowicki redist_parser = gic_acpi_parse_madt_redist; 1351b70fb7afSTomasz Nowicki } 1352b70fb7afSTomasz Nowicki 1353b70fb7afSTomasz Nowicki /* Collect redistributor base addresses in GICR entries */ 1354b70fb7afSTomasz Nowicki if (acpi_table_parse_madt(type, redist_parser, 0) > 0) 1355b70fb7afSTomasz Nowicki return 0; 1356b70fb7afSTomasz Nowicki 1357b70fb7afSTomasz Nowicki pr_info("No valid GICR entries exist\n"); 1358b70fb7afSTomasz Nowicki return -ENODEV; 1359b70fb7afSTomasz Nowicki } 1360b70fb7afSTomasz Nowicki 1361ffa7d616STomasz Nowicki static int __init gic_acpi_match_gicr(struct acpi_subtable_header *header, 1362ffa7d616STomasz Nowicki const unsigned long end) 1363ffa7d616STomasz Nowicki { 1364ffa7d616STomasz Nowicki /* Subtable presence means that redist exists, that's it */ 1365ffa7d616STomasz Nowicki return 0; 1366ffa7d616STomasz Nowicki } 1367ffa7d616STomasz Nowicki 1368b70fb7afSTomasz Nowicki static int __init gic_acpi_match_gicc(struct acpi_subtable_header *header, 1369b70fb7afSTomasz Nowicki const unsigned long end) 1370b70fb7afSTomasz Nowicki { 1371b70fb7afSTomasz Nowicki struct acpi_madt_generic_interrupt *gicc = 1372b70fb7afSTomasz Nowicki (struct acpi_madt_generic_interrupt *)header; 1373b70fb7afSTomasz Nowicki 1374b70fb7afSTomasz Nowicki /* 1375b70fb7afSTomasz Nowicki * If GICC is enabled and has valid gicr base address, then it means 1376b70fb7afSTomasz Nowicki * GICR base is presented via GICC 1377b70fb7afSTomasz Nowicki */ 1378b70fb7afSTomasz Nowicki if ((gicc->flags & ACPI_MADT_ENABLED) && gicc->gicr_base_address) 1379b70fb7afSTomasz Nowicki return 0; 1380b70fb7afSTomasz Nowicki 1381b70fb7afSTomasz Nowicki return -ENODEV; 1382b70fb7afSTomasz Nowicki } 1383b70fb7afSTomasz Nowicki 1384b70fb7afSTomasz Nowicki static int __init gic_acpi_count_gicr_regions(void) 1385b70fb7afSTomasz Nowicki { 1386b70fb7afSTomasz Nowicki int count; 1387b70fb7afSTomasz Nowicki 1388b70fb7afSTomasz Nowicki /* 1389b70fb7afSTomasz Nowicki * Count how many redistributor regions we have. It is not allowed 1390b70fb7afSTomasz Nowicki * to mix redistributor description, GICR and GICC subtables have to be 1391b70fb7afSTomasz Nowicki * mutually exclusive. 1392b70fb7afSTomasz Nowicki */ 1393b70fb7afSTomasz Nowicki count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR, 1394b70fb7afSTomasz Nowicki gic_acpi_match_gicr, 0); 1395b70fb7afSTomasz Nowicki if (count > 0) { 1396611f039fSJulien Grall acpi_data.single_redist = false; 1397b70fb7afSTomasz Nowicki return count; 1398b70fb7afSTomasz Nowicki } 1399b70fb7afSTomasz Nowicki 1400b70fb7afSTomasz Nowicki count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT, 1401b70fb7afSTomasz Nowicki gic_acpi_match_gicc, 0); 1402b70fb7afSTomasz Nowicki if (count > 0) 1403611f039fSJulien Grall acpi_data.single_redist = true; 1404b70fb7afSTomasz Nowicki 1405b70fb7afSTomasz Nowicki return count; 1406b70fb7afSTomasz Nowicki } 1407b70fb7afSTomasz Nowicki 1408ffa7d616STomasz Nowicki static bool __init acpi_validate_gic_table(struct acpi_subtable_header *header, 1409ffa7d616STomasz Nowicki struct acpi_probe_entry *ape) 1410ffa7d616STomasz Nowicki { 1411ffa7d616STomasz Nowicki struct acpi_madt_generic_distributor *dist; 1412ffa7d616STomasz Nowicki int count; 1413ffa7d616STomasz Nowicki 1414ffa7d616STomasz Nowicki dist = (struct acpi_madt_generic_distributor *)header; 1415ffa7d616STomasz Nowicki if (dist->version != ape->driver_data) 1416ffa7d616STomasz Nowicki return false; 1417ffa7d616STomasz Nowicki 1418ffa7d616STomasz Nowicki /* We need to do that exercise anyway, the sooner the better */ 1419b70fb7afSTomasz Nowicki count = gic_acpi_count_gicr_regions(); 1420ffa7d616STomasz Nowicki if (count <= 0) 1421ffa7d616STomasz Nowicki return false; 1422ffa7d616STomasz Nowicki 1423611f039fSJulien Grall acpi_data.nr_redist_regions = count; 1424ffa7d616STomasz Nowicki return true; 1425ffa7d616STomasz Nowicki } 1426ffa7d616STomasz Nowicki 14271839e576SJulien Grall static int __init gic_acpi_parse_virt_madt_gicc(struct acpi_subtable_header *header, 14281839e576SJulien Grall const unsigned long end) 14291839e576SJulien Grall { 14301839e576SJulien Grall struct acpi_madt_generic_interrupt *gicc = 14311839e576SJulien Grall (struct acpi_madt_generic_interrupt *)header; 14321839e576SJulien Grall int maint_irq_mode; 14331839e576SJulien Grall static int first_madt = true; 14341839e576SJulien Grall 14351839e576SJulien Grall /* Skip unusable CPUs */ 14361839e576SJulien Grall if (!(gicc->flags & ACPI_MADT_ENABLED)) 14371839e576SJulien Grall return 0; 14381839e576SJulien Grall 14391839e576SJulien Grall maint_irq_mode = (gicc->flags & ACPI_MADT_VGIC_IRQ_MODE) ? 14401839e576SJulien Grall ACPI_EDGE_SENSITIVE : ACPI_LEVEL_SENSITIVE; 14411839e576SJulien Grall 14421839e576SJulien Grall if (first_madt) { 14431839e576SJulien Grall first_madt = false; 14441839e576SJulien Grall 14451839e576SJulien Grall acpi_data.maint_irq = gicc->vgic_interrupt; 14461839e576SJulien Grall acpi_data.maint_irq_mode = maint_irq_mode; 14471839e576SJulien Grall acpi_data.vcpu_base = gicc->gicv_base_address; 14481839e576SJulien Grall 14491839e576SJulien Grall return 0; 14501839e576SJulien Grall } 14511839e576SJulien Grall 14521839e576SJulien Grall /* 14531839e576SJulien Grall * The maintenance interrupt and GICV should be the same for every CPU 14541839e576SJulien Grall */ 14551839e576SJulien Grall if ((acpi_data.maint_irq != gicc->vgic_interrupt) || 14561839e576SJulien Grall (acpi_data.maint_irq_mode != maint_irq_mode) || 14571839e576SJulien Grall (acpi_data.vcpu_base != gicc->gicv_base_address)) 14581839e576SJulien Grall return -EINVAL; 14591839e576SJulien Grall 14601839e576SJulien Grall return 0; 14611839e576SJulien Grall } 14621839e576SJulien Grall 14631839e576SJulien Grall static bool __init gic_acpi_collect_virt_info(void) 14641839e576SJulien Grall { 14651839e576SJulien Grall int count; 14661839e576SJulien Grall 14671839e576SJulien Grall count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT, 14681839e576SJulien Grall gic_acpi_parse_virt_madt_gicc, 0); 14691839e576SJulien Grall 14701839e576SJulien Grall return (count > 0); 14711839e576SJulien Grall } 14721839e576SJulien Grall 1473ffa7d616STomasz Nowicki #define ACPI_GICV3_DIST_MEM_SIZE (SZ_64K) 14741839e576SJulien Grall #define ACPI_GICV2_VCTRL_MEM_SIZE (SZ_4K) 14751839e576SJulien Grall #define ACPI_GICV2_VCPU_MEM_SIZE (SZ_8K) 14761839e576SJulien Grall 14771839e576SJulien Grall static void __init gic_acpi_setup_kvm_info(void) 14781839e576SJulien Grall { 14791839e576SJulien Grall int irq; 14801839e576SJulien Grall 14811839e576SJulien Grall if (!gic_acpi_collect_virt_info()) { 14821839e576SJulien Grall pr_warn("Unable to get hardware information used for virtualization\n"); 14831839e576SJulien Grall return; 14841839e576SJulien Grall } 14851839e576SJulien Grall 14861839e576SJulien Grall gic_v3_kvm_info.type = GIC_V3; 14871839e576SJulien Grall 14881839e576SJulien Grall irq = acpi_register_gsi(NULL, acpi_data.maint_irq, 14891839e576SJulien Grall acpi_data.maint_irq_mode, 14901839e576SJulien Grall ACPI_ACTIVE_HIGH); 14911839e576SJulien Grall if (irq <= 0) 14921839e576SJulien Grall return; 14931839e576SJulien Grall 14941839e576SJulien Grall gic_v3_kvm_info.maint_irq = irq; 14951839e576SJulien Grall 14961839e576SJulien Grall if (acpi_data.vcpu_base) { 14971839e576SJulien Grall struct resource *vcpu = &gic_v3_kvm_info.vcpu; 14981839e576SJulien Grall 14991839e576SJulien Grall vcpu->flags = IORESOURCE_MEM; 15001839e576SJulien Grall vcpu->start = acpi_data.vcpu_base; 15011839e576SJulien Grall vcpu->end = vcpu->start + ACPI_GICV2_VCPU_MEM_SIZE - 1; 15021839e576SJulien Grall } 15031839e576SJulien Grall 15044bdf5025SMarc Zyngier gic_v3_kvm_info.has_v4 = gic_data.rdists.has_vlpis; 15051839e576SJulien Grall gic_set_kvm_info(&gic_v3_kvm_info); 15061839e576SJulien Grall } 1507ffa7d616STomasz Nowicki 1508ffa7d616STomasz Nowicki static int __init 1509ffa7d616STomasz Nowicki gic_acpi_init(struct acpi_subtable_header *header, const unsigned long end) 1510ffa7d616STomasz Nowicki { 1511ffa7d616STomasz Nowicki struct acpi_madt_generic_distributor *dist; 1512ffa7d616STomasz Nowicki struct fwnode_handle *domain_handle; 1513611f039fSJulien Grall size_t size; 1514b70fb7afSTomasz Nowicki int i, err; 1515ffa7d616STomasz Nowicki 1516ffa7d616STomasz Nowicki /* Get distributor base address */ 1517ffa7d616STomasz Nowicki dist = (struct acpi_madt_generic_distributor *)header; 1518611f039fSJulien Grall acpi_data.dist_base = ioremap(dist->base_address, 1519611f039fSJulien Grall ACPI_GICV3_DIST_MEM_SIZE); 1520611f039fSJulien Grall if (!acpi_data.dist_base) { 1521ffa7d616STomasz Nowicki pr_err("Unable to map GICD registers\n"); 1522ffa7d616STomasz Nowicki return -ENOMEM; 1523ffa7d616STomasz Nowicki } 1524ffa7d616STomasz Nowicki 1525611f039fSJulien Grall err = gic_validate_dist_version(acpi_data.dist_base); 1526ffa7d616STomasz Nowicki if (err) { 152771192a68SArvind Yadav pr_err("No distributor detected at @%p, giving up\n", 1528611f039fSJulien Grall acpi_data.dist_base); 1529ffa7d616STomasz Nowicki goto out_dist_unmap; 1530ffa7d616STomasz Nowicki } 1531ffa7d616STomasz Nowicki 1532611f039fSJulien Grall size = sizeof(*acpi_data.redist_regs) * acpi_data.nr_redist_regions; 1533611f039fSJulien Grall acpi_data.redist_regs = kzalloc(size, GFP_KERNEL); 1534611f039fSJulien Grall if (!acpi_data.redist_regs) { 1535ffa7d616STomasz Nowicki err = -ENOMEM; 1536ffa7d616STomasz Nowicki goto out_dist_unmap; 1537ffa7d616STomasz Nowicki } 1538ffa7d616STomasz Nowicki 1539b70fb7afSTomasz Nowicki err = gic_acpi_collect_gicr_base(); 1540b70fb7afSTomasz Nowicki if (err) 1541ffa7d616STomasz Nowicki goto out_redist_unmap; 1542ffa7d616STomasz Nowicki 1543611f039fSJulien Grall domain_handle = irq_domain_alloc_fwnode(acpi_data.dist_base); 1544ffa7d616STomasz Nowicki if (!domain_handle) { 1545ffa7d616STomasz Nowicki err = -ENOMEM; 1546ffa7d616STomasz Nowicki goto out_redist_unmap; 1547ffa7d616STomasz Nowicki } 1548ffa7d616STomasz Nowicki 1549611f039fSJulien Grall err = gic_init_bases(acpi_data.dist_base, acpi_data.redist_regs, 1550611f039fSJulien Grall acpi_data.nr_redist_regions, 0, domain_handle); 1551ffa7d616STomasz Nowicki if (err) 1552ffa7d616STomasz Nowicki goto out_fwhandle_free; 1553ffa7d616STomasz Nowicki 1554ffa7d616STomasz Nowicki acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, domain_handle); 15551839e576SJulien Grall gic_acpi_setup_kvm_info(); 15561839e576SJulien Grall 1557ffa7d616STomasz Nowicki return 0; 1558ffa7d616STomasz Nowicki 1559ffa7d616STomasz Nowicki out_fwhandle_free: 1560ffa7d616STomasz Nowicki irq_domain_free_fwnode(domain_handle); 1561ffa7d616STomasz Nowicki out_redist_unmap: 1562611f039fSJulien Grall for (i = 0; i < acpi_data.nr_redist_regions; i++) 1563611f039fSJulien Grall if (acpi_data.redist_regs[i].redist_base) 1564611f039fSJulien Grall iounmap(acpi_data.redist_regs[i].redist_base); 1565611f039fSJulien Grall kfree(acpi_data.redist_regs); 1566ffa7d616STomasz Nowicki out_dist_unmap: 1567611f039fSJulien Grall iounmap(acpi_data.dist_base); 1568ffa7d616STomasz Nowicki return err; 1569ffa7d616STomasz Nowicki } 1570ffa7d616STomasz Nowicki IRQCHIP_ACPI_DECLARE(gic_v3, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 1571ffa7d616STomasz Nowicki acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V3, 1572ffa7d616STomasz Nowicki gic_acpi_init); 1573ffa7d616STomasz Nowicki IRQCHIP_ACPI_DECLARE(gic_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 1574ffa7d616STomasz Nowicki acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V4, 1575ffa7d616STomasz Nowicki gic_acpi_init); 1576ffa7d616STomasz Nowicki IRQCHIP_ACPI_DECLARE(gic_v3_or_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 1577ffa7d616STomasz Nowicki acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_NONE, 1578ffa7d616STomasz Nowicki gic_acpi_init); 1579ffa7d616STomasz Nowicki #endif 1580