1021f6537SMarc Zyngier /* 2021f6537SMarc Zyngier * Copyright (C) 2013, 2014 ARM Limited, All Rights Reserved. 3021f6537SMarc Zyngier * Author: Marc Zyngier <marc.zyngier@arm.com> 4021f6537SMarc Zyngier * 5021f6537SMarc Zyngier * This program is free software; you can redistribute it and/or modify 6021f6537SMarc Zyngier * it under the terms of the GNU General Public License version 2 as 7021f6537SMarc Zyngier * published by the Free Software Foundation. 8021f6537SMarc Zyngier * 9021f6537SMarc Zyngier * This program is distributed in the hope that it will be useful, 10021f6537SMarc Zyngier * but WITHOUT ANY WARRANTY; without even the implied warranty of 11021f6537SMarc Zyngier * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12021f6537SMarc Zyngier * GNU General Public License for more details. 13021f6537SMarc Zyngier * 14021f6537SMarc Zyngier * You should have received a copy of the GNU General Public License 15021f6537SMarc Zyngier * along with this program. If not, see <http://www.gnu.org/licenses/>. 16021f6537SMarc Zyngier */ 17021f6537SMarc Zyngier 1868628bb8SJulien Grall #define pr_fmt(fmt) "GICv3: " fmt 1968628bb8SJulien Grall 20ffa7d616STomasz Nowicki #include <linux/acpi.h> 21021f6537SMarc Zyngier #include <linux/cpu.h> 223708d52fSSudeep Holla #include <linux/cpu_pm.h> 23021f6537SMarc Zyngier #include <linux/delay.h> 24021f6537SMarc Zyngier #include <linux/interrupt.h> 25ffa7d616STomasz Nowicki #include <linux/irqdomain.h> 26021f6537SMarc Zyngier #include <linux/of.h> 27021f6537SMarc Zyngier #include <linux/of_address.h> 28021f6537SMarc Zyngier #include <linux/of_irq.h> 29021f6537SMarc Zyngier #include <linux/percpu.h> 30021f6537SMarc Zyngier #include <linux/slab.h> 31021f6537SMarc Zyngier 3241a83e06SJoel Porquet #include <linux/irqchip.h> 331839e576SJulien Grall #include <linux/irqchip/arm-gic-common.h> 34021f6537SMarc Zyngier #include <linux/irqchip/arm-gic-v3.h> 35e3825ba1SMarc Zyngier #include <linux/irqchip/irq-partition-percpu.h> 36021f6537SMarc Zyngier 37021f6537SMarc Zyngier #include <asm/cputype.h> 38021f6537SMarc Zyngier #include <asm/exception.h> 39021f6537SMarc Zyngier #include <asm/smp_plat.h> 400b6a3da9SMarc Zyngier #include <asm/virt.h> 41021f6537SMarc Zyngier 42021f6537SMarc Zyngier #include "irq-gic-common.h" 43021f6537SMarc Zyngier 44f5c1434cSMarc Zyngier struct redist_region { 45f5c1434cSMarc Zyngier void __iomem *redist_base; 46f5c1434cSMarc Zyngier phys_addr_t phys_base; 47b70fb7afSTomasz Nowicki bool single_redist; 48f5c1434cSMarc Zyngier }; 49f5c1434cSMarc Zyngier 50021f6537SMarc Zyngier struct gic_chip_data { 51e3825ba1SMarc Zyngier struct fwnode_handle *fwnode; 52021f6537SMarc Zyngier void __iomem *dist_base; 53f5c1434cSMarc Zyngier struct redist_region *redist_regions; 54f5c1434cSMarc Zyngier struct rdists rdists; 55021f6537SMarc Zyngier struct irq_domain *domain; 56021f6537SMarc Zyngier u64 redist_stride; 57f5c1434cSMarc Zyngier u32 nr_redist_regions; 58021f6537SMarc Zyngier unsigned int irq_nr; 59e3825ba1SMarc Zyngier struct partition_desc *ppi_descs[16]; 60021f6537SMarc Zyngier }; 61021f6537SMarc Zyngier 62021f6537SMarc Zyngier static struct gic_chip_data gic_data __read_mostly; 630b6a3da9SMarc Zyngier static struct static_key supports_deactivate = STATIC_KEY_INIT_TRUE; 64021f6537SMarc Zyngier 651839e576SJulien Grall static struct gic_kvm_info gic_v3_kvm_info; 661839e576SJulien Grall 67f5c1434cSMarc Zyngier #define gic_data_rdist() (this_cpu_ptr(gic_data.rdists.rdist)) 68f5c1434cSMarc Zyngier #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base) 69021f6537SMarc Zyngier #define gic_data_rdist_sgi_base() (gic_data_rdist_rd_base() + SZ_64K) 70021f6537SMarc Zyngier 71021f6537SMarc Zyngier /* Our default, arbitrary priority value. Linux only uses one anyway. */ 72021f6537SMarc Zyngier #define DEFAULT_PMR_VALUE 0xf0 73021f6537SMarc Zyngier 74021f6537SMarc Zyngier static inline unsigned int gic_irq(struct irq_data *d) 75021f6537SMarc Zyngier { 76021f6537SMarc Zyngier return d->hwirq; 77021f6537SMarc Zyngier } 78021f6537SMarc Zyngier 79021f6537SMarc Zyngier static inline int gic_irq_in_rdist(struct irq_data *d) 80021f6537SMarc Zyngier { 81021f6537SMarc Zyngier return gic_irq(d) < 32; 82021f6537SMarc Zyngier } 83021f6537SMarc Zyngier 84021f6537SMarc Zyngier static inline void __iomem *gic_dist_base(struct irq_data *d) 85021f6537SMarc Zyngier { 86021f6537SMarc Zyngier if (gic_irq_in_rdist(d)) /* SGI+PPI -> SGI_base for this CPU */ 87021f6537SMarc Zyngier return gic_data_rdist_sgi_base(); 88021f6537SMarc Zyngier 89021f6537SMarc Zyngier if (d->hwirq <= 1023) /* SPI -> dist_base */ 90021f6537SMarc Zyngier return gic_data.dist_base; 91021f6537SMarc Zyngier 92021f6537SMarc Zyngier return NULL; 93021f6537SMarc Zyngier } 94021f6537SMarc Zyngier 95021f6537SMarc Zyngier static void gic_do_wait_for_rwp(void __iomem *base) 96021f6537SMarc Zyngier { 97021f6537SMarc Zyngier u32 count = 1000000; /* 1s! */ 98021f6537SMarc Zyngier 99021f6537SMarc Zyngier while (readl_relaxed(base + GICD_CTLR) & GICD_CTLR_RWP) { 100021f6537SMarc Zyngier count--; 101021f6537SMarc Zyngier if (!count) { 102021f6537SMarc Zyngier pr_err_ratelimited("RWP timeout, gone fishing\n"); 103021f6537SMarc Zyngier return; 104021f6537SMarc Zyngier } 105021f6537SMarc Zyngier cpu_relax(); 106021f6537SMarc Zyngier udelay(1); 107021f6537SMarc Zyngier }; 108021f6537SMarc Zyngier } 109021f6537SMarc Zyngier 110021f6537SMarc Zyngier /* Wait for completion of a distributor change */ 111021f6537SMarc Zyngier static void gic_dist_wait_for_rwp(void) 112021f6537SMarc Zyngier { 113021f6537SMarc Zyngier gic_do_wait_for_rwp(gic_data.dist_base); 114021f6537SMarc Zyngier } 115021f6537SMarc Zyngier 116021f6537SMarc Zyngier /* Wait for completion of a redistributor change */ 117021f6537SMarc Zyngier static void gic_redist_wait_for_rwp(void) 118021f6537SMarc Zyngier { 119021f6537SMarc Zyngier gic_do_wait_for_rwp(gic_data_rdist_rd_base()); 120021f6537SMarc Zyngier } 121021f6537SMarc Zyngier 1227936e914SJean-Philippe Brucker #ifdef CONFIG_ARM64 1236d4e11c5SRobert Richter 1246d4e11c5SRobert Richter static u64 __maybe_unused gic_read_iar(void) 1256d4e11c5SRobert Richter { 126a4023f68SSuzuki K Poulose if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_23154)) 1276d4e11c5SRobert Richter return gic_read_iar_cavium_thunderx(); 1286d4e11c5SRobert Richter else 1296d4e11c5SRobert Richter return gic_read_iar_common(); 1306d4e11c5SRobert Richter } 1317936e914SJean-Philippe Brucker #endif 132021f6537SMarc Zyngier 133a2c22510SSudeep Holla static void gic_enable_redist(bool enable) 134021f6537SMarc Zyngier { 135021f6537SMarc Zyngier void __iomem *rbase; 136021f6537SMarc Zyngier u32 count = 1000000; /* 1s! */ 137021f6537SMarc Zyngier u32 val; 138021f6537SMarc Zyngier 139021f6537SMarc Zyngier rbase = gic_data_rdist_rd_base(); 140021f6537SMarc Zyngier 141021f6537SMarc Zyngier val = readl_relaxed(rbase + GICR_WAKER); 142a2c22510SSudeep Holla if (enable) 143a2c22510SSudeep Holla /* Wake up this CPU redistributor */ 144021f6537SMarc Zyngier val &= ~GICR_WAKER_ProcessorSleep; 145a2c22510SSudeep Holla else 146a2c22510SSudeep Holla val |= GICR_WAKER_ProcessorSleep; 147021f6537SMarc Zyngier writel_relaxed(val, rbase + GICR_WAKER); 148021f6537SMarc Zyngier 149a2c22510SSudeep Holla if (!enable) { /* Check that GICR_WAKER is writeable */ 150a2c22510SSudeep Holla val = readl_relaxed(rbase + GICR_WAKER); 151a2c22510SSudeep Holla if (!(val & GICR_WAKER_ProcessorSleep)) 152a2c22510SSudeep Holla return; /* No PM support in this redistributor */ 153021f6537SMarc Zyngier } 154a2c22510SSudeep Holla 155d102eb5cSDan Carpenter while (--count) { 156a2c22510SSudeep Holla val = readl_relaxed(rbase + GICR_WAKER); 157cf1d9d11SAndrew Jones if (enable ^ (bool)(val & GICR_WAKER_ChildrenAsleep)) 158a2c22510SSudeep Holla break; 159021f6537SMarc Zyngier cpu_relax(); 160021f6537SMarc Zyngier udelay(1); 161021f6537SMarc Zyngier }; 162a2c22510SSudeep Holla if (!count) 163a2c22510SSudeep Holla pr_err_ratelimited("redistributor failed to %s...\n", 164a2c22510SSudeep Holla enable ? "wakeup" : "sleep"); 165021f6537SMarc Zyngier } 166021f6537SMarc Zyngier 167021f6537SMarc Zyngier /* 168021f6537SMarc Zyngier * Routines to disable, enable, EOI and route interrupts 169021f6537SMarc Zyngier */ 170b594c6e2SMarc Zyngier static int gic_peek_irq(struct irq_data *d, u32 offset) 171b594c6e2SMarc Zyngier { 172b594c6e2SMarc Zyngier u32 mask = 1 << (gic_irq(d) % 32); 173b594c6e2SMarc Zyngier void __iomem *base; 174b594c6e2SMarc Zyngier 175b594c6e2SMarc Zyngier if (gic_irq_in_rdist(d)) 176b594c6e2SMarc Zyngier base = gic_data_rdist_sgi_base(); 177b594c6e2SMarc Zyngier else 178b594c6e2SMarc Zyngier base = gic_data.dist_base; 179b594c6e2SMarc Zyngier 180b594c6e2SMarc Zyngier return !!(readl_relaxed(base + offset + (gic_irq(d) / 32) * 4) & mask); 181b594c6e2SMarc Zyngier } 182b594c6e2SMarc Zyngier 183021f6537SMarc Zyngier static void gic_poke_irq(struct irq_data *d, u32 offset) 184021f6537SMarc Zyngier { 185021f6537SMarc Zyngier u32 mask = 1 << (gic_irq(d) % 32); 186021f6537SMarc Zyngier void (*rwp_wait)(void); 187021f6537SMarc Zyngier void __iomem *base; 188021f6537SMarc Zyngier 189021f6537SMarc Zyngier if (gic_irq_in_rdist(d)) { 190021f6537SMarc Zyngier base = gic_data_rdist_sgi_base(); 191021f6537SMarc Zyngier rwp_wait = gic_redist_wait_for_rwp; 192021f6537SMarc Zyngier } else { 193021f6537SMarc Zyngier base = gic_data.dist_base; 194021f6537SMarc Zyngier rwp_wait = gic_dist_wait_for_rwp; 195021f6537SMarc Zyngier } 196021f6537SMarc Zyngier 197021f6537SMarc Zyngier writel_relaxed(mask, base + offset + (gic_irq(d) / 32) * 4); 198021f6537SMarc Zyngier rwp_wait(); 199021f6537SMarc Zyngier } 200021f6537SMarc Zyngier 201021f6537SMarc Zyngier static void gic_mask_irq(struct irq_data *d) 202021f6537SMarc Zyngier { 203021f6537SMarc Zyngier gic_poke_irq(d, GICD_ICENABLER); 204021f6537SMarc Zyngier } 205021f6537SMarc Zyngier 2060b6a3da9SMarc Zyngier static void gic_eoimode1_mask_irq(struct irq_data *d) 2070b6a3da9SMarc Zyngier { 2080b6a3da9SMarc Zyngier gic_mask_irq(d); 209530bf353SMarc Zyngier /* 210530bf353SMarc Zyngier * When masking a forwarded interrupt, make sure it is 211530bf353SMarc Zyngier * deactivated as well. 212530bf353SMarc Zyngier * 213530bf353SMarc Zyngier * This ensures that an interrupt that is getting 214530bf353SMarc Zyngier * disabled/masked will not get "stuck", because there is 215530bf353SMarc Zyngier * noone to deactivate it (guest is being terminated). 216530bf353SMarc Zyngier */ 2174df7f54dSThomas Gleixner if (irqd_is_forwarded_to_vcpu(d)) 218530bf353SMarc Zyngier gic_poke_irq(d, GICD_ICACTIVER); 2190b6a3da9SMarc Zyngier } 2200b6a3da9SMarc Zyngier 221021f6537SMarc Zyngier static void gic_unmask_irq(struct irq_data *d) 222021f6537SMarc Zyngier { 223021f6537SMarc Zyngier gic_poke_irq(d, GICD_ISENABLER); 224021f6537SMarc Zyngier } 225021f6537SMarc Zyngier 226b594c6e2SMarc Zyngier static int gic_irq_set_irqchip_state(struct irq_data *d, 227b594c6e2SMarc Zyngier enum irqchip_irq_state which, bool val) 228b594c6e2SMarc Zyngier { 229b594c6e2SMarc Zyngier u32 reg; 230b594c6e2SMarc Zyngier 231b594c6e2SMarc Zyngier if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */ 232b594c6e2SMarc Zyngier return -EINVAL; 233b594c6e2SMarc Zyngier 234b594c6e2SMarc Zyngier switch (which) { 235b594c6e2SMarc Zyngier case IRQCHIP_STATE_PENDING: 236b594c6e2SMarc Zyngier reg = val ? GICD_ISPENDR : GICD_ICPENDR; 237b594c6e2SMarc Zyngier break; 238b594c6e2SMarc Zyngier 239b594c6e2SMarc Zyngier case IRQCHIP_STATE_ACTIVE: 240b594c6e2SMarc Zyngier reg = val ? GICD_ISACTIVER : GICD_ICACTIVER; 241b594c6e2SMarc Zyngier break; 242b594c6e2SMarc Zyngier 243b594c6e2SMarc Zyngier case IRQCHIP_STATE_MASKED: 244b594c6e2SMarc Zyngier reg = val ? GICD_ICENABLER : GICD_ISENABLER; 245b594c6e2SMarc Zyngier break; 246b594c6e2SMarc Zyngier 247b594c6e2SMarc Zyngier default: 248b594c6e2SMarc Zyngier return -EINVAL; 249b594c6e2SMarc Zyngier } 250b594c6e2SMarc Zyngier 251b594c6e2SMarc Zyngier gic_poke_irq(d, reg); 252b594c6e2SMarc Zyngier return 0; 253b594c6e2SMarc Zyngier } 254b594c6e2SMarc Zyngier 255b594c6e2SMarc Zyngier static int gic_irq_get_irqchip_state(struct irq_data *d, 256b594c6e2SMarc Zyngier enum irqchip_irq_state which, bool *val) 257b594c6e2SMarc Zyngier { 258b594c6e2SMarc Zyngier if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */ 259b594c6e2SMarc Zyngier return -EINVAL; 260b594c6e2SMarc Zyngier 261b594c6e2SMarc Zyngier switch (which) { 262b594c6e2SMarc Zyngier case IRQCHIP_STATE_PENDING: 263b594c6e2SMarc Zyngier *val = gic_peek_irq(d, GICD_ISPENDR); 264b594c6e2SMarc Zyngier break; 265b594c6e2SMarc Zyngier 266b594c6e2SMarc Zyngier case IRQCHIP_STATE_ACTIVE: 267b594c6e2SMarc Zyngier *val = gic_peek_irq(d, GICD_ISACTIVER); 268b594c6e2SMarc Zyngier break; 269b594c6e2SMarc Zyngier 270b594c6e2SMarc Zyngier case IRQCHIP_STATE_MASKED: 271b594c6e2SMarc Zyngier *val = !gic_peek_irq(d, GICD_ISENABLER); 272b594c6e2SMarc Zyngier break; 273b594c6e2SMarc Zyngier 274b594c6e2SMarc Zyngier default: 275b594c6e2SMarc Zyngier return -EINVAL; 276b594c6e2SMarc Zyngier } 277b594c6e2SMarc Zyngier 278b594c6e2SMarc Zyngier return 0; 279b594c6e2SMarc Zyngier } 280b594c6e2SMarc Zyngier 281021f6537SMarc Zyngier static void gic_eoi_irq(struct irq_data *d) 282021f6537SMarc Zyngier { 283021f6537SMarc Zyngier gic_write_eoir(gic_irq(d)); 284021f6537SMarc Zyngier } 285021f6537SMarc Zyngier 2860b6a3da9SMarc Zyngier static void gic_eoimode1_eoi_irq(struct irq_data *d) 2870b6a3da9SMarc Zyngier { 2880b6a3da9SMarc Zyngier /* 289530bf353SMarc Zyngier * No need to deactivate an LPI, or an interrupt that 290530bf353SMarc Zyngier * is is getting forwarded to a vcpu. 2910b6a3da9SMarc Zyngier */ 2924df7f54dSThomas Gleixner if (gic_irq(d) >= 8192 || irqd_is_forwarded_to_vcpu(d)) 2930b6a3da9SMarc Zyngier return; 2940b6a3da9SMarc Zyngier gic_write_dir(gic_irq(d)); 2950b6a3da9SMarc Zyngier } 2960b6a3da9SMarc Zyngier 297021f6537SMarc Zyngier static int gic_set_type(struct irq_data *d, unsigned int type) 298021f6537SMarc Zyngier { 299021f6537SMarc Zyngier unsigned int irq = gic_irq(d); 300021f6537SMarc Zyngier void (*rwp_wait)(void); 301021f6537SMarc Zyngier void __iomem *base; 302021f6537SMarc Zyngier 303021f6537SMarc Zyngier /* Interrupt configuration for SGIs can't be changed */ 304021f6537SMarc Zyngier if (irq < 16) 305021f6537SMarc Zyngier return -EINVAL; 306021f6537SMarc Zyngier 307fb7e7debSLiviu Dudau /* SPIs have restrictions on the supported types */ 308fb7e7debSLiviu Dudau if (irq >= 32 && type != IRQ_TYPE_LEVEL_HIGH && 309fb7e7debSLiviu Dudau type != IRQ_TYPE_EDGE_RISING) 310021f6537SMarc Zyngier return -EINVAL; 311021f6537SMarc Zyngier 312021f6537SMarc Zyngier if (gic_irq_in_rdist(d)) { 313021f6537SMarc Zyngier base = gic_data_rdist_sgi_base(); 314021f6537SMarc Zyngier rwp_wait = gic_redist_wait_for_rwp; 315021f6537SMarc Zyngier } else { 316021f6537SMarc Zyngier base = gic_data.dist_base; 317021f6537SMarc Zyngier rwp_wait = gic_dist_wait_for_rwp; 318021f6537SMarc Zyngier } 319021f6537SMarc Zyngier 320fb7e7debSLiviu Dudau return gic_configure_irq(irq, type, base, rwp_wait); 321021f6537SMarc Zyngier } 322021f6537SMarc Zyngier 323530bf353SMarc Zyngier static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu) 324530bf353SMarc Zyngier { 3254df7f54dSThomas Gleixner if (vcpu) 3264df7f54dSThomas Gleixner irqd_set_forwarded_to_vcpu(d); 3274df7f54dSThomas Gleixner else 3284df7f54dSThomas Gleixner irqd_clr_forwarded_to_vcpu(d); 329530bf353SMarc Zyngier return 0; 330530bf353SMarc Zyngier } 331530bf353SMarc Zyngier 332f6c86a41SJean-Philippe Brucker static u64 gic_mpidr_to_affinity(unsigned long mpidr) 333021f6537SMarc Zyngier { 334021f6537SMarc Zyngier u64 aff; 335021f6537SMarc Zyngier 336f6c86a41SJean-Philippe Brucker aff = ((u64)MPIDR_AFFINITY_LEVEL(mpidr, 3) << 32 | 337021f6537SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 | 338021f6537SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | 339021f6537SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 0)); 340021f6537SMarc Zyngier 341021f6537SMarc Zyngier return aff; 342021f6537SMarc Zyngier } 343021f6537SMarc Zyngier 344021f6537SMarc Zyngier static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) 345021f6537SMarc Zyngier { 346f6c86a41SJean-Philippe Brucker u32 irqnr; 347021f6537SMarc Zyngier 348021f6537SMarc Zyngier do { 349021f6537SMarc Zyngier irqnr = gic_read_iar(); 350021f6537SMarc Zyngier 351da33f31dSMarc Zyngier if (likely(irqnr > 15 && irqnr < 1020) || irqnr >= 8192) { 352ebc6de00SMarc Zyngier int err; 3530b6a3da9SMarc Zyngier 3540b6a3da9SMarc Zyngier if (static_key_true(&supports_deactivate)) 3550b6a3da9SMarc Zyngier gic_write_eoir(irqnr); 3560b6a3da9SMarc Zyngier 357ebc6de00SMarc Zyngier err = handle_domain_irq(gic_data.domain, irqnr, regs); 358ebc6de00SMarc Zyngier if (err) { 359da33f31dSMarc Zyngier WARN_ONCE(true, "Unexpected interrupt received!\n"); 3600b6a3da9SMarc Zyngier if (static_key_true(&supports_deactivate)) { 3610b6a3da9SMarc Zyngier if (irqnr < 8192) 3620b6a3da9SMarc Zyngier gic_write_dir(irqnr); 3630b6a3da9SMarc Zyngier } else { 364021f6537SMarc Zyngier gic_write_eoir(irqnr); 365021f6537SMarc Zyngier } 3660b6a3da9SMarc Zyngier } 367ebc6de00SMarc Zyngier continue; 368ebc6de00SMarc Zyngier } 369021f6537SMarc Zyngier if (irqnr < 16) { 370021f6537SMarc Zyngier gic_write_eoir(irqnr); 3710b6a3da9SMarc Zyngier if (static_key_true(&supports_deactivate)) 3720b6a3da9SMarc Zyngier gic_write_dir(irqnr); 373021f6537SMarc Zyngier #ifdef CONFIG_SMP 374f86c4fbdSWill Deacon /* 375f86c4fbdSWill Deacon * Unlike GICv2, we don't need an smp_rmb() here. 376f86c4fbdSWill Deacon * The control dependency from gic_read_iar to 377f86c4fbdSWill Deacon * the ISB in gic_write_eoir is enough to ensure 378f86c4fbdSWill Deacon * that any shared data read by handle_IPI will 379f86c4fbdSWill Deacon * be read after the ACK. 380f86c4fbdSWill Deacon */ 381021f6537SMarc Zyngier handle_IPI(irqnr, regs); 382021f6537SMarc Zyngier #else 383021f6537SMarc Zyngier WARN_ONCE(true, "Unexpected SGI received!\n"); 384021f6537SMarc Zyngier #endif 385021f6537SMarc Zyngier continue; 386021f6537SMarc Zyngier } 387021f6537SMarc Zyngier } while (irqnr != ICC_IAR1_EL1_SPURIOUS); 388021f6537SMarc Zyngier } 389021f6537SMarc Zyngier 390021f6537SMarc Zyngier static void __init gic_dist_init(void) 391021f6537SMarc Zyngier { 392021f6537SMarc Zyngier unsigned int i; 393021f6537SMarc Zyngier u64 affinity; 394021f6537SMarc Zyngier void __iomem *base = gic_data.dist_base; 395021f6537SMarc Zyngier 396021f6537SMarc Zyngier /* Disable the distributor */ 397021f6537SMarc Zyngier writel_relaxed(0, base + GICD_CTLR); 398021f6537SMarc Zyngier gic_dist_wait_for_rwp(); 399021f6537SMarc Zyngier 4007c9b9730SMarc Zyngier /* 4017c9b9730SMarc Zyngier * Configure SPIs as non-secure Group-1. This will only matter 4027c9b9730SMarc Zyngier * if the GIC only has a single security state. This will not 4037c9b9730SMarc Zyngier * do the right thing if the kernel is running in secure mode, 4047c9b9730SMarc Zyngier * but that's not the intended use case anyway. 4057c9b9730SMarc Zyngier */ 4067c9b9730SMarc Zyngier for (i = 32; i < gic_data.irq_nr; i += 32) 4077c9b9730SMarc Zyngier writel_relaxed(~0, base + GICD_IGROUPR + i / 8); 4087c9b9730SMarc Zyngier 409021f6537SMarc Zyngier gic_dist_config(base, gic_data.irq_nr, gic_dist_wait_for_rwp); 410021f6537SMarc Zyngier 411021f6537SMarc Zyngier /* Enable distributor with ARE, Group1 */ 412021f6537SMarc Zyngier writel_relaxed(GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G1A | GICD_CTLR_ENABLE_G1, 413021f6537SMarc Zyngier base + GICD_CTLR); 414021f6537SMarc Zyngier 415021f6537SMarc Zyngier /* 416021f6537SMarc Zyngier * Set all global interrupts to the boot CPU only. ARE must be 417021f6537SMarc Zyngier * enabled. 418021f6537SMarc Zyngier */ 419021f6537SMarc Zyngier affinity = gic_mpidr_to_affinity(cpu_logical_map(smp_processor_id())); 420021f6537SMarc Zyngier for (i = 32; i < gic_data.irq_nr; i++) 42172c97126SJean-Philippe Brucker gic_write_irouter(affinity, base + GICD_IROUTER + i * 8); 422021f6537SMarc Zyngier } 423021f6537SMarc Zyngier 424021f6537SMarc Zyngier static int gic_populate_rdist(void) 425021f6537SMarc Zyngier { 426f6c86a41SJean-Philippe Brucker unsigned long mpidr = cpu_logical_map(smp_processor_id()); 427021f6537SMarc Zyngier u64 typer; 428021f6537SMarc Zyngier u32 aff; 429021f6537SMarc Zyngier int i; 430021f6537SMarc Zyngier 431021f6537SMarc Zyngier /* 432021f6537SMarc Zyngier * Convert affinity to a 32bit value that can be matched to 433021f6537SMarc Zyngier * GICR_TYPER bits [63:32]. 434021f6537SMarc Zyngier */ 435021f6537SMarc Zyngier aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 24 | 436021f6537SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 | 437021f6537SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | 438021f6537SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 0)); 439021f6537SMarc Zyngier 440f5c1434cSMarc Zyngier for (i = 0; i < gic_data.nr_redist_regions; i++) { 441f5c1434cSMarc Zyngier void __iomem *ptr = gic_data.redist_regions[i].redist_base; 442021f6537SMarc Zyngier u32 reg; 443021f6537SMarc Zyngier 444021f6537SMarc Zyngier reg = readl_relaxed(ptr + GICR_PIDR2) & GIC_PIDR2_ARCH_MASK; 445021f6537SMarc Zyngier if (reg != GIC_PIDR2_ARCH_GICv3 && 446021f6537SMarc Zyngier reg != GIC_PIDR2_ARCH_GICv4) { /* We're in trouble... */ 447021f6537SMarc Zyngier pr_warn("No redistributor present @%p\n", ptr); 448021f6537SMarc Zyngier break; 449021f6537SMarc Zyngier } 450021f6537SMarc Zyngier 451021f6537SMarc Zyngier do { 45272c97126SJean-Philippe Brucker typer = gic_read_typer(ptr + GICR_TYPER); 453021f6537SMarc Zyngier if ((typer >> 32) == aff) { 454f5c1434cSMarc Zyngier u64 offset = ptr - gic_data.redist_regions[i].redist_base; 455021f6537SMarc Zyngier gic_data_rdist_rd_base() = ptr; 456f5c1434cSMarc Zyngier gic_data_rdist()->phys_base = gic_data.redist_regions[i].phys_base + offset; 457f6c86a41SJean-Philippe Brucker pr_info("CPU%d: found redistributor %lx region %d:%pa\n", 458f6c86a41SJean-Philippe Brucker smp_processor_id(), mpidr, i, 459f6c86a41SJean-Philippe Brucker &gic_data_rdist()->phys_base); 460021f6537SMarc Zyngier return 0; 461021f6537SMarc Zyngier } 462021f6537SMarc Zyngier 463b70fb7afSTomasz Nowicki if (gic_data.redist_regions[i].single_redist) 464b70fb7afSTomasz Nowicki break; 465b70fb7afSTomasz Nowicki 466021f6537SMarc Zyngier if (gic_data.redist_stride) { 467021f6537SMarc Zyngier ptr += gic_data.redist_stride; 468021f6537SMarc Zyngier } else { 469021f6537SMarc Zyngier ptr += SZ_64K * 2; /* Skip RD_base + SGI_base */ 470021f6537SMarc Zyngier if (typer & GICR_TYPER_VLPIS) 471021f6537SMarc Zyngier ptr += SZ_64K * 2; /* Skip VLPI_base + reserved page */ 472021f6537SMarc Zyngier } 473021f6537SMarc Zyngier } while (!(typer & GICR_TYPER_LAST)); 474021f6537SMarc Zyngier } 475021f6537SMarc Zyngier 476021f6537SMarc Zyngier /* We couldn't even deal with ourselves... */ 477f6c86a41SJean-Philippe Brucker WARN(true, "CPU%d: mpidr %lx has no re-distributor!\n", 478f6c86a41SJean-Philippe Brucker smp_processor_id(), mpidr); 479021f6537SMarc Zyngier return -ENODEV; 480021f6537SMarc Zyngier } 481021f6537SMarc Zyngier 4823708d52fSSudeep Holla static void gic_cpu_sys_reg_init(void) 483021f6537SMarc Zyngier { 4847cabd008SMarc Zyngier /* 4857cabd008SMarc Zyngier * Need to check that the SRE bit has actually been set. If 4867cabd008SMarc Zyngier * not, it means that SRE is disabled at EL2. We're going to 4877cabd008SMarc Zyngier * die painfully, and there is nothing we can do about it. 4887cabd008SMarc Zyngier * 4897cabd008SMarc Zyngier * Kindly inform the luser. 4907cabd008SMarc Zyngier */ 4917cabd008SMarc Zyngier if (!gic_enable_sre()) 4927cabd008SMarc Zyngier pr_err("GIC: unable to set SRE (disabled at EL2), panic ahead\n"); 493021f6537SMarc Zyngier 494021f6537SMarc Zyngier /* Set priority mask register */ 495021f6537SMarc Zyngier gic_write_pmr(DEFAULT_PMR_VALUE); 496021f6537SMarc Zyngier 49791ef8442SDaniel Thompson /* 49891ef8442SDaniel Thompson * Some firmwares hand over to the kernel with the BPR changed from 49991ef8442SDaniel Thompson * its reset value (and with a value large enough to prevent 50091ef8442SDaniel Thompson * any pre-emptive interrupts from working at all). Writing a zero 50191ef8442SDaniel Thompson * to BPR restores is reset value. 50291ef8442SDaniel Thompson */ 50391ef8442SDaniel Thompson gic_write_bpr1(0); 50491ef8442SDaniel Thompson 5050b6a3da9SMarc Zyngier if (static_key_true(&supports_deactivate)) { 5060b6a3da9SMarc Zyngier /* EOI drops priority only (mode 1) */ 5070b6a3da9SMarc Zyngier gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop); 5080b6a3da9SMarc Zyngier } else { 509021f6537SMarc Zyngier /* EOI deactivates interrupt too (mode 0) */ 510021f6537SMarc Zyngier gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop_dir); 5110b6a3da9SMarc Zyngier } 512021f6537SMarc Zyngier 513021f6537SMarc Zyngier /* ... and let's hit the road... */ 514021f6537SMarc Zyngier gic_write_grpen1(1); 515021f6537SMarc Zyngier } 516021f6537SMarc Zyngier 517da33f31dSMarc Zyngier static int gic_dist_supports_lpis(void) 518da33f31dSMarc Zyngier { 519da33f31dSMarc Zyngier return !!(readl_relaxed(gic_data.dist_base + GICD_TYPER) & GICD_TYPER_LPIS); 520da33f31dSMarc Zyngier } 521da33f31dSMarc Zyngier 522021f6537SMarc Zyngier static void gic_cpu_init(void) 523021f6537SMarc Zyngier { 524021f6537SMarc Zyngier void __iomem *rbase; 525021f6537SMarc Zyngier 526021f6537SMarc Zyngier /* Register ourselves with the rest of the world */ 527021f6537SMarc Zyngier if (gic_populate_rdist()) 528021f6537SMarc Zyngier return; 529021f6537SMarc Zyngier 530a2c22510SSudeep Holla gic_enable_redist(true); 531021f6537SMarc Zyngier 532021f6537SMarc Zyngier rbase = gic_data_rdist_sgi_base(); 533021f6537SMarc Zyngier 5347c9b9730SMarc Zyngier /* Configure SGIs/PPIs as non-secure Group-1 */ 5357c9b9730SMarc Zyngier writel_relaxed(~0, rbase + GICR_IGROUPR0); 5367c9b9730SMarc Zyngier 537021f6537SMarc Zyngier gic_cpu_config(rbase, gic_redist_wait_for_rwp); 538021f6537SMarc Zyngier 539da33f31dSMarc Zyngier /* Give LPIs a spin */ 540da33f31dSMarc Zyngier if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis()) 541da33f31dSMarc Zyngier its_cpu_init(); 542da33f31dSMarc Zyngier 5433708d52fSSudeep Holla /* initialise system registers */ 5443708d52fSSudeep Holla gic_cpu_sys_reg_init(); 545021f6537SMarc Zyngier } 546021f6537SMarc Zyngier 547021f6537SMarc Zyngier #ifdef CONFIG_SMP 548021f6537SMarc Zyngier 5496670a6d8SRichard Cochran static int gic_starting_cpu(unsigned int cpu) 5506670a6d8SRichard Cochran { 5516670a6d8SRichard Cochran gic_cpu_init(); 5526670a6d8SRichard Cochran return 0; 5536670a6d8SRichard Cochran } 554021f6537SMarc Zyngier 555021f6537SMarc Zyngier static u16 gic_compute_target_list(int *base_cpu, const struct cpumask *mask, 556f6c86a41SJean-Philippe Brucker unsigned long cluster_id) 557021f6537SMarc Zyngier { 558727653d6SJames Morse int next_cpu, cpu = *base_cpu; 559f6c86a41SJean-Philippe Brucker unsigned long mpidr = cpu_logical_map(cpu); 560021f6537SMarc Zyngier u16 tlist = 0; 561021f6537SMarc Zyngier 562021f6537SMarc Zyngier while (cpu < nr_cpu_ids) { 563021f6537SMarc Zyngier /* 564021f6537SMarc Zyngier * If we ever get a cluster of more than 16 CPUs, just 565021f6537SMarc Zyngier * scream and skip that CPU. 566021f6537SMarc Zyngier */ 567021f6537SMarc Zyngier if (WARN_ON((mpidr & 0xff) >= 16)) 568021f6537SMarc Zyngier goto out; 569021f6537SMarc Zyngier 570021f6537SMarc Zyngier tlist |= 1 << (mpidr & 0xf); 571021f6537SMarc Zyngier 572727653d6SJames Morse next_cpu = cpumask_next(cpu, mask); 573727653d6SJames Morse if (next_cpu >= nr_cpu_ids) 574021f6537SMarc Zyngier goto out; 575727653d6SJames Morse cpu = next_cpu; 576021f6537SMarc Zyngier 577021f6537SMarc Zyngier mpidr = cpu_logical_map(cpu); 578021f6537SMarc Zyngier 579021f6537SMarc Zyngier if (cluster_id != (mpidr & ~0xffUL)) { 580021f6537SMarc Zyngier cpu--; 581021f6537SMarc Zyngier goto out; 582021f6537SMarc Zyngier } 583021f6537SMarc Zyngier } 584021f6537SMarc Zyngier out: 585021f6537SMarc Zyngier *base_cpu = cpu; 586021f6537SMarc Zyngier return tlist; 587021f6537SMarc Zyngier } 588021f6537SMarc Zyngier 5897e580278SAndre Przywara #define MPIDR_TO_SGI_AFFINITY(cluster_id, level) \ 5907e580278SAndre Przywara (MPIDR_AFFINITY_LEVEL(cluster_id, level) \ 5917e580278SAndre Przywara << ICC_SGI1R_AFFINITY_## level ##_SHIFT) 5927e580278SAndre Przywara 593021f6537SMarc Zyngier static void gic_send_sgi(u64 cluster_id, u16 tlist, unsigned int irq) 594021f6537SMarc Zyngier { 595021f6537SMarc Zyngier u64 val; 596021f6537SMarc Zyngier 5977e580278SAndre Przywara val = (MPIDR_TO_SGI_AFFINITY(cluster_id, 3) | 5987e580278SAndre Przywara MPIDR_TO_SGI_AFFINITY(cluster_id, 2) | 5997e580278SAndre Przywara irq << ICC_SGI1R_SGI_ID_SHIFT | 6007e580278SAndre Przywara MPIDR_TO_SGI_AFFINITY(cluster_id, 1) | 6017e580278SAndre Przywara tlist << ICC_SGI1R_TARGET_LIST_SHIFT); 602021f6537SMarc Zyngier 603021f6537SMarc Zyngier pr_debug("CPU%d: ICC_SGI1R_EL1 %llx\n", smp_processor_id(), val); 604021f6537SMarc Zyngier gic_write_sgi1r(val); 605021f6537SMarc Zyngier } 606021f6537SMarc Zyngier 607021f6537SMarc Zyngier static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) 608021f6537SMarc Zyngier { 609021f6537SMarc Zyngier int cpu; 610021f6537SMarc Zyngier 611021f6537SMarc Zyngier if (WARN_ON(irq >= 16)) 612021f6537SMarc Zyngier return; 613021f6537SMarc Zyngier 614021f6537SMarc Zyngier /* 615021f6537SMarc Zyngier * Ensure that stores to Normal memory are visible to the 616021f6537SMarc Zyngier * other CPUs before issuing the IPI. 617021f6537SMarc Zyngier */ 618021f6537SMarc Zyngier smp_wmb(); 619021f6537SMarc Zyngier 620f9b531feSRusty Russell for_each_cpu(cpu, mask) { 621f6c86a41SJean-Philippe Brucker unsigned long cluster_id = cpu_logical_map(cpu) & ~0xffUL; 622021f6537SMarc Zyngier u16 tlist; 623021f6537SMarc Zyngier 624021f6537SMarc Zyngier tlist = gic_compute_target_list(&cpu, mask, cluster_id); 625021f6537SMarc Zyngier gic_send_sgi(cluster_id, tlist, irq); 626021f6537SMarc Zyngier } 627021f6537SMarc Zyngier 628021f6537SMarc Zyngier /* Force the above writes to ICC_SGI1R_EL1 to be executed */ 629021f6537SMarc Zyngier isb(); 630021f6537SMarc Zyngier } 631021f6537SMarc Zyngier 632021f6537SMarc Zyngier static void gic_smp_init(void) 633021f6537SMarc Zyngier { 634021f6537SMarc Zyngier set_smp_cross_call(gic_raise_softirq); 6356896bcd1SThomas Gleixner cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_GIC_STARTING, 63673c1b41eSThomas Gleixner "irqchip/arm/gicv3:starting", 63773c1b41eSThomas Gleixner gic_starting_cpu, NULL); 638021f6537SMarc Zyngier } 639021f6537SMarc Zyngier 640021f6537SMarc Zyngier static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, 641021f6537SMarc Zyngier bool force) 642021f6537SMarc Zyngier { 643021f6537SMarc Zyngier unsigned int cpu = cpumask_any_and(mask_val, cpu_online_mask); 644021f6537SMarc Zyngier void __iomem *reg; 645021f6537SMarc Zyngier int enabled; 646021f6537SMarc Zyngier u64 val; 647021f6537SMarc Zyngier 648021f6537SMarc Zyngier if (gic_irq_in_rdist(d)) 649021f6537SMarc Zyngier return -EINVAL; 650021f6537SMarc Zyngier 651021f6537SMarc Zyngier /* If interrupt was enabled, disable it first */ 652021f6537SMarc Zyngier enabled = gic_peek_irq(d, GICD_ISENABLER); 653021f6537SMarc Zyngier if (enabled) 654021f6537SMarc Zyngier gic_mask_irq(d); 655021f6537SMarc Zyngier 656021f6537SMarc Zyngier reg = gic_dist_base(d) + GICD_IROUTER + (gic_irq(d) * 8); 657021f6537SMarc Zyngier val = gic_mpidr_to_affinity(cpu_logical_map(cpu)); 658021f6537SMarc Zyngier 65972c97126SJean-Philippe Brucker gic_write_irouter(val, reg); 660021f6537SMarc Zyngier 661021f6537SMarc Zyngier /* 662021f6537SMarc Zyngier * If the interrupt was enabled, enabled it again. Otherwise, 663021f6537SMarc Zyngier * just wait for the distributor to have digested our changes. 664021f6537SMarc Zyngier */ 665021f6537SMarc Zyngier if (enabled) 666021f6537SMarc Zyngier gic_unmask_irq(d); 667021f6537SMarc Zyngier else 668021f6537SMarc Zyngier gic_dist_wait_for_rwp(); 669021f6537SMarc Zyngier 6700fc6fa29SAntoine Tenart return IRQ_SET_MASK_OK_DONE; 671021f6537SMarc Zyngier } 672021f6537SMarc Zyngier #else 673021f6537SMarc Zyngier #define gic_set_affinity NULL 674021f6537SMarc Zyngier #define gic_smp_init() do { } while(0) 675021f6537SMarc Zyngier #endif 676021f6537SMarc Zyngier 6773708d52fSSudeep Holla #ifdef CONFIG_CPU_PM 678ccd9432aSSudeep Holla /* Check whether it's single security state view */ 679ccd9432aSSudeep Holla static bool gic_dist_security_disabled(void) 680ccd9432aSSudeep Holla { 681ccd9432aSSudeep Holla return readl_relaxed(gic_data.dist_base + GICD_CTLR) & GICD_CTLR_DS; 682ccd9432aSSudeep Holla } 683ccd9432aSSudeep Holla 6843708d52fSSudeep Holla static int gic_cpu_pm_notifier(struct notifier_block *self, 6853708d52fSSudeep Holla unsigned long cmd, void *v) 6863708d52fSSudeep Holla { 6873708d52fSSudeep Holla if (cmd == CPU_PM_EXIT) { 688ccd9432aSSudeep Holla if (gic_dist_security_disabled()) 6893708d52fSSudeep Holla gic_enable_redist(true); 6903708d52fSSudeep Holla gic_cpu_sys_reg_init(); 691ccd9432aSSudeep Holla } else if (cmd == CPU_PM_ENTER && gic_dist_security_disabled()) { 6923708d52fSSudeep Holla gic_write_grpen1(0); 6933708d52fSSudeep Holla gic_enable_redist(false); 6943708d52fSSudeep Holla } 6953708d52fSSudeep Holla return NOTIFY_OK; 6963708d52fSSudeep Holla } 6973708d52fSSudeep Holla 6983708d52fSSudeep Holla static struct notifier_block gic_cpu_pm_notifier_block = { 6993708d52fSSudeep Holla .notifier_call = gic_cpu_pm_notifier, 7003708d52fSSudeep Holla }; 7013708d52fSSudeep Holla 7023708d52fSSudeep Holla static void gic_cpu_pm_init(void) 7033708d52fSSudeep Holla { 7043708d52fSSudeep Holla cpu_pm_register_notifier(&gic_cpu_pm_notifier_block); 7053708d52fSSudeep Holla } 7063708d52fSSudeep Holla 7073708d52fSSudeep Holla #else 7083708d52fSSudeep Holla static inline void gic_cpu_pm_init(void) { } 7093708d52fSSudeep Holla #endif /* CONFIG_CPU_PM */ 7103708d52fSSudeep Holla 711021f6537SMarc Zyngier static struct irq_chip gic_chip = { 712021f6537SMarc Zyngier .name = "GICv3", 713021f6537SMarc Zyngier .irq_mask = gic_mask_irq, 714021f6537SMarc Zyngier .irq_unmask = gic_unmask_irq, 715021f6537SMarc Zyngier .irq_eoi = gic_eoi_irq, 716021f6537SMarc Zyngier .irq_set_type = gic_set_type, 717021f6537SMarc Zyngier .irq_set_affinity = gic_set_affinity, 718b594c6e2SMarc Zyngier .irq_get_irqchip_state = gic_irq_get_irqchip_state, 719b594c6e2SMarc Zyngier .irq_set_irqchip_state = gic_irq_set_irqchip_state, 72055963c9fSSudeep Holla .flags = IRQCHIP_SET_TYPE_MASKED, 721021f6537SMarc Zyngier }; 722021f6537SMarc Zyngier 7230b6a3da9SMarc Zyngier static struct irq_chip gic_eoimode1_chip = { 7240b6a3da9SMarc Zyngier .name = "GICv3", 7250b6a3da9SMarc Zyngier .irq_mask = gic_eoimode1_mask_irq, 7260b6a3da9SMarc Zyngier .irq_unmask = gic_unmask_irq, 7270b6a3da9SMarc Zyngier .irq_eoi = gic_eoimode1_eoi_irq, 7280b6a3da9SMarc Zyngier .irq_set_type = gic_set_type, 7290b6a3da9SMarc Zyngier .irq_set_affinity = gic_set_affinity, 7300b6a3da9SMarc Zyngier .irq_get_irqchip_state = gic_irq_get_irqchip_state, 7310b6a3da9SMarc Zyngier .irq_set_irqchip_state = gic_irq_set_irqchip_state, 732530bf353SMarc Zyngier .irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity, 7330b6a3da9SMarc Zyngier .flags = IRQCHIP_SET_TYPE_MASKED, 7340b6a3da9SMarc Zyngier }; 7350b6a3da9SMarc Zyngier 736da33f31dSMarc Zyngier #define GIC_ID_NR (1U << gic_data.rdists.id_bits) 737da33f31dSMarc Zyngier 738021f6537SMarc Zyngier static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq, 739021f6537SMarc Zyngier irq_hw_number_t hw) 740021f6537SMarc Zyngier { 7410b6a3da9SMarc Zyngier struct irq_chip *chip = &gic_chip; 7420b6a3da9SMarc Zyngier 7430b6a3da9SMarc Zyngier if (static_key_true(&supports_deactivate)) 7440b6a3da9SMarc Zyngier chip = &gic_eoimode1_chip; 7450b6a3da9SMarc Zyngier 746021f6537SMarc Zyngier /* SGIs are private to the core kernel */ 747021f6537SMarc Zyngier if (hw < 16) 748021f6537SMarc Zyngier return -EPERM; 749da33f31dSMarc Zyngier /* Nothing here */ 750da33f31dSMarc Zyngier if (hw >= gic_data.irq_nr && hw < 8192) 751da33f31dSMarc Zyngier return -EPERM; 752da33f31dSMarc Zyngier /* Off limits */ 753da33f31dSMarc Zyngier if (hw >= GIC_ID_NR) 754da33f31dSMarc Zyngier return -EPERM; 755da33f31dSMarc Zyngier 756021f6537SMarc Zyngier /* PPIs */ 757021f6537SMarc Zyngier if (hw < 32) { 758021f6537SMarc Zyngier irq_set_percpu_devid(irq); 7590b6a3da9SMarc Zyngier irq_domain_set_info(d, irq, hw, chip, d->host_data, 760443acc4fSMarc Zyngier handle_percpu_devid_irq, NULL, NULL); 761d17cab44SRob Herring irq_set_status_flags(irq, IRQ_NOAUTOEN); 762021f6537SMarc Zyngier } 763021f6537SMarc Zyngier /* SPIs */ 764021f6537SMarc Zyngier if (hw >= 32 && hw < gic_data.irq_nr) { 7650b6a3da9SMarc Zyngier irq_domain_set_info(d, irq, hw, chip, d->host_data, 766443acc4fSMarc Zyngier handle_fasteoi_irq, NULL, NULL); 767d17cab44SRob Herring irq_set_probe(irq); 768021f6537SMarc Zyngier } 769da33f31dSMarc Zyngier /* LPIs */ 770da33f31dSMarc Zyngier if (hw >= 8192 && hw < GIC_ID_NR) { 771da33f31dSMarc Zyngier if (!gic_dist_supports_lpis()) 772da33f31dSMarc Zyngier return -EPERM; 7730b6a3da9SMarc Zyngier irq_domain_set_info(d, irq, hw, chip, d->host_data, 774da33f31dSMarc Zyngier handle_fasteoi_irq, NULL, NULL); 775da33f31dSMarc Zyngier } 776da33f31dSMarc Zyngier 777021f6537SMarc Zyngier return 0; 778021f6537SMarc Zyngier } 779021f6537SMarc Zyngier 780f833f57fSMarc Zyngier static int gic_irq_domain_translate(struct irq_domain *d, 781f833f57fSMarc Zyngier struct irq_fwspec *fwspec, 782f833f57fSMarc Zyngier unsigned long *hwirq, 783f833f57fSMarc Zyngier unsigned int *type) 784021f6537SMarc Zyngier { 785f833f57fSMarc Zyngier if (is_of_node(fwspec->fwnode)) { 786f833f57fSMarc Zyngier if (fwspec->param_count < 3) 787021f6537SMarc Zyngier return -EINVAL; 788021f6537SMarc Zyngier 789db8c70ecSMarc Zyngier switch (fwspec->param[0]) { 790db8c70ecSMarc Zyngier case 0: /* SPI */ 791db8c70ecSMarc Zyngier *hwirq = fwspec->param[1] + 32; 792db8c70ecSMarc Zyngier break; 793db8c70ecSMarc Zyngier case 1: /* PPI */ 794f833f57fSMarc Zyngier *hwirq = fwspec->param[1] + 16; 795db8c70ecSMarc Zyngier break; 796db8c70ecSMarc Zyngier case GIC_IRQ_TYPE_LPI: /* LPI */ 797db8c70ecSMarc Zyngier *hwirq = fwspec->param[1]; 798db8c70ecSMarc Zyngier break; 799db8c70ecSMarc Zyngier default: 800db8c70ecSMarc Zyngier return -EINVAL; 801db8c70ecSMarc Zyngier } 802f833f57fSMarc Zyngier 803f833f57fSMarc Zyngier *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; 804f833f57fSMarc Zyngier return 0; 805021f6537SMarc Zyngier } 806021f6537SMarc Zyngier 807ffa7d616STomasz Nowicki if (is_fwnode_irqchip(fwspec->fwnode)) { 808ffa7d616STomasz Nowicki if(fwspec->param_count != 2) 809ffa7d616STomasz Nowicki return -EINVAL; 810ffa7d616STomasz Nowicki 811ffa7d616STomasz Nowicki *hwirq = fwspec->param[0]; 812ffa7d616STomasz Nowicki *type = fwspec->param[1]; 813ffa7d616STomasz Nowicki return 0; 814ffa7d616STomasz Nowicki } 815ffa7d616STomasz Nowicki 816f833f57fSMarc Zyngier return -EINVAL; 817021f6537SMarc Zyngier } 818021f6537SMarc Zyngier 819443acc4fSMarc Zyngier static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, 820443acc4fSMarc Zyngier unsigned int nr_irqs, void *arg) 821443acc4fSMarc Zyngier { 822443acc4fSMarc Zyngier int i, ret; 823443acc4fSMarc Zyngier irq_hw_number_t hwirq; 824443acc4fSMarc Zyngier unsigned int type = IRQ_TYPE_NONE; 825f833f57fSMarc Zyngier struct irq_fwspec *fwspec = arg; 826443acc4fSMarc Zyngier 827f833f57fSMarc Zyngier ret = gic_irq_domain_translate(domain, fwspec, &hwirq, &type); 828443acc4fSMarc Zyngier if (ret) 829443acc4fSMarc Zyngier return ret; 830443acc4fSMarc Zyngier 831443acc4fSMarc Zyngier for (i = 0; i < nr_irqs; i++) 832443acc4fSMarc Zyngier gic_irq_domain_map(domain, virq + i, hwirq + i); 833443acc4fSMarc Zyngier 834443acc4fSMarc Zyngier return 0; 835443acc4fSMarc Zyngier } 836443acc4fSMarc Zyngier 837443acc4fSMarc Zyngier static void gic_irq_domain_free(struct irq_domain *domain, unsigned int virq, 838443acc4fSMarc Zyngier unsigned int nr_irqs) 839443acc4fSMarc Zyngier { 840443acc4fSMarc Zyngier int i; 841443acc4fSMarc Zyngier 842443acc4fSMarc Zyngier for (i = 0; i < nr_irqs; i++) { 843443acc4fSMarc Zyngier struct irq_data *d = irq_domain_get_irq_data(domain, virq + i); 844443acc4fSMarc Zyngier irq_set_handler(virq + i, NULL); 845443acc4fSMarc Zyngier irq_domain_reset_irq_data(d); 846443acc4fSMarc Zyngier } 847443acc4fSMarc Zyngier } 848443acc4fSMarc Zyngier 849e3825ba1SMarc Zyngier static int gic_irq_domain_select(struct irq_domain *d, 850e3825ba1SMarc Zyngier struct irq_fwspec *fwspec, 851e3825ba1SMarc Zyngier enum irq_domain_bus_token bus_token) 852e3825ba1SMarc Zyngier { 853e3825ba1SMarc Zyngier /* Not for us */ 854e3825ba1SMarc Zyngier if (fwspec->fwnode != d->fwnode) 855e3825ba1SMarc Zyngier return 0; 856e3825ba1SMarc Zyngier 857e3825ba1SMarc Zyngier /* If this is not DT, then we have a single domain */ 858e3825ba1SMarc Zyngier if (!is_of_node(fwspec->fwnode)) 859e3825ba1SMarc Zyngier return 1; 860e3825ba1SMarc Zyngier 861e3825ba1SMarc Zyngier /* 862e3825ba1SMarc Zyngier * If this is a PPI and we have a 4th (non-null) parameter, 863e3825ba1SMarc Zyngier * then we need to match the partition domain. 864e3825ba1SMarc Zyngier */ 865e3825ba1SMarc Zyngier if (fwspec->param_count >= 4 && 866e3825ba1SMarc Zyngier fwspec->param[0] == 1 && fwspec->param[3] != 0) 867e3825ba1SMarc Zyngier return d == partition_get_domain(gic_data.ppi_descs[fwspec->param[1]]); 868e3825ba1SMarc Zyngier 869e3825ba1SMarc Zyngier return d == gic_data.domain; 870e3825ba1SMarc Zyngier } 871e3825ba1SMarc Zyngier 872021f6537SMarc Zyngier static const struct irq_domain_ops gic_irq_domain_ops = { 873f833f57fSMarc Zyngier .translate = gic_irq_domain_translate, 874443acc4fSMarc Zyngier .alloc = gic_irq_domain_alloc, 875443acc4fSMarc Zyngier .free = gic_irq_domain_free, 876e3825ba1SMarc Zyngier .select = gic_irq_domain_select, 877e3825ba1SMarc Zyngier }; 878e3825ba1SMarc Zyngier 879e3825ba1SMarc Zyngier static int partition_domain_translate(struct irq_domain *d, 880e3825ba1SMarc Zyngier struct irq_fwspec *fwspec, 881e3825ba1SMarc Zyngier unsigned long *hwirq, 882e3825ba1SMarc Zyngier unsigned int *type) 883e3825ba1SMarc Zyngier { 884e3825ba1SMarc Zyngier struct device_node *np; 885e3825ba1SMarc Zyngier int ret; 886e3825ba1SMarc Zyngier 887e3825ba1SMarc Zyngier np = of_find_node_by_phandle(fwspec->param[3]); 888e3825ba1SMarc Zyngier if (WARN_ON(!np)) 889e3825ba1SMarc Zyngier return -EINVAL; 890e3825ba1SMarc Zyngier 891e3825ba1SMarc Zyngier ret = partition_translate_id(gic_data.ppi_descs[fwspec->param[1]], 892e3825ba1SMarc Zyngier of_node_to_fwnode(np)); 893e3825ba1SMarc Zyngier if (ret < 0) 894e3825ba1SMarc Zyngier return ret; 895e3825ba1SMarc Zyngier 896e3825ba1SMarc Zyngier *hwirq = ret; 897e3825ba1SMarc Zyngier *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; 898e3825ba1SMarc Zyngier 899e3825ba1SMarc Zyngier return 0; 900e3825ba1SMarc Zyngier } 901e3825ba1SMarc Zyngier 902e3825ba1SMarc Zyngier static const struct irq_domain_ops partition_domain_ops = { 903e3825ba1SMarc Zyngier .translate = partition_domain_translate, 904e3825ba1SMarc Zyngier .select = gic_irq_domain_select, 905021f6537SMarc Zyngier }; 906021f6537SMarc Zyngier 907db57d746STomasz Nowicki static int __init gic_init_bases(void __iomem *dist_base, 908db57d746STomasz Nowicki struct redist_region *rdist_regs, 909db57d746STomasz Nowicki u32 nr_redist_regions, 910db57d746STomasz Nowicki u64 redist_stride, 911db57d746STomasz Nowicki struct fwnode_handle *handle) 912db57d746STomasz Nowicki { 913db57d746STomasz Nowicki u32 typer; 914db57d746STomasz Nowicki int gic_irqs; 915db57d746STomasz Nowicki int err; 916db57d746STomasz Nowicki 917db57d746STomasz Nowicki if (!is_hyp_mode_available()) 918db57d746STomasz Nowicki static_key_slow_dec(&supports_deactivate); 919db57d746STomasz Nowicki 920db57d746STomasz Nowicki if (static_key_true(&supports_deactivate)) 921db57d746STomasz Nowicki pr_info("GIC: Using split EOI/Deactivate mode\n"); 922db57d746STomasz Nowicki 923e3825ba1SMarc Zyngier gic_data.fwnode = handle; 924db57d746STomasz Nowicki gic_data.dist_base = dist_base; 925db57d746STomasz Nowicki gic_data.redist_regions = rdist_regs; 926db57d746STomasz Nowicki gic_data.nr_redist_regions = nr_redist_regions; 927db57d746STomasz Nowicki gic_data.redist_stride = redist_stride; 928db57d746STomasz Nowicki 929db57d746STomasz Nowicki /* 930db57d746STomasz Nowicki * Find out how many interrupts are supported. 931db57d746STomasz Nowicki * The GIC only supports up to 1020 interrupt sources (SGI+PPI+SPI) 932db57d746STomasz Nowicki */ 933db57d746STomasz Nowicki typer = readl_relaxed(gic_data.dist_base + GICD_TYPER); 934db57d746STomasz Nowicki gic_data.rdists.id_bits = GICD_TYPER_ID_BITS(typer); 935db57d746STomasz Nowicki gic_irqs = GICD_TYPER_IRQS(typer); 936db57d746STomasz Nowicki if (gic_irqs > 1020) 937db57d746STomasz Nowicki gic_irqs = 1020; 938db57d746STomasz Nowicki gic_data.irq_nr = gic_irqs; 939db57d746STomasz Nowicki 940db57d746STomasz Nowicki gic_data.domain = irq_domain_create_tree(handle, &gic_irq_domain_ops, 941db57d746STomasz Nowicki &gic_data); 942db57d746STomasz Nowicki gic_data.rdists.rdist = alloc_percpu(typeof(*gic_data.rdists.rdist)); 943db57d746STomasz Nowicki 944db57d746STomasz Nowicki if (WARN_ON(!gic_data.domain) || WARN_ON(!gic_data.rdists.rdist)) { 945db57d746STomasz Nowicki err = -ENOMEM; 946db57d746STomasz Nowicki goto out_free; 947db57d746STomasz Nowicki } 948db57d746STomasz Nowicki 949db57d746STomasz Nowicki set_handle_irq(gic_handle_irq); 950db57d746STomasz Nowicki 951db40f0a7STomasz Nowicki if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis()) 952db40f0a7STomasz Nowicki its_init(handle, &gic_data.rdists, gic_data.domain); 953db57d746STomasz Nowicki 954db57d746STomasz Nowicki gic_smp_init(); 955db57d746STomasz Nowicki gic_dist_init(); 956db57d746STomasz Nowicki gic_cpu_init(); 957db57d746STomasz Nowicki gic_cpu_pm_init(); 958db57d746STomasz Nowicki 959db57d746STomasz Nowicki return 0; 960db57d746STomasz Nowicki 961db57d746STomasz Nowicki out_free: 962db57d746STomasz Nowicki if (gic_data.domain) 963db57d746STomasz Nowicki irq_domain_remove(gic_data.domain); 964db57d746STomasz Nowicki free_percpu(gic_data.rdists.rdist); 965db57d746STomasz Nowicki return err; 966db57d746STomasz Nowicki } 967db57d746STomasz Nowicki 968db57d746STomasz Nowicki static int __init gic_validate_dist_version(void __iomem *dist_base) 969db57d746STomasz Nowicki { 970db57d746STomasz Nowicki u32 reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK; 971db57d746STomasz Nowicki 972db57d746STomasz Nowicki if (reg != GIC_PIDR2_ARCH_GICv3 && reg != GIC_PIDR2_ARCH_GICv4) 973db57d746STomasz Nowicki return -ENODEV; 974db57d746STomasz Nowicki 975db57d746STomasz Nowicki return 0; 976db57d746STomasz Nowicki } 977db57d746STomasz Nowicki 978e3825ba1SMarc Zyngier static int get_cpu_number(struct device_node *dn) 979e3825ba1SMarc Zyngier { 980e3825ba1SMarc Zyngier const __be32 *cell; 981e3825ba1SMarc Zyngier u64 hwid; 982e3825ba1SMarc Zyngier int i; 983e3825ba1SMarc Zyngier 984e3825ba1SMarc Zyngier cell = of_get_property(dn, "reg", NULL); 985e3825ba1SMarc Zyngier if (!cell) 986e3825ba1SMarc Zyngier return -1; 987e3825ba1SMarc Zyngier 988e3825ba1SMarc Zyngier hwid = of_read_number(cell, of_n_addr_cells(dn)); 989e3825ba1SMarc Zyngier 990e3825ba1SMarc Zyngier /* 991e3825ba1SMarc Zyngier * Non affinity bits must be set to 0 in the DT 992e3825ba1SMarc Zyngier */ 993e3825ba1SMarc Zyngier if (hwid & ~MPIDR_HWID_BITMASK) 994e3825ba1SMarc Zyngier return -1; 995e3825ba1SMarc Zyngier 996e3825ba1SMarc Zyngier for (i = 0; i < num_possible_cpus(); i++) 997e3825ba1SMarc Zyngier if (cpu_logical_map(i) == hwid) 998e3825ba1SMarc Zyngier return i; 999e3825ba1SMarc Zyngier 1000e3825ba1SMarc Zyngier return -1; 1001e3825ba1SMarc Zyngier } 1002e3825ba1SMarc Zyngier 1003e3825ba1SMarc Zyngier /* Create all possible partitions at boot time */ 10047beaa24bSLinus Torvalds static void __init gic_populate_ppi_partitions(struct device_node *gic_node) 1005e3825ba1SMarc Zyngier { 1006e3825ba1SMarc Zyngier struct device_node *parts_node, *child_part; 1007e3825ba1SMarc Zyngier int part_idx = 0, i; 1008e3825ba1SMarc Zyngier int nr_parts; 1009e3825ba1SMarc Zyngier struct partition_affinity *parts; 1010e3825ba1SMarc Zyngier 1011e3825ba1SMarc Zyngier parts_node = of_find_node_by_name(gic_node, "ppi-partitions"); 1012e3825ba1SMarc Zyngier if (!parts_node) 1013e3825ba1SMarc Zyngier return; 1014e3825ba1SMarc Zyngier 1015e3825ba1SMarc Zyngier nr_parts = of_get_child_count(parts_node); 1016e3825ba1SMarc Zyngier 1017e3825ba1SMarc Zyngier if (!nr_parts) 1018e3825ba1SMarc Zyngier return; 1019e3825ba1SMarc Zyngier 1020e3825ba1SMarc Zyngier parts = kzalloc(sizeof(*parts) * nr_parts, GFP_KERNEL); 1021e3825ba1SMarc Zyngier if (WARN_ON(!parts)) 1022e3825ba1SMarc Zyngier return; 1023e3825ba1SMarc Zyngier 1024e3825ba1SMarc Zyngier for_each_child_of_node(parts_node, child_part) { 1025e3825ba1SMarc Zyngier struct partition_affinity *part; 1026e3825ba1SMarc Zyngier int n; 1027e3825ba1SMarc Zyngier 1028e3825ba1SMarc Zyngier part = &parts[part_idx]; 1029e3825ba1SMarc Zyngier 1030e3825ba1SMarc Zyngier part->partition_id = of_node_to_fwnode(child_part); 1031e3825ba1SMarc Zyngier 1032e3825ba1SMarc Zyngier pr_info("GIC: PPI partition %s[%d] { ", 1033e3825ba1SMarc Zyngier child_part->name, part_idx); 1034e3825ba1SMarc Zyngier 1035e3825ba1SMarc Zyngier n = of_property_count_elems_of_size(child_part, "affinity", 1036e3825ba1SMarc Zyngier sizeof(u32)); 1037e3825ba1SMarc Zyngier WARN_ON(n <= 0); 1038e3825ba1SMarc Zyngier 1039e3825ba1SMarc Zyngier for (i = 0; i < n; i++) { 1040e3825ba1SMarc Zyngier int err, cpu; 1041e3825ba1SMarc Zyngier u32 cpu_phandle; 1042e3825ba1SMarc Zyngier struct device_node *cpu_node; 1043e3825ba1SMarc Zyngier 1044e3825ba1SMarc Zyngier err = of_property_read_u32_index(child_part, "affinity", 1045e3825ba1SMarc Zyngier i, &cpu_phandle); 1046e3825ba1SMarc Zyngier if (WARN_ON(err)) 1047e3825ba1SMarc Zyngier continue; 1048e3825ba1SMarc Zyngier 1049e3825ba1SMarc Zyngier cpu_node = of_find_node_by_phandle(cpu_phandle); 1050e3825ba1SMarc Zyngier if (WARN_ON(!cpu_node)) 1051e3825ba1SMarc Zyngier continue; 1052e3825ba1SMarc Zyngier 1053e3825ba1SMarc Zyngier cpu = get_cpu_number(cpu_node); 1054e3825ba1SMarc Zyngier if (WARN_ON(cpu == -1)) 1055e3825ba1SMarc Zyngier continue; 1056e3825ba1SMarc Zyngier 1057e3825ba1SMarc Zyngier pr_cont("%s[%d] ", cpu_node->full_name, cpu); 1058e3825ba1SMarc Zyngier 1059e3825ba1SMarc Zyngier cpumask_set_cpu(cpu, &part->mask); 1060e3825ba1SMarc Zyngier } 1061e3825ba1SMarc Zyngier 1062e3825ba1SMarc Zyngier pr_cont("}\n"); 1063e3825ba1SMarc Zyngier part_idx++; 1064e3825ba1SMarc Zyngier } 1065e3825ba1SMarc Zyngier 1066e3825ba1SMarc Zyngier for (i = 0; i < 16; i++) { 1067e3825ba1SMarc Zyngier unsigned int irq; 1068e3825ba1SMarc Zyngier struct partition_desc *desc; 1069e3825ba1SMarc Zyngier struct irq_fwspec ppi_fwspec = { 1070e3825ba1SMarc Zyngier .fwnode = gic_data.fwnode, 1071e3825ba1SMarc Zyngier .param_count = 3, 1072e3825ba1SMarc Zyngier .param = { 1073e3825ba1SMarc Zyngier [0] = 1, 1074e3825ba1SMarc Zyngier [1] = i, 1075e3825ba1SMarc Zyngier [2] = IRQ_TYPE_NONE, 1076e3825ba1SMarc Zyngier }, 1077e3825ba1SMarc Zyngier }; 1078e3825ba1SMarc Zyngier 1079e3825ba1SMarc Zyngier irq = irq_create_fwspec_mapping(&ppi_fwspec); 1080e3825ba1SMarc Zyngier if (WARN_ON(!irq)) 1081e3825ba1SMarc Zyngier continue; 1082e3825ba1SMarc Zyngier desc = partition_create_desc(gic_data.fwnode, parts, nr_parts, 1083e3825ba1SMarc Zyngier irq, &partition_domain_ops); 1084e3825ba1SMarc Zyngier if (WARN_ON(!desc)) 1085e3825ba1SMarc Zyngier continue; 1086e3825ba1SMarc Zyngier 1087e3825ba1SMarc Zyngier gic_data.ppi_descs[i] = desc; 1088e3825ba1SMarc Zyngier } 1089e3825ba1SMarc Zyngier } 1090e3825ba1SMarc Zyngier 10911839e576SJulien Grall static void __init gic_of_setup_kvm_info(struct device_node *node) 10921839e576SJulien Grall { 10931839e576SJulien Grall int ret; 10941839e576SJulien Grall struct resource r; 10951839e576SJulien Grall u32 gicv_idx; 10961839e576SJulien Grall 10971839e576SJulien Grall gic_v3_kvm_info.type = GIC_V3; 10981839e576SJulien Grall 10991839e576SJulien Grall gic_v3_kvm_info.maint_irq = irq_of_parse_and_map(node, 0); 11001839e576SJulien Grall if (!gic_v3_kvm_info.maint_irq) 11011839e576SJulien Grall return; 11021839e576SJulien Grall 11031839e576SJulien Grall if (of_property_read_u32(node, "#redistributor-regions", 11041839e576SJulien Grall &gicv_idx)) 11051839e576SJulien Grall gicv_idx = 1; 11061839e576SJulien Grall 11071839e576SJulien Grall gicv_idx += 3; /* Also skip GICD, GICC, GICH */ 11081839e576SJulien Grall ret = of_address_to_resource(node, gicv_idx, &r); 11091839e576SJulien Grall if (!ret) 11101839e576SJulien Grall gic_v3_kvm_info.vcpu = r; 11111839e576SJulien Grall 11121839e576SJulien Grall gic_set_kvm_info(&gic_v3_kvm_info); 11131839e576SJulien Grall } 11141839e576SJulien Grall 1115021f6537SMarc Zyngier static int __init gic_of_init(struct device_node *node, struct device_node *parent) 1116021f6537SMarc Zyngier { 1117021f6537SMarc Zyngier void __iomem *dist_base; 1118f5c1434cSMarc Zyngier struct redist_region *rdist_regs; 1119021f6537SMarc Zyngier u64 redist_stride; 1120f5c1434cSMarc Zyngier u32 nr_redist_regions; 1121db57d746STomasz Nowicki int err, i; 1122021f6537SMarc Zyngier 1123021f6537SMarc Zyngier dist_base = of_iomap(node, 0); 1124021f6537SMarc Zyngier if (!dist_base) { 1125021f6537SMarc Zyngier pr_err("%s: unable to map gic dist registers\n", 1126021f6537SMarc Zyngier node->full_name); 1127021f6537SMarc Zyngier return -ENXIO; 1128021f6537SMarc Zyngier } 1129021f6537SMarc Zyngier 1130db57d746STomasz Nowicki err = gic_validate_dist_version(dist_base); 1131db57d746STomasz Nowicki if (err) { 1132021f6537SMarc Zyngier pr_err("%s: no distributor detected, giving up\n", 1133021f6537SMarc Zyngier node->full_name); 1134021f6537SMarc Zyngier goto out_unmap_dist; 1135021f6537SMarc Zyngier } 1136021f6537SMarc Zyngier 1137f5c1434cSMarc Zyngier if (of_property_read_u32(node, "#redistributor-regions", &nr_redist_regions)) 1138f5c1434cSMarc Zyngier nr_redist_regions = 1; 1139021f6537SMarc Zyngier 1140f5c1434cSMarc Zyngier rdist_regs = kzalloc(sizeof(*rdist_regs) * nr_redist_regions, GFP_KERNEL); 1141f5c1434cSMarc Zyngier if (!rdist_regs) { 1142021f6537SMarc Zyngier err = -ENOMEM; 1143021f6537SMarc Zyngier goto out_unmap_dist; 1144021f6537SMarc Zyngier } 1145021f6537SMarc Zyngier 1146f5c1434cSMarc Zyngier for (i = 0; i < nr_redist_regions; i++) { 1147f5c1434cSMarc Zyngier struct resource res; 1148f5c1434cSMarc Zyngier int ret; 1149f5c1434cSMarc Zyngier 1150f5c1434cSMarc Zyngier ret = of_address_to_resource(node, 1 + i, &res); 1151f5c1434cSMarc Zyngier rdist_regs[i].redist_base = of_iomap(node, 1 + i); 1152f5c1434cSMarc Zyngier if (ret || !rdist_regs[i].redist_base) { 1153021f6537SMarc Zyngier pr_err("%s: couldn't map region %d\n", 1154021f6537SMarc Zyngier node->full_name, i); 1155021f6537SMarc Zyngier err = -ENODEV; 1156021f6537SMarc Zyngier goto out_unmap_rdist; 1157021f6537SMarc Zyngier } 1158f5c1434cSMarc Zyngier rdist_regs[i].phys_base = res.start; 1159021f6537SMarc Zyngier } 1160021f6537SMarc Zyngier 1161021f6537SMarc Zyngier if (of_property_read_u64(node, "redistributor-stride", &redist_stride)) 1162021f6537SMarc Zyngier redist_stride = 0; 1163021f6537SMarc Zyngier 1164db57d746STomasz Nowicki err = gic_init_bases(dist_base, rdist_regs, nr_redist_regions, 1165db57d746STomasz Nowicki redist_stride, &node->fwnode); 1166e3825ba1SMarc Zyngier if (err) 1167e3825ba1SMarc Zyngier goto out_unmap_rdist; 1168e3825ba1SMarc Zyngier 1169e3825ba1SMarc Zyngier gic_populate_ppi_partitions(node); 11701839e576SJulien Grall gic_of_setup_kvm_info(node); 1171021f6537SMarc Zyngier return 0; 1172021f6537SMarc Zyngier 1173021f6537SMarc Zyngier out_unmap_rdist: 1174f5c1434cSMarc Zyngier for (i = 0; i < nr_redist_regions; i++) 1175f5c1434cSMarc Zyngier if (rdist_regs[i].redist_base) 1176f5c1434cSMarc Zyngier iounmap(rdist_regs[i].redist_base); 1177f5c1434cSMarc Zyngier kfree(rdist_regs); 1178021f6537SMarc Zyngier out_unmap_dist: 1179021f6537SMarc Zyngier iounmap(dist_base); 1180021f6537SMarc Zyngier return err; 1181021f6537SMarc Zyngier } 1182021f6537SMarc Zyngier 1183021f6537SMarc Zyngier IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init); 1184ffa7d616STomasz Nowicki 1185ffa7d616STomasz Nowicki #ifdef CONFIG_ACPI 1186611f039fSJulien Grall static struct 1187611f039fSJulien Grall { 1188611f039fSJulien Grall void __iomem *dist_base; 1189611f039fSJulien Grall struct redist_region *redist_regs; 1190611f039fSJulien Grall u32 nr_redist_regions; 1191611f039fSJulien Grall bool single_redist; 11921839e576SJulien Grall u32 maint_irq; 11931839e576SJulien Grall int maint_irq_mode; 11941839e576SJulien Grall phys_addr_t vcpu_base; 1195611f039fSJulien Grall } acpi_data __initdata; 1196b70fb7afSTomasz Nowicki 1197b70fb7afSTomasz Nowicki static void __init 1198b70fb7afSTomasz Nowicki gic_acpi_register_redist(phys_addr_t phys_base, void __iomem *redist_base) 1199b70fb7afSTomasz Nowicki { 1200b70fb7afSTomasz Nowicki static int count = 0; 1201b70fb7afSTomasz Nowicki 1202611f039fSJulien Grall acpi_data.redist_regs[count].phys_base = phys_base; 1203611f039fSJulien Grall acpi_data.redist_regs[count].redist_base = redist_base; 1204611f039fSJulien Grall acpi_data.redist_regs[count].single_redist = acpi_data.single_redist; 1205b70fb7afSTomasz Nowicki count++; 1206b70fb7afSTomasz Nowicki } 1207ffa7d616STomasz Nowicki 1208ffa7d616STomasz Nowicki static int __init 1209ffa7d616STomasz Nowicki gic_acpi_parse_madt_redist(struct acpi_subtable_header *header, 1210ffa7d616STomasz Nowicki const unsigned long end) 1211ffa7d616STomasz Nowicki { 1212ffa7d616STomasz Nowicki struct acpi_madt_generic_redistributor *redist = 1213ffa7d616STomasz Nowicki (struct acpi_madt_generic_redistributor *)header; 1214ffa7d616STomasz Nowicki void __iomem *redist_base; 1215ffa7d616STomasz Nowicki 1216ffa7d616STomasz Nowicki redist_base = ioremap(redist->base_address, redist->length); 1217ffa7d616STomasz Nowicki if (!redist_base) { 1218ffa7d616STomasz Nowicki pr_err("Couldn't map GICR region @%llx\n", redist->base_address); 1219ffa7d616STomasz Nowicki return -ENOMEM; 1220ffa7d616STomasz Nowicki } 1221ffa7d616STomasz Nowicki 1222b70fb7afSTomasz Nowicki gic_acpi_register_redist(redist->base_address, redist_base); 1223ffa7d616STomasz Nowicki return 0; 1224ffa7d616STomasz Nowicki } 1225ffa7d616STomasz Nowicki 1226b70fb7afSTomasz Nowicki static int __init 1227b70fb7afSTomasz Nowicki gic_acpi_parse_madt_gicc(struct acpi_subtable_header *header, 1228b70fb7afSTomasz Nowicki const unsigned long end) 1229b70fb7afSTomasz Nowicki { 1230b70fb7afSTomasz Nowicki struct acpi_madt_generic_interrupt *gicc = 1231b70fb7afSTomasz Nowicki (struct acpi_madt_generic_interrupt *)header; 1232611f039fSJulien Grall u32 reg = readl_relaxed(acpi_data.dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK; 1233b70fb7afSTomasz Nowicki u32 size = reg == GIC_PIDR2_ARCH_GICv4 ? SZ_64K * 4 : SZ_64K * 2; 1234b70fb7afSTomasz Nowicki void __iomem *redist_base; 1235b70fb7afSTomasz Nowicki 1236b70fb7afSTomasz Nowicki redist_base = ioremap(gicc->gicr_base_address, size); 1237b70fb7afSTomasz Nowicki if (!redist_base) 1238b70fb7afSTomasz Nowicki return -ENOMEM; 1239b70fb7afSTomasz Nowicki 1240b70fb7afSTomasz Nowicki gic_acpi_register_redist(gicc->gicr_base_address, redist_base); 1241b70fb7afSTomasz Nowicki return 0; 1242b70fb7afSTomasz Nowicki } 1243b70fb7afSTomasz Nowicki 1244b70fb7afSTomasz Nowicki static int __init gic_acpi_collect_gicr_base(void) 1245b70fb7afSTomasz Nowicki { 1246b70fb7afSTomasz Nowicki acpi_tbl_entry_handler redist_parser; 1247b70fb7afSTomasz Nowicki enum acpi_madt_type type; 1248b70fb7afSTomasz Nowicki 1249611f039fSJulien Grall if (acpi_data.single_redist) { 1250b70fb7afSTomasz Nowicki type = ACPI_MADT_TYPE_GENERIC_INTERRUPT; 1251b70fb7afSTomasz Nowicki redist_parser = gic_acpi_parse_madt_gicc; 1252b70fb7afSTomasz Nowicki } else { 1253b70fb7afSTomasz Nowicki type = ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR; 1254b70fb7afSTomasz Nowicki redist_parser = gic_acpi_parse_madt_redist; 1255b70fb7afSTomasz Nowicki } 1256b70fb7afSTomasz Nowicki 1257b70fb7afSTomasz Nowicki /* Collect redistributor base addresses in GICR entries */ 1258b70fb7afSTomasz Nowicki if (acpi_table_parse_madt(type, redist_parser, 0) > 0) 1259b70fb7afSTomasz Nowicki return 0; 1260b70fb7afSTomasz Nowicki 1261b70fb7afSTomasz Nowicki pr_info("No valid GICR entries exist\n"); 1262b70fb7afSTomasz Nowicki return -ENODEV; 1263b70fb7afSTomasz Nowicki } 1264b70fb7afSTomasz Nowicki 1265ffa7d616STomasz Nowicki static int __init gic_acpi_match_gicr(struct acpi_subtable_header *header, 1266ffa7d616STomasz Nowicki const unsigned long end) 1267ffa7d616STomasz Nowicki { 1268ffa7d616STomasz Nowicki /* Subtable presence means that redist exists, that's it */ 1269ffa7d616STomasz Nowicki return 0; 1270ffa7d616STomasz Nowicki } 1271ffa7d616STomasz Nowicki 1272b70fb7afSTomasz Nowicki static int __init gic_acpi_match_gicc(struct acpi_subtable_header *header, 1273b70fb7afSTomasz Nowicki const unsigned long end) 1274b70fb7afSTomasz Nowicki { 1275b70fb7afSTomasz Nowicki struct acpi_madt_generic_interrupt *gicc = 1276b70fb7afSTomasz Nowicki (struct acpi_madt_generic_interrupt *)header; 1277b70fb7afSTomasz Nowicki 1278b70fb7afSTomasz Nowicki /* 1279b70fb7afSTomasz Nowicki * If GICC is enabled and has valid gicr base address, then it means 1280b70fb7afSTomasz Nowicki * GICR base is presented via GICC 1281b70fb7afSTomasz Nowicki */ 1282b70fb7afSTomasz Nowicki if ((gicc->flags & ACPI_MADT_ENABLED) && gicc->gicr_base_address) 1283b70fb7afSTomasz Nowicki return 0; 1284b70fb7afSTomasz Nowicki 1285b70fb7afSTomasz Nowicki return -ENODEV; 1286b70fb7afSTomasz Nowicki } 1287b70fb7afSTomasz Nowicki 1288b70fb7afSTomasz Nowicki static int __init gic_acpi_count_gicr_regions(void) 1289b70fb7afSTomasz Nowicki { 1290b70fb7afSTomasz Nowicki int count; 1291b70fb7afSTomasz Nowicki 1292b70fb7afSTomasz Nowicki /* 1293b70fb7afSTomasz Nowicki * Count how many redistributor regions we have. It is not allowed 1294b70fb7afSTomasz Nowicki * to mix redistributor description, GICR and GICC subtables have to be 1295b70fb7afSTomasz Nowicki * mutually exclusive. 1296b70fb7afSTomasz Nowicki */ 1297b70fb7afSTomasz Nowicki count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR, 1298b70fb7afSTomasz Nowicki gic_acpi_match_gicr, 0); 1299b70fb7afSTomasz Nowicki if (count > 0) { 1300611f039fSJulien Grall acpi_data.single_redist = false; 1301b70fb7afSTomasz Nowicki return count; 1302b70fb7afSTomasz Nowicki } 1303b70fb7afSTomasz Nowicki 1304b70fb7afSTomasz Nowicki count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT, 1305b70fb7afSTomasz Nowicki gic_acpi_match_gicc, 0); 1306b70fb7afSTomasz Nowicki if (count > 0) 1307611f039fSJulien Grall acpi_data.single_redist = true; 1308b70fb7afSTomasz Nowicki 1309b70fb7afSTomasz Nowicki return count; 1310b70fb7afSTomasz Nowicki } 1311b70fb7afSTomasz Nowicki 1312ffa7d616STomasz Nowicki static bool __init acpi_validate_gic_table(struct acpi_subtable_header *header, 1313ffa7d616STomasz Nowicki struct acpi_probe_entry *ape) 1314ffa7d616STomasz Nowicki { 1315ffa7d616STomasz Nowicki struct acpi_madt_generic_distributor *dist; 1316ffa7d616STomasz Nowicki int count; 1317ffa7d616STomasz Nowicki 1318ffa7d616STomasz Nowicki dist = (struct acpi_madt_generic_distributor *)header; 1319ffa7d616STomasz Nowicki if (dist->version != ape->driver_data) 1320ffa7d616STomasz Nowicki return false; 1321ffa7d616STomasz Nowicki 1322ffa7d616STomasz Nowicki /* We need to do that exercise anyway, the sooner the better */ 1323b70fb7afSTomasz Nowicki count = gic_acpi_count_gicr_regions(); 1324ffa7d616STomasz Nowicki if (count <= 0) 1325ffa7d616STomasz Nowicki return false; 1326ffa7d616STomasz Nowicki 1327611f039fSJulien Grall acpi_data.nr_redist_regions = count; 1328ffa7d616STomasz Nowicki return true; 1329ffa7d616STomasz Nowicki } 1330ffa7d616STomasz Nowicki 13311839e576SJulien Grall static int __init gic_acpi_parse_virt_madt_gicc(struct acpi_subtable_header *header, 13321839e576SJulien Grall const unsigned long end) 13331839e576SJulien Grall { 13341839e576SJulien Grall struct acpi_madt_generic_interrupt *gicc = 13351839e576SJulien Grall (struct acpi_madt_generic_interrupt *)header; 13361839e576SJulien Grall int maint_irq_mode; 13371839e576SJulien Grall static int first_madt = true; 13381839e576SJulien Grall 13391839e576SJulien Grall /* Skip unusable CPUs */ 13401839e576SJulien Grall if (!(gicc->flags & ACPI_MADT_ENABLED)) 13411839e576SJulien Grall return 0; 13421839e576SJulien Grall 13431839e576SJulien Grall maint_irq_mode = (gicc->flags & ACPI_MADT_VGIC_IRQ_MODE) ? 13441839e576SJulien Grall ACPI_EDGE_SENSITIVE : ACPI_LEVEL_SENSITIVE; 13451839e576SJulien Grall 13461839e576SJulien Grall if (first_madt) { 13471839e576SJulien Grall first_madt = false; 13481839e576SJulien Grall 13491839e576SJulien Grall acpi_data.maint_irq = gicc->vgic_interrupt; 13501839e576SJulien Grall acpi_data.maint_irq_mode = maint_irq_mode; 13511839e576SJulien Grall acpi_data.vcpu_base = gicc->gicv_base_address; 13521839e576SJulien Grall 13531839e576SJulien Grall return 0; 13541839e576SJulien Grall } 13551839e576SJulien Grall 13561839e576SJulien Grall /* 13571839e576SJulien Grall * The maintenance interrupt and GICV should be the same for every CPU 13581839e576SJulien Grall */ 13591839e576SJulien Grall if ((acpi_data.maint_irq != gicc->vgic_interrupt) || 13601839e576SJulien Grall (acpi_data.maint_irq_mode != maint_irq_mode) || 13611839e576SJulien Grall (acpi_data.vcpu_base != gicc->gicv_base_address)) 13621839e576SJulien Grall return -EINVAL; 13631839e576SJulien Grall 13641839e576SJulien Grall return 0; 13651839e576SJulien Grall } 13661839e576SJulien Grall 13671839e576SJulien Grall static bool __init gic_acpi_collect_virt_info(void) 13681839e576SJulien Grall { 13691839e576SJulien Grall int count; 13701839e576SJulien Grall 13711839e576SJulien Grall count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT, 13721839e576SJulien Grall gic_acpi_parse_virt_madt_gicc, 0); 13731839e576SJulien Grall 13741839e576SJulien Grall return (count > 0); 13751839e576SJulien Grall } 13761839e576SJulien Grall 1377ffa7d616STomasz Nowicki #define ACPI_GICV3_DIST_MEM_SIZE (SZ_64K) 13781839e576SJulien Grall #define ACPI_GICV2_VCTRL_MEM_SIZE (SZ_4K) 13791839e576SJulien Grall #define ACPI_GICV2_VCPU_MEM_SIZE (SZ_8K) 13801839e576SJulien Grall 13811839e576SJulien Grall static void __init gic_acpi_setup_kvm_info(void) 13821839e576SJulien Grall { 13831839e576SJulien Grall int irq; 13841839e576SJulien Grall 13851839e576SJulien Grall if (!gic_acpi_collect_virt_info()) { 13861839e576SJulien Grall pr_warn("Unable to get hardware information used for virtualization\n"); 13871839e576SJulien Grall return; 13881839e576SJulien Grall } 13891839e576SJulien Grall 13901839e576SJulien Grall gic_v3_kvm_info.type = GIC_V3; 13911839e576SJulien Grall 13921839e576SJulien Grall irq = acpi_register_gsi(NULL, acpi_data.maint_irq, 13931839e576SJulien Grall acpi_data.maint_irq_mode, 13941839e576SJulien Grall ACPI_ACTIVE_HIGH); 13951839e576SJulien Grall if (irq <= 0) 13961839e576SJulien Grall return; 13971839e576SJulien Grall 13981839e576SJulien Grall gic_v3_kvm_info.maint_irq = irq; 13991839e576SJulien Grall 14001839e576SJulien Grall if (acpi_data.vcpu_base) { 14011839e576SJulien Grall struct resource *vcpu = &gic_v3_kvm_info.vcpu; 14021839e576SJulien Grall 14031839e576SJulien Grall vcpu->flags = IORESOURCE_MEM; 14041839e576SJulien Grall vcpu->start = acpi_data.vcpu_base; 14051839e576SJulien Grall vcpu->end = vcpu->start + ACPI_GICV2_VCPU_MEM_SIZE - 1; 14061839e576SJulien Grall } 14071839e576SJulien Grall 14081839e576SJulien Grall gic_set_kvm_info(&gic_v3_kvm_info); 14091839e576SJulien Grall } 1410ffa7d616STomasz Nowicki 1411ffa7d616STomasz Nowicki static int __init 1412ffa7d616STomasz Nowicki gic_acpi_init(struct acpi_subtable_header *header, const unsigned long end) 1413ffa7d616STomasz Nowicki { 1414ffa7d616STomasz Nowicki struct acpi_madt_generic_distributor *dist; 1415ffa7d616STomasz Nowicki struct fwnode_handle *domain_handle; 1416611f039fSJulien Grall size_t size; 1417b70fb7afSTomasz Nowicki int i, err; 1418ffa7d616STomasz Nowicki 1419ffa7d616STomasz Nowicki /* Get distributor base address */ 1420ffa7d616STomasz Nowicki dist = (struct acpi_madt_generic_distributor *)header; 1421611f039fSJulien Grall acpi_data.dist_base = ioremap(dist->base_address, 1422611f039fSJulien Grall ACPI_GICV3_DIST_MEM_SIZE); 1423611f039fSJulien Grall if (!acpi_data.dist_base) { 1424ffa7d616STomasz Nowicki pr_err("Unable to map GICD registers\n"); 1425ffa7d616STomasz Nowicki return -ENOMEM; 1426ffa7d616STomasz Nowicki } 1427ffa7d616STomasz Nowicki 1428611f039fSJulien Grall err = gic_validate_dist_version(acpi_data.dist_base); 1429ffa7d616STomasz Nowicki if (err) { 1430611f039fSJulien Grall pr_err("No distributor detected at @%p, giving up", 1431611f039fSJulien Grall acpi_data.dist_base); 1432ffa7d616STomasz Nowicki goto out_dist_unmap; 1433ffa7d616STomasz Nowicki } 1434ffa7d616STomasz Nowicki 1435611f039fSJulien Grall size = sizeof(*acpi_data.redist_regs) * acpi_data.nr_redist_regions; 1436611f039fSJulien Grall acpi_data.redist_regs = kzalloc(size, GFP_KERNEL); 1437611f039fSJulien Grall if (!acpi_data.redist_regs) { 1438ffa7d616STomasz Nowicki err = -ENOMEM; 1439ffa7d616STomasz Nowicki goto out_dist_unmap; 1440ffa7d616STomasz Nowicki } 1441ffa7d616STomasz Nowicki 1442b70fb7afSTomasz Nowicki err = gic_acpi_collect_gicr_base(); 1443b70fb7afSTomasz Nowicki if (err) 1444ffa7d616STomasz Nowicki goto out_redist_unmap; 1445ffa7d616STomasz Nowicki 1446611f039fSJulien Grall domain_handle = irq_domain_alloc_fwnode(acpi_data.dist_base); 1447ffa7d616STomasz Nowicki if (!domain_handle) { 1448ffa7d616STomasz Nowicki err = -ENOMEM; 1449ffa7d616STomasz Nowicki goto out_redist_unmap; 1450ffa7d616STomasz Nowicki } 1451ffa7d616STomasz Nowicki 1452611f039fSJulien Grall err = gic_init_bases(acpi_data.dist_base, acpi_data.redist_regs, 1453611f039fSJulien Grall acpi_data.nr_redist_regions, 0, domain_handle); 1454ffa7d616STomasz Nowicki if (err) 1455ffa7d616STomasz Nowicki goto out_fwhandle_free; 1456ffa7d616STomasz Nowicki 1457ffa7d616STomasz Nowicki acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, domain_handle); 14581839e576SJulien Grall gic_acpi_setup_kvm_info(); 14591839e576SJulien Grall 1460ffa7d616STomasz Nowicki return 0; 1461ffa7d616STomasz Nowicki 1462ffa7d616STomasz Nowicki out_fwhandle_free: 1463ffa7d616STomasz Nowicki irq_domain_free_fwnode(domain_handle); 1464ffa7d616STomasz Nowicki out_redist_unmap: 1465611f039fSJulien Grall for (i = 0; i < acpi_data.nr_redist_regions; i++) 1466611f039fSJulien Grall if (acpi_data.redist_regs[i].redist_base) 1467611f039fSJulien Grall iounmap(acpi_data.redist_regs[i].redist_base); 1468611f039fSJulien Grall kfree(acpi_data.redist_regs); 1469ffa7d616STomasz Nowicki out_dist_unmap: 1470611f039fSJulien Grall iounmap(acpi_data.dist_base); 1471ffa7d616STomasz Nowicki return err; 1472ffa7d616STomasz Nowicki } 1473ffa7d616STomasz Nowicki IRQCHIP_ACPI_DECLARE(gic_v3, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 1474ffa7d616STomasz Nowicki acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V3, 1475ffa7d616STomasz Nowicki gic_acpi_init); 1476ffa7d616STomasz Nowicki IRQCHIP_ACPI_DECLARE(gic_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 1477ffa7d616STomasz Nowicki acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V4, 1478ffa7d616STomasz Nowicki gic_acpi_init); 1479ffa7d616STomasz Nowicki IRQCHIP_ACPI_DECLARE(gic_v3_or_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 1480ffa7d616STomasz Nowicki acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_NONE, 1481ffa7d616STomasz Nowicki gic_acpi_init); 1482ffa7d616STomasz Nowicki #endif 1483