1021f6537SMarc Zyngier /* 20edc23eaSMarc Zyngier * Copyright (C) 2013-2017 ARM Limited, All Rights Reserved. 3021f6537SMarc Zyngier * Author: Marc Zyngier <marc.zyngier@arm.com> 4021f6537SMarc Zyngier * 5021f6537SMarc Zyngier * This program is free software; you can redistribute it and/or modify 6021f6537SMarc Zyngier * it under the terms of the GNU General Public License version 2 as 7021f6537SMarc Zyngier * published by the Free Software Foundation. 8021f6537SMarc Zyngier * 9021f6537SMarc Zyngier * This program is distributed in the hope that it will be useful, 10021f6537SMarc Zyngier * but WITHOUT ANY WARRANTY; without even the implied warranty of 11021f6537SMarc Zyngier * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12021f6537SMarc Zyngier * GNU General Public License for more details. 13021f6537SMarc Zyngier * 14021f6537SMarc Zyngier * You should have received a copy of the GNU General Public License 15021f6537SMarc Zyngier * along with this program. If not, see <http://www.gnu.org/licenses/>. 16021f6537SMarc Zyngier */ 17021f6537SMarc Zyngier 1868628bb8SJulien Grall #define pr_fmt(fmt) "GICv3: " fmt 1968628bb8SJulien Grall 20ffa7d616STomasz Nowicki #include <linux/acpi.h> 21021f6537SMarc Zyngier #include <linux/cpu.h> 223708d52fSSudeep Holla #include <linux/cpu_pm.h> 23021f6537SMarc Zyngier #include <linux/delay.h> 24021f6537SMarc Zyngier #include <linux/interrupt.h> 25ffa7d616STomasz Nowicki #include <linux/irqdomain.h> 26021f6537SMarc Zyngier #include <linux/of.h> 27021f6537SMarc Zyngier #include <linux/of_address.h> 28021f6537SMarc Zyngier #include <linux/of_irq.h> 29021f6537SMarc Zyngier #include <linux/percpu.h> 30101b35f7SJulien Thierry #include <linux/refcount.h> 31021f6537SMarc Zyngier #include <linux/slab.h> 32021f6537SMarc Zyngier 3341a83e06SJoel Porquet #include <linux/irqchip.h> 341839e576SJulien Grall #include <linux/irqchip/arm-gic-common.h> 35021f6537SMarc Zyngier #include <linux/irqchip/arm-gic-v3.h> 36e3825ba1SMarc Zyngier #include <linux/irqchip/irq-partition-percpu.h> 37021f6537SMarc Zyngier 38021f6537SMarc Zyngier #include <asm/cputype.h> 39021f6537SMarc Zyngier #include <asm/exception.h> 40021f6537SMarc Zyngier #include <asm/smp_plat.h> 410b6a3da9SMarc Zyngier #include <asm/virt.h> 42021f6537SMarc Zyngier 43021f6537SMarc Zyngier #include "irq-gic-common.h" 44021f6537SMarc Zyngier 45f32c9266SJulien Thierry #define GICD_INT_NMI_PRI (GICD_INT_DEF_PRI & ~0x80) 46f32c9266SJulien Thierry 479c8114c2SSrinivas Kandagatla #define FLAGS_WORKAROUND_GICR_WAKER_MSM8996 (1ULL << 0) 489c8114c2SSrinivas Kandagatla 49f5c1434cSMarc Zyngier struct redist_region { 50f5c1434cSMarc Zyngier void __iomem *redist_base; 51f5c1434cSMarc Zyngier phys_addr_t phys_base; 52b70fb7afSTomasz Nowicki bool single_redist; 53f5c1434cSMarc Zyngier }; 54f5c1434cSMarc Zyngier 55021f6537SMarc Zyngier struct gic_chip_data { 56e3825ba1SMarc Zyngier struct fwnode_handle *fwnode; 57021f6537SMarc Zyngier void __iomem *dist_base; 58f5c1434cSMarc Zyngier struct redist_region *redist_regions; 59f5c1434cSMarc Zyngier struct rdists rdists; 60021f6537SMarc Zyngier struct irq_domain *domain; 61021f6537SMarc Zyngier u64 redist_stride; 62f5c1434cSMarc Zyngier u32 nr_redist_regions; 639c8114c2SSrinivas Kandagatla u64 flags; 64eda0d04aSShanker Donthineni bool has_rss; 65021f6537SMarc Zyngier unsigned int irq_nr; 66e3825ba1SMarc Zyngier struct partition_desc *ppi_descs[16]; 67021f6537SMarc Zyngier }; 68021f6537SMarc Zyngier 69021f6537SMarc Zyngier static struct gic_chip_data gic_data __read_mostly; 70d01d3274SDavidlohr Bueso static DEFINE_STATIC_KEY_TRUE(supports_deactivate_key); 71021f6537SMarc Zyngier 72d98d0a99SJulien Thierry /* 73d98d0a99SJulien Thierry * The behaviours of RPR and PMR registers differ depending on the value of 74d98d0a99SJulien Thierry * SCR_EL3.FIQ, and the behaviour of non-secure priority registers of the 75d98d0a99SJulien Thierry * distributor and redistributors depends on whether security is enabled in the 76d98d0a99SJulien Thierry * GIC. 77d98d0a99SJulien Thierry * 78d98d0a99SJulien Thierry * When security is enabled, non-secure priority values from the (re)distributor 79d98d0a99SJulien Thierry * are presented to the GIC CPUIF as follow: 80d98d0a99SJulien Thierry * (GIC_(R)DIST_PRI[irq] >> 1) | 0x80; 81d98d0a99SJulien Thierry * 82d98d0a99SJulien Thierry * If SCR_EL3.FIQ == 1, the values writen to/read from PMR and RPR at non-secure 83d98d0a99SJulien Thierry * EL1 are subject to a similar operation thus matching the priorities presented 84d98d0a99SJulien Thierry * from the (re)distributor when security is enabled. 85d98d0a99SJulien Thierry * 86d98d0a99SJulien Thierry * see GICv3/GICv4 Architecture Specification (IHI0069D): 87d98d0a99SJulien Thierry * - section 4.8.1 Non-secure accesses to register fields for Secure interrupt 88d98d0a99SJulien Thierry * priorities. 89d98d0a99SJulien Thierry * - Figure 4-7 Secure read of the priority field for a Non-secure Group 1 90d98d0a99SJulien Thierry * interrupt. 91d98d0a99SJulien Thierry * 92d98d0a99SJulien Thierry * For now, we only support pseudo-NMIs if we have non-secure view of 93d98d0a99SJulien Thierry * priorities. 94d98d0a99SJulien Thierry */ 95d98d0a99SJulien Thierry static DEFINE_STATIC_KEY_FALSE(supports_pseudo_nmis); 96d98d0a99SJulien Thierry 97101b35f7SJulien Thierry /* ppi_nmi_refs[n] == number of cpus having ppi[n + 16] set as NMI */ 98101b35f7SJulien Thierry static refcount_t ppi_nmi_refs[16]; 99101b35f7SJulien Thierry 1001839e576SJulien Grall static struct gic_kvm_info gic_v3_kvm_info; 101eda0d04aSShanker Donthineni static DEFINE_PER_CPU(bool, has_rss); 1021839e576SJulien Grall 103eda0d04aSShanker Donthineni #define MPIDR_RS(mpidr) (((mpidr) & 0xF0UL) >> 4) 104f5c1434cSMarc Zyngier #define gic_data_rdist() (this_cpu_ptr(gic_data.rdists.rdist)) 105f5c1434cSMarc Zyngier #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base) 106021f6537SMarc Zyngier #define gic_data_rdist_sgi_base() (gic_data_rdist_rd_base() + SZ_64K) 107021f6537SMarc Zyngier 108021f6537SMarc Zyngier /* Our default, arbitrary priority value. Linux only uses one anyway. */ 109021f6537SMarc Zyngier #define DEFAULT_PMR_VALUE 0xf0 110021f6537SMarc Zyngier 111021f6537SMarc Zyngier static inline unsigned int gic_irq(struct irq_data *d) 112021f6537SMarc Zyngier { 113021f6537SMarc Zyngier return d->hwirq; 114021f6537SMarc Zyngier } 115021f6537SMarc Zyngier 116021f6537SMarc Zyngier static inline int gic_irq_in_rdist(struct irq_data *d) 117021f6537SMarc Zyngier { 118021f6537SMarc Zyngier return gic_irq(d) < 32; 119021f6537SMarc Zyngier } 120021f6537SMarc Zyngier 121021f6537SMarc Zyngier static inline void __iomem *gic_dist_base(struct irq_data *d) 122021f6537SMarc Zyngier { 123021f6537SMarc Zyngier if (gic_irq_in_rdist(d)) /* SGI+PPI -> SGI_base for this CPU */ 124021f6537SMarc Zyngier return gic_data_rdist_sgi_base(); 125021f6537SMarc Zyngier 126021f6537SMarc Zyngier if (d->hwirq <= 1023) /* SPI -> dist_base */ 127021f6537SMarc Zyngier return gic_data.dist_base; 128021f6537SMarc Zyngier 129021f6537SMarc Zyngier return NULL; 130021f6537SMarc Zyngier } 131021f6537SMarc Zyngier 132021f6537SMarc Zyngier static void gic_do_wait_for_rwp(void __iomem *base) 133021f6537SMarc Zyngier { 134021f6537SMarc Zyngier u32 count = 1000000; /* 1s! */ 135021f6537SMarc Zyngier 136021f6537SMarc Zyngier while (readl_relaxed(base + GICD_CTLR) & GICD_CTLR_RWP) { 137021f6537SMarc Zyngier count--; 138021f6537SMarc Zyngier if (!count) { 139021f6537SMarc Zyngier pr_err_ratelimited("RWP timeout, gone fishing\n"); 140021f6537SMarc Zyngier return; 141021f6537SMarc Zyngier } 142021f6537SMarc Zyngier cpu_relax(); 143021f6537SMarc Zyngier udelay(1); 144021f6537SMarc Zyngier }; 145021f6537SMarc Zyngier } 146021f6537SMarc Zyngier 147021f6537SMarc Zyngier /* Wait for completion of a distributor change */ 148021f6537SMarc Zyngier static void gic_dist_wait_for_rwp(void) 149021f6537SMarc Zyngier { 150021f6537SMarc Zyngier gic_do_wait_for_rwp(gic_data.dist_base); 151021f6537SMarc Zyngier } 152021f6537SMarc Zyngier 153021f6537SMarc Zyngier /* Wait for completion of a redistributor change */ 154021f6537SMarc Zyngier static void gic_redist_wait_for_rwp(void) 155021f6537SMarc Zyngier { 156021f6537SMarc Zyngier gic_do_wait_for_rwp(gic_data_rdist_rd_base()); 157021f6537SMarc Zyngier } 158021f6537SMarc Zyngier 1597936e914SJean-Philippe Brucker #ifdef CONFIG_ARM64 1606d4e11c5SRobert Richter 1616d4e11c5SRobert Richter static u64 __maybe_unused gic_read_iar(void) 1626d4e11c5SRobert Richter { 163a4023f68SSuzuki K Poulose if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_23154)) 1646d4e11c5SRobert Richter return gic_read_iar_cavium_thunderx(); 1656d4e11c5SRobert Richter else 1666d4e11c5SRobert Richter return gic_read_iar_common(); 1676d4e11c5SRobert Richter } 1687936e914SJean-Philippe Brucker #endif 169021f6537SMarc Zyngier 170a2c22510SSudeep Holla static void gic_enable_redist(bool enable) 171021f6537SMarc Zyngier { 172021f6537SMarc Zyngier void __iomem *rbase; 173021f6537SMarc Zyngier u32 count = 1000000; /* 1s! */ 174021f6537SMarc Zyngier u32 val; 175021f6537SMarc Zyngier 1769c8114c2SSrinivas Kandagatla if (gic_data.flags & FLAGS_WORKAROUND_GICR_WAKER_MSM8996) 1779c8114c2SSrinivas Kandagatla return; 1789c8114c2SSrinivas Kandagatla 179021f6537SMarc Zyngier rbase = gic_data_rdist_rd_base(); 180021f6537SMarc Zyngier 181021f6537SMarc Zyngier val = readl_relaxed(rbase + GICR_WAKER); 182a2c22510SSudeep Holla if (enable) 183a2c22510SSudeep Holla /* Wake up this CPU redistributor */ 184021f6537SMarc Zyngier val &= ~GICR_WAKER_ProcessorSleep; 185a2c22510SSudeep Holla else 186a2c22510SSudeep Holla val |= GICR_WAKER_ProcessorSleep; 187021f6537SMarc Zyngier writel_relaxed(val, rbase + GICR_WAKER); 188021f6537SMarc Zyngier 189a2c22510SSudeep Holla if (!enable) { /* Check that GICR_WAKER is writeable */ 190a2c22510SSudeep Holla val = readl_relaxed(rbase + GICR_WAKER); 191a2c22510SSudeep Holla if (!(val & GICR_WAKER_ProcessorSleep)) 192a2c22510SSudeep Holla return; /* No PM support in this redistributor */ 193021f6537SMarc Zyngier } 194a2c22510SSudeep Holla 195d102eb5cSDan Carpenter while (--count) { 196a2c22510SSudeep Holla val = readl_relaxed(rbase + GICR_WAKER); 197cf1d9d11SAndrew Jones if (enable ^ (bool)(val & GICR_WAKER_ChildrenAsleep)) 198a2c22510SSudeep Holla break; 199021f6537SMarc Zyngier cpu_relax(); 200021f6537SMarc Zyngier udelay(1); 201021f6537SMarc Zyngier }; 202a2c22510SSudeep Holla if (!count) 203a2c22510SSudeep Holla pr_err_ratelimited("redistributor failed to %s...\n", 204a2c22510SSudeep Holla enable ? "wakeup" : "sleep"); 205021f6537SMarc Zyngier } 206021f6537SMarc Zyngier 207021f6537SMarc Zyngier /* 208021f6537SMarc Zyngier * Routines to disable, enable, EOI and route interrupts 209021f6537SMarc Zyngier */ 210b594c6e2SMarc Zyngier static int gic_peek_irq(struct irq_data *d, u32 offset) 211b594c6e2SMarc Zyngier { 212b594c6e2SMarc Zyngier u32 mask = 1 << (gic_irq(d) % 32); 213b594c6e2SMarc Zyngier void __iomem *base; 214b594c6e2SMarc Zyngier 215b594c6e2SMarc Zyngier if (gic_irq_in_rdist(d)) 216b594c6e2SMarc Zyngier base = gic_data_rdist_sgi_base(); 217b594c6e2SMarc Zyngier else 218b594c6e2SMarc Zyngier base = gic_data.dist_base; 219b594c6e2SMarc Zyngier 220b594c6e2SMarc Zyngier return !!(readl_relaxed(base + offset + (gic_irq(d) / 32) * 4) & mask); 221b594c6e2SMarc Zyngier } 222b594c6e2SMarc Zyngier 223021f6537SMarc Zyngier static void gic_poke_irq(struct irq_data *d, u32 offset) 224021f6537SMarc Zyngier { 225021f6537SMarc Zyngier u32 mask = 1 << (gic_irq(d) % 32); 226021f6537SMarc Zyngier void (*rwp_wait)(void); 227021f6537SMarc Zyngier void __iomem *base; 228021f6537SMarc Zyngier 229021f6537SMarc Zyngier if (gic_irq_in_rdist(d)) { 230021f6537SMarc Zyngier base = gic_data_rdist_sgi_base(); 231021f6537SMarc Zyngier rwp_wait = gic_redist_wait_for_rwp; 232021f6537SMarc Zyngier } else { 233021f6537SMarc Zyngier base = gic_data.dist_base; 234021f6537SMarc Zyngier rwp_wait = gic_dist_wait_for_rwp; 235021f6537SMarc Zyngier } 236021f6537SMarc Zyngier 237021f6537SMarc Zyngier writel_relaxed(mask, base + offset + (gic_irq(d) / 32) * 4); 238021f6537SMarc Zyngier rwp_wait(); 239021f6537SMarc Zyngier } 240021f6537SMarc Zyngier 241021f6537SMarc Zyngier static void gic_mask_irq(struct irq_data *d) 242021f6537SMarc Zyngier { 243021f6537SMarc Zyngier gic_poke_irq(d, GICD_ICENABLER); 244021f6537SMarc Zyngier } 245021f6537SMarc Zyngier 2460b6a3da9SMarc Zyngier static void gic_eoimode1_mask_irq(struct irq_data *d) 2470b6a3da9SMarc Zyngier { 2480b6a3da9SMarc Zyngier gic_mask_irq(d); 249530bf353SMarc Zyngier /* 250530bf353SMarc Zyngier * When masking a forwarded interrupt, make sure it is 251530bf353SMarc Zyngier * deactivated as well. 252530bf353SMarc Zyngier * 253530bf353SMarc Zyngier * This ensures that an interrupt that is getting 254530bf353SMarc Zyngier * disabled/masked will not get "stuck", because there is 255530bf353SMarc Zyngier * noone to deactivate it (guest is being terminated). 256530bf353SMarc Zyngier */ 2574df7f54dSThomas Gleixner if (irqd_is_forwarded_to_vcpu(d)) 258530bf353SMarc Zyngier gic_poke_irq(d, GICD_ICACTIVER); 2590b6a3da9SMarc Zyngier } 2600b6a3da9SMarc Zyngier 261021f6537SMarc Zyngier static void gic_unmask_irq(struct irq_data *d) 262021f6537SMarc Zyngier { 263021f6537SMarc Zyngier gic_poke_irq(d, GICD_ISENABLER); 264021f6537SMarc Zyngier } 265021f6537SMarc Zyngier 266d98d0a99SJulien Thierry static inline bool gic_supports_nmi(void) 267d98d0a99SJulien Thierry { 268d98d0a99SJulien Thierry return IS_ENABLED(CONFIG_ARM64_PSEUDO_NMI) && 269d98d0a99SJulien Thierry static_branch_likely(&supports_pseudo_nmis); 270d98d0a99SJulien Thierry } 271d98d0a99SJulien Thierry 272b594c6e2SMarc Zyngier static int gic_irq_set_irqchip_state(struct irq_data *d, 273b594c6e2SMarc Zyngier enum irqchip_irq_state which, bool val) 274b594c6e2SMarc Zyngier { 275b594c6e2SMarc Zyngier u32 reg; 276b594c6e2SMarc Zyngier 277b594c6e2SMarc Zyngier if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */ 278b594c6e2SMarc Zyngier return -EINVAL; 279b594c6e2SMarc Zyngier 280b594c6e2SMarc Zyngier switch (which) { 281b594c6e2SMarc Zyngier case IRQCHIP_STATE_PENDING: 282b594c6e2SMarc Zyngier reg = val ? GICD_ISPENDR : GICD_ICPENDR; 283b594c6e2SMarc Zyngier break; 284b594c6e2SMarc Zyngier 285b594c6e2SMarc Zyngier case IRQCHIP_STATE_ACTIVE: 286b594c6e2SMarc Zyngier reg = val ? GICD_ISACTIVER : GICD_ICACTIVER; 287b594c6e2SMarc Zyngier break; 288b594c6e2SMarc Zyngier 289b594c6e2SMarc Zyngier case IRQCHIP_STATE_MASKED: 290b594c6e2SMarc Zyngier reg = val ? GICD_ICENABLER : GICD_ISENABLER; 291b594c6e2SMarc Zyngier break; 292b594c6e2SMarc Zyngier 293b594c6e2SMarc Zyngier default: 294b594c6e2SMarc Zyngier return -EINVAL; 295b594c6e2SMarc Zyngier } 296b594c6e2SMarc Zyngier 297b594c6e2SMarc Zyngier gic_poke_irq(d, reg); 298b594c6e2SMarc Zyngier return 0; 299b594c6e2SMarc Zyngier } 300b594c6e2SMarc Zyngier 301b594c6e2SMarc Zyngier static int gic_irq_get_irqchip_state(struct irq_data *d, 302b594c6e2SMarc Zyngier enum irqchip_irq_state which, bool *val) 303b594c6e2SMarc Zyngier { 304b594c6e2SMarc Zyngier if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */ 305b594c6e2SMarc Zyngier return -EINVAL; 306b594c6e2SMarc Zyngier 307b594c6e2SMarc Zyngier switch (which) { 308b594c6e2SMarc Zyngier case IRQCHIP_STATE_PENDING: 309b594c6e2SMarc Zyngier *val = gic_peek_irq(d, GICD_ISPENDR); 310b594c6e2SMarc Zyngier break; 311b594c6e2SMarc Zyngier 312b594c6e2SMarc Zyngier case IRQCHIP_STATE_ACTIVE: 313b594c6e2SMarc Zyngier *val = gic_peek_irq(d, GICD_ISACTIVER); 314b594c6e2SMarc Zyngier break; 315b594c6e2SMarc Zyngier 316b594c6e2SMarc Zyngier case IRQCHIP_STATE_MASKED: 317b594c6e2SMarc Zyngier *val = !gic_peek_irq(d, GICD_ISENABLER); 318b594c6e2SMarc Zyngier break; 319b594c6e2SMarc Zyngier 320b594c6e2SMarc Zyngier default: 321b594c6e2SMarc Zyngier return -EINVAL; 322b594c6e2SMarc Zyngier } 323b594c6e2SMarc Zyngier 324b594c6e2SMarc Zyngier return 0; 325b594c6e2SMarc Zyngier } 326b594c6e2SMarc Zyngier 327101b35f7SJulien Thierry static void gic_irq_set_prio(struct irq_data *d, u8 prio) 328101b35f7SJulien Thierry { 329101b35f7SJulien Thierry void __iomem *base = gic_dist_base(d); 330101b35f7SJulien Thierry 331101b35f7SJulien Thierry writeb_relaxed(prio, base + GICD_IPRIORITYR + gic_irq(d)); 332101b35f7SJulien Thierry } 333101b35f7SJulien Thierry 334101b35f7SJulien Thierry static int gic_irq_nmi_setup(struct irq_data *d) 335101b35f7SJulien Thierry { 336101b35f7SJulien Thierry struct irq_desc *desc = irq_to_desc(d->irq); 337101b35f7SJulien Thierry 338101b35f7SJulien Thierry if (!gic_supports_nmi()) 339101b35f7SJulien Thierry return -EINVAL; 340101b35f7SJulien Thierry 341101b35f7SJulien Thierry if (gic_peek_irq(d, GICD_ISENABLER)) { 342101b35f7SJulien Thierry pr_err("Cannot set NMI property of enabled IRQ %u\n", d->irq); 343101b35f7SJulien Thierry return -EINVAL; 344101b35f7SJulien Thierry } 345101b35f7SJulien Thierry 346101b35f7SJulien Thierry /* 347101b35f7SJulien Thierry * A secondary irq_chip should be in charge of LPI request, 348101b35f7SJulien Thierry * it should not be possible to get there 349101b35f7SJulien Thierry */ 350101b35f7SJulien Thierry if (WARN_ON(gic_irq(d) >= 8192)) 351101b35f7SJulien Thierry return -EINVAL; 352101b35f7SJulien Thierry 353101b35f7SJulien Thierry /* desc lock should already be held */ 354101b35f7SJulien Thierry if (gic_irq(d) < 32) { 355101b35f7SJulien Thierry /* Setting up PPI as NMI, only switch handler for first NMI */ 356101b35f7SJulien Thierry if (!refcount_inc_not_zero(&ppi_nmi_refs[gic_irq(d) - 16])) { 357101b35f7SJulien Thierry refcount_set(&ppi_nmi_refs[gic_irq(d) - 16], 1); 358101b35f7SJulien Thierry desc->handle_irq = handle_percpu_devid_fasteoi_nmi; 359101b35f7SJulien Thierry } 360101b35f7SJulien Thierry } else { 361101b35f7SJulien Thierry desc->handle_irq = handle_fasteoi_nmi; 362101b35f7SJulien Thierry } 363101b35f7SJulien Thierry 364101b35f7SJulien Thierry gic_irq_set_prio(d, GICD_INT_NMI_PRI); 365101b35f7SJulien Thierry 366101b35f7SJulien Thierry return 0; 367101b35f7SJulien Thierry } 368101b35f7SJulien Thierry 369101b35f7SJulien Thierry static void gic_irq_nmi_teardown(struct irq_data *d) 370101b35f7SJulien Thierry { 371101b35f7SJulien Thierry struct irq_desc *desc = irq_to_desc(d->irq); 372101b35f7SJulien Thierry 373101b35f7SJulien Thierry if (WARN_ON(!gic_supports_nmi())) 374101b35f7SJulien Thierry return; 375101b35f7SJulien Thierry 376101b35f7SJulien Thierry if (gic_peek_irq(d, GICD_ISENABLER)) { 377101b35f7SJulien Thierry pr_err("Cannot set NMI property of enabled IRQ %u\n", d->irq); 378101b35f7SJulien Thierry return; 379101b35f7SJulien Thierry } 380101b35f7SJulien Thierry 381101b35f7SJulien Thierry /* 382101b35f7SJulien Thierry * A secondary irq_chip should be in charge of LPI request, 383101b35f7SJulien Thierry * it should not be possible to get there 384101b35f7SJulien Thierry */ 385101b35f7SJulien Thierry if (WARN_ON(gic_irq(d) >= 8192)) 386101b35f7SJulien Thierry return; 387101b35f7SJulien Thierry 388101b35f7SJulien Thierry /* desc lock should already be held */ 389101b35f7SJulien Thierry if (gic_irq(d) < 32) { 390101b35f7SJulien Thierry /* Tearing down NMI, only switch handler for last NMI */ 391101b35f7SJulien Thierry if (refcount_dec_and_test(&ppi_nmi_refs[gic_irq(d) - 16])) 392101b35f7SJulien Thierry desc->handle_irq = handle_percpu_devid_irq; 393101b35f7SJulien Thierry } else { 394101b35f7SJulien Thierry desc->handle_irq = handle_fasteoi_irq; 395101b35f7SJulien Thierry } 396101b35f7SJulien Thierry 397101b35f7SJulien Thierry gic_irq_set_prio(d, GICD_INT_DEF_PRI); 398101b35f7SJulien Thierry } 399101b35f7SJulien Thierry 400021f6537SMarc Zyngier static void gic_eoi_irq(struct irq_data *d) 401021f6537SMarc Zyngier { 402021f6537SMarc Zyngier gic_write_eoir(gic_irq(d)); 403021f6537SMarc Zyngier } 404021f6537SMarc Zyngier 4050b6a3da9SMarc Zyngier static void gic_eoimode1_eoi_irq(struct irq_data *d) 4060b6a3da9SMarc Zyngier { 4070b6a3da9SMarc Zyngier /* 408530bf353SMarc Zyngier * No need to deactivate an LPI, or an interrupt that 409530bf353SMarc Zyngier * is is getting forwarded to a vcpu. 4100b6a3da9SMarc Zyngier */ 4114df7f54dSThomas Gleixner if (gic_irq(d) >= 8192 || irqd_is_forwarded_to_vcpu(d)) 4120b6a3da9SMarc Zyngier return; 4130b6a3da9SMarc Zyngier gic_write_dir(gic_irq(d)); 4140b6a3da9SMarc Zyngier } 4150b6a3da9SMarc Zyngier 416021f6537SMarc Zyngier static int gic_set_type(struct irq_data *d, unsigned int type) 417021f6537SMarc Zyngier { 418021f6537SMarc Zyngier unsigned int irq = gic_irq(d); 419021f6537SMarc Zyngier void (*rwp_wait)(void); 420021f6537SMarc Zyngier void __iomem *base; 421021f6537SMarc Zyngier 422021f6537SMarc Zyngier /* Interrupt configuration for SGIs can't be changed */ 423021f6537SMarc Zyngier if (irq < 16) 424021f6537SMarc Zyngier return -EINVAL; 425021f6537SMarc Zyngier 426fb7e7debSLiviu Dudau /* SPIs have restrictions on the supported types */ 427fb7e7debSLiviu Dudau if (irq >= 32 && type != IRQ_TYPE_LEVEL_HIGH && 428fb7e7debSLiviu Dudau type != IRQ_TYPE_EDGE_RISING) 429021f6537SMarc Zyngier return -EINVAL; 430021f6537SMarc Zyngier 431021f6537SMarc Zyngier if (gic_irq_in_rdist(d)) { 432021f6537SMarc Zyngier base = gic_data_rdist_sgi_base(); 433021f6537SMarc Zyngier rwp_wait = gic_redist_wait_for_rwp; 434021f6537SMarc Zyngier } else { 435021f6537SMarc Zyngier base = gic_data.dist_base; 436021f6537SMarc Zyngier rwp_wait = gic_dist_wait_for_rwp; 437021f6537SMarc Zyngier } 438021f6537SMarc Zyngier 439fb7e7debSLiviu Dudau return gic_configure_irq(irq, type, base, rwp_wait); 440021f6537SMarc Zyngier } 441021f6537SMarc Zyngier 442530bf353SMarc Zyngier static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu) 443530bf353SMarc Zyngier { 4444df7f54dSThomas Gleixner if (vcpu) 4454df7f54dSThomas Gleixner irqd_set_forwarded_to_vcpu(d); 4464df7f54dSThomas Gleixner else 4474df7f54dSThomas Gleixner irqd_clr_forwarded_to_vcpu(d); 448530bf353SMarc Zyngier return 0; 449530bf353SMarc Zyngier } 450530bf353SMarc Zyngier 451f6c86a41SJean-Philippe Brucker static u64 gic_mpidr_to_affinity(unsigned long mpidr) 452021f6537SMarc Zyngier { 453021f6537SMarc Zyngier u64 aff; 454021f6537SMarc Zyngier 455f6c86a41SJean-Philippe Brucker aff = ((u64)MPIDR_AFFINITY_LEVEL(mpidr, 3) << 32 | 456021f6537SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 | 457021f6537SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | 458021f6537SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 0)); 459021f6537SMarc Zyngier 460021f6537SMarc Zyngier return aff; 461021f6537SMarc Zyngier } 462021f6537SMarc Zyngier 463f32c9266SJulien Thierry static void gic_deactivate_unhandled(u32 irqnr) 464f32c9266SJulien Thierry { 465f32c9266SJulien Thierry if (static_branch_likely(&supports_deactivate_key)) { 466f32c9266SJulien Thierry if (irqnr < 8192) 467f32c9266SJulien Thierry gic_write_dir(irqnr); 468f32c9266SJulien Thierry } else { 469f32c9266SJulien Thierry gic_write_eoir(irqnr); 470f32c9266SJulien Thierry } 471f32c9266SJulien Thierry } 472f32c9266SJulien Thierry 473f32c9266SJulien Thierry static inline void gic_handle_nmi(u32 irqnr, struct pt_regs *regs) 474f32c9266SJulien Thierry { 475f32c9266SJulien Thierry int err; 476f32c9266SJulien Thierry 477f32c9266SJulien Thierry if (static_branch_likely(&supports_deactivate_key)) 478f32c9266SJulien Thierry gic_write_eoir(irqnr); 479f32c9266SJulien Thierry /* 480f32c9266SJulien Thierry * Leave the PSR.I bit set to prevent other NMIs to be 481f32c9266SJulien Thierry * received while handling this one. 482f32c9266SJulien Thierry * PSR.I will be restored when we ERET to the 483f32c9266SJulien Thierry * interrupted context. 484f32c9266SJulien Thierry */ 485f32c9266SJulien Thierry err = handle_domain_nmi(gic_data.domain, irqnr, regs); 486f32c9266SJulien Thierry if (err) 487f32c9266SJulien Thierry gic_deactivate_unhandled(irqnr); 488f32c9266SJulien Thierry } 489f32c9266SJulien Thierry 490021f6537SMarc Zyngier static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) 491021f6537SMarc Zyngier { 492f6c86a41SJean-Philippe Brucker u32 irqnr; 493021f6537SMarc Zyngier 494021f6537SMarc Zyngier irqnr = gic_read_iar(); 495021f6537SMarc Zyngier 496f32c9266SJulien Thierry if (gic_supports_nmi() && 497f32c9266SJulien Thierry unlikely(gic_read_rpr() == GICD_INT_NMI_PRI)) { 498f32c9266SJulien Thierry gic_handle_nmi(irqnr, regs); 499f32c9266SJulien Thierry return; 500f32c9266SJulien Thierry } 501f32c9266SJulien Thierry 5023f1f3234SJulien Thierry if (gic_prio_masking_enabled()) { 5033f1f3234SJulien Thierry gic_pmr_mask_irqs(); 5043f1f3234SJulien Thierry gic_arch_enable_irqs(); 5053f1f3234SJulien Thierry } 5063f1f3234SJulien Thierry 507da33f31dSMarc Zyngier if (likely(irqnr > 15 && irqnr < 1020) || irqnr >= 8192) { 508ebc6de00SMarc Zyngier int err; 5090b6a3da9SMarc Zyngier 510d01d3274SDavidlohr Bueso if (static_branch_likely(&supports_deactivate_key)) 5110b6a3da9SMarc Zyngier gic_write_eoir(irqnr); 51239a06b67SWill Deacon else 51339a06b67SWill Deacon isb(); 5140b6a3da9SMarc Zyngier 515ebc6de00SMarc Zyngier err = handle_domain_irq(gic_data.domain, irqnr, regs); 516ebc6de00SMarc Zyngier if (err) { 517da33f31dSMarc Zyngier WARN_ONCE(true, "Unexpected interrupt received!\n"); 518f32c9266SJulien Thierry gic_deactivate_unhandled(irqnr); 5190b6a3da9SMarc Zyngier } 520342677d7SJulien Thierry return; 521ebc6de00SMarc Zyngier } 522021f6537SMarc Zyngier if (irqnr < 16) { 523021f6537SMarc Zyngier gic_write_eoir(irqnr); 524d01d3274SDavidlohr Bueso if (static_branch_likely(&supports_deactivate_key)) 5250b6a3da9SMarc Zyngier gic_write_dir(irqnr); 526021f6537SMarc Zyngier #ifdef CONFIG_SMP 527f86c4fbdSWill Deacon /* 528f86c4fbdSWill Deacon * Unlike GICv2, we don't need an smp_rmb() here. 529f86c4fbdSWill Deacon * The control dependency from gic_read_iar to 530f86c4fbdSWill Deacon * the ISB in gic_write_eoir is enough to ensure 531f86c4fbdSWill Deacon * that any shared data read by handle_IPI will 532f86c4fbdSWill Deacon * be read after the ACK. 533f86c4fbdSWill Deacon */ 534021f6537SMarc Zyngier handle_IPI(irqnr, regs); 535021f6537SMarc Zyngier #else 536021f6537SMarc Zyngier WARN_ONCE(true, "Unexpected SGI received!\n"); 537021f6537SMarc Zyngier #endif 538021f6537SMarc Zyngier } 539021f6537SMarc Zyngier } 540021f6537SMarc Zyngier 541b5cf6073SJulien Thierry static u32 gic_get_pribits(void) 542b5cf6073SJulien Thierry { 543b5cf6073SJulien Thierry u32 pribits; 544b5cf6073SJulien Thierry 545b5cf6073SJulien Thierry pribits = gic_read_ctlr(); 546b5cf6073SJulien Thierry pribits &= ICC_CTLR_EL1_PRI_BITS_MASK; 547b5cf6073SJulien Thierry pribits >>= ICC_CTLR_EL1_PRI_BITS_SHIFT; 548b5cf6073SJulien Thierry pribits++; 549b5cf6073SJulien Thierry 550b5cf6073SJulien Thierry return pribits; 551b5cf6073SJulien Thierry } 552b5cf6073SJulien Thierry 553b5cf6073SJulien Thierry static bool gic_has_group0(void) 554b5cf6073SJulien Thierry { 555b5cf6073SJulien Thierry u32 val; 556e7932188SJulien Thierry u32 old_pmr; 557e7932188SJulien Thierry 558e7932188SJulien Thierry old_pmr = gic_read_pmr(); 559b5cf6073SJulien Thierry 560b5cf6073SJulien Thierry /* 561b5cf6073SJulien Thierry * Let's find out if Group0 is under control of EL3 or not by 562b5cf6073SJulien Thierry * setting the highest possible, non-zero priority in PMR. 563b5cf6073SJulien Thierry * 564b5cf6073SJulien Thierry * If SCR_EL3.FIQ is set, the priority gets shifted down in 565b5cf6073SJulien Thierry * order for the CPU interface to set bit 7, and keep the 566b5cf6073SJulien Thierry * actual priority in the non-secure range. In the process, it 567b5cf6073SJulien Thierry * looses the least significant bit and the actual priority 568b5cf6073SJulien Thierry * becomes 0x80. Reading it back returns 0, indicating that 569b5cf6073SJulien Thierry * we're don't have access to Group0. 570b5cf6073SJulien Thierry */ 571b5cf6073SJulien Thierry gic_write_pmr(BIT(8 - gic_get_pribits())); 572b5cf6073SJulien Thierry val = gic_read_pmr(); 573b5cf6073SJulien Thierry 574e7932188SJulien Thierry gic_write_pmr(old_pmr); 575e7932188SJulien Thierry 576b5cf6073SJulien Thierry return val != 0; 577b5cf6073SJulien Thierry } 578b5cf6073SJulien Thierry 579021f6537SMarc Zyngier static void __init gic_dist_init(void) 580021f6537SMarc Zyngier { 581021f6537SMarc Zyngier unsigned int i; 582021f6537SMarc Zyngier u64 affinity; 583021f6537SMarc Zyngier void __iomem *base = gic_data.dist_base; 584021f6537SMarc Zyngier 585021f6537SMarc Zyngier /* Disable the distributor */ 586021f6537SMarc Zyngier writel_relaxed(0, base + GICD_CTLR); 587021f6537SMarc Zyngier gic_dist_wait_for_rwp(); 588021f6537SMarc Zyngier 5897c9b9730SMarc Zyngier /* 5907c9b9730SMarc Zyngier * Configure SPIs as non-secure Group-1. This will only matter 5917c9b9730SMarc Zyngier * if the GIC only has a single security state. This will not 5927c9b9730SMarc Zyngier * do the right thing if the kernel is running in secure mode, 5937c9b9730SMarc Zyngier * but that's not the intended use case anyway. 5947c9b9730SMarc Zyngier */ 5957c9b9730SMarc Zyngier for (i = 32; i < gic_data.irq_nr; i += 32) 5967c9b9730SMarc Zyngier writel_relaxed(~0, base + GICD_IGROUPR + i / 8); 5977c9b9730SMarc Zyngier 598021f6537SMarc Zyngier gic_dist_config(base, gic_data.irq_nr, gic_dist_wait_for_rwp); 599021f6537SMarc Zyngier 600021f6537SMarc Zyngier /* Enable distributor with ARE, Group1 */ 601021f6537SMarc Zyngier writel_relaxed(GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G1A | GICD_CTLR_ENABLE_G1, 602021f6537SMarc Zyngier base + GICD_CTLR); 603021f6537SMarc Zyngier 604021f6537SMarc Zyngier /* 605021f6537SMarc Zyngier * Set all global interrupts to the boot CPU only. ARE must be 606021f6537SMarc Zyngier * enabled. 607021f6537SMarc Zyngier */ 608021f6537SMarc Zyngier affinity = gic_mpidr_to_affinity(cpu_logical_map(smp_processor_id())); 609021f6537SMarc Zyngier for (i = 32; i < gic_data.irq_nr; i++) 61072c97126SJean-Philippe Brucker gic_write_irouter(affinity, base + GICD_IROUTER + i * 8); 611021f6537SMarc Zyngier } 612021f6537SMarc Zyngier 6130d94ded2SMarc Zyngier static int gic_iterate_rdists(int (*fn)(struct redist_region *, void __iomem *)) 614021f6537SMarc Zyngier { 6150d94ded2SMarc Zyngier int ret = -ENODEV; 616021f6537SMarc Zyngier int i; 617021f6537SMarc Zyngier 618f5c1434cSMarc Zyngier for (i = 0; i < gic_data.nr_redist_regions; i++) { 619f5c1434cSMarc Zyngier void __iomem *ptr = gic_data.redist_regions[i].redist_base; 6200d94ded2SMarc Zyngier u64 typer; 621021f6537SMarc Zyngier u32 reg; 622021f6537SMarc Zyngier 623021f6537SMarc Zyngier reg = readl_relaxed(ptr + GICR_PIDR2) & GIC_PIDR2_ARCH_MASK; 624021f6537SMarc Zyngier if (reg != GIC_PIDR2_ARCH_GICv3 && 625021f6537SMarc Zyngier reg != GIC_PIDR2_ARCH_GICv4) { /* We're in trouble... */ 626021f6537SMarc Zyngier pr_warn("No redistributor present @%p\n", ptr); 627021f6537SMarc Zyngier break; 628021f6537SMarc Zyngier } 629021f6537SMarc Zyngier 630021f6537SMarc Zyngier do { 63172c97126SJean-Philippe Brucker typer = gic_read_typer(ptr + GICR_TYPER); 6320d94ded2SMarc Zyngier ret = fn(gic_data.redist_regions + i, ptr); 6330d94ded2SMarc Zyngier if (!ret) 634021f6537SMarc Zyngier return 0; 635021f6537SMarc Zyngier 636b70fb7afSTomasz Nowicki if (gic_data.redist_regions[i].single_redist) 637b70fb7afSTomasz Nowicki break; 638b70fb7afSTomasz Nowicki 639021f6537SMarc Zyngier if (gic_data.redist_stride) { 640021f6537SMarc Zyngier ptr += gic_data.redist_stride; 641021f6537SMarc Zyngier } else { 642021f6537SMarc Zyngier ptr += SZ_64K * 2; /* Skip RD_base + SGI_base */ 643021f6537SMarc Zyngier if (typer & GICR_TYPER_VLPIS) 644021f6537SMarc Zyngier ptr += SZ_64K * 2; /* Skip VLPI_base + reserved page */ 645021f6537SMarc Zyngier } 646021f6537SMarc Zyngier } while (!(typer & GICR_TYPER_LAST)); 647021f6537SMarc Zyngier } 648021f6537SMarc Zyngier 6490d94ded2SMarc Zyngier return ret ? -ENODEV : 0; 6500d94ded2SMarc Zyngier } 6510d94ded2SMarc Zyngier 6520d94ded2SMarc Zyngier static int __gic_populate_rdist(struct redist_region *region, void __iomem *ptr) 6530d94ded2SMarc Zyngier { 6540d94ded2SMarc Zyngier unsigned long mpidr = cpu_logical_map(smp_processor_id()); 6550d94ded2SMarc Zyngier u64 typer; 6560d94ded2SMarc Zyngier u32 aff; 6570d94ded2SMarc Zyngier 6580d94ded2SMarc Zyngier /* 6590d94ded2SMarc Zyngier * Convert affinity to a 32bit value that can be matched to 6600d94ded2SMarc Zyngier * GICR_TYPER bits [63:32]. 6610d94ded2SMarc Zyngier */ 6620d94ded2SMarc Zyngier aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 24 | 6630d94ded2SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 | 6640d94ded2SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | 6650d94ded2SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 0)); 6660d94ded2SMarc Zyngier 6670d94ded2SMarc Zyngier typer = gic_read_typer(ptr + GICR_TYPER); 6680d94ded2SMarc Zyngier if ((typer >> 32) == aff) { 6690d94ded2SMarc Zyngier u64 offset = ptr - region->redist_base; 6700d94ded2SMarc Zyngier gic_data_rdist_rd_base() = ptr; 6710d94ded2SMarc Zyngier gic_data_rdist()->phys_base = region->phys_base + offset; 6720d94ded2SMarc Zyngier 6730d94ded2SMarc Zyngier pr_info("CPU%d: found redistributor %lx region %d:%pa\n", 6740d94ded2SMarc Zyngier smp_processor_id(), mpidr, 6750d94ded2SMarc Zyngier (int)(region - gic_data.redist_regions), 6760d94ded2SMarc Zyngier &gic_data_rdist()->phys_base); 6770d94ded2SMarc Zyngier return 0; 6780d94ded2SMarc Zyngier } 6790d94ded2SMarc Zyngier 6800d94ded2SMarc Zyngier /* Try next one */ 6810d94ded2SMarc Zyngier return 1; 6820d94ded2SMarc Zyngier } 6830d94ded2SMarc Zyngier 6840d94ded2SMarc Zyngier static int gic_populate_rdist(void) 6850d94ded2SMarc Zyngier { 6860d94ded2SMarc Zyngier if (gic_iterate_rdists(__gic_populate_rdist) == 0) 6870d94ded2SMarc Zyngier return 0; 6880d94ded2SMarc Zyngier 689021f6537SMarc Zyngier /* We couldn't even deal with ourselves... */ 690f6c86a41SJean-Philippe Brucker WARN(true, "CPU%d: mpidr %lx has no re-distributor!\n", 6910d94ded2SMarc Zyngier smp_processor_id(), 6920d94ded2SMarc Zyngier (unsigned long)cpu_logical_map(smp_processor_id())); 693021f6537SMarc Zyngier return -ENODEV; 694021f6537SMarc Zyngier } 695021f6537SMarc Zyngier 6960edc23eaSMarc Zyngier static int __gic_update_vlpi_properties(struct redist_region *region, 6970edc23eaSMarc Zyngier void __iomem *ptr) 6980edc23eaSMarc Zyngier { 6990edc23eaSMarc Zyngier u64 typer = gic_read_typer(ptr + GICR_TYPER); 7000edc23eaSMarc Zyngier gic_data.rdists.has_vlpis &= !!(typer & GICR_TYPER_VLPIS); 7010edc23eaSMarc Zyngier gic_data.rdists.has_direct_lpi &= !!(typer & GICR_TYPER_DirectLPIS); 7020edc23eaSMarc Zyngier 7030edc23eaSMarc Zyngier return 1; 7040edc23eaSMarc Zyngier } 7050edc23eaSMarc Zyngier 7060edc23eaSMarc Zyngier static void gic_update_vlpi_properties(void) 7070edc23eaSMarc Zyngier { 7080edc23eaSMarc Zyngier gic_iterate_rdists(__gic_update_vlpi_properties); 7090edc23eaSMarc Zyngier pr_info("%sVLPI support, %sdirect LPI support\n", 7100edc23eaSMarc Zyngier !gic_data.rdists.has_vlpis ? "no " : "", 7110edc23eaSMarc Zyngier !gic_data.rdists.has_direct_lpi ? "no " : ""); 7120edc23eaSMarc Zyngier } 7130edc23eaSMarc Zyngier 714d98d0a99SJulien Thierry /* Check whether it's single security state view */ 715d98d0a99SJulien Thierry static inline bool gic_dist_security_disabled(void) 716d98d0a99SJulien Thierry { 717d98d0a99SJulien Thierry return readl_relaxed(gic_data.dist_base + GICD_CTLR) & GICD_CTLR_DS; 718d98d0a99SJulien Thierry } 719d98d0a99SJulien Thierry 7203708d52fSSudeep Holla static void gic_cpu_sys_reg_init(void) 721021f6537SMarc Zyngier { 722eda0d04aSShanker Donthineni int i, cpu = smp_processor_id(); 723eda0d04aSShanker Donthineni u64 mpidr = cpu_logical_map(cpu); 724eda0d04aSShanker Donthineni u64 need_rss = MPIDR_RS(mpidr); 72533625282SMarc Zyngier bool group0; 726b5cf6073SJulien Thierry u32 pribits; 727eda0d04aSShanker Donthineni 7287cabd008SMarc Zyngier /* 7297cabd008SMarc Zyngier * Need to check that the SRE bit has actually been set. If 7307cabd008SMarc Zyngier * not, it means that SRE is disabled at EL2. We're going to 7317cabd008SMarc Zyngier * die painfully, and there is nothing we can do about it. 7327cabd008SMarc Zyngier * 7337cabd008SMarc Zyngier * Kindly inform the luser. 7347cabd008SMarc Zyngier */ 7357cabd008SMarc Zyngier if (!gic_enable_sre()) 7367cabd008SMarc Zyngier pr_err("GIC: unable to set SRE (disabled at EL2), panic ahead\n"); 737021f6537SMarc Zyngier 738b5cf6073SJulien Thierry pribits = gic_get_pribits(); 73933625282SMarc Zyngier 740b5cf6073SJulien Thierry group0 = gic_has_group0(); 74133625282SMarc Zyngier 742021f6537SMarc Zyngier /* Set priority mask register */ 743d98d0a99SJulien Thierry if (!gic_prio_masking_enabled()) { 74433625282SMarc Zyngier write_gicreg(DEFAULT_PMR_VALUE, ICC_PMR_EL1); 745d98d0a99SJulien Thierry } else { 746d98d0a99SJulien Thierry /* 747d98d0a99SJulien Thierry * Mismatch configuration with boot CPU, the system is likely 748d98d0a99SJulien Thierry * to die as interrupt masking will not work properly on all 749d98d0a99SJulien Thierry * CPUs 750d98d0a99SJulien Thierry */ 751d98d0a99SJulien Thierry WARN_ON(gic_supports_nmi() && group0 && 752d98d0a99SJulien Thierry !gic_dist_security_disabled()); 753d98d0a99SJulien Thierry } 754021f6537SMarc Zyngier 75591ef8442SDaniel Thompson /* 75691ef8442SDaniel Thompson * Some firmwares hand over to the kernel with the BPR changed from 75791ef8442SDaniel Thompson * its reset value (and with a value large enough to prevent 75891ef8442SDaniel Thompson * any pre-emptive interrupts from working at all). Writing a zero 75991ef8442SDaniel Thompson * to BPR restores is reset value. 76091ef8442SDaniel Thompson */ 76191ef8442SDaniel Thompson gic_write_bpr1(0); 76291ef8442SDaniel Thompson 763d01d3274SDavidlohr Bueso if (static_branch_likely(&supports_deactivate_key)) { 7640b6a3da9SMarc Zyngier /* EOI drops priority only (mode 1) */ 7650b6a3da9SMarc Zyngier gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop); 7660b6a3da9SMarc Zyngier } else { 767021f6537SMarc Zyngier /* EOI deactivates interrupt too (mode 0) */ 768021f6537SMarc Zyngier gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop_dir); 7690b6a3da9SMarc Zyngier } 770021f6537SMarc Zyngier 77133625282SMarc Zyngier /* Always whack Group0 before Group1 */ 77233625282SMarc Zyngier if (group0) { 77333625282SMarc Zyngier switch(pribits) { 77433625282SMarc Zyngier case 8: 77533625282SMarc Zyngier case 7: 77633625282SMarc Zyngier write_gicreg(0, ICC_AP0R3_EL1); 77733625282SMarc Zyngier write_gicreg(0, ICC_AP0R2_EL1); 77852f8c8b3SAnders Roxell /* Fall through */ 77933625282SMarc Zyngier case 6: 78033625282SMarc Zyngier write_gicreg(0, ICC_AP0R1_EL1); 78152f8c8b3SAnders Roxell /* Fall through */ 78233625282SMarc Zyngier case 5: 78333625282SMarc Zyngier case 4: 78433625282SMarc Zyngier write_gicreg(0, ICC_AP0R0_EL1); 78533625282SMarc Zyngier } 786d6062a6dSMarc Zyngier 78733625282SMarc Zyngier isb(); 78833625282SMarc Zyngier } 78933625282SMarc Zyngier 79033625282SMarc Zyngier switch(pribits) { 791d6062a6dSMarc Zyngier case 8: 792d6062a6dSMarc Zyngier case 7: 793d6062a6dSMarc Zyngier write_gicreg(0, ICC_AP1R3_EL1); 794d6062a6dSMarc Zyngier write_gicreg(0, ICC_AP1R2_EL1); 79552f8c8b3SAnders Roxell /* Fall through */ 796d6062a6dSMarc Zyngier case 6: 797d6062a6dSMarc Zyngier write_gicreg(0, ICC_AP1R1_EL1); 79852f8c8b3SAnders Roxell /* Fall through */ 799d6062a6dSMarc Zyngier case 5: 800d6062a6dSMarc Zyngier case 4: 801d6062a6dSMarc Zyngier write_gicreg(0, ICC_AP1R0_EL1); 802d6062a6dSMarc Zyngier } 803d6062a6dSMarc Zyngier 804d6062a6dSMarc Zyngier isb(); 805d6062a6dSMarc Zyngier 806021f6537SMarc Zyngier /* ... and let's hit the road... */ 807021f6537SMarc Zyngier gic_write_grpen1(1); 808eda0d04aSShanker Donthineni 809eda0d04aSShanker Donthineni /* Keep the RSS capability status in per_cpu variable */ 810eda0d04aSShanker Donthineni per_cpu(has_rss, cpu) = !!(gic_read_ctlr() & ICC_CTLR_EL1_RSS); 811eda0d04aSShanker Donthineni 812eda0d04aSShanker Donthineni /* Check all the CPUs have capable of sending SGIs to other CPUs */ 813eda0d04aSShanker Donthineni for_each_online_cpu(i) { 814eda0d04aSShanker Donthineni bool have_rss = per_cpu(has_rss, i) && per_cpu(has_rss, cpu); 815eda0d04aSShanker Donthineni 816eda0d04aSShanker Donthineni need_rss |= MPIDR_RS(cpu_logical_map(i)); 817eda0d04aSShanker Donthineni if (need_rss && (!have_rss)) 818eda0d04aSShanker Donthineni pr_crit("CPU%d (%lx) can't SGI CPU%d (%lx), no RSS\n", 819eda0d04aSShanker Donthineni cpu, (unsigned long)mpidr, 820eda0d04aSShanker Donthineni i, (unsigned long)cpu_logical_map(i)); 821eda0d04aSShanker Donthineni } 822eda0d04aSShanker Donthineni 823eda0d04aSShanker Donthineni /** 824eda0d04aSShanker Donthineni * GIC spec says, when ICC_CTLR_EL1.RSS==1 and GICD_TYPER.RSS==0, 825eda0d04aSShanker Donthineni * writing ICC_ASGI1R_EL1 register with RS != 0 is a CONSTRAINED 826eda0d04aSShanker Donthineni * UNPREDICTABLE choice of : 827eda0d04aSShanker Donthineni * - The write is ignored. 828eda0d04aSShanker Donthineni * - The RS field is treated as 0. 829eda0d04aSShanker Donthineni */ 830eda0d04aSShanker Donthineni if (need_rss && (!gic_data.has_rss)) 831eda0d04aSShanker Donthineni pr_crit_once("RSS is required but GICD doesn't support it\n"); 832021f6537SMarc Zyngier } 833021f6537SMarc Zyngier 834f736d65dSMarc Zyngier static bool gicv3_nolpi; 835f736d65dSMarc Zyngier 836f736d65dSMarc Zyngier static int __init gicv3_nolpi_cfg(char *buf) 837f736d65dSMarc Zyngier { 838f736d65dSMarc Zyngier return strtobool(buf, &gicv3_nolpi); 839f736d65dSMarc Zyngier } 840f736d65dSMarc Zyngier early_param("irqchip.gicv3_nolpi", gicv3_nolpi_cfg); 841f736d65dSMarc Zyngier 842da33f31dSMarc Zyngier static int gic_dist_supports_lpis(void) 843da33f31dSMarc Zyngier { 844d38a71c5SMarc Zyngier return (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && 845d38a71c5SMarc Zyngier !!(readl_relaxed(gic_data.dist_base + GICD_TYPER) & GICD_TYPER_LPIS) && 846d38a71c5SMarc Zyngier !gicv3_nolpi); 847da33f31dSMarc Zyngier } 848da33f31dSMarc Zyngier 849021f6537SMarc Zyngier static void gic_cpu_init(void) 850021f6537SMarc Zyngier { 851021f6537SMarc Zyngier void __iomem *rbase; 852021f6537SMarc Zyngier 853021f6537SMarc Zyngier /* Register ourselves with the rest of the world */ 854021f6537SMarc Zyngier if (gic_populate_rdist()) 855021f6537SMarc Zyngier return; 856021f6537SMarc Zyngier 857a2c22510SSudeep Holla gic_enable_redist(true); 858021f6537SMarc Zyngier 859021f6537SMarc Zyngier rbase = gic_data_rdist_sgi_base(); 860021f6537SMarc Zyngier 8617c9b9730SMarc Zyngier /* Configure SGIs/PPIs as non-secure Group-1 */ 8627c9b9730SMarc Zyngier writel_relaxed(~0, rbase + GICR_IGROUPR0); 8637c9b9730SMarc Zyngier 864021f6537SMarc Zyngier gic_cpu_config(rbase, gic_redist_wait_for_rwp); 865021f6537SMarc Zyngier 8663708d52fSSudeep Holla /* initialise system registers */ 8673708d52fSSudeep Holla gic_cpu_sys_reg_init(); 868021f6537SMarc Zyngier } 869021f6537SMarc Zyngier 870021f6537SMarc Zyngier #ifdef CONFIG_SMP 871021f6537SMarc Zyngier 872eda0d04aSShanker Donthineni #define MPIDR_TO_SGI_RS(mpidr) (MPIDR_RS(mpidr) << ICC_SGI1R_RS_SHIFT) 873eda0d04aSShanker Donthineni #define MPIDR_TO_SGI_CLUSTER_ID(mpidr) ((mpidr) & ~0xFUL) 874eda0d04aSShanker Donthineni 8756670a6d8SRichard Cochran static int gic_starting_cpu(unsigned int cpu) 8766670a6d8SRichard Cochran { 8776670a6d8SRichard Cochran gic_cpu_init(); 878d38a71c5SMarc Zyngier 879d38a71c5SMarc Zyngier if (gic_dist_supports_lpis()) 880d38a71c5SMarc Zyngier its_cpu_init(); 881d38a71c5SMarc Zyngier 8826670a6d8SRichard Cochran return 0; 8836670a6d8SRichard Cochran } 884021f6537SMarc Zyngier 885021f6537SMarc Zyngier static u16 gic_compute_target_list(int *base_cpu, const struct cpumask *mask, 886f6c86a41SJean-Philippe Brucker unsigned long cluster_id) 887021f6537SMarc Zyngier { 888727653d6SJames Morse int next_cpu, cpu = *base_cpu; 889f6c86a41SJean-Philippe Brucker unsigned long mpidr = cpu_logical_map(cpu); 890021f6537SMarc Zyngier u16 tlist = 0; 891021f6537SMarc Zyngier 892021f6537SMarc Zyngier while (cpu < nr_cpu_ids) { 893021f6537SMarc Zyngier tlist |= 1 << (mpidr & 0xf); 894021f6537SMarc Zyngier 895727653d6SJames Morse next_cpu = cpumask_next(cpu, mask); 896727653d6SJames Morse if (next_cpu >= nr_cpu_ids) 897021f6537SMarc Zyngier goto out; 898727653d6SJames Morse cpu = next_cpu; 899021f6537SMarc Zyngier 900021f6537SMarc Zyngier mpidr = cpu_logical_map(cpu); 901021f6537SMarc Zyngier 902eda0d04aSShanker Donthineni if (cluster_id != MPIDR_TO_SGI_CLUSTER_ID(mpidr)) { 903021f6537SMarc Zyngier cpu--; 904021f6537SMarc Zyngier goto out; 905021f6537SMarc Zyngier } 906021f6537SMarc Zyngier } 907021f6537SMarc Zyngier out: 908021f6537SMarc Zyngier *base_cpu = cpu; 909021f6537SMarc Zyngier return tlist; 910021f6537SMarc Zyngier } 911021f6537SMarc Zyngier 9127e580278SAndre Przywara #define MPIDR_TO_SGI_AFFINITY(cluster_id, level) \ 9137e580278SAndre Przywara (MPIDR_AFFINITY_LEVEL(cluster_id, level) \ 9147e580278SAndre Przywara << ICC_SGI1R_AFFINITY_## level ##_SHIFT) 9157e580278SAndre Przywara 916021f6537SMarc Zyngier static void gic_send_sgi(u64 cluster_id, u16 tlist, unsigned int irq) 917021f6537SMarc Zyngier { 918021f6537SMarc Zyngier u64 val; 919021f6537SMarc Zyngier 9207e580278SAndre Przywara val = (MPIDR_TO_SGI_AFFINITY(cluster_id, 3) | 9217e580278SAndre Przywara MPIDR_TO_SGI_AFFINITY(cluster_id, 2) | 9227e580278SAndre Przywara irq << ICC_SGI1R_SGI_ID_SHIFT | 9237e580278SAndre Przywara MPIDR_TO_SGI_AFFINITY(cluster_id, 1) | 924eda0d04aSShanker Donthineni MPIDR_TO_SGI_RS(cluster_id) | 9257e580278SAndre Przywara tlist << ICC_SGI1R_TARGET_LIST_SHIFT); 926021f6537SMarc Zyngier 927b6dd4d83SMark Salter pr_devel("CPU%d: ICC_SGI1R_EL1 %llx\n", smp_processor_id(), val); 928021f6537SMarc Zyngier gic_write_sgi1r(val); 929021f6537SMarc Zyngier } 930021f6537SMarc Zyngier 931021f6537SMarc Zyngier static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) 932021f6537SMarc Zyngier { 933021f6537SMarc Zyngier int cpu; 934021f6537SMarc Zyngier 935021f6537SMarc Zyngier if (WARN_ON(irq >= 16)) 936021f6537SMarc Zyngier return; 937021f6537SMarc Zyngier 938021f6537SMarc Zyngier /* 939021f6537SMarc Zyngier * Ensure that stores to Normal memory are visible to the 940021f6537SMarc Zyngier * other CPUs before issuing the IPI. 941021f6537SMarc Zyngier */ 94221ec30c0SShanker Donthineni wmb(); 943021f6537SMarc Zyngier 944f9b531feSRusty Russell for_each_cpu(cpu, mask) { 945eda0d04aSShanker Donthineni u64 cluster_id = MPIDR_TO_SGI_CLUSTER_ID(cpu_logical_map(cpu)); 946021f6537SMarc Zyngier u16 tlist; 947021f6537SMarc Zyngier 948021f6537SMarc Zyngier tlist = gic_compute_target_list(&cpu, mask, cluster_id); 949021f6537SMarc Zyngier gic_send_sgi(cluster_id, tlist, irq); 950021f6537SMarc Zyngier } 951021f6537SMarc Zyngier 952021f6537SMarc Zyngier /* Force the above writes to ICC_SGI1R_EL1 to be executed */ 953021f6537SMarc Zyngier isb(); 954021f6537SMarc Zyngier } 955021f6537SMarc Zyngier 956021f6537SMarc Zyngier static void gic_smp_init(void) 957021f6537SMarc Zyngier { 958021f6537SMarc Zyngier set_smp_cross_call(gic_raise_softirq); 9596896bcd1SThomas Gleixner cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_GIC_STARTING, 96073c1b41eSThomas Gleixner "irqchip/arm/gicv3:starting", 96173c1b41eSThomas Gleixner gic_starting_cpu, NULL); 962021f6537SMarc Zyngier } 963021f6537SMarc Zyngier 964021f6537SMarc Zyngier static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, 965021f6537SMarc Zyngier bool force) 966021f6537SMarc Zyngier { 96765a30f8bSSuzuki K Poulose unsigned int cpu; 968021f6537SMarc Zyngier void __iomem *reg; 969021f6537SMarc Zyngier int enabled; 970021f6537SMarc Zyngier u64 val; 971021f6537SMarc Zyngier 97265a30f8bSSuzuki K Poulose if (force) 97365a30f8bSSuzuki K Poulose cpu = cpumask_first(mask_val); 97465a30f8bSSuzuki K Poulose else 97565a30f8bSSuzuki K Poulose cpu = cpumask_any_and(mask_val, cpu_online_mask); 97665a30f8bSSuzuki K Poulose 977866d7c1bSSuzuki K Poulose if (cpu >= nr_cpu_ids) 978866d7c1bSSuzuki K Poulose return -EINVAL; 979866d7c1bSSuzuki K Poulose 980021f6537SMarc Zyngier if (gic_irq_in_rdist(d)) 981021f6537SMarc Zyngier return -EINVAL; 982021f6537SMarc Zyngier 983021f6537SMarc Zyngier /* If interrupt was enabled, disable it first */ 984021f6537SMarc Zyngier enabled = gic_peek_irq(d, GICD_ISENABLER); 985021f6537SMarc Zyngier if (enabled) 986021f6537SMarc Zyngier gic_mask_irq(d); 987021f6537SMarc Zyngier 988021f6537SMarc Zyngier reg = gic_dist_base(d) + GICD_IROUTER + (gic_irq(d) * 8); 989021f6537SMarc Zyngier val = gic_mpidr_to_affinity(cpu_logical_map(cpu)); 990021f6537SMarc Zyngier 99172c97126SJean-Philippe Brucker gic_write_irouter(val, reg); 992021f6537SMarc Zyngier 993021f6537SMarc Zyngier /* 994021f6537SMarc Zyngier * If the interrupt was enabled, enabled it again. Otherwise, 995021f6537SMarc Zyngier * just wait for the distributor to have digested our changes. 996021f6537SMarc Zyngier */ 997021f6537SMarc Zyngier if (enabled) 998021f6537SMarc Zyngier gic_unmask_irq(d); 999021f6537SMarc Zyngier else 1000021f6537SMarc Zyngier gic_dist_wait_for_rwp(); 1001021f6537SMarc Zyngier 1002956ae91aSMarc Zyngier irq_data_update_effective_affinity(d, cpumask_of(cpu)); 1003956ae91aSMarc Zyngier 10040fc6fa29SAntoine Tenart return IRQ_SET_MASK_OK_DONE; 1005021f6537SMarc Zyngier } 1006021f6537SMarc Zyngier #else 1007021f6537SMarc Zyngier #define gic_set_affinity NULL 1008021f6537SMarc Zyngier #define gic_smp_init() do { } while(0) 1009021f6537SMarc Zyngier #endif 1010021f6537SMarc Zyngier 10113708d52fSSudeep Holla #ifdef CONFIG_CPU_PM 10123708d52fSSudeep Holla static int gic_cpu_pm_notifier(struct notifier_block *self, 10133708d52fSSudeep Holla unsigned long cmd, void *v) 10143708d52fSSudeep Holla { 10153708d52fSSudeep Holla if (cmd == CPU_PM_EXIT) { 1016ccd9432aSSudeep Holla if (gic_dist_security_disabled()) 10173708d52fSSudeep Holla gic_enable_redist(true); 10183708d52fSSudeep Holla gic_cpu_sys_reg_init(); 1019ccd9432aSSudeep Holla } else if (cmd == CPU_PM_ENTER && gic_dist_security_disabled()) { 10203708d52fSSudeep Holla gic_write_grpen1(0); 10213708d52fSSudeep Holla gic_enable_redist(false); 10223708d52fSSudeep Holla } 10233708d52fSSudeep Holla return NOTIFY_OK; 10243708d52fSSudeep Holla } 10253708d52fSSudeep Holla 10263708d52fSSudeep Holla static struct notifier_block gic_cpu_pm_notifier_block = { 10273708d52fSSudeep Holla .notifier_call = gic_cpu_pm_notifier, 10283708d52fSSudeep Holla }; 10293708d52fSSudeep Holla 10303708d52fSSudeep Holla static void gic_cpu_pm_init(void) 10313708d52fSSudeep Holla { 10323708d52fSSudeep Holla cpu_pm_register_notifier(&gic_cpu_pm_notifier_block); 10333708d52fSSudeep Holla } 10343708d52fSSudeep Holla 10353708d52fSSudeep Holla #else 10363708d52fSSudeep Holla static inline void gic_cpu_pm_init(void) { } 10373708d52fSSudeep Holla #endif /* CONFIG_CPU_PM */ 10383708d52fSSudeep Holla 1039021f6537SMarc Zyngier static struct irq_chip gic_chip = { 1040021f6537SMarc Zyngier .name = "GICv3", 1041021f6537SMarc Zyngier .irq_mask = gic_mask_irq, 1042021f6537SMarc Zyngier .irq_unmask = gic_unmask_irq, 1043021f6537SMarc Zyngier .irq_eoi = gic_eoi_irq, 1044021f6537SMarc Zyngier .irq_set_type = gic_set_type, 1045021f6537SMarc Zyngier .irq_set_affinity = gic_set_affinity, 1046b594c6e2SMarc Zyngier .irq_get_irqchip_state = gic_irq_get_irqchip_state, 1047b594c6e2SMarc Zyngier .irq_set_irqchip_state = gic_irq_set_irqchip_state, 1048101b35f7SJulien Thierry .irq_nmi_setup = gic_irq_nmi_setup, 1049101b35f7SJulien Thierry .irq_nmi_teardown = gic_irq_nmi_teardown, 10504110b5cbSMarc Zyngier .flags = IRQCHIP_SET_TYPE_MASKED | 10514110b5cbSMarc Zyngier IRQCHIP_SKIP_SET_WAKE | 10524110b5cbSMarc Zyngier IRQCHIP_MASK_ON_SUSPEND, 1053021f6537SMarc Zyngier }; 1054021f6537SMarc Zyngier 10550b6a3da9SMarc Zyngier static struct irq_chip gic_eoimode1_chip = { 10560b6a3da9SMarc Zyngier .name = "GICv3", 10570b6a3da9SMarc Zyngier .irq_mask = gic_eoimode1_mask_irq, 10580b6a3da9SMarc Zyngier .irq_unmask = gic_unmask_irq, 10590b6a3da9SMarc Zyngier .irq_eoi = gic_eoimode1_eoi_irq, 10600b6a3da9SMarc Zyngier .irq_set_type = gic_set_type, 10610b6a3da9SMarc Zyngier .irq_set_affinity = gic_set_affinity, 10620b6a3da9SMarc Zyngier .irq_get_irqchip_state = gic_irq_get_irqchip_state, 10630b6a3da9SMarc Zyngier .irq_set_irqchip_state = gic_irq_set_irqchip_state, 1064530bf353SMarc Zyngier .irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity, 1065101b35f7SJulien Thierry .irq_nmi_setup = gic_irq_nmi_setup, 1066101b35f7SJulien Thierry .irq_nmi_teardown = gic_irq_nmi_teardown, 10674110b5cbSMarc Zyngier .flags = IRQCHIP_SET_TYPE_MASKED | 10684110b5cbSMarc Zyngier IRQCHIP_SKIP_SET_WAKE | 10694110b5cbSMarc Zyngier IRQCHIP_MASK_ON_SUSPEND, 10700b6a3da9SMarc Zyngier }; 10710b6a3da9SMarc Zyngier 1072a4f9edb2SMarc Zyngier #define GIC_ID_NR (1U << GICD_TYPER_ID_BITS(gic_data.rdists.gicd_typer)) 1073da33f31dSMarc Zyngier 1074021f6537SMarc Zyngier static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq, 1075021f6537SMarc Zyngier irq_hw_number_t hw) 1076021f6537SMarc Zyngier { 10770b6a3da9SMarc Zyngier struct irq_chip *chip = &gic_chip; 10780b6a3da9SMarc Zyngier 1079d01d3274SDavidlohr Bueso if (static_branch_likely(&supports_deactivate_key)) 10800b6a3da9SMarc Zyngier chip = &gic_eoimode1_chip; 10810b6a3da9SMarc Zyngier 1082021f6537SMarc Zyngier /* SGIs are private to the core kernel */ 1083021f6537SMarc Zyngier if (hw < 16) 1084021f6537SMarc Zyngier return -EPERM; 1085da33f31dSMarc Zyngier /* Nothing here */ 1086da33f31dSMarc Zyngier if (hw >= gic_data.irq_nr && hw < 8192) 1087da33f31dSMarc Zyngier return -EPERM; 1088da33f31dSMarc Zyngier /* Off limits */ 1089da33f31dSMarc Zyngier if (hw >= GIC_ID_NR) 1090da33f31dSMarc Zyngier return -EPERM; 1091da33f31dSMarc Zyngier 1092021f6537SMarc Zyngier /* PPIs */ 1093021f6537SMarc Zyngier if (hw < 32) { 1094021f6537SMarc Zyngier irq_set_percpu_devid(irq); 10950b6a3da9SMarc Zyngier irq_domain_set_info(d, irq, hw, chip, d->host_data, 1096443acc4fSMarc Zyngier handle_percpu_devid_irq, NULL, NULL); 1097d17cab44SRob Herring irq_set_status_flags(irq, IRQ_NOAUTOEN); 1098021f6537SMarc Zyngier } 1099021f6537SMarc Zyngier /* SPIs */ 1100021f6537SMarc Zyngier if (hw >= 32 && hw < gic_data.irq_nr) { 11010b6a3da9SMarc Zyngier irq_domain_set_info(d, irq, hw, chip, d->host_data, 1102443acc4fSMarc Zyngier handle_fasteoi_irq, NULL, NULL); 1103d17cab44SRob Herring irq_set_probe(irq); 1104956ae91aSMarc Zyngier irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(irq))); 1105021f6537SMarc Zyngier } 1106da33f31dSMarc Zyngier /* LPIs */ 1107da33f31dSMarc Zyngier if (hw >= 8192 && hw < GIC_ID_NR) { 1108da33f31dSMarc Zyngier if (!gic_dist_supports_lpis()) 1109da33f31dSMarc Zyngier return -EPERM; 11100b6a3da9SMarc Zyngier irq_domain_set_info(d, irq, hw, chip, d->host_data, 1111da33f31dSMarc Zyngier handle_fasteoi_irq, NULL, NULL); 1112da33f31dSMarc Zyngier } 1113da33f31dSMarc Zyngier 1114021f6537SMarc Zyngier return 0; 1115021f6537SMarc Zyngier } 1116021f6537SMarc Zyngier 111765da7d19SMarc Zyngier #define GIC_IRQ_TYPE_PARTITION (GIC_IRQ_TYPE_LPI + 1) 111865da7d19SMarc Zyngier 1119f833f57fSMarc Zyngier static int gic_irq_domain_translate(struct irq_domain *d, 1120f833f57fSMarc Zyngier struct irq_fwspec *fwspec, 1121f833f57fSMarc Zyngier unsigned long *hwirq, 1122f833f57fSMarc Zyngier unsigned int *type) 1123021f6537SMarc Zyngier { 1124f833f57fSMarc Zyngier if (is_of_node(fwspec->fwnode)) { 1125f833f57fSMarc Zyngier if (fwspec->param_count < 3) 1126021f6537SMarc Zyngier return -EINVAL; 1127021f6537SMarc Zyngier 1128db8c70ecSMarc Zyngier switch (fwspec->param[0]) { 1129db8c70ecSMarc Zyngier case 0: /* SPI */ 1130db8c70ecSMarc Zyngier *hwirq = fwspec->param[1] + 32; 1131db8c70ecSMarc Zyngier break; 1132db8c70ecSMarc Zyngier case 1: /* PPI */ 113365da7d19SMarc Zyngier case GIC_IRQ_TYPE_PARTITION: 1134f833f57fSMarc Zyngier *hwirq = fwspec->param[1] + 16; 1135db8c70ecSMarc Zyngier break; 1136db8c70ecSMarc Zyngier case GIC_IRQ_TYPE_LPI: /* LPI */ 1137db8c70ecSMarc Zyngier *hwirq = fwspec->param[1]; 1138db8c70ecSMarc Zyngier break; 1139db8c70ecSMarc Zyngier default: 1140db8c70ecSMarc Zyngier return -EINVAL; 1141db8c70ecSMarc Zyngier } 1142f833f57fSMarc Zyngier 1143f833f57fSMarc Zyngier *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; 11446ef6386eSMarc Zyngier 114565da7d19SMarc Zyngier /* 114665da7d19SMarc Zyngier * Make it clear that broken DTs are... broken. 114765da7d19SMarc Zyngier * Partitionned PPIs are an unfortunate exception. 114865da7d19SMarc Zyngier */ 114965da7d19SMarc Zyngier WARN_ON(*type == IRQ_TYPE_NONE && 115065da7d19SMarc Zyngier fwspec->param[0] != GIC_IRQ_TYPE_PARTITION); 1151f833f57fSMarc Zyngier return 0; 1152021f6537SMarc Zyngier } 1153021f6537SMarc Zyngier 1154ffa7d616STomasz Nowicki if (is_fwnode_irqchip(fwspec->fwnode)) { 1155ffa7d616STomasz Nowicki if(fwspec->param_count != 2) 1156ffa7d616STomasz Nowicki return -EINVAL; 1157ffa7d616STomasz Nowicki 1158ffa7d616STomasz Nowicki *hwirq = fwspec->param[0]; 1159ffa7d616STomasz Nowicki *type = fwspec->param[1]; 11606ef6386eSMarc Zyngier 11616ef6386eSMarc Zyngier WARN_ON(*type == IRQ_TYPE_NONE); 1162ffa7d616STomasz Nowicki return 0; 1163ffa7d616STomasz Nowicki } 1164ffa7d616STomasz Nowicki 1165f833f57fSMarc Zyngier return -EINVAL; 1166021f6537SMarc Zyngier } 1167021f6537SMarc Zyngier 1168443acc4fSMarc Zyngier static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, 1169443acc4fSMarc Zyngier unsigned int nr_irqs, void *arg) 1170443acc4fSMarc Zyngier { 1171443acc4fSMarc Zyngier int i, ret; 1172443acc4fSMarc Zyngier irq_hw_number_t hwirq; 1173443acc4fSMarc Zyngier unsigned int type = IRQ_TYPE_NONE; 1174f833f57fSMarc Zyngier struct irq_fwspec *fwspec = arg; 1175443acc4fSMarc Zyngier 1176f833f57fSMarc Zyngier ret = gic_irq_domain_translate(domain, fwspec, &hwirq, &type); 1177443acc4fSMarc Zyngier if (ret) 1178443acc4fSMarc Zyngier return ret; 1179443acc4fSMarc Zyngier 118063c16c6eSSuzuki K Poulose for (i = 0; i < nr_irqs; i++) { 118163c16c6eSSuzuki K Poulose ret = gic_irq_domain_map(domain, virq + i, hwirq + i); 118263c16c6eSSuzuki K Poulose if (ret) 118363c16c6eSSuzuki K Poulose return ret; 118463c16c6eSSuzuki K Poulose } 1185443acc4fSMarc Zyngier 1186443acc4fSMarc Zyngier return 0; 1187443acc4fSMarc Zyngier } 1188443acc4fSMarc Zyngier 1189443acc4fSMarc Zyngier static void gic_irq_domain_free(struct irq_domain *domain, unsigned int virq, 1190443acc4fSMarc Zyngier unsigned int nr_irqs) 1191443acc4fSMarc Zyngier { 1192443acc4fSMarc Zyngier int i; 1193443acc4fSMarc Zyngier 1194443acc4fSMarc Zyngier for (i = 0; i < nr_irqs; i++) { 1195443acc4fSMarc Zyngier struct irq_data *d = irq_domain_get_irq_data(domain, virq + i); 1196443acc4fSMarc Zyngier irq_set_handler(virq + i, NULL); 1197443acc4fSMarc Zyngier irq_domain_reset_irq_data(d); 1198443acc4fSMarc Zyngier } 1199443acc4fSMarc Zyngier } 1200443acc4fSMarc Zyngier 1201e3825ba1SMarc Zyngier static int gic_irq_domain_select(struct irq_domain *d, 1202e3825ba1SMarc Zyngier struct irq_fwspec *fwspec, 1203e3825ba1SMarc Zyngier enum irq_domain_bus_token bus_token) 1204e3825ba1SMarc Zyngier { 1205e3825ba1SMarc Zyngier /* Not for us */ 1206e3825ba1SMarc Zyngier if (fwspec->fwnode != d->fwnode) 1207e3825ba1SMarc Zyngier return 0; 1208e3825ba1SMarc Zyngier 1209e3825ba1SMarc Zyngier /* If this is not DT, then we have a single domain */ 1210e3825ba1SMarc Zyngier if (!is_of_node(fwspec->fwnode)) 1211e3825ba1SMarc Zyngier return 1; 1212e3825ba1SMarc Zyngier 1213e3825ba1SMarc Zyngier /* 1214e3825ba1SMarc Zyngier * If this is a PPI and we have a 4th (non-null) parameter, 1215e3825ba1SMarc Zyngier * then we need to match the partition domain. 1216e3825ba1SMarc Zyngier */ 1217e3825ba1SMarc Zyngier if (fwspec->param_count >= 4 && 1218e3825ba1SMarc Zyngier fwspec->param[0] == 1 && fwspec->param[3] != 0) 1219e3825ba1SMarc Zyngier return d == partition_get_domain(gic_data.ppi_descs[fwspec->param[1]]); 1220e3825ba1SMarc Zyngier 1221e3825ba1SMarc Zyngier return d == gic_data.domain; 1222e3825ba1SMarc Zyngier } 1223e3825ba1SMarc Zyngier 1224021f6537SMarc Zyngier static const struct irq_domain_ops gic_irq_domain_ops = { 1225f833f57fSMarc Zyngier .translate = gic_irq_domain_translate, 1226443acc4fSMarc Zyngier .alloc = gic_irq_domain_alloc, 1227443acc4fSMarc Zyngier .free = gic_irq_domain_free, 1228e3825ba1SMarc Zyngier .select = gic_irq_domain_select, 1229e3825ba1SMarc Zyngier }; 1230e3825ba1SMarc Zyngier 1231e3825ba1SMarc Zyngier static int partition_domain_translate(struct irq_domain *d, 1232e3825ba1SMarc Zyngier struct irq_fwspec *fwspec, 1233e3825ba1SMarc Zyngier unsigned long *hwirq, 1234e3825ba1SMarc Zyngier unsigned int *type) 1235e3825ba1SMarc Zyngier { 1236e3825ba1SMarc Zyngier struct device_node *np; 1237e3825ba1SMarc Zyngier int ret; 1238e3825ba1SMarc Zyngier 1239e3825ba1SMarc Zyngier np = of_find_node_by_phandle(fwspec->param[3]); 1240e3825ba1SMarc Zyngier if (WARN_ON(!np)) 1241e3825ba1SMarc Zyngier return -EINVAL; 1242e3825ba1SMarc Zyngier 1243e3825ba1SMarc Zyngier ret = partition_translate_id(gic_data.ppi_descs[fwspec->param[1]], 1244e3825ba1SMarc Zyngier of_node_to_fwnode(np)); 1245e3825ba1SMarc Zyngier if (ret < 0) 1246e3825ba1SMarc Zyngier return ret; 1247e3825ba1SMarc Zyngier 1248e3825ba1SMarc Zyngier *hwirq = ret; 1249e3825ba1SMarc Zyngier *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; 1250e3825ba1SMarc Zyngier 1251e3825ba1SMarc Zyngier return 0; 1252e3825ba1SMarc Zyngier } 1253e3825ba1SMarc Zyngier 1254e3825ba1SMarc Zyngier static const struct irq_domain_ops partition_domain_ops = { 1255e3825ba1SMarc Zyngier .translate = partition_domain_translate, 1256e3825ba1SMarc Zyngier .select = gic_irq_domain_select, 1257021f6537SMarc Zyngier }; 1258021f6537SMarc Zyngier 12599c8114c2SSrinivas Kandagatla static bool gic_enable_quirk_msm8996(void *data) 12609c8114c2SSrinivas Kandagatla { 12619c8114c2SSrinivas Kandagatla struct gic_chip_data *d = data; 12629c8114c2SSrinivas Kandagatla 12639c8114c2SSrinivas Kandagatla d->flags |= FLAGS_WORKAROUND_GICR_WAKER_MSM8996; 12649c8114c2SSrinivas Kandagatla 12659c8114c2SSrinivas Kandagatla return true; 12669c8114c2SSrinivas Kandagatla } 12679c8114c2SSrinivas Kandagatla 1268d98d0a99SJulien Thierry static void gic_enable_nmi_support(void) 1269d98d0a99SJulien Thierry { 1270101b35f7SJulien Thierry int i; 1271101b35f7SJulien Thierry 1272101b35f7SJulien Thierry for (i = 0; i < 16; i++) 1273101b35f7SJulien Thierry refcount_set(&ppi_nmi_refs[i], 0); 1274101b35f7SJulien Thierry 1275d98d0a99SJulien Thierry static_branch_enable(&supports_pseudo_nmis); 1276101b35f7SJulien Thierry 1277101b35f7SJulien Thierry if (static_branch_likely(&supports_deactivate_key)) 1278101b35f7SJulien Thierry gic_eoimode1_chip.flags |= IRQCHIP_SUPPORTS_NMI; 1279101b35f7SJulien Thierry else 1280101b35f7SJulien Thierry gic_chip.flags |= IRQCHIP_SUPPORTS_NMI; 1281d98d0a99SJulien Thierry } 1282d98d0a99SJulien Thierry 1283db57d746STomasz Nowicki static int __init gic_init_bases(void __iomem *dist_base, 1284db57d746STomasz Nowicki struct redist_region *rdist_regs, 1285db57d746STomasz Nowicki u32 nr_redist_regions, 1286db57d746STomasz Nowicki u64 redist_stride, 1287db57d746STomasz Nowicki struct fwnode_handle *handle) 1288db57d746STomasz Nowicki { 1289db57d746STomasz Nowicki u32 typer; 1290db57d746STomasz Nowicki int gic_irqs; 1291db57d746STomasz Nowicki int err; 1292db57d746STomasz Nowicki 1293db57d746STomasz Nowicki if (!is_hyp_mode_available()) 1294d01d3274SDavidlohr Bueso static_branch_disable(&supports_deactivate_key); 1295db57d746STomasz Nowicki 1296d01d3274SDavidlohr Bueso if (static_branch_likely(&supports_deactivate_key)) 1297db57d746STomasz Nowicki pr_info("GIC: Using split EOI/Deactivate mode\n"); 1298db57d746STomasz Nowicki 1299e3825ba1SMarc Zyngier gic_data.fwnode = handle; 1300db57d746STomasz Nowicki gic_data.dist_base = dist_base; 1301db57d746STomasz Nowicki gic_data.redist_regions = rdist_regs; 1302db57d746STomasz Nowicki gic_data.nr_redist_regions = nr_redist_regions; 1303db57d746STomasz Nowicki gic_data.redist_stride = redist_stride; 1304db57d746STomasz Nowicki 1305db57d746STomasz Nowicki /* 1306db57d746STomasz Nowicki * Find out how many interrupts are supported. 1307db57d746STomasz Nowicki * The GIC only supports up to 1020 interrupt sources (SGI+PPI+SPI) 1308db57d746STomasz Nowicki */ 1309db57d746STomasz Nowicki typer = readl_relaxed(gic_data.dist_base + GICD_TYPER); 1310a4f9edb2SMarc Zyngier gic_data.rdists.gicd_typer = typer; 1311db57d746STomasz Nowicki gic_irqs = GICD_TYPER_IRQS(typer); 1312db57d746STomasz Nowicki if (gic_irqs > 1020) 1313db57d746STomasz Nowicki gic_irqs = 1020; 1314db57d746STomasz Nowicki gic_data.irq_nr = gic_irqs; 1315db57d746STomasz Nowicki 1316db57d746STomasz Nowicki gic_data.domain = irq_domain_create_tree(handle, &gic_irq_domain_ops, 1317db57d746STomasz Nowicki &gic_data); 1318b2425b51SMarc Zyngier irq_domain_update_bus_token(gic_data.domain, DOMAIN_BUS_WIRED); 1319db57d746STomasz Nowicki gic_data.rdists.rdist = alloc_percpu(typeof(*gic_data.rdists.rdist)); 13200edc23eaSMarc Zyngier gic_data.rdists.has_vlpis = true; 13210edc23eaSMarc Zyngier gic_data.rdists.has_direct_lpi = true; 1322db57d746STomasz Nowicki 1323db57d746STomasz Nowicki if (WARN_ON(!gic_data.domain) || WARN_ON(!gic_data.rdists.rdist)) { 1324db57d746STomasz Nowicki err = -ENOMEM; 1325db57d746STomasz Nowicki goto out_free; 1326db57d746STomasz Nowicki } 1327db57d746STomasz Nowicki 1328eda0d04aSShanker Donthineni gic_data.has_rss = !!(typer & GICD_TYPER_RSS); 1329eda0d04aSShanker Donthineni pr_info("Distributor has %sRange Selector support\n", 1330eda0d04aSShanker Donthineni gic_data.has_rss ? "" : "no "); 1331eda0d04aSShanker Donthineni 133250528752SMarc Zyngier if (typer & GICD_TYPER_MBIS) { 133350528752SMarc Zyngier err = mbi_init(handle, gic_data.domain); 133450528752SMarc Zyngier if (err) 133550528752SMarc Zyngier pr_err("Failed to initialize MBIs\n"); 133650528752SMarc Zyngier } 133750528752SMarc Zyngier 1338db57d746STomasz Nowicki set_handle_irq(gic_handle_irq); 1339db57d746STomasz Nowicki 13400edc23eaSMarc Zyngier gic_update_vlpi_properties(); 13410edc23eaSMarc Zyngier 1342db57d746STomasz Nowicki gic_smp_init(); 1343db57d746STomasz Nowicki gic_dist_init(); 1344db57d746STomasz Nowicki gic_cpu_init(); 1345db57d746STomasz Nowicki gic_cpu_pm_init(); 1346db57d746STomasz Nowicki 1347d38a71c5SMarc Zyngier if (gic_dist_supports_lpis()) { 1348d38a71c5SMarc Zyngier its_init(handle, &gic_data.rdists, gic_data.domain); 1349d38a71c5SMarc Zyngier its_cpu_init(); 135090b4c555SZeev Zilberman } else { 135190b4c555SZeev Zilberman if (IS_ENABLED(CONFIG_ARM_GIC_V2M)) 135290b4c555SZeev Zilberman gicv2m_init(handle, gic_data.domain); 1353d38a71c5SMarc Zyngier } 1354d38a71c5SMarc Zyngier 1355d98d0a99SJulien Thierry if (gic_prio_masking_enabled()) { 1356d98d0a99SJulien Thierry if (!gic_has_group0() || gic_dist_security_disabled()) 1357d98d0a99SJulien Thierry gic_enable_nmi_support(); 1358d98d0a99SJulien Thierry else 1359d98d0a99SJulien Thierry pr_warn("SCR_EL3.FIQ is cleared, cannot enable use of pseudo-NMIs\n"); 1360d98d0a99SJulien Thierry } 1361d98d0a99SJulien Thierry 1362db57d746STomasz Nowicki return 0; 1363db57d746STomasz Nowicki 1364db57d746STomasz Nowicki out_free: 1365db57d746STomasz Nowicki if (gic_data.domain) 1366db57d746STomasz Nowicki irq_domain_remove(gic_data.domain); 1367db57d746STomasz Nowicki free_percpu(gic_data.rdists.rdist); 1368db57d746STomasz Nowicki return err; 1369db57d746STomasz Nowicki } 1370db57d746STomasz Nowicki 1371db57d746STomasz Nowicki static int __init gic_validate_dist_version(void __iomem *dist_base) 1372db57d746STomasz Nowicki { 1373db57d746STomasz Nowicki u32 reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK; 1374db57d746STomasz Nowicki 1375db57d746STomasz Nowicki if (reg != GIC_PIDR2_ARCH_GICv3 && reg != GIC_PIDR2_ARCH_GICv4) 1376db57d746STomasz Nowicki return -ENODEV; 1377db57d746STomasz Nowicki 1378db57d746STomasz Nowicki return 0; 1379db57d746STomasz Nowicki } 1380db57d746STomasz Nowicki 1381e3825ba1SMarc Zyngier /* Create all possible partitions at boot time */ 13827beaa24bSLinus Torvalds static void __init gic_populate_ppi_partitions(struct device_node *gic_node) 1383e3825ba1SMarc Zyngier { 1384e3825ba1SMarc Zyngier struct device_node *parts_node, *child_part; 1385e3825ba1SMarc Zyngier int part_idx = 0, i; 1386e3825ba1SMarc Zyngier int nr_parts; 1387e3825ba1SMarc Zyngier struct partition_affinity *parts; 1388e3825ba1SMarc Zyngier 138900ee9a1cSJohan Hovold parts_node = of_get_child_by_name(gic_node, "ppi-partitions"); 1390e3825ba1SMarc Zyngier if (!parts_node) 1391e3825ba1SMarc Zyngier return; 1392e3825ba1SMarc Zyngier 1393e3825ba1SMarc Zyngier nr_parts = of_get_child_count(parts_node); 1394e3825ba1SMarc Zyngier 1395e3825ba1SMarc Zyngier if (!nr_parts) 139600ee9a1cSJohan Hovold goto out_put_node; 1397e3825ba1SMarc Zyngier 13986396bb22SKees Cook parts = kcalloc(nr_parts, sizeof(*parts), GFP_KERNEL); 1399e3825ba1SMarc Zyngier if (WARN_ON(!parts)) 140000ee9a1cSJohan Hovold goto out_put_node; 1401e3825ba1SMarc Zyngier 1402e3825ba1SMarc Zyngier for_each_child_of_node(parts_node, child_part) { 1403e3825ba1SMarc Zyngier struct partition_affinity *part; 1404e3825ba1SMarc Zyngier int n; 1405e3825ba1SMarc Zyngier 1406e3825ba1SMarc Zyngier part = &parts[part_idx]; 1407e3825ba1SMarc Zyngier 1408e3825ba1SMarc Zyngier part->partition_id = of_node_to_fwnode(child_part); 1409e3825ba1SMarc Zyngier 14102ef790dcSRob Herring pr_info("GIC: PPI partition %pOFn[%d] { ", 14112ef790dcSRob Herring child_part, part_idx); 1412e3825ba1SMarc Zyngier 1413e3825ba1SMarc Zyngier n = of_property_count_elems_of_size(child_part, "affinity", 1414e3825ba1SMarc Zyngier sizeof(u32)); 1415e3825ba1SMarc Zyngier WARN_ON(n <= 0); 1416e3825ba1SMarc Zyngier 1417e3825ba1SMarc Zyngier for (i = 0; i < n; i++) { 1418e3825ba1SMarc Zyngier int err, cpu; 1419e3825ba1SMarc Zyngier u32 cpu_phandle; 1420e3825ba1SMarc Zyngier struct device_node *cpu_node; 1421e3825ba1SMarc Zyngier 1422e3825ba1SMarc Zyngier err = of_property_read_u32_index(child_part, "affinity", 1423e3825ba1SMarc Zyngier i, &cpu_phandle); 1424e3825ba1SMarc Zyngier if (WARN_ON(err)) 1425e3825ba1SMarc Zyngier continue; 1426e3825ba1SMarc Zyngier 1427e3825ba1SMarc Zyngier cpu_node = of_find_node_by_phandle(cpu_phandle); 1428e3825ba1SMarc Zyngier if (WARN_ON(!cpu_node)) 1429e3825ba1SMarc Zyngier continue; 1430e3825ba1SMarc Zyngier 1431c08ec7daSSuzuki K Poulose cpu = of_cpu_node_to_id(cpu_node); 1432c08ec7daSSuzuki K Poulose if (WARN_ON(cpu < 0)) 1433e3825ba1SMarc Zyngier continue; 1434e3825ba1SMarc Zyngier 1435e81f54c6SRob Herring pr_cont("%pOF[%d] ", cpu_node, cpu); 1436e3825ba1SMarc Zyngier 1437e3825ba1SMarc Zyngier cpumask_set_cpu(cpu, &part->mask); 1438e3825ba1SMarc Zyngier } 1439e3825ba1SMarc Zyngier 1440e3825ba1SMarc Zyngier pr_cont("}\n"); 1441e3825ba1SMarc Zyngier part_idx++; 1442e3825ba1SMarc Zyngier } 1443e3825ba1SMarc Zyngier 1444e3825ba1SMarc Zyngier for (i = 0; i < 16; i++) { 1445e3825ba1SMarc Zyngier unsigned int irq; 1446e3825ba1SMarc Zyngier struct partition_desc *desc; 1447e3825ba1SMarc Zyngier struct irq_fwspec ppi_fwspec = { 1448e3825ba1SMarc Zyngier .fwnode = gic_data.fwnode, 1449e3825ba1SMarc Zyngier .param_count = 3, 1450e3825ba1SMarc Zyngier .param = { 145165da7d19SMarc Zyngier [0] = GIC_IRQ_TYPE_PARTITION, 1452e3825ba1SMarc Zyngier [1] = i, 1453e3825ba1SMarc Zyngier [2] = IRQ_TYPE_NONE, 1454e3825ba1SMarc Zyngier }, 1455e3825ba1SMarc Zyngier }; 1456e3825ba1SMarc Zyngier 1457e3825ba1SMarc Zyngier irq = irq_create_fwspec_mapping(&ppi_fwspec); 1458e3825ba1SMarc Zyngier if (WARN_ON(!irq)) 1459e3825ba1SMarc Zyngier continue; 1460e3825ba1SMarc Zyngier desc = partition_create_desc(gic_data.fwnode, parts, nr_parts, 1461e3825ba1SMarc Zyngier irq, &partition_domain_ops); 1462e3825ba1SMarc Zyngier if (WARN_ON(!desc)) 1463e3825ba1SMarc Zyngier continue; 1464e3825ba1SMarc Zyngier 1465e3825ba1SMarc Zyngier gic_data.ppi_descs[i] = desc; 1466e3825ba1SMarc Zyngier } 146700ee9a1cSJohan Hovold 146800ee9a1cSJohan Hovold out_put_node: 146900ee9a1cSJohan Hovold of_node_put(parts_node); 1470e3825ba1SMarc Zyngier } 1471e3825ba1SMarc Zyngier 14721839e576SJulien Grall static void __init gic_of_setup_kvm_info(struct device_node *node) 14731839e576SJulien Grall { 14741839e576SJulien Grall int ret; 14751839e576SJulien Grall struct resource r; 14761839e576SJulien Grall u32 gicv_idx; 14771839e576SJulien Grall 14781839e576SJulien Grall gic_v3_kvm_info.type = GIC_V3; 14791839e576SJulien Grall 14801839e576SJulien Grall gic_v3_kvm_info.maint_irq = irq_of_parse_and_map(node, 0); 14811839e576SJulien Grall if (!gic_v3_kvm_info.maint_irq) 14821839e576SJulien Grall return; 14831839e576SJulien Grall 14841839e576SJulien Grall if (of_property_read_u32(node, "#redistributor-regions", 14851839e576SJulien Grall &gicv_idx)) 14861839e576SJulien Grall gicv_idx = 1; 14871839e576SJulien Grall 14881839e576SJulien Grall gicv_idx += 3; /* Also skip GICD, GICC, GICH */ 14891839e576SJulien Grall ret = of_address_to_resource(node, gicv_idx, &r); 14901839e576SJulien Grall if (!ret) 14911839e576SJulien Grall gic_v3_kvm_info.vcpu = r; 14921839e576SJulien Grall 14934bdf5025SMarc Zyngier gic_v3_kvm_info.has_v4 = gic_data.rdists.has_vlpis; 14941839e576SJulien Grall gic_set_kvm_info(&gic_v3_kvm_info); 14951839e576SJulien Grall } 14961839e576SJulien Grall 1497f70fdb42SSrinivas Kandagatla static const struct gic_quirk gic_quirks[] = { 1498f70fdb42SSrinivas Kandagatla { 14999c8114c2SSrinivas Kandagatla .desc = "GICv3: Qualcomm MSM8996 broken firmware", 15009c8114c2SSrinivas Kandagatla .compatible = "qcom,msm8996-gic-v3", 15019c8114c2SSrinivas Kandagatla .init = gic_enable_quirk_msm8996, 15029c8114c2SSrinivas Kandagatla }, 15039c8114c2SSrinivas Kandagatla { 1504f70fdb42SSrinivas Kandagatla } 1505f70fdb42SSrinivas Kandagatla }; 1506f70fdb42SSrinivas Kandagatla 1507021f6537SMarc Zyngier static int __init gic_of_init(struct device_node *node, struct device_node *parent) 1508021f6537SMarc Zyngier { 1509021f6537SMarc Zyngier void __iomem *dist_base; 1510f5c1434cSMarc Zyngier struct redist_region *rdist_regs; 1511021f6537SMarc Zyngier u64 redist_stride; 1512f5c1434cSMarc Zyngier u32 nr_redist_regions; 1513db57d746STomasz Nowicki int err, i; 1514021f6537SMarc Zyngier 1515021f6537SMarc Zyngier dist_base = of_iomap(node, 0); 1516021f6537SMarc Zyngier if (!dist_base) { 1517e81f54c6SRob Herring pr_err("%pOF: unable to map gic dist registers\n", node); 1518021f6537SMarc Zyngier return -ENXIO; 1519021f6537SMarc Zyngier } 1520021f6537SMarc Zyngier 1521db57d746STomasz Nowicki err = gic_validate_dist_version(dist_base); 1522db57d746STomasz Nowicki if (err) { 1523e81f54c6SRob Herring pr_err("%pOF: no distributor detected, giving up\n", node); 1524021f6537SMarc Zyngier goto out_unmap_dist; 1525021f6537SMarc Zyngier } 1526021f6537SMarc Zyngier 1527f5c1434cSMarc Zyngier if (of_property_read_u32(node, "#redistributor-regions", &nr_redist_regions)) 1528f5c1434cSMarc Zyngier nr_redist_regions = 1; 1529021f6537SMarc Zyngier 15306396bb22SKees Cook rdist_regs = kcalloc(nr_redist_regions, sizeof(*rdist_regs), 15316396bb22SKees Cook GFP_KERNEL); 1532f5c1434cSMarc Zyngier if (!rdist_regs) { 1533021f6537SMarc Zyngier err = -ENOMEM; 1534021f6537SMarc Zyngier goto out_unmap_dist; 1535021f6537SMarc Zyngier } 1536021f6537SMarc Zyngier 1537f5c1434cSMarc Zyngier for (i = 0; i < nr_redist_regions; i++) { 1538f5c1434cSMarc Zyngier struct resource res; 1539f5c1434cSMarc Zyngier int ret; 1540f5c1434cSMarc Zyngier 1541f5c1434cSMarc Zyngier ret = of_address_to_resource(node, 1 + i, &res); 1542f5c1434cSMarc Zyngier rdist_regs[i].redist_base = of_iomap(node, 1 + i); 1543f5c1434cSMarc Zyngier if (ret || !rdist_regs[i].redist_base) { 1544e81f54c6SRob Herring pr_err("%pOF: couldn't map region %d\n", node, i); 1545021f6537SMarc Zyngier err = -ENODEV; 1546021f6537SMarc Zyngier goto out_unmap_rdist; 1547021f6537SMarc Zyngier } 1548f5c1434cSMarc Zyngier rdist_regs[i].phys_base = res.start; 1549021f6537SMarc Zyngier } 1550021f6537SMarc Zyngier 1551021f6537SMarc Zyngier if (of_property_read_u64(node, "redistributor-stride", &redist_stride)) 1552021f6537SMarc Zyngier redist_stride = 0; 1553021f6537SMarc Zyngier 1554f70fdb42SSrinivas Kandagatla gic_enable_of_quirks(node, gic_quirks, &gic_data); 1555f70fdb42SSrinivas Kandagatla 1556db57d746STomasz Nowicki err = gic_init_bases(dist_base, rdist_regs, nr_redist_regions, 1557db57d746STomasz Nowicki redist_stride, &node->fwnode); 1558e3825ba1SMarc Zyngier if (err) 1559e3825ba1SMarc Zyngier goto out_unmap_rdist; 1560e3825ba1SMarc Zyngier 1561e3825ba1SMarc Zyngier gic_populate_ppi_partitions(node); 1562d33a3c8cSChristoffer Dall 1563d01d3274SDavidlohr Bueso if (static_branch_likely(&supports_deactivate_key)) 15641839e576SJulien Grall gic_of_setup_kvm_info(node); 1565021f6537SMarc Zyngier return 0; 1566021f6537SMarc Zyngier 1567021f6537SMarc Zyngier out_unmap_rdist: 1568f5c1434cSMarc Zyngier for (i = 0; i < nr_redist_regions; i++) 1569f5c1434cSMarc Zyngier if (rdist_regs[i].redist_base) 1570f5c1434cSMarc Zyngier iounmap(rdist_regs[i].redist_base); 1571f5c1434cSMarc Zyngier kfree(rdist_regs); 1572021f6537SMarc Zyngier out_unmap_dist: 1573021f6537SMarc Zyngier iounmap(dist_base); 1574021f6537SMarc Zyngier return err; 1575021f6537SMarc Zyngier } 1576021f6537SMarc Zyngier 1577021f6537SMarc Zyngier IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init); 1578ffa7d616STomasz Nowicki 1579ffa7d616STomasz Nowicki #ifdef CONFIG_ACPI 1580611f039fSJulien Grall static struct 1581611f039fSJulien Grall { 1582611f039fSJulien Grall void __iomem *dist_base; 1583611f039fSJulien Grall struct redist_region *redist_regs; 1584611f039fSJulien Grall u32 nr_redist_regions; 1585611f039fSJulien Grall bool single_redist; 15861839e576SJulien Grall u32 maint_irq; 15871839e576SJulien Grall int maint_irq_mode; 15881839e576SJulien Grall phys_addr_t vcpu_base; 1589611f039fSJulien Grall } acpi_data __initdata; 1590b70fb7afSTomasz Nowicki 1591b70fb7afSTomasz Nowicki static void __init 1592b70fb7afSTomasz Nowicki gic_acpi_register_redist(phys_addr_t phys_base, void __iomem *redist_base) 1593b70fb7afSTomasz Nowicki { 1594b70fb7afSTomasz Nowicki static int count = 0; 1595b70fb7afSTomasz Nowicki 1596611f039fSJulien Grall acpi_data.redist_regs[count].phys_base = phys_base; 1597611f039fSJulien Grall acpi_data.redist_regs[count].redist_base = redist_base; 1598611f039fSJulien Grall acpi_data.redist_regs[count].single_redist = acpi_data.single_redist; 1599b70fb7afSTomasz Nowicki count++; 1600b70fb7afSTomasz Nowicki } 1601ffa7d616STomasz Nowicki 1602ffa7d616STomasz Nowicki static int __init 160360574d1eSKeith Busch gic_acpi_parse_madt_redist(union acpi_subtable_headers *header, 1604ffa7d616STomasz Nowicki const unsigned long end) 1605ffa7d616STomasz Nowicki { 1606ffa7d616STomasz Nowicki struct acpi_madt_generic_redistributor *redist = 1607ffa7d616STomasz Nowicki (struct acpi_madt_generic_redistributor *)header; 1608ffa7d616STomasz Nowicki void __iomem *redist_base; 1609ffa7d616STomasz Nowicki 1610ffa7d616STomasz Nowicki redist_base = ioremap(redist->base_address, redist->length); 1611ffa7d616STomasz Nowicki if (!redist_base) { 1612ffa7d616STomasz Nowicki pr_err("Couldn't map GICR region @%llx\n", redist->base_address); 1613ffa7d616STomasz Nowicki return -ENOMEM; 1614ffa7d616STomasz Nowicki } 1615ffa7d616STomasz Nowicki 1616b70fb7afSTomasz Nowicki gic_acpi_register_redist(redist->base_address, redist_base); 1617ffa7d616STomasz Nowicki return 0; 1618ffa7d616STomasz Nowicki } 1619ffa7d616STomasz Nowicki 1620b70fb7afSTomasz Nowicki static int __init 162160574d1eSKeith Busch gic_acpi_parse_madt_gicc(union acpi_subtable_headers *header, 1622b70fb7afSTomasz Nowicki const unsigned long end) 1623b70fb7afSTomasz Nowicki { 1624b70fb7afSTomasz Nowicki struct acpi_madt_generic_interrupt *gicc = 1625b70fb7afSTomasz Nowicki (struct acpi_madt_generic_interrupt *)header; 1626611f039fSJulien Grall u32 reg = readl_relaxed(acpi_data.dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK; 1627b70fb7afSTomasz Nowicki u32 size = reg == GIC_PIDR2_ARCH_GICv4 ? SZ_64K * 4 : SZ_64K * 2; 1628b70fb7afSTomasz Nowicki void __iomem *redist_base; 1629b70fb7afSTomasz Nowicki 1630ebe2f871SShanker Donthineni /* GICC entry which has !ACPI_MADT_ENABLED is not unusable so skip */ 1631ebe2f871SShanker Donthineni if (!(gicc->flags & ACPI_MADT_ENABLED)) 1632ebe2f871SShanker Donthineni return 0; 1633ebe2f871SShanker Donthineni 1634b70fb7afSTomasz Nowicki redist_base = ioremap(gicc->gicr_base_address, size); 1635b70fb7afSTomasz Nowicki if (!redist_base) 1636b70fb7afSTomasz Nowicki return -ENOMEM; 1637b70fb7afSTomasz Nowicki 1638b70fb7afSTomasz Nowicki gic_acpi_register_redist(gicc->gicr_base_address, redist_base); 1639b70fb7afSTomasz Nowicki return 0; 1640b70fb7afSTomasz Nowicki } 1641b70fb7afSTomasz Nowicki 1642b70fb7afSTomasz Nowicki static int __init gic_acpi_collect_gicr_base(void) 1643b70fb7afSTomasz Nowicki { 1644b70fb7afSTomasz Nowicki acpi_tbl_entry_handler redist_parser; 1645b70fb7afSTomasz Nowicki enum acpi_madt_type type; 1646b70fb7afSTomasz Nowicki 1647611f039fSJulien Grall if (acpi_data.single_redist) { 1648b70fb7afSTomasz Nowicki type = ACPI_MADT_TYPE_GENERIC_INTERRUPT; 1649b70fb7afSTomasz Nowicki redist_parser = gic_acpi_parse_madt_gicc; 1650b70fb7afSTomasz Nowicki } else { 1651b70fb7afSTomasz Nowicki type = ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR; 1652b70fb7afSTomasz Nowicki redist_parser = gic_acpi_parse_madt_redist; 1653b70fb7afSTomasz Nowicki } 1654b70fb7afSTomasz Nowicki 1655b70fb7afSTomasz Nowicki /* Collect redistributor base addresses in GICR entries */ 1656b70fb7afSTomasz Nowicki if (acpi_table_parse_madt(type, redist_parser, 0) > 0) 1657b70fb7afSTomasz Nowicki return 0; 1658b70fb7afSTomasz Nowicki 1659b70fb7afSTomasz Nowicki pr_info("No valid GICR entries exist\n"); 1660b70fb7afSTomasz Nowicki return -ENODEV; 1661b70fb7afSTomasz Nowicki } 1662b70fb7afSTomasz Nowicki 166360574d1eSKeith Busch static int __init gic_acpi_match_gicr(union acpi_subtable_headers *header, 1664ffa7d616STomasz Nowicki const unsigned long end) 1665ffa7d616STomasz Nowicki { 1666ffa7d616STomasz Nowicki /* Subtable presence means that redist exists, that's it */ 1667ffa7d616STomasz Nowicki return 0; 1668ffa7d616STomasz Nowicki } 1669ffa7d616STomasz Nowicki 167060574d1eSKeith Busch static int __init gic_acpi_match_gicc(union acpi_subtable_headers *header, 1671b70fb7afSTomasz Nowicki const unsigned long end) 1672b70fb7afSTomasz Nowicki { 1673b70fb7afSTomasz Nowicki struct acpi_madt_generic_interrupt *gicc = 1674b70fb7afSTomasz Nowicki (struct acpi_madt_generic_interrupt *)header; 1675b70fb7afSTomasz Nowicki 1676b70fb7afSTomasz Nowicki /* 1677b70fb7afSTomasz Nowicki * If GICC is enabled and has valid gicr base address, then it means 1678b70fb7afSTomasz Nowicki * GICR base is presented via GICC 1679b70fb7afSTomasz Nowicki */ 1680b70fb7afSTomasz Nowicki if ((gicc->flags & ACPI_MADT_ENABLED) && gicc->gicr_base_address) 1681b70fb7afSTomasz Nowicki return 0; 1682b70fb7afSTomasz Nowicki 1683ebe2f871SShanker Donthineni /* 1684ebe2f871SShanker Donthineni * It's perfectly valid firmware can pass disabled GICC entry, driver 1685ebe2f871SShanker Donthineni * should not treat as errors, skip the entry instead of probe fail. 1686ebe2f871SShanker Donthineni */ 1687ebe2f871SShanker Donthineni if (!(gicc->flags & ACPI_MADT_ENABLED)) 1688ebe2f871SShanker Donthineni return 0; 1689ebe2f871SShanker Donthineni 1690b70fb7afSTomasz Nowicki return -ENODEV; 1691b70fb7afSTomasz Nowicki } 1692b70fb7afSTomasz Nowicki 1693b70fb7afSTomasz Nowicki static int __init gic_acpi_count_gicr_regions(void) 1694b70fb7afSTomasz Nowicki { 1695b70fb7afSTomasz Nowicki int count; 1696b70fb7afSTomasz Nowicki 1697b70fb7afSTomasz Nowicki /* 1698b70fb7afSTomasz Nowicki * Count how many redistributor regions we have. It is not allowed 1699b70fb7afSTomasz Nowicki * to mix redistributor description, GICR and GICC subtables have to be 1700b70fb7afSTomasz Nowicki * mutually exclusive. 1701b70fb7afSTomasz Nowicki */ 1702b70fb7afSTomasz Nowicki count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR, 1703b70fb7afSTomasz Nowicki gic_acpi_match_gicr, 0); 1704b70fb7afSTomasz Nowicki if (count > 0) { 1705611f039fSJulien Grall acpi_data.single_redist = false; 1706b70fb7afSTomasz Nowicki return count; 1707b70fb7afSTomasz Nowicki } 1708b70fb7afSTomasz Nowicki 1709b70fb7afSTomasz Nowicki count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT, 1710b70fb7afSTomasz Nowicki gic_acpi_match_gicc, 0); 1711b70fb7afSTomasz Nowicki if (count > 0) 1712611f039fSJulien Grall acpi_data.single_redist = true; 1713b70fb7afSTomasz Nowicki 1714b70fb7afSTomasz Nowicki return count; 1715b70fb7afSTomasz Nowicki } 1716b70fb7afSTomasz Nowicki 1717ffa7d616STomasz Nowicki static bool __init acpi_validate_gic_table(struct acpi_subtable_header *header, 1718ffa7d616STomasz Nowicki struct acpi_probe_entry *ape) 1719ffa7d616STomasz Nowicki { 1720ffa7d616STomasz Nowicki struct acpi_madt_generic_distributor *dist; 1721ffa7d616STomasz Nowicki int count; 1722ffa7d616STomasz Nowicki 1723ffa7d616STomasz Nowicki dist = (struct acpi_madt_generic_distributor *)header; 1724ffa7d616STomasz Nowicki if (dist->version != ape->driver_data) 1725ffa7d616STomasz Nowicki return false; 1726ffa7d616STomasz Nowicki 1727ffa7d616STomasz Nowicki /* We need to do that exercise anyway, the sooner the better */ 1728b70fb7afSTomasz Nowicki count = gic_acpi_count_gicr_regions(); 1729ffa7d616STomasz Nowicki if (count <= 0) 1730ffa7d616STomasz Nowicki return false; 1731ffa7d616STomasz Nowicki 1732611f039fSJulien Grall acpi_data.nr_redist_regions = count; 1733ffa7d616STomasz Nowicki return true; 1734ffa7d616STomasz Nowicki } 1735ffa7d616STomasz Nowicki 173660574d1eSKeith Busch static int __init gic_acpi_parse_virt_madt_gicc(union acpi_subtable_headers *header, 17371839e576SJulien Grall const unsigned long end) 17381839e576SJulien Grall { 17391839e576SJulien Grall struct acpi_madt_generic_interrupt *gicc = 17401839e576SJulien Grall (struct acpi_madt_generic_interrupt *)header; 17411839e576SJulien Grall int maint_irq_mode; 17421839e576SJulien Grall static int first_madt = true; 17431839e576SJulien Grall 17441839e576SJulien Grall /* Skip unusable CPUs */ 17451839e576SJulien Grall if (!(gicc->flags & ACPI_MADT_ENABLED)) 17461839e576SJulien Grall return 0; 17471839e576SJulien Grall 17481839e576SJulien Grall maint_irq_mode = (gicc->flags & ACPI_MADT_VGIC_IRQ_MODE) ? 17491839e576SJulien Grall ACPI_EDGE_SENSITIVE : ACPI_LEVEL_SENSITIVE; 17501839e576SJulien Grall 17511839e576SJulien Grall if (first_madt) { 17521839e576SJulien Grall first_madt = false; 17531839e576SJulien Grall 17541839e576SJulien Grall acpi_data.maint_irq = gicc->vgic_interrupt; 17551839e576SJulien Grall acpi_data.maint_irq_mode = maint_irq_mode; 17561839e576SJulien Grall acpi_data.vcpu_base = gicc->gicv_base_address; 17571839e576SJulien Grall 17581839e576SJulien Grall return 0; 17591839e576SJulien Grall } 17601839e576SJulien Grall 17611839e576SJulien Grall /* 17621839e576SJulien Grall * The maintenance interrupt and GICV should be the same for every CPU 17631839e576SJulien Grall */ 17641839e576SJulien Grall if ((acpi_data.maint_irq != gicc->vgic_interrupt) || 17651839e576SJulien Grall (acpi_data.maint_irq_mode != maint_irq_mode) || 17661839e576SJulien Grall (acpi_data.vcpu_base != gicc->gicv_base_address)) 17671839e576SJulien Grall return -EINVAL; 17681839e576SJulien Grall 17691839e576SJulien Grall return 0; 17701839e576SJulien Grall } 17711839e576SJulien Grall 17721839e576SJulien Grall static bool __init gic_acpi_collect_virt_info(void) 17731839e576SJulien Grall { 17741839e576SJulien Grall int count; 17751839e576SJulien Grall 17761839e576SJulien Grall count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT, 17771839e576SJulien Grall gic_acpi_parse_virt_madt_gicc, 0); 17781839e576SJulien Grall 17791839e576SJulien Grall return (count > 0); 17801839e576SJulien Grall } 17811839e576SJulien Grall 1782ffa7d616STomasz Nowicki #define ACPI_GICV3_DIST_MEM_SIZE (SZ_64K) 17831839e576SJulien Grall #define ACPI_GICV2_VCTRL_MEM_SIZE (SZ_4K) 17841839e576SJulien Grall #define ACPI_GICV2_VCPU_MEM_SIZE (SZ_8K) 17851839e576SJulien Grall 17861839e576SJulien Grall static void __init gic_acpi_setup_kvm_info(void) 17871839e576SJulien Grall { 17881839e576SJulien Grall int irq; 17891839e576SJulien Grall 17901839e576SJulien Grall if (!gic_acpi_collect_virt_info()) { 17911839e576SJulien Grall pr_warn("Unable to get hardware information used for virtualization\n"); 17921839e576SJulien Grall return; 17931839e576SJulien Grall } 17941839e576SJulien Grall 17951839e576SJulien Grall gic_v3_kvm_info.type = GIC_V3; 17961839e576SJulien Grall 17971839e576SJulien Grall irq = acpi_register_gsi(NULL, acpi_data.maint_irq, 17981839e576SJulien Grall acpi_data.maint_irq_mode, 17991839e576SJulien Grall ACPI_ACTIVE_HIGH); 18001839e576SJulien Grall if (irq <= 0) 18011839e576SJulien Grall return; 18021839e576SJulien Grall 18031839e576SJulien Grall gic_v3_kvm_info.maint_irq = irq; 18041839e576SJulien Grall 18051839e576SJulien Grall if (acpi_data.vcpu_base) { 18061839e576SJulien Grall struct resource *vcpu = &gic_v3_kvm_info.vcpu; 18071839e576SJulien Grall 18081839e576SJulien Grall vcpu->flags = IORESOURCE_MEM; 18091839e576SJulien Grall vcpu->start = acpi_data.vcpu_base; 18101839e576SJulien Grall vcpu->end = vcpu->start + ACPI_GICV2_VCPU_MEM_SIZE - 1; 18111839e576SJulien Grall } 18121839e576SJulien Grall 18134bdf5025SMarc Zyngier gic_v3_kvm_info.has_v4 = gic_data.rdists.has_vlpis; 18141839e576SJulien Grall gic_set_kvm_info(&gic_v3_kvm_info); 18151839e576SJulien Grall } 1816ffa7d616STomasz Nowicki 1817ffa7d616STomasz Nowicki static int __init 1818ffa7d616STomasz Nowicki gic_acpi_init(struct acpi_subtable_header *header, const unsigned long end) 1819ffa7d616STomasz Nowicki { 1820ffa7d616STomasz Nowicki struct acpi_madt_generic_distributor *dist; 1821ffa7d616STomasz Nowicki struct fwnode_handle *domain_handle; 1822611f039fSJulien Grall size_t size; 1823b70fb7afSTomasz Nowicki int i, err; 1824ffa7d616STomasz Nowicki 1825ffa7d616STomasz Nowicki /* Get distributor base address */ 1826ffa7d616STomasz Nowicki dist = (struct acpi_madt_generic_distributor *)header; 1827611f039fSJulien Grall acpi_data.dist_base = ioremap(dist->base_address, 1828611f039fSJulien Grall ACPI_GICV3_DIST_MEM_SIZE); 1829611f039fSJulien Grall if (!acpi_data.dist_base) { 1830ffa7d616STomasz Nowicki pr_err("Unable to map GICD registers\n"); 1831ffa7d616STomasz Nowicki return -ENOMEM; 1832ffa7d616STomasz Nowicki } 1833ffa7d616STomasz Nowicki 1834611f039fSJulien Grall err = gic_validate_dist_version(acpi_data.dist_base); 1835ffa7d616STomasz Nowicki if (err) { 183671192a68SArvind Yadav pr_err("No distributor detected at @%p, giving up\n", 1837611f039fSJulien Grall acpi_data.dist_base); 1838ffa7d616STomasz Nowicki goto out_dist_unmap; 1839ffa7d616STomasz Nowicki } 1840ffa7d616STomasz Nowicki 1841611f039fSJulien Grall size = sizeof(*acpi_data.redist_regs) * acpi_data.nr_redist_regions; 1842611f039fSJulien Grall acpi_data.redist_regs = kzalloc(size, GFP_KERNEL); 1843611f039fSJulien Grall if (!acpi_data.redist_regs) { 1844ffa7d616STomasz Nowicki err = -ENOMEM; 1845ffa7d616STomasz Nowicki goto out_dist_unmap; 1846ffa7d616STomasz Nowicki } 1847ffa7d616STomasz Nowicki 1848b70fb7afSTomasz Nowicki err = gic_acpi_collect_gicr_base(); 1849b70fb7afSTomasz Nowicki if (err) 1850ffa7d616STomasz Nowicki goto out_redist_unmap; 1851ffa7d616STomasz Nowicki 1852611f039fSJulien Grall domain_handle = irq_domain_alloc_fwnode(acpi_data.dist_base); 1853ffa7d616STomasz Nowicki if (!domain_handle) { 1854ffa7d616STomasz Nowicki err = -ENOMEM; 1855ffa7d616STomasz Nowicki goto out_redist_unmap; 1856ffa7d616STomasz Nowicki } 1857ffa7d616STomasz Nowicki 1858611f039fSJulien Grall err = gic_init_bases(acpi_data.dist_base, acpi_data.redist_regs, 1859611f039fSJulien Grall acpi_data.nr_redist_regions, 0, domain_handle); 1860ffa7d616STomasz Nowicki if (err) 1861ffa7d616STomasz Nowicki goto out_fwhandle_free; 1862ffa7d616STomasz Nowicki 1863ffa7d616STomasz Nowicki acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, domain_handle); 1864d33a3c8cSChristoffer Dall 1865d01d3274SDavidlohr Bueso if (static_branch_likely(&supports_deactivate_key)) 18661839e576SJulien Grall gic_acpi_setup_kvm_info(); 18671839e576SJulien Grall 1868ffa7d616STomasz Nowicki return 0; 1869ffa7d616STomasz Nowicki 1870ffa7d616STomasz Nowicki out_fwhandle_free: 1871ffa7d616STomasz Nowicki irq_domain_free_fwnode(domain_handle); 1872ffa7d616STomasz Nowicki out_redist_unmap: 1873611f039fSJulien Grall for (i = 0; i < acpi_data.nr_redist_regions; i++) 1874611f039fSJulien Grall if (acpi_data.redist_regs[i].redist_base) 1875611f039fSJulien Grall iounmap(acpi_data.redist_regs[i].redist_base); 1876611f039fSJulien Grall kfree(acpi_data.redist_regs); 1877ffa7d616STomasz Nowicki out_dist_unmap: 1878611f039fSJulien Grall iounmap(acpi_data.dist_base); 1879ffa7d616STomasz Nowicki return err; 1880ffa7d616STomasz Nowicki } 1881ffa7d616STomasz Nowicki IRQCHIP_ACPI_DECLARE(gic_v3, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 1882ffa7d616STomasz Nowicki acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V3, 1883ffa7d616STomasz Nowicki gic_acpi_init); 1884ffa7d616STomasz Nowicki IRQCHIP_ACPI_DECLARE(gic_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 1885ffa7d616STomasz Nowicki acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V4, 1886ffa7d616STomasz Nowicki gic_acpi_init); 1887ffa7d616STomasz Nowicki IRQCHIP_ACPI_DECLARE(gic_v3_or_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 1888ffa7d616STomasz Nowicki acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_NONE, 1889ffa7d616STomasz Nowicki gic_acpi_init); 1890ffa7d616STomasz Nowicki #endif 1891