1021f6537SMarc Zyngier /* 20edc23eaSMarc Zyngier * Copyright (C) 2013-2017 ARM Limited, All Rights Reserved. 3021f6537SMarc Zyngier * Author: Marc Zyngier <marc.zyngier@arm.com> 4021f6537SMarc Zyngier * 5021f6537SMarc Zyngier * This program is free software; you can redistribute it and/or modify 6021f6537SMarc Zyngier * it under the terms of the GNU General Public License version 2 as 7021f6537SMarc Zyngier * published by the Free Software Foundation. 8021f6537SMarc Zyngier * 9021f6537SMarc Zyngier * This program is distributed in the hope that it will be useful, 10021f6537SMarc Zyngier * but WITHOUT ANY WARRANTY; without even the implied warranty of 11021f6537SMarc Zyngier * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12021f6537SMarc Zyngier * GNU General Public License for more details. 13021f6537SMarc Zyngier * 14021f6537SMarc Zyngier * You should have received a copy of the GNU General Public License 15021f6537SMarc Zyngier * along with this program. If not, see <http://www.gnu.org/licenses/>. 16021f6537SMarc Zyngier */ 17021f6537SMarc Zyngier 1868628bb8SJulien Grall #define pr_fmt(fmt) "GICv3: " fmt 1968628bb8SJulien Grall 20ffa7d616STomasz Nowicki #include <linux/acpi.h> 21021f6537SMarc Zyngier #include <linux/cpu.h> 223708d52fSSudeep Holla #include <linux/cpu_pm.h> 23021f6537SMarc Zyngier #include <linux/delay.h> 24021f6537SMarc Zyngier #include <linux/interrupt.h> 25ffa7d616STomasz Nowicki #include <linux/irqdomain.h> 26021f6537SMarc Zyngier #include <linux/of.h> 27021f6537SMarc Zyngier #include <linux/of_address.h> 28021f6537SMarc Zyngier #include <linux/of_irq.h> 29021f6537SMarc Zyngier #include <linux/percpu.h> 30021f6537SMarc Zyngier #include <linux/slab.h> 31021f6537SMarc Zyngier 3241a83e06SJoel Porquet #include <linux/irqchip.h> 331839e576SJulien Grall #include <linux/irqchip/arm-gic-common.h> 34021f6537SMarc Zyngier #include <linux/irqchip/arm-gic-v3.h> 35e3825ba1SMarc Zyngier #include <linux/irqchip/irq-partition-percpu.h> 36021f6537SMarc Zyngier 37021f6537SMarc Zyngier #include <asm/cputype.h> 38021f6537SMarc Zyngier #include <asm/exception.h> 39021f6537SMarc Zyngier #include <asm/smp_plat.h> 400b6a3da9SMarc Zyngier #include <asm/virt.h> 41021f6537SMarc Zyngier 42021f6537SMarc Zyngier #include "irq-gic-common.h" 43021f6537SMarc Zyngier 44f5c1434cSMarc Zyngier struct redist_region { 45f5c1434cSMarc Zyngier void __iomem *redist_base; 46f5c1434cSMarc Zyngier phys_addr_t phys_base; 47b70fb7afSTomasz Nowicki bool single_redist; 48f5c1434cSMarc Zyngier }; 49f5c1434cSMarc Zyngier 50021f6537SMarc Zyngier struct gic_chip_data { 51e3825ba1SMarc Zyngier struct fwnode_handle *fwnode; 52021f6537SMarc Zyngier void __iomem *dist_base; 53f5c1434cSMarc Zyngier struct redist_region *redist_regions; 54f5c1434cSMarc Zyngier struct rdists rdists; 55021f6537SMarc Zyngier struct irq_domain *domain; 56021f6537SMarc Zyngier u64 redist_stride; 57f5c1434cSMarc Zyngier u32 nr_redist_regions; 58eda0d04aSShanker Donthineni bool has_rss; 59021f6537SMarc Zyngier unsigned int irq_nr; 60e3825ba1SMarc Zyngier struct partition_desc *ppi_descs[16]; 61021f6537SMarc Zyngier }; 62021f6537SMarc Zyngier 63021f6537SMarc Zyngier static struct gic_chip_data gic_data __read_mostly; 64d01d3274SDavidlohr Bueso static DEFINE_STATIC_KEY_TRUE(supports_deactivate_key); 65021f6537SMarc Zyngier 661839e576SJulien Grall static struct gic_kvm_info gic_v3_kvm_info; 67eda0d04aSShanker Donthineni static DEFINE_PER_CPU(bool, has_rss); 681839e576SJulien Grall 69eda0d04aSShanker Donthineni #define MPIDR_RS(mpidr) (((mpidr) & 0xF0UL) >> 4) 70f5c1434cSMarc Zyngier #define gic_data_rdist() (this_cpu_ptr(gic_data.rdists.rdist)) 71f5c1434cSMarc Zyngier #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base) 72021f6537SMarc Zyngier #define gic_data_rdist_sgi_base() (gic_data_rdist_rd_base() + SZ_64K) 73021f6537SMarc Zyngier 74021f6537SMarc Zyngier /* Our default, arbitrary priority value. Linux only uses one anyway. */ 75021f6537SMarc Zyngier #define DEFAULT_PMR_VALUE 0xf0 76021f6537SMarc Zyngier 77021f6537SMarc Zyngier static inline unsigned int gic_irq(struct irq_data *d) 78021f6537SMarc Zyngier { 79021f6537SMarc Zyngier return d->hwirq; 80021f6537SMarc Zyngier } 81021f6537SMarc Zyngier 82021f6537SMarc Zyngier static inline int gic_irq_in_rdist(struct irq_data *d) 83021f6537SMarc Zyngier { 84021f6537SMarc Zyngier return gic_irq(d) < 32; 85021f6537SMarc Zyngier } 86021f6537SMarc Zyngier 87021f6537SMarc Zyngier static inline void __iomem *gic_dist_base(struct irq_data *d) 88021f6537SMarc Zyngier { 89021f6537SMarc Zyngier if (gic_irq_in_rdist(d)) /* SGI+PPI -> SGI_base for this CPU */ 90021f6537SMarc Zyngier return gic_data_rdist_sgi_base(); 91021f6537SMarc Zyngier 92021f6537SMarc Zyngier if (d->hwirq <= 1023) /* SPI -> dist_base */ 93021f6537SMarc Zyngier return gic_data.dist_base; 94021f6537SMarc Zyngier 95021f6537SMarc Zyngier return NULL; 96021f6537SMarc Zyngier } 97021f6537SMarc Zyngier 98021f6537SMarc Zyngier static void gic_do_wait_for_rwp(void __iomem *base) 99021f6537SMarc Zyngier { 100021f6537SMarc Zyngier u32 count = 1000000; /* 1s! */ 101021f6537SMarc Zyngier 102021f6537SMarc Zyngier while (readl_relaxed(base + GICD_CTLR) & GICD_CTLR_RWP) { 103021f6537SMarc Zyngier count--; 104021f6537SMarc Zyngier if (!count) { 105021f6537SMarc Zyngier pr_err_ratelimited("RWP timeout, gone fishing\n"); 106021f6537SMarc Zyngier return; 107021f6537SMarc Zyngier } 108021f6537SMarc Zyngier cpu_relax(); 109021f6537SMarc Zyngier udelay(1); 110021f6537SMarc Zyngier }; 111021f6537SMarc Zyngier } 112021f6537SMarc Zyngier 113021f6537SMarc Zyngier /* Wait for completion of a distributor change */ 114021f6537SMarc Zyngier static void gic_dist_wait_for_rwp(void) 115021f6537SMarc Zyngier { 116021f6537SMarc Zyngier gic_do_wait_for_rwp(gic_data.dist_base); 117021f6537SMarc Zyngier } 118021f6537SMarc Zyngier 119021f6537SMarc Zyngier /* Wait for completion of a redistributor change */ 120021f6537SMarc Zyngier static void gic_redist_wait_for_rwp(void) 121021f6537SMarc Zyngier { 122021f6537SMarc Zyngier gic_do_wait_for_rwp(gic_data_rdist_rd_base()); 123021f6537SMarc Zyngier } 124021f6537SMarc Zyngier 1257936e914SJean-Philippe Brucker #ifdef CONFIG_ARM64 1266d4e11c5SRobert Richter 1276d4e11c5SRobert Richter static u64 __maybe_unused gic_read_iar(void) 1286d4e11c5SRobert Richter { 129a4023f68SSuzuki K Poulose if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_23154)) 1306d4e11c5SRobert Richter return gic_read_iar_cavium_thunderx(); 1316d4e11c5SRobert Richter else 1326d4e11c5SRobert Richter return gic_read_iar_common(); 1336d4e11c5SRobert Richter } 1347936e914SJean-Philippe Brucker #endif 135021f6537SMarc Zyngier 136a2c22510SSudeep Holla static void gic_enable_redist(bool enable) 137021f6537SMarc Zyngier { 138021f6537SMarc Zyngier void __iomem *rbase; 139021f6537SMarc Zyngier u32 count = 1000000; /* 1s! */ 140021f6537SMarc Zyngier u32 val; 141021f6537SMarc Zyngier 142021f6537SMarc Zyngier rbase = gic_data_rdist_rd_base(); 143021f6537SMarc Zyngier 144021f6537SMarc Zyngier val = readl_relaxed(rbase + GICR_WAKER); 145a2c22510SSudeep Holla if (enable) 146a2c22510SSudeep Holla /* Wake up this CPU redistributor */ 147021f6537SMarc Zyngier val &= ~GICR_WAKER_ProcessorSleep; 148a2c22510SSudeep Holla else 149a2c22510SSudeep Holla val |= GICR_WAKER_ProcessorSleep; 150021f6537SMarc Zyngier writel_relaxed(val, rbase + GICR_WAKER); 151021f6537SMarc Zyngier 152a2c22510SSudeep Holla if (!enable) { /* Check that GICR_WAKER is writeable */ 153a2c22510SSudeep Holla val = readl_relaxed(rbase + GICR_WAKER); 154a2c22510SSudeep Holla if (!(val & GICR_WAKER_ProcessorSleep)) 155a2c22510SSudeep Holla return; /* No PM support in this redistributor */ 156021f6537SMarc Zyngier } 157a2c22510SSudeep Holla 158d102eb5cSDan Carpenter while (--count) { 159a2c22510SSudeep Holla val = readl_relaxed(rbase + GICR_WAKER); 160cf1d9d11SAndrew Jones if (enable ^ (bool)(val & GICR_WAKER_ChildrenAsleep)) 161a2c22510SSudeep Holla break; 162021f6537SMarc Zyngier cpu_relax(); 163021f6537SMarc Zyngier udelay(1); 164021f6537SMarc Zyngier }; 165a2c22510SSudeep Holla if (!count) 166a2c22510SSudeep Holla pr_err_ratelimited("redistributor failed to %s...\n", 167a2c22510SSudeep Holla enable ? "wakeup" : "sleep"); 168021f6537SMarc Zyngier } 169021f6537SMarc Zyngier 170021f6537SMarc Zyngier /* 171021f6537SMarc Zyngier * Routines to disable, enable, EOI and route interrupts 172021f6537SMarc Zyngier */ 173b594c6e2SMarc Zyngier static int gic_peek_irq(struct irq_data *d, u32 offset) 174b594c6e2SMarc Zyngier { 175b594c6e2SMarc Zyngier u32 mask = 1 << (gic_irq(d) % 32); 176b594c6e2SMarc Zyngier void __iomem *base; 177b594c6e2SMarc Zyngier 178b594c6e2SMarc Zyngier if (gic_irq_in_rdist(d)) 179b594c6e2SMarc Zyngier base = gic_data_rdist_sgi_base(); 180b594c6e2SMarc Zyngier else 181b594c6e2SMarc Zyngier base = gic_data.dist_base; 182b594c6e2SMarc Zyngier 183b594c6e2SMarc Zyngier return !!(readl_relaxed(base + offset + (gic_irq(d) / 32) * 4) & mask); 184b594c6e2SMarc Zyngier } 185b594c6e2SMarc Zyngier 186021f6537SMarc Zyngier static void gic_poke_irq(struct irq_data *d, u32 offset) 187021f6537SMarc Zyngier { 188021f6537SMarc Zyngier u32 mask = 1 << (gic_irq(d) % 32); 189021f6537SMarc Zyngier void (*rwp_wait)(void); 190021f6537SMarc Zyngier void __iomem *base; 191021f6537SMarc Zyngier 192021f6537SMarc Zyngier if (gic_irq_in_rdist(d)) { 193021f6537SMarc Zyngier base = gic_data_rdist_sgi_base(); 194021f6537SMarc Zyngier rwp_wait = gic_redist_wait_for_rwp; 195021f6537SMarc Zyngier } else { 196021f6537SMarc Zyngier base = gic_data.dist_base; 197021f6537SMarc Zyngier rwp_wait = gic_dist_wait_for_rwp; 198021f6537SMarc Zyngier } 199021f6537SMarc Zyngier 200021f6537SMarc Zyngier writel_relaxed(mask, base + offset + (gic_irq(d) / 32) * 4); 201021f6537SMarc Zyngier rwp_wait(); 202021f6537SMarc Zyngier } 203021f6537SMarc Zyngier 204021f6537SMarc Zyngier static void gic_mask_irq(struct irq_data *d) 205021f6537SMarc Zyngier { 206021f6537SMarc Zyngier gic_poke_irq(d, GICD_ICENABLER); 207021f6537SMarc Zyngier } 208021f6537SMarc Zyngier 2090b6a3da9SMarc Zyngier static void gic_eoimode1_mask_irq(struct irq_data *d) 2100b6a3da9SMarc Zyngier { 2110b6a3da9SMarc Zyngier gic_mask_irq(d); 212530bf353SMarc Zyngier /* 213530bf353SMarc Zyngier * When masking a forwarded interrupt, make sure it is 214530bf353SMarc Zyngier * deactivated as well. 215530bf353SMarc Zyngier * 216530bf353SMarc Zyngier * This ensures that an interrupt that is getting 217530bf353SMarc Zyngier * disabled/masked will not get "stuck", because there is 218530bf353SMarc Zyngier * noone to deactivate it (guest is being terminated). 219530bf353SMarc Zyngier */ 2204df7f54dSThomas Gleixner if (irqd_is_forwarded_to_vcpu(d)) 221530bf353SMarc Zyngier gic_poke_irq(d, GICD_ICACTIVER); 2220b6a3da9SMarc Zyngier } 2230b6a3da9SMarc Zyngier 224021f6537SMarc Zyngier static void gic_unmask_irq(struct irq_data *d) 225021f6537SMarc Zyngier { 226021f6537SMarc Zyngier gic_poke_irq(d, GICD_ISENABLER); 227021f6537SMarc Zyngier } 228021f6537SMarc Zyngier 229b594c6e2SMarc Zyngier static int gic_irq_set_irqchip_state(struct irq_data *d, 230b594c6e2SMarc Zyngier enum irqchip_irq_state which, bool val) 231b594c6e2SMarc Zyngier { 232b594c6e2SMarc Zyngier u32 reg; 233b594c6e2SMarc Zyngier 234b594c6e2SMarc Zyngier if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */ 235b594c6e2SMarc Zyngier return -EINVAL; 236b594c6e2SMarc Zyngier 237b594c6e2SMarc Zyngier switch (which) { 238b594c6e2SMarc Zyngier case IRQCHIP_STATE_PENDING: 239b594c6e2SMarc Zyngier reg = val ? GICD_ISPENDR : GICD_ICPENDR; 240b594c6e2SMarc Zyngier break; 241b594c6e2SMarc Zyngier 242b594c6e2SMarc Zyngier case IRQCHIP_STATE_ACTIVE: 243b594c6e2SMarc Zyngier reg = val ? GICD_ISACTIVER : GICD_ICACTIVER; 244b594c6e2SMarc Zyngier break; 245b594c6e2SMarc Zyngier 246b594c6e2SMarc Zyngier case IRQCHIP_STATE_MASKED: 247b594c6e2SMarc Zyngier reg = val ? GICD_ICENABLER : GICD_ISENABLER; 248b594c6e2SMarc Zyngier break; 249b594c6e2SMarc Zyngier 250b594c6e2SMarc Zyngier default: 251b594c6e2SMarc Zyngier return -EINVAL; 252b594c6e2SMarc Zyngier } 253b594c6e2SMarc Zyngier 254b594c6e2SMarc Zyngier gic_poke_irq(d, reg); 255b594c6e2SMarc Zyngier return 0; 256b594c6e2SMarc Zyngier } 257b594c6e2SMarc Zyngier 258b594c6e2SMarc Zyngier static int gic_irq_get_irqchip_state(struct irq_data *d, 259b594c6e2SMarc Zyngier enum irqchip_irq_state which, bool *val) 260b594c6e2SMarc Zyngier { 261b594c6e2SMarc Zyngier if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */ 262b594c6e2SMarc Zyngier return -EINVAL; 263b594c6e2SMarc Zyngier 264b594c6e2SMarc Zyngier switch (which) { 265b594c6e2SMarc Zyngier case IRQCHIP_STATE_PENDING: 266b594c6e2SMarc Zyngier *val = gic_peek_irq(d, GICD_ISPENDR); 267b594c6e2SMarc Zyngier break; 268b594c6e2SMarc Zyngier 269b594c6e2SMarc Zyngier case IRQCHIP_STATE_ACTIVE: 270b594c6e2SMarc Zyngier *val = gic_peek_irq(d, GICD_ISACTIVER); 271b594c6e2SMarc Zyngier break; 272b594c6e2SMarc Zyngier 273b594c6e2SMarc Zyngier case IRQCHIP_STATE_MASKED: 274b594c6e2SMarc Zyngier *val = !gic_peek_irq(d, GICD_ISENABLER); 275b594c6e2SMarc Zyngier break; 276b594c6e2SMarc Zyngier 277b594c6e2SMarc Zyngier default: 278b594c6e2SMarc Zyngier return -EINVAL; 279b594c6e2SMarc Zyngier } 280b594c6e2SMarc Zyngier 281b594c6e2SMarc Zyngier return 0; 282b594c6e2SMarc Zyngier } 283b594c6e2SMarc Zyngier 284021f6537SMarc Zyngier static void gic_eoi_irq(struct irq_data *d) 285021f6537SMarc Zyngier { 286021f6537SMarc Zyngier gic_write_eoir(gic_irq(d)); 287021f6537SMarc Zyngier } 288021f6537SMarc Zyngier 2890b6a3da9SMarc Zyngier static void gic_eoimode1_eoi_irq(struct irq_data *d) 2900b6a3da9SMarc Zyngier { 2910b6a3da9SMarc Zyngier /* 292530bf353SMarc Zyngier * No need to deactivate an LPI, or an interrupt that 293530bf353SMarc Zyngier * is is getting forwarded to a vcpu. 2940b6a3da9SMarc Zyngier */ 2954df7f54dSThomas Gleixner if (gic_irq(d) >= 8192 || irqd_is_forwarded_to_vcpu(d)) 2960b6a3da9SMarc Zyngier return; 2970b6a3da9SMarc Zyngier gic_write_dir(gic_irq(d)); 2980b6a3da9SMarc Zyngier } 2990b6a3da9SMarc Zyngier 300021f6537SMarc Zyngier static int gic_set_type(struct irq_data *d, unsigned int type) 301021f6537SMarc Zyngier { 302021f6537SMarc Zyngier unsigned int irq = gic_irq(d); 303021f6537SMarc Zyngier void (*rwp_wait)(void); 304021f6537SMarc Zyngier void __iomem *base; 305021f6537SMarc Zyngier 306021f6537SMarc Zyngier /* Interrupt configuration for SGIs can't be changed */ 307021f6537SMarc Zyngier if (irq < 16) 308021f6537SMarc Zyngier return -EINVAL; 309021f6537SMarc Zyngier 310fb7e7debSLiviu Dudau /* SPIs have restrictions on the supported types */ 311fb7e7debSLiviu Dudau if (irq >= 32 && type != IRQ_TYPE_LEVEL_HIGH && 312fb7e7debSLiviu Dudau type != IRQ_TYPE_EDGE_RISING) 313021f6537SMarc Zyngier return -EINVAL; 314021f6537SMarc Zyngier 315021f6537SMarc Zyngier if (gic_irq_in_rdist(d)) { 316021f6537SMarc Zyngier base = gic_data_rdist_sgi_base(); 317021f6537SMarc Zyngier rwp_wait = gic_redist_wait_for_rwp; 318021f6537SMarc Zyngier } else { 319021f6537SMarc Zyngier base = gic_data.dist_base; 320021f6537SMarc Zyngier rwp_wait = gic_dist_wait_for_rwp; 321021f6537SMarc Zyngier } 322021f6537SMarc Zyngier 323fb7e7debSLiviu Dudau return gic_configure_irq(irq, type, base, rwp_wait); 324021f6537SMarc Zyngier } 325021f6537SMarc Zyngier 326530bf353SMarc Zyngier static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu) 327530bf353SMarc Zyngier { 3284df7f54dSThomas Gleixner if (vcpu) 3294df7f54dSThomas Gleixner irqd_set_forwarded_to_vcpu(d); 3304df7f54dSThomas Gleixner else 3314df7f54dSThomas Gleixner irqd_clr_forwarded_to_vcpu(d); 332530bf353SMarc Zyngier return 0; 333530bf353SMarc Zyngier } 334530bf353SMarc Zyngier 335f6c86a41SJean-Philippe Brucker static u64 gic_mpidr_to_affinity(unsigned long mpidr) 336021f6537SMarc Zyngier { 337021f6537SMarc Zyngier u64 aff; 338021f6537SMarc Zyngier 339f6c86a41SJean-Philippe Brucker aff = ((u64)MPIDR_AFFINITY_LEVEL(mpidr, 3) << 32 | 340021f6537SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 | 341021f6537SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | 342021f6537SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 0)); 343021f6537SMarc Zyngier 344021f6537SMarc Zyngier return aff; 345021f6537SMarc Zyngier } 346021f6537SMarc Zyngier 347021f6537SMarc Zyngier static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) 348021f6537SMarc Zyngier { 349f6c86a41SJean-Philippe Brucker u32 irqnr; 350021f6537SMarc Zyngier 351021f6537SMarc Zyngier do { 352021f6537SMarc Zyngier irqnr = gic_read_iar(); 353021f6537SMarc Zyngier 354da33f31dSMarc Zyngier if (likely(irqnr > 15 && irqnr < 1020) || irqnr >= 8192) { 355ebc6de00SMarc Zyngier int err; 3560b6a3da9SMarc Zyngier 357d01d3274SDavidlohr Bueso if (static_branch_likely(&supports_deactivate_key)) 3580b6a3da9SMarc Zyngier gic_write_eoir(irqnr); 35939a06b67SWill Deacon else 36039a06b67SWill Deacon isb(); 3610b6a3da9SMarc Zyngier 362ebc6de00SMarc Zyngier err = handle_domain_irq(gic_data.domain, irqnr, regs); 363ebc6de00SMarc Zyngier if (err) { 364da33f31dSMarc Zyngier WARN_ONCE(true, "Unexpected interrupt received!\n"); 365d01d3274SDavidlohr Bueso if (static_branch_likely(&supports_deactivate_key)) { 3660b6a3da9SMarc Zyngier if (irqnr < 8192) 3670b6a3da9SMarc Zyngier gic_write_dir(irqnr); 3680b6a3da9SMarc Zyngier } else { 369021f6537SMarc Zyngier gic_write_eoir(irqnr); 370021f6537SMarc Zyngier } 3710b6a3da9SMarc Zyngier } 372ebc6de00SMarc Zyngier continue; 373ebc6de00SMarc Zyngier } 374021f6537SMarc Zyngier if (irqnr < 16) { 375021f6537SMarc Zyngier gic_write_eoir(irqnr); 376d01d3274SDavidlohr Bueso if (static_branch_likely(&supports_deactivate_key)) 3770b6a3da9SMarc Zyngier gic_write_dir(irqnr); 378021f6537SMarc Zyngier #ifdef CONFIG_SMP 379f86c4fbdSWill Deacon /* 380f86c4fbdSWill Deacon * Unlike GICv2, we don't need an smp_rmb() here. 381f86c4fbdSWill Deacon * The control dependency from gic_read_iar to 382f86c4fbdSWill Deacon * the ISB in gic_write_eoir is enough to ensure 383f86c4fbdSWill Deacon * that any shared data read by handle_IPI will 384f86c4fbdSWill Deacon * be read after the ACK. 385f86c4fbdSWill Deacon */ 386021f6537SMarc Zyngier handle_IPI(irqnr, regs); 387021f6537SMarc Zyngier #else 388021f6537SMarc Zyngier WARN_ONCE(true, "Unexpected SGI received!\n"); 389021f6537SMarc Zyngier #endif 390021f6537SMarc Zyngier continue; 391021f6537SMarc Zyngier } 392021f6537SMarc Zyngier } while (irqnr != ICC_IAR1_EL1_SPURIOUS); 393021f6537SMarc Zyngier } 394021f6537SMarc Zyngier 395021f6537SMarc Zyngier static void __init gic_dist_init(void) 396021f6537SMarc Zyngier { 397021f6537SMarc Zyngier unsigned int i; 398021f6537SMarc Zyngier u64 affinity; 399021f6537SMarc Zyngier void __iomem *base = gic_data.dist_base; 400021f6537SMarc Zyngier 401021f6537SMarc Zyngier /* Disable the distributor */ 402021f6537SMarc Zyngier writel_relaxed(0, base + GICD_CTLR); 403021f6537SMarc Zyngier gic_dist_wait_for_rwp(); 404021f6537SMarc Zyngier 4057c9b9730SMarc Zyngier /* 4067c9b9730SMarc Zyngier * Configure SPIs as non-secure Group-1. This will only matter 4077c9b9730SMarc Zyngier * if the GIC only has a single security state. This will not 4087c9b9730SMarc Zyngier * do the right thing if the kernel is running in secure mode, 4097c9b9730SMarc Zyngier * but that's not the intended use case anyway. 4107c9b9730SMarc Zyngier */ 4117c9b9730SMarc Zyngier for (i = 32; i < gic_data.irq_nr; i += 32) 4127c9b9730SMarc Zyngier writel_relaxed(~0, base + GICD_IGROUPR + i / 8); 4137c9b9730SMarc Zyngier 414021f6537SMarc Zyngier gic_dist_config(base, gic_data.irq_nr, gic_dist_wait_for_rwp); 415021f6537SMarc Zyngier 416021f6537SMarc Zyngier /* Enable distributor with ARE, Group1 */ 417021f6537SMarc Zyngier writel_relaxed(GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G1A | GICD_CTLR_ENABLE_G1, 418021f6537SMarc Zyngier base + GICD_CTLR); 419021f6537SMarc Zyngier 420021f6537SMarc Zyngier /* 421021f6537SMarc Zyngier * Set all global interrupts to the boot CPU only. ARE must be 422021f6537SMarc Zyngier * enabled. 423021f6537SMarc Zyngier */ 424021f6537SMarc Zyngier affinity = gic_mpidr_to_affinity(cpu_logical_map(smp_processor_id())); 425021f6537SMarc Zyngier for (i = 32; i < gic_data.irq_nr; i++) 42672c97126SJean-Philippe Brucker gic_write_irouter(affinity, base + GICD_IROUTER + i * 8); 427021f6537SMarc Zyngier } 428021f6537SMarc Zyngier 4290d94ded2SMarc Zyngier static int gic_iterate_rdists(int (*fn)(struct redist_region *, void __iomem *)) 430021f6537SMarc Zyngier { 4310d94ded2SMarc Zyngier int ret = -ENODEV; 432021f6537SMarc Zyngier int i; 433021f6537SMarc Zyngier 434f5c1434cSMarc Zyngier for (i = 0; i < gic_data.nr_redist_regions; i++) { 435f5c1434cSMarc Zyngier void __iomem *ptr = gic_data.redist_regions[i].redist_base; 4360d94ded2SMarc Zyngier u64 typer; 437021f6537SMarc Zyngier u32 reg; 438021f6537SMarc Zyngier 439021f6537SMarc Zyngier reg = readl_relaxed(ptr + GICR_PIDR2) & GIC_PIDR2_ARCH_MASK; 440021f6537SMarc Zyngier if (reg != GIC_PIDR2_ARCH_GICv3 && 441021f6537SMarc Zyngier reg != GIC_PIDR2_ARCH_GICv4) { /* We're in trouble... */ 442021f6537SMarc Zyngier pr_warn("No redistributor present @%p\n", ptr); 443021f6537SMarc Zyngier break; 444021f6537SMarc Zyngier } 445021f6537SMarc Zyngier 446021f6537SMarc Zyngier do { 44772c97126SJean-Philippe Brucker typer = gic_read_typer(ptr + GICR_TYPER); 4480d94ded2SMarc Zyngier ret = fn(gic_data.redist_regions + i, ptr); 4490d94ded2SMarc Zyngier if (!ret) 450021f6537SMarc Zyngier return 0; 451021f6537SMarc Zyngier 452b70fb7afSTomasz Nowicki if (gic_data.redist_regions[i].single_redist) 453b70fb7afSTomasz Nowicki break; 454b70fb7afSTomasz Nowicki 455021f6537SMarc Zyngier if (gic_data.redist_stride) { 456021f6537SMarc Zyngier ptr += gic_data.redist_stride; 457021f6537SMarc Zyngier } else { 458021f6537SMarc Zyngier ptr += SZ_64K * 2; /* Skip RD_base + SGI_base */ 459021f6537SMarc Zyngier if (typer & GICR_TYPER_VLPIS) 460021f6537SMarc Zyngier ptr += SZ_64K * 2; /* Skip VLPI_base + reserved page */ 461021f6537SMarc Zyngier } 462021f6537SMarc Zyngier } while (!(typer & GICR_TYPER_LAST)); 463021f6537SMarc Zyngier } 464021f6537SMarc Zyngier 4650d94ded2SMarc Zyngier return ret ? -ENODEV : 0; 4660d94ded2SMarc Zyngier } 4670d94ded2SMarc Zyngier 4680d94ded2SMarc Zyngier static int __gic_populate_rdist(struct redist_region *region, void __iomem *ptr) 4690d94ded2SMarc Zyngier { 4700d94ded2SMarc Zyngier unsigned long mpidr = cpu_logical_map(smp_processor_id()); 4710d94ded2SMarc Zyngier u64 typer; 4720d94ded2SMarc Zyngier u32 aff; 4730d94ded2SMarc Zyngier 4740d94ded2SMarc Zyngier /* 4750d94ded2SMarc Zyngier * Convert affinity to a 32bit value that can be matched to 4760d94ded2SMarc Zyngier * GICR_TYPER bits [63:32]. 4770d94ded2SMarc Zyngier */ 4780d94ded2SMarc Zyngier aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 24 | 4790d94ded2SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 | 4800d94ded2SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | 4810d94ded2SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 0)); 4820d94ded2SMarc Zyngier 4830d94ded2SMarc Zyngier typer = gic_read_typer(ptr + GICR_TYPER); 4840d94ded2SMarc Zyngier if ((typer >> 32) == aff) { 4850d94ded2SMarc Zyngier u64 offset = ptr - region->redist_base; 4860d94ded2SMarc Zyngier gic_data_rdist_rd_base() = ptr; 4870d94ded2SMarc Zyngier gic_data_rdist()->phys_base = region->phys_base + offset; 4880d94ded2SMarc Zyngier 4890d94ded2SMarc Zyngier pr_info("CPU%d: found redistributor %lx region %d:%pa\n", 4900d94ded2SMarc Zyngier smp_processor_id(), mpidr, 4910d94ded2SMarc Zyngier (int)(region - gic_data.redist_regions), 4920d94ded2SMarc Zyngier &gic_data_rdist()->phys_base); 4930d94ded2SMarc Zyngier return 0; 4940d94ded2SMarc Zyngier } 4950d94ded2SMarc Zyngier 4960d94ded2SMarc Zyngier /* Try next one */ 4970d94ded2SMarc Zyngier return 1; 4980d94ded2SMarc Zyngier } 4990d94ded2SMarc Zyngier 5000d94ded2SMarc Zyngier static int gic_populate_rdist(void) 5010d94ded2SMarc Zyngier { 5020d94ded2SMarc Zyngier if (gic_iterate_rdists(__gic_populate_rdist) == 0) 5030d94ded2SMarc Zyngier return 0; 5040d94ded2SMarc Zyngier 505021f6537SMarc Zyngier /* We couldn't even deal with ourselves... */ 506f6c86a41SJean-Philippe Brucker WARN(true, "CPU%d: mpidr %lx has no re-distributor!\n", 5070d94ded2SMarc Zyngier smp_processor_id(), 5080d94ded2SMarc Zyngier (unsigned long)cpu_logical_map(smp_processor_id())); 509021f6537SMarc Zyngier return -ENODEV; 510021f6537SMarc Zyngier } 511021f6537SMarc Zyngier 5120edc23eaSMarc Zyngier static int __gic_update_vlpi_properties(struct redist_region *region, 5130edc23eaSMarc Zyngier void __iomem *ptr) 5140edc23eaSMarc Zyngier { 5150edc23eaSMarc Zyngier u64 typer = gic_read_typer(ptr + GICR_TYPER); 5160edc23eaSMarc Zyngier gic_data.rdists.has_vlpis &= !!(typer & GICR_TYPER_VLPIS); 5170edc23eaSMarc Zyngier gic_data.rdists.has_direct_lpi &= !!(typer & GICR_TYPER_DirectLPIS); 5180edc23eaSMarc Zyngier 5190edc23eaSMarc Zyngier return 1; 5200edc23eaSMarc Zyngier } 5210edc23eaSMarc Zyngier 5220edc23eaSMarc Zyngier static void gic_update_vlpi_properties(void) 5230edc23eaSMarc Zyngier { 5240edc23eaSMarc Zyngier gic_iterate_rdists(__gic_update_vlpi_properties); 5250edc23eaSMarc Zyngier pr_info("%sVLPI support, %sdirect LPI support\n", 5260edc23eaSMarc Zyngier !gic_data.rdists.has_vlpis ? "no " : "", 5270edc23eaSMarc Zyngier !gic_data.rdists.has_direct_lpi ? "no " : ""); 5280edc23eaSMarc Zyngier } 5290edc23eaSMarc Zyngier 5303708d52fSSudeep Holla static void gic_cpu_sys_reg_init(void) 531021f6537SMarc Zyngier { 532eda0d04aSShanker Donthineni int i, cpu = smp_processor_id(); 533eda0d04aSShanker Donthineni u64 mpidr = cpu_logical_map(cpu); 534eda0d04aSShanker Donthineni u64 need_rss = MPIDR_RS(mpidr); 53533625282SMarc Zyngier bool group0; 53633625282SMarc Zyngier u32 val, pribits; 537eda0d04aSShanker Donthineni 5387cabd008SMarc Zyngier /* 5397cabd008SMarc Zyngier * Need to check that the SRE bit has actually been set. If 5407cabd008SMarc Zyngier * not, it means that SRE is disabled at EL2. We're going to 5417cabd008SMarc Zyngier * die painfully, and there is nothing we can do about it. 5427cabd008SMarc Zyngier * 5437cabd008SMarc Zyngier * Kindly inform the luser. 5447cabd008SMarc Zyngier */ 5457cabd008SMarc Zyngier if (!gic_enable_sre()) 5467cabd008SMarc Zyngier pr_err("GIC: unable to set SRE (disabled at EL2), panic ahead\n"); 547021f6537SMarc Zyngier 54833625282SMarc Zyngier pribits = gic_read_ctlr(); 54933625282SMarc Zyngier pribits &= ICC_CTLR_EL1_PRI_BITS_MASK; 55033625282SMarc Zyngier pribits >>= ICC_CTLR_EL1_PRI_BITS_SHIFT; 55133625282SMarc Zyngier pribits++; 55233625282SMarc Zyngier 55333625282SMarc Zyngier /* 55433625282SMarc Zyngier * Let's find out if Group0 is under control of EL3 or not by 55533625282SMarc Zyngier * setting the highest possible, non-zero priority in PMR. 55633625282SMarc Zyngier * 55733625282SMarc Zyngier * If SCR_EL3.FIQ is set, the priority gets shifted down in 55833625282SMarc Zyngier * order for the CPU interface to set bit 7, and keep the 55933625282SMarc Zyngier * actual priority in the non-secure range. In the process, it 56033625282SMarc Zyngier * looses the least significant bit and the actual priority 56133625282SMarc Zyngier * becomes 0x80. Reading it back returns 0, indicating that 56233625282SMarc Zyngier * we're don't have access to Group0. 56333625282SMarc Zyngier */ 56433625282SMarc Zyngier write_gicreg(BIT(8 - pribits), ICC_PMR_EL1); 56533625282SMarc Zyngier val = read_gicreg(ICC_PMR_EL1); 56633625282SMarc Zyngier group0 = val != 0; 56733625282SMarc Zyngier 568021f6537SMarc Zyngier /* Set priority mask register */ 56933625282SMarc Zyngier write_gicreg(DEFAULT_PMR_VALUE, ICC_PMR_EL1); 570021f6537SMarc Zyngier 57191ef8442SDaniel Thompson /* 57291ef8442SDaniel Thompson * Some firmwares hand over to the kernel with the BPR changed from 57391ef8442SDaniel Thompson * its reset value (and with a value large enough to prevent 57491ef8442SDaniel Thompson * any pre-emptive interrupts from working at all). Writing a zero 57591ef8442SDaniel Thompson * to BPR restores is reset value. 57691ef8442SDaniel Thompson */ 57791ef8442SDaniel Thompson gic_write_bpr1(0); 57891ef8442SDaniel Thompson 579d01d3274SDavidlohr Bueso if (static_branch_likely(&supports_deactivate_key)) { 5800b6a3da9SMarc Zyngier /* EOI drops priority only (mode 1) */ 5810b6a3da9SMarc Zyngier gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop); 5820b6a3da9SMarc Zyngier } else { 583021f6537SMarc Zyngier /* EOI deactivates interrupt too (mode 0) */ 584021f6537SMarc Zyngier gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop_dir); 5850b6a3da9SMarc Zyngier } 586021f6537SMarc Zyngier 58733625282SMarc Zyngier /* Always whack Group0 before Group1 */ 58833625282SMarc Zyngier if (group0) { 58933625282SMarc Zyngier switch(pribits) { 59033625282SMarc Zyngier case 8: 59133625282SMarc Zyngier case 7: 59233625282SMarc Zyngier write_gicreg(0, ICC_AP0R3_EL1); 59333625282SMarc Zyngier write_gicreg(0, ICC_AP0R2_EL1); 59433625282SMarc Zyngier case 6: 59533625282SMarc Zyngier write_gicreg(0, ICC_AP0R1_EL1); 59633625282SMarc Zyngier case 5: 59733625282SMarc Zyngier case 4: 59833625282SMarc Zyngier write_gicreg(0, ICC_AP0R0_EL1); 59933625282SMarc Zyngier } 600d6062a6dSMarc Zyngier 60133625282SMarc Zyngier isb(); 60233625282SMarc Zyngier } 60333625282SMarc Zyngier 60433625282SMarc Zyngier switch(pribits) { 605d6062a6dSMarc Zyngier case 8: 606d6062a6dSMarc Zyngier case 7: 607d6062a6dSMarc Zyngier write_gicreg(0, ICC_AP1R3_EL1); 608d6062a6dSMarc Zyngier write_gicreg(0, ICC_AP1R2_EL1); 609d6062a6dSMarc Zyngier case 6: 610d6062a6dSMarc Zyngier write_gicreg(0, ICC_AP1R1_EL1); 611d6062a6dSMarc Zyngier case 5: 612d6062a6dSMarc Zyngier case 4: 613d6062a6dSMarc Zyngier write_gicreg(0, ICC_AP1R0_EL1); 614d6062a6dSMarc Zyngier } 615d6062a6dSMarc Zyngier 616d6062a6dSMarc Zyngier isb(); 617d6062a6dSMarc Zyngier 618021f6537SMarc Zyngier /* ... and let's hit the road... */ 619021f6537SMarc Zyngier gic_write_grpen1(1); 620eda0d04aSShanker Donthineni 621eda0d04aSShanker Donthineni /* Keep the RSS capability status in per_cpu variable */ 622eda0d04aSShanker Donthineni per_cpu(has_rss, cpu) = !!(gic_read_ctlr() & ICC_CTLR_EL1_RSS); 623eda0d04aSShanker Donthineni 624eda0d04aSShanker Donthineni /* Check all the CPUs have capable of sending SGIs to other CPUs */ 625eda0d04aSShanker Donthineni for_each_online_cpu(i) { 626eda0d04aSShanker Donthineni bool have_rss = per_cpu(has_rss, i) && per_cpu(has_rss, cpu); 627eda0d04aSShanker Donthineni 628eda0d04aSShanker Donthineni need_rss |= MPIDR_RS(cpu_logical_map(i)); 629eda0d04aSShanker Donthineni if (need_rss && (!have_rss)) 630eda0d04aSShanker Donthineni pr_crit("CPU%d (%lx) can't SGI CPU%d (%lx), no RSS\n", 631eda0d04aSShanker Donthineni cpu, (unsigned long)mpidr, 632eda0d04aSShanker Donthineni i, (unsigned long)cpu_logical_map(i)); 633eda0d04aSShanker Donthineni } 634eda0d04aSShanker Donthineni 635eda0d04aSShanker Donthineni /** 636eda0d04aSShanker Donthineni * GIC spec says, when ICC_CTLR_EL1.RSS==1 and GICD_TYPER.RSS==0, 637eda0d04aSShanker Donthineni * writing ICC_ASGI1R_EL1 register with RS != 0 is a CONSTRAINED 638eda0d04aSShanker Donthineni * UNPREDICTABLE choice of : 639eda0d04aSShanker Donthineni * - The write is ignored. 640eda0d04aSShanker Donthineni * - The RS field is treated as 0. 641eda0d04aSShanker Donthineni */ 642eda0d04aSShanker Donthineni if (need_rss && (!gic_data.has_rss)) 643eda0d04aSShanker Donthineni pr_crit_once("RSS is required but GICD doesn't support it\n"); 644021f6537SMarc Zyngier } 645021f6537SMarc Zyngier 646f736d65dSMarc Zyngier static bool gicv3_nolpi; 647f736d65dSMarc Zyngier 648f736d65dSMarc Zyngier static int __init gicv3_nolpi_cfg(char *buf) 649f736d65dSMarc Zyngier { 650f736d65dSMarc Zyngier return strtobool(buf, &gicv3_nolpi); 651f736d65dSMarc Zyngier } 652f736d65dSMarc Zyngier early_param("irqchip.gicv3_nolpi", gicv3_nolpi_cfg); 653f736d65dSMarc Zyngier 654da33f31dSMarc Zyngier static int gic_dist_supports_lpis(void) 655da33f31dSMarc Zyngier { 656f736d65dSMarc Zyngier return !!(readl_relaxed(gic_data.dist_base + GICD_TYPER) & GICD_TYPER_LPIS) && !gicv3_nolpi; 657da33f31dSMarc Zyngier } 658da33f31dSMarc Zyngier 659021f6537SMarc Zyngier static void gic_cpu_init(void) 660021f6537SMarc Zyngier { 661021f6537SMarc Zyngier void __iomem *rbase; 662021f6537SMarc Zyngier 663021f6537SMarc Zyngier /* Register ourselves with the rest of the world */ 664021f6537SMarc Zyngier if (gic_populate_rdist()) 665021f6537SMarc Zyngier return; 666021f6537SMarc Zyngier 667a2c22510SSudeep Holla gic_enable_redist(true); 668021f6537SMarc Zyngier 669021f6537SMarc Zyngier rbase = gic_data_rdist_sgi_base(); 670021f6537SMarc Zyngier 6717c9b9730SMarc Zyngier /* Configure SGIs/PPIs as non-secure Group-1 */ 6727c9b9730SMarc Zyngier writel_relaxed(~0, rbase + GICR_IGROUPR0); 6737c9b9730SMarc Zyngier 674021f6537SMarc Zyngier gic_cpu_config(rbase, gic_redist_wait_for_rwp); 675021f6537SMarc Zyngier 676da33f31dSMarc Zyngier /* Give LPIs a spin */ 677da33f31dSMarc Zyngier if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis()) 678da33f31dSMarc Zyngier its_cpu_init(); 679da33f31dSMarc Zyngier 6803708d52fSSudeep Holla /* initialise system registers */ 6813708d52fSSudeep Holla gic_cpu_sys_reg_init(); 682021f6537SMarc Zyngier } 683021f6537SMarc Zyngier 684021f6537SMarc Zyngier #ifdef CONFIG_SMP 685021f6537SMarc Zyngier 686eda0d04aSShanker Donthineni #define MPIDR_TO_SGI_RS(mpidr) (MPIDR_RS(mpidr) << ICC_SGI1R_RS_SHIFT) 687eda0d04aSShanker Donthineni #define MPIDR_TO_SGI_CLUSTER_ID(mpidr) ((mpidr) & ~0xFUL) 688eda0d04aSShanker Donthineni 6896670a6d8SRichard Cochran static int gic_starting_cpu(unsigned int cpu) 6906670a6d8SRichard Cochran { 6916670a6d8SRichard Cochran gic_cpu_init(); 6926670a6d8SRichard Cochran return 0; 6936670a6d8SRichard Cochran } 694021f6537SMarc Zyngier 695021f6537SMarc Zyngier static u16 gic_compute_target_list(int *base_cpu, const struct cpumask *mask, 696f6c86a41SJean-Philippe Brucker unsigned long cluster_id) 697021f6537SMarc Zyngier { 698727653d6SJames Morse int next_cpu, cpu = *base_cpu; 699f6c86a41SJean-Philippe Brucker unsigned long mpidr = cpu_logical_map(cpu); 700021f6537SMarc Zyngier u16 tlist = 0; 701021f6537SMarc Zyngier 702021f6537SMarc Zyngier while (cpu < nr_cpu_ids) { 703021f6537SMarc Zyngier tlist |= 1 << (mpidr & 0xf); 704021f6537SMarc Zyngier 705727653d6SJames Morse next_cpu = cpumask_next(cpu, mask); 706727653d6SJames Morse if (next_cpu >= nr_cpu_ids) 707021f6537SMarc Zyngier goto out; 708727653d6SJames Morse cpu = next_cpu; 709021f6537SMarc Zyngier 710021f6537SMarc Zyngier mpidr = cpu_logical_map(cpu); 711021f6537SMarc Zyngier 712eda0d04aSShanker Donthineni if (cluster_id != MPIDR_TO_SGI_CLUSTER_ID(mpidr)) { 713021f6537SMarc Zyngier cpu--; 714021f6537SMarc Zyngier goto out; 715021f6537SMarc Zyngier } 716021f6537SMarc Zyngier } 717021f6537SMarc Zyngier out: 718021f6537SMarc Zyngier *base_cpu = cpu; 719021f6537SMarc Zyngier return tlist; 720021f6537SMarc Zyngier } 721021f6537SMarc Zyngier 7227e580278SAndre Przywara #define MPIDR_TO_SGI_AFFINITY(cluster_id, level) \ 7237e580278SAndre Przywara (MPIDR_AFFINITY_LEVEL(cluster_id, level) \ 7247e580278SAndre Przywara << ICC_SGI1R_AFFINITY_## level ##_SHIFT) 7257e580278SAndre Przywara 726021f6537SMarc Zyngier static void gic_send_sgi(u64 cluster_id, u16 tlist, unsigned int irq) 727021f6537SMarc Zyngier { 728021f6537SMarc Zyngier u64 val; 729021f6537SMarc Zyngier 7307e580278SAndre Przywara val = (MPIDR_TO_SGI_AFFINITY(cluster_id, 3) | 7317e580278SAndre Przywara MPIDR_TO_SGI_AFFINITY(cluster_id, 2) | 7327e580278SAndre Przywara irq << ICC_SGI1R_SGI_ID_SHIFT | 7337e580278SAndre Przywara MPIDR_TO_SGI_AFFINITY(cluster_id, 1) | 734eda0d04aSShanker Donthineni MPIDR_TO_SGI_RS(cluster_id) | 7357e580278SAndre Przywara tlist << ICC_SGI1R_TARGET_LIST_SHIFT); 736021f6537SMarc Zyngier 737b6dd4d83SMark Salter pr_devel("CPU%d: ICC_SGI1R_EL1 %llx\n", smp_processor_id(), val); 738021f6537SMarc Zyngier gic_write_sgi1r(val); 739021f6537SMarc Zyngier } 740021f6537SMarc Zyngier 741021f6537SMarc Zyngier static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) 742021f6537SMarc Zyngier { 743021f6537SMarc Zyngier int cpu; 744021f6537SMarc Zyngier 745021f6537SMarc Zyngier if (WARN_ON(irq >= 16)) 746021f6537SMarc Zyngier return; 747021f6537SMarc Zyngier 748021f6537SMarc Zyngier /* 749021f6537SMarc Zyngier * Ensure that stores to Normal memory are visible to the 750021f6537SMarc Zyngier * other CPUs before issuing the IPI. 751021f6537SMarc Zyngier */ 75221ec30c0SShanker Donthineni wmb(); 753021f6537SMarc Zyngier 754f9b531feSRusty Russell for_each_cpu(cpu, mask) { 755eda0d04aSShanker Donthineni u64 cluster_id = MPIDR_TO_SGI_CLUSTER_ID(cpu_logical_map(cpu)); 756021f6537SMarc Zyngier u16 tlist; 757021f6537SMarc Zyngier 758021f6537SMarc Zyngier tlist = gic_compute_target_list(&cpu, mask, cluster_id); 759021f6537SMarc Zyngier gic_send_sgi(cluster_id, tlist, irq); 760021f6537SMarc Zyngier } 761021f6537SMarc Zyngier 762021f6537SMarc Zyngier /* Force the above writes to ICC_SGI1R_EL1 to be executed */ 763021f6537SMarc Zyngier isb(); 764021f6537SMarc Zyngier } 765021f6537SMarc Zyngier 766021f6537SMarc Zyngier static void gic_smp_init(void) 767021f6537SMarc Zyngier { 768021f6537SMarc Zyngier set_smp_cross_call(gic_raise_softirq); 7696896bcd1SThomas Gleixner cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_GIC_STARTING, 77073c1b41eSThomas Gleixner "irqchip/arm/gicv3:starting", 77173c1b41eSThomas Gleixner gic_starting_cpu, NULL); 772021f6537SMarc Zyngier } 773021f6537SMarc Zyngier 774021f6537SMarc Zyngier static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, 775021f6537SMarc Zyngier bool force) 776021f6537SMarc Zyngier { 77765a30f8bSSuzuki K Poulose unsigned int cpu; 778021f6537SMarc Zyngier void __iomem *reg; 779021f6537SMarc Zyngier int enabled; 780021f6537SMarc Zyngier u64 val; 781021f6537SMarc Zyngier 78265a30f8bSSuzuki K Poulose if (force) 78365a30f8bSSuzuki K Poulose cpu = cpumask_first(mask_val); 78465a30f8bSSuzuki K Poulose else 78565a30f8bSSuzuki K Poulose cpu = cpumask_any_and(mask_val, cpu_online_mask); 78665a30f8bSSuzuki K Poulose 787866d7c1bSSuzuki K Poulose if (cpu >= nr_cpu_ids) 788866d7c1bSSuzuki K Poulose return -EINVAL; 789866d7c1bSSuzuki K Poulose 790021f6537SMarc Zyngier if (gic_irq_in_rdist(d)) 791021f6537SMarc Zyngier return -EINVAL; 792021f6537SMarc Zyngier 793021f6537SMarc Zyngier /* If interrupt was enabled, disable it first */ 794021f6537SMarc Zyngier enabled = gic_peek_irq(d, GICD_ISENABLER); 795021f6537SMarc Zyngier if (enabled) 796021f6537SMarc Zyngier gic_mask_irq(d); 797021f6537SMarc Zyngier 798021f6537SMarc Zyngier reg = gic_dist_base(d) + GICD_IROUTER + (gic_irq(d) * 8); 799021f6537SMarc Zyngier val = gic_mpidr_to_affinity(cpu_logical_map(cpu)); 800021f6537SMarc Zyngier 80172c97126SJean-Philippe Brucker gic_write_irouter(val, reg); 802021f6537SMarc Zyngier 803021f6537SMarc Zyngier /* 804021f6537SMarc Zyngier * If the interrupt was enabled, enabled it again. Otherwise, 805021f6537SMarc Zyngier * just wait for the distributor to have digested our changes. 806021f6537SMarc Zyngier */ 807021f6537SMarc Zyngier if (enabled) 808021f6537SMarc Zyngier gic_unmask_irq(d); 809021f6537SMarc Zyngier else 810021f6537SMarc Zyngier gic_dist_wait_for_rwp(); 811021f6537SMarc Zyngier 812956ae91aSMarc Zyngier irq_data_update_effective_affinity(d, cpumask_of(cpu)); 813956ae91aSMarc Zyngier 8140fc6fa29SAntoine Tenart return IRQ_SET_MASK_OK_DONE; 815021f6537SMarc Zyngier } 816021f6537SMarc Zyngier #else 817021f6537SMarc Zyngier #define gic_set_affinity NULL 818021f6537SMarc Zyngier #define gic_smp_init() do { } while(0) 819021f6537SMarc Zyngier #endif 820021f6537SMarc Zyngier 8213708d52fSSudeep Holla #ifdef CONFIG_CPU_PM 822ccd9432aSSudeep Holla /* Check whether it's single security state view */ 823ccd9432aSSudeep Holla static bool gic_dist_security_disabled(void) 824ccd9432aSSudeep Holla { 825ccd9432aSSudeep Holla return readl_relaxed(gic_data.dist_base + GICD_CTLR) & GICD_CTLR_DS; 826ccd9432aSSudeep Holla } 827ccd9432aSSudeep Holla 8283708d52fSSudeep Holla static int gic_cpu_pm_notifier(struct notifier_block *self, 8293708d52fSSudeep Holla unsigned long cmd, void *v) 8303708d52fSSudeep Holla { 8313708d52fSSudeep Holla if (cmd == CPU_PM_EXIT) { 832ccd9432aSSudeep Holla if (gic_dist_security_disabled()) 8333708d52fSSudeep Holla gic_enable_redist(true); 8343708d52fSSudeep Holla gic_cpu_sys_reg_init(); 835ccd9432aSSudeep Holla } else if (cmd == CPU_PM_ENTER && gic_dist_security_disabled()) { 8363708d52fSSudeep Holla gic_write_grpen1(0); 8373708d52fSSudeep Holla gic_enable_redist(false); 8383708d52fSSudeep Holla } 8393708d52fSSudeep Holla return NOTIFY_OK; 8403708d52fSSudeep Holla } 8413708d52fSSudeep Holla 8423708d52fSSudeep Holla static struct notifier_block gic_cpu_pm_notifier_block = { 8433708d52fSSudeep Holla .notifier_call = gic_cpu_pm_notifier, 8443708d52fSSudeep Holla }; 8453708d52fSSudeep Holla 8463708d52fSSudeep Holla static void gic_cpu_pm_init(void) 8473708d52fSSudeep Holla { 8483708d52fSSudeep Holla cpu_pm_register_notifier(&gic_cpu_pm_notifier_block); 8493708d52fSSudeep Holla } 8503708d52fSSudeep Holla 8513708d52fSSudeep Holla #else 8523708d52fSSudeep Holla static inline void gic_cpu_pm_init(void) { } 8533708d52fSSudeep Holla #endif /* CONFIG_CPU_PM */ 8543708d52fSSudeep Holla 855021f6537SMarc Zyngier static struct irq_chip gic_chip = { 856021f6537SMarc Zyngier .name = "GICv3", 857021f6537SMarc Zyngier .irq_mask = gic_mask_irq, 858021f6537SMarc Zyngier .irq_unmask = gic_unmask_irq, 859021f6537SMarc Zyngier .irq_eoi = gic_eoi_irq, 860021f6537SMarc Zyngier .irq_set_type = gic_set_type, 861021f6537SMarc Zyngier .irq_set_affinity = gic_set_affinity, 862b594c6e2SMarc Zyngier .irq_get_irqchip_state = gic_irq_get_irqchip_state, 863b594c6e2SMarc Zyngier .irq_set_irqchip_state = gic_irq_set_irqchip_state, 86455963c9fSSudeep Holla .flags = IRQCHIP_SET_TYPE_MASKED, 865021f6537SMarc Zyngier }; 866021f6537SMarc Zyngier 8670b6a3da9SMarc Zyngier static struct irq_chip gic_eoimode1_chip = { 8680b6a3da9SMarc Zyngier .name = "GICv3", 8690b6a3da9SMarc Zyngier .irq_mask = gic_eoimode1_mask_irq, 8700b6a3da9SMarc Zyngier .irq_unmask = gic_unmask_irq, 8710b6a3da9SMarc Zyngier .irq_eoi = gic_eoimode1_eoi_irq, 8720b6a3da9SMarc Zyngier .irq_set_type = gic_set_type, 8730b6a3da9SMarc Zyngier .irq_set_affinity = gic_set_affinity, 8740b6a3da9SMarc Zyngier .irq_get_irqchip_state = gic_irq_get_irqchip_state, 8750b6a3da9SMarc Zyngier .irq_set_irqchip_state = gic_irq_set_irqchip_state, 876530bf353SMarc Zyngier .irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity, 8770b6a3da9SMarc Zyngier .flags = IRQCHIP_SET_TYPE_MASKED, 8780b6a3da9SMarc Zyngier }; 8790b6a3da9SMarc Zyngier 880da33f31dSMarc Zyngier #define GIC_ID_NR (1U << gic_data.rdists.id_bits) 881da33f31dSMarc Zyngier 882021f6537SMarc Zyngier static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq, 883021f6537SMarc Zyngier irq_hw_number_t hw) 884021f6537SMarc Zyngier { 8850b6a3da9SMarc Zyngier struct irq_chip *chip = &gic_chip; 8860b6a3da9SMarc Zyngier 887d01d3274SDavidlohr Bueso if (static_branch_likely(&supports_deactivate_key)) 8880b6a3da9SMarc Zyngier chip = &gic_eoimode1_chip; 8890b6a3da9SMarc Zyngier 890021f6537SMarc Zyngier /* SGIs are private to the core kernel */ 891021f6537SMarc Zyngier if (hw < 16) 892021f6537SMarc Zyngier return -EPERM; 893da33f31dSMarc Zyngier /* Nothing here */ 894da33f31dSMarc Zyngier if (hw >= gic_data.irq_nr && hw < 8192) 895da33f31dSMarc Zyngier return -EPERM; 896da33f31dSMarc Zyngier /* Off limits */ 897da33f31dSMarc Zyngier if (hw >= GIC_ID_NR) 898da33f31dSMarc Zyngier return -EPERM; 899da33f31dSMarc Zyngier 900021f6537SMarc Zyngier /* PPIs */ 901021f6537SMarc Zyngier if (hw < 32) { 902021f6537SMarc Zyngier irq_set_percpu_devid(irq); 9030b6a3da9SMarc Zyngier irq_domain_set_info(d, irq, hw, chip, d->host_data, 904443acc4fSMarc Zyngier handle_percpu_devid_irq, NULL, NULL); 905d17cab44SRob Herring irq_set_status_flags(irq, IRQ_NOAUTOEN); 906021f6537SMarc Zyngier } 907021f6537SMarc Zyngier /* SPIs */ 908021f6537SMarc Zyngier if (hw >= 32 && hw < gic_data.irq_nr) { 9090b6a3da9SMarc Zyngier irq_domain_set_info(d, irq, hw, chip, d->host_data, 910443acc4fSMarc Zyngier handle_fasteoi_irq, NULL, NULL); 911d17cab44SRob Herring irq_set_probe(irq); 912956ae91aSMarc Zyngier irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(irq))); 913021f6537SMarc Zyngier } 914da33f31dSMarc Zyngier /* LPIs */ 915da33f31dSMarc Zyngier if (hw >= 8192 && hw < GIC_ID_NR) { 916da33f31dSMarc Zyngier if (!gic_dist_supports_lpis()) 917da33f31dSMarc Zyngier return -EPERM; 9180b6a3da9SMarc Zyngier irq_domain_set_info(d, irq, hw, chip, d->host_data, 919da33f31dSMarc Zyngier handle_fasteoi_irq, NULL, NULL); 920da33f31dSMarc Zyngier } 921da33f31dSMarc Zyngier 922021f6537SMarc Zyngier return 0; 923021f6537SMarc Zyngier } 924021f6537SMarc Zyngier 92565da7d19SMarc Zyngier #define GIC_IRQ_TYPE_PARTITION (GIC_IRQ_TYPE_LPI + 1) 92665da7d19SMarc Zyngier 927f833f57fSMarc Zyngier static int gic_irq_domain_translate(struct irq_domain *d, 928f833f57fSMarc Zyngier struct irq_fwspec *fwspec, 929f833f57fSMarc Zyngier unsigned long *hwirq, 930f833f57fSMarc Zyngier unsigned int *type) 931021f6537SMarc Zyngier { 932f833f57fSMarc Zyngier if (is_of_node(fwspec->fwnode)) { 933f833f57fSMarc Zyngier if (fwspec->param_count < 3) 934021f6537SMarc Zyngier return -EINVAL; 935021f6537SMarc Zyngier 936db8c70ecSMarc Zyngier switch (fwspec->param[0]) { 937db8c70ecSMarc Zyngier case 0: /* SPI */ 938db8c70ecSMarc Zyngier *hwirq = fwspec->param[1] + 32; 939db8c70ecSMarc Zyngier break; 940db8c70ecSMarc Zyngier case 1: /* PPI */ 94165da7d19SMarc Zyngier case GIC_IRQ_TYPE_PARTITION: 942f833f57fSMarc Zyngier *hwirq = fwspec->param[1] + 16; 943db8c70ecSMarc Zyngier break; 944db8c70ecSMarc Zyngier case GIC_IRQ_TYPE_LPI: /* LPI */ 945db8c70ecSMarc Zyngier *hwirq = fwspec->param[1]; 946db8c70ecSMarc Zyngier break; 947db8c70ecSMarc Zyngier default: 948db8c70ecSMarc Zyngier return -EINVAL; 949db8c70ecSMarc Zyngier } 950f833f57fSMarc Zyngier 951f833f57fSMarc Zyngier *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; 9526ef6386eSMarc Zyngier 95365da7d19SMarc Zyngier /* 95465da7d19SMarc Zyngier * Make it clear that broken DTs are... broken. 95565da7d19SMarc Zyngier * Partitionned PPIs are an unfortunate exception. 95665da7d19SMarc Zyngier */ 95765da7d19SMarc Zyngier WARN_ON(*type == IRQ_TYPE_NONE && 95865da7d19SMarc Zyngier fwspec->param[0] != GIC_IRQ_TYPE_PARTITION); 959f833f57fSMarc Zyngier return 0; 960021f6537SMarc Zyngier } 961021f6537SMarc Zyngier 962ffa7d616STomasz Nowicki if (is_fwnode_irqchip(fwspec->fwnode)) { 963ffa7d616STomasz Nowicki if(fwspec->param_count != 2) 964ffa7d616STomasz Nowicki return -EINVAL; 965ffa7d616STomasz Nowicki 966ffa7d616STomasz Nowicki *hwirq = fwspec->param[0]; 967ffa7d616STomasz Nowicki *type = fwspec->param[1]; 9686ef6386eSMarc Zyngier 9696ef6386eSMarc Zyngier WARN_ON(*type == IRQ_TYPE_NONE); 970ffa7d616STomasz Nowicki return 0; 971ffa7d616STomasz Nowicki } 972ffa7d616STomasz Nowicki 973f833f57fSMarc Zyngier return -EINVAL; 974021f6537SMarc Zyngier } 975021f6537SMarc Zyngier 976443acc4fSMarc Zyngier static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, 977443acc4fSMarc Zyngier unsigned int nr_irqs, void *arg) 978443acc4fSMarc Zyngier { 979443acc4fSMarc Zyngier int i, ret; 980443acc4fSMarc Zyngier irq_hw_number_t hwirq; 981443acc4fSMarc Zyngier unsigned int type = IRQ_TYPE_NONE; 982f833f57fSMarc Zyngier struct irq_fwspec *fwspec = arg; 983443acc4fSMarc Zyngier 984f833f57fSMarc Zyngier ret = gic_irq_domain_translate(domain, fwspec, &hwirq, &type); 985443acc4fSMarc Zyngier if (ret) 986443acc4fSMarc Zyngier return ret; 987443acc4fSMarc Zyngier 98863c16c6eSSuzuki K Poulose for (i = 0; i < nr_irqs; i++) { 98963c16c6eSSuzuki K Poulose ret = gic_irq_domain_map(domain, virq + i, hwirq + i); 99063c16c6eSSuzuki K Poulose if (ret) 99163c16c6eSSuzuki K Poulose return ret; 99263c16c6eSSuzuki K Poulose } 993443acc4fSMarc Zyngier 994443acc4fSMarc Zyngier return 0; 995443acc4fSMarc Zyngier } 996443acc4fSMarc Zyngier 997443acc4fSMarc Zyngier static void gic_irq_domain_free(struct irq_domain *domain, unsigned int virq, 998443acc4fSMarc Zyngier unsigned int nr_irqs) 999443acc4fSMarc Zyngier { 1000443acc4fSMarc Zyngier int i; 1001443acc4fSMarc Zyngier 1002443acc4fSMarc Zyngier for (i = 0; i < nr_irqs; i++) { 1003443acc4fSMarc Zyngier struct irq_data *d = irq_domain_get_irq_data(domain, virq + i); 1004443acc4fSMarc Zyngier irq_set_handler(virq + i, NULL); 1005443acc4fSMarc Zyngier irq_domain_reset_irq_data(d); 1006443acc4fSMarc Zyngier } 1007443acc4fSMarc Zyngier } 1008443acc4fSMarc Zyngier 1009e3825ba1SMarc Zyngier static int gic_irq_domain_select(struct irq_domain *d, 1010e3825ba1SMarc Zyngier struct irq_fwspec *fwspec, 1011e3825ba1SMarc Zyngier enum irq_domain_bus_token bus_token) 1012e3825ba1SMarc Zyngier { 1013e3825ba1SMarc Zyngier /* Not for us */ 1014e3825ba1SMarc Zyngier if (fwspec->fwnode != d->fwnode) 1015e3825ba1SMarc Zyngier return 0; 1016e3825ba1SMarc Zyngier 1017e3825ba1SMarc Zyngier /* If this is not DT, then we have a single domain */ 1018e3825ba1SMarc Zyngier if (!is_of_node(fwspec->fwnode)) 1019e3825ba1SMarc Zyngier return 1; 1020e3825ba1SMarc Zyngier 1021e3825ba1SMarc Zyngier /* 1022e3825ba1SMarc Zyngier * If this is a PPI and we have a 4th (non-null) parameter, 1023e3825ba1SMarc Zyngier * then we need to match the partition domain. 1024e3825ba1SMarc Zyngier */ 1025e3825ba1SMarc Zyngier if (fwspec->param_count >= 4 && 1026e3825ba1SMarc Zyngier fwspec->param[0] == 1 && fwspec->param[3] != 0) 1027e3825ba1SMarc Zyngier return d == partition_get_domain(gic_data.ppi_descs[fwspec->param[1]]); 1028e3825ba1SMarc Zyngier 1029e3825ba1SMarc Zyngier return d == gic_data.domain; 1030e3825ba1SMarc Zyngier } 1031e3825ba1SMarc Zyngier 1032021f6537SMarc Zyngier static const struct irq_domain_ops gic_irq_domain_ops = { 1033f833f57fSMarc Zyngier .translate = gic_irq_domain_translate, 1034443acc4fSMarc Zyngier .alloc = gic_irq_domain_alloc, 1035443acc4fSMarc Zyngier .free = gic_irq_domain_free, 1036e3825ba1SMarc Zyngier .select = gic_irq_domain_select, 1037e3825ba1SMarc Zyngier }; 1038e3825ba1SMarc Zyngier 1039e3825ba1SMarc Zyngier static int partition_domain_translate(struct irq_domain *d, 1040e3825ba1SMarc Zyngier struct irq_fwspec *fwspec, 1041e3825ba1SMarc Zyngier unsigned long *hwirq, 1042e3825ba1SMarc Zyngier unsigned int *type) 1043e3825ba1SMarc Zyngier { 1044e3825ba1SMarc Zyngier struct device_node *np; 1045e3825ba1SMarc Zyngier int ret; 1046e3825ba1SMarc Zyngier 1047e3825ba1SMarc Zyngier np = of_find_node_by_phandle(fwspec->param[3]); 1048e3825ba1SMarc Zyngier if (WARN_ON(!np)) 1049e3825ba1SMarc Zyngier return -EINVAL; 1050e3825ba1SMarc Zyngier 1051e3825ba1SMarc Zyngier ret = partition_translate_id(gic_data.ppi_descs[fwspec->param[1]], 1052e3825ba1SMarc Zyngier of_node_to_fwnode(np)); 1053e3825ba1SMarc Zyngier if (ret < 0) 1054e3825ba1SMarc Zyngier return ret; 1055e3825ba1SMarc Zyngier 1056e3825ba1SMarc Zyngier *hwirq = ret; 1057e3825ba1SMarc Zyngier *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; 1058e3825ba1SMarc Zyngier 1059e3825ba1SMarc Zyngier return 0; 1060e3825ba1SMarc Zyngier } 1061e3825ba1SMarc Zyngier 1062e3825ba1SMarc Zyngier static const struct irq_domain_ops partition_domain_ops = { 1063e3825ba1SMarc Zyngier .translate = partition_domain_translate, 1064e3825ba1SMarc Zyngier .select = gic_irq_domain_select, 1065021f6537SMarc Zyngier }; 1066021f6537SMarc Zyngier 1067db57d746STomasz Nowicki static int __init gic_init_bases(void __iomem *dist_base, 1068db57d746STomasz Nowicki struct redist_region *rdist_regs, 1069db57d746STomasz Nowicki u32 nr_redist_regions, 1070db57d746STomasz Nowicki u64 redist_stride, 1071db57d746STomasz Nowicki struct fwnode_handle *handle) 1072db57d746STomasz Nowicki { 1073db57d746STomasz Nowicki u32 typer; 1074db57d746STomasz Nowicki int gic_irqs; 1075db57d746STomasz Nowicki int err; 1076db57d746STomasz Nowicki 1077db57d746STomasz Nowicki if (!is_hyp_mode_available()) 1078d01d3274SDavidlohr Bueso static_branch_disable(&supports_deactivate_key); 1079db57d746STomasz Nowicki 1080d01d3274SDavidlohr Bueso if (static_branch_likely(&supports_deactivate_key)) 1081db57d746STomasz Nowicki pr_info("GIC: Using split EOI/Deactivate mode\n"); 1082db57d746STomasz Nowicki 1083e3825ba1SMarc Zyngier gic_data.fwnode = handle; 1084db57d746STomasz Nowicki gic_data.dist_base = dist_base; 1085db57d746STomasz Nowicki gic_data.redist_regions = rdist_regs; 1086db57d746STomasz Nowicki gic_data.nr_redist_regions = nr_redist_regions; 1087db57d746STomasz Nowicki gic_data.redist_stride = redist_stride; 1088db57d746STomasz Nowicki 1089db57d746STomasz Nowicki /* 1090db57d746STomasz Nowicki * Find out how many interrupts are supported. 1091db57d746STomasz Nowicki * The GIC only supports up to 1020 interrupt sources (SGI+PPI+SPI) 1092db57d746STomasz Nowicki */ 1093db57d746STomasz Nowicki typer = readl_relaxed(gic_data.dist_base + GICD_TYPER); 1094db57d746STomasz Nowicki gic_data.rdists.id_bits = GICD_TYPER_ID_BITS(typer); 1095db57d746STomasz Nowicki gic_irqs = GICD_TYPER_IRQS(typer); 1096db57d746STomasz Nowicki if (gic_irqs > 1020) 1097db57d746STomasz Nowicki gic_irqs = 1020; 1098db57d746STomasz Nowicki gic_data.irq_nr = gic_irqs; 1099db57d746STomasz Nowicki 1100db57d746STomasz Nowicki gic_data.domain = irq_domain_create_tree(handle, &gic_irq_domain_ops, 1101db57d746STomasz Nowicki &gic_data); 1102b2425b51SMarc Zyngier irq_domain_update_bus_token(gic_data.domain, DOMAIN_BUS_WIRED); 1103db57d746STomasz Nowicki gic_data.rdists.rdist = alloc_percpu(typeof(*gic_data.rdists.rdist)); 11040edc23eaSMarc Zyngier gic_data.rdists.has_vlpis = true; 11050edc23eaSMarc Zyngier gic_data.rdists.has_direct_lpi = true; 1106db57d746STomasz Nowicki 1107db57d746STomasz Nowicki if (WARN_ON(!gic_data.domain) || WARN_ON(!gic_data.rdists.rdist)) { 1108db57d746STomasz Nowicki err = -ENOMEM; 1109db57d746STomasz Nowicki goto out_free; 1110db57d746STomasz Nowicki } 1111db57d746STomasz Nowicki 1112eda0d04aSShanker Donthineni gic_data.has_rss = !!(typer & GICD_TYPER_RSS); 1113eda0d04aSShanker Donthineni pr_info("Distributor has %sRange Selector support\n", 1114eda0d04aSShanker Donthineni gic_data.has_rss ? "" : "no "); 1115eda0d04aSShanker Donthineni 111650528752SMarc Zyngier if (typer & GICD_TYPER_MBIS) { 111750528752SMarc Zyngier err = mbi_init(handle, gic_data.domain); 111850528752SMarc Zyngier if (err) 111950528752SMarc Zyngier pr_err("Failed to initialize MBIs\n"); 112050528752SMarc Zyngier } 112150528752SMarc Zyngier 1122db57d746STomasz Nowicki set_handle_irq(gic_handle_irq); 1123db57d746STomasz Nowicki 11240edc23eaSMarc Zyngier gic_update_vlpi_properties(); 11250edc23eaSMarc Zyngier 1126db40f0a7STomasz Nowicki if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis()) 1127db40f0a7STomasz Nowicki its_init(handle, &gic_data.rdists, gic_data.domain); 1128db57d746STomasz Nowicki 1129db57d746STomasz Nowicki gic_smp_init(); 1130db57d746STomasz Nowicki gic_dist_init(); 1131db57d746STomasz Nowicki gic_cpu_init(); 1132db57d746STomasz Nowicki gic_cpu_pm_init(); 1133db57d746STomasz Nowicki 1134db57d746STomasz Nowicki return 0; 1135db57d746STomasz Nowicki 1136db57d746STomasz Nowicki out_free: 1137db57d746STomasz Nowicki if (gic_data.domain) 1138db57d746STomasz Nowicki irq_domain_remove(gic_data.domain); 1139db57d746STomasz Nowicki free_percpu(gic_data.rdists.rdist); 1140db57d746STomasz Nowicki return err; 1141db57d746STomasz Nowicki } 1142db57d746STomasz Nowicki 1143db57d746STomasz Nowicki static int __init gic_validate_dist_version(void __iomem *dist_base) 1144db57d746STomasz Nowicki { 1145db57d746STomasz Nowicki u32 reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK; 1146db57d746STomasz Nowicki 1147db57d746STomasz Nowicki if (reg != GIC_PIDR2_ARCH_GICv3 && reg != GIC_PIDR2_ARCH_GICv4) 1148db57d746STomasz Nowicki return -ENODEV; 1149db57d746STomasz Nowicki 1150db57d746STomasz Nowicki return 0; 1151db57d746STomasz Nowicki } 1152db57d746STomasz Nowicki 1153e3825ba1SMarc Zyngier /* Create all possible partitions at boot time */ 11547beaa24bSLinus Torvalds static void __init gic_populate_ppi_partitions(struct device_node *gic_node) 1155e3825ba1SMarc Zyngier { 1156e3825ba1SMarc Zyngier struct device_node *parts_node, *child_part; 1157e3825ba1SMarc Zyngier int part_idx = 0, i; 1158e3825ba1SMarc Zyngier int nr_parts; 1159e3825ba1SMarc Zyngier struct partition_affinity *parts; 1160e3825ba1SMarc Zyngier 116100ee9a1cSJohan Hovold parts_node = of_get_child_by_name(gic_node, "ppi-partitions"); 1162e3825ba1SMarc Zyngier if (!parts_node) 1163e3825ba1SMarc Zyngier return; 1164e3825ba1SMarc Zyngier 1165e3825ba1SMarc Zyngier nr_parts = of_get_child_count(parts_node); 1166e3825ba1SMarc Zyngier 1167e3825ba1SMarc Zyngier if (!nr_parts) 116800ee9a1cSJohan Hovold goto out_put_node; 1169e3825ba1SMarc Zyngier 1170e3825ba1SMarc Zyngier parts = kzalloc(sizeof(*parts) * nr_parts, GFP_KERNEL); 1171e3825ba1SMarc Zyngier if (WARN_ON(!parts)) 117200ee9a1cSJohan Hovold goto out_put_node; 1173e3825ba1SMarc Zyngier 1174e3825ba1SMarc Zyngier for_each_child_of_node(parts_node, child_part) { 1175e3825ba1SMarc Zyngier struct partition_affinity *part; 1176e3825ba1SMarc Zyngier int n; 1177e3825ba1SMarc Zyngier 1178e3825ba1SMarc Zyngier part = &parts[part_idx]; 1179e3825ba1SMarc Zyngier 1180e3825ba1SMarc Zyngier part->partition_id = of_node_to_fwnode(child_part); 1181e3825ba1SMarc Zyngier 1182e3825ba1SMarc Zyngier pr_info("GIC: PPI partition %s[%d] { ", 1183e3825ba1SMarc Zyngier child_part->name, part_idx); 1184e3825ba1SMarc Zyngier 1185e3825ba1SMarc Zyngier n = of_property_count_elems_of_size(child_part, "affinity", 1186e3825ba1SMarc Zyngier sizeof(u32)); 1187e3825ba1SMarc Zyngier WARN_ON(n <= 0); 1188e3825ba1SMarc Zyngier 1189e3825ba1SMarc Zyngier for (i = 0; i < n; i++) { 1190e3825ba1SMarc Zyngier int err, cpu; 1191e3825ba1SMarc Zyngier u32 cpu_phandle; 1192e3825ba1SMarc Zyngier struct device_node *cpu_node; 1193e3825ba1SMarc Zyngier 1194e3825ba1SMarc Zyngier err = of_property_read_u32_index(child_part, "affinity", 1195e3825ba1SMarc Zyngier i, &cpu_phandle); 1196e3825ba1SMarc Zyngier if (WARN_ON(err)) 1197e3825ba1SMarc Zyngier continue; 1198e3825ba1SMarc Zyngier 1199e3825ba1SMarc Zyngier cpu_node = of_find_node_by_phandle(cpu_phandle); 1200e3825ba1SMarc Zyngier if (WARN_ON(!cpu_node)) 1201e3825ba1SMarc Zyngier continue; 1202e3825ba1SMarc Zyngier 1203c08ec7daSSuzuki K Poulose cpu = of_cpu_node_to_id(cpu_node); 1204c08ec7daSSuzuki K Poulose if (WARN_ON(cpu < 0)) 1205e3825ba1SMarc Zyngier continue; 1206e3825ba1SMarc Zyngier 1207e81f54c6SRob Herring pr_cont("%pOF[%d] ", cpu_node, cpu); 1208e3825ba1SMarc Zyngier 1209e3825ba1SMarc Zyngier cpumask_set_cpu(cpu, &part->mask); 1210e3825ba1SMarc Zyngier } 1211e3825ba1SMarc Zyngier 1212e3825ba1SMarc Zyngier pr_cont("}\n"); 1213e3825ba1SMarc Zyngier part_idx++; 1214e3825ba1SMarc Zyngier } 1215e3825ba1SMarc Zyngier 1216e3825ba1SMarc Zyngier for (i = 0; i < 16; i++) { 1217e3825ba1SMarc Zyngier unsigned int irq; 1218e3825ba1SMarc Zyngier struct partition_desc *desc; 1219e3825ba1SMarc Zyngier struct irq_fwspec ppi_fwspec = { 1220e3825ba1SMarc Zyngier .fwnode = gic_data.fwnode, 1221e3825ba1SMarc Zyngier .param_count = 3, 1222e3825ba1SMarc Zyngier .param = { 122365da7d19SMarc Zyngier [0] = GIC_IRQ_TYPE_PARTITION, 1224e3825ba1SMarc Zyngier [1] = i, 1225e3825ba1SMarc Zyngier [2] = IRQ_TYPE_NONE, 1226e3825ba1SMarc Zyngier }, 1227e3825ba1SMarc Zyngier }; 1228e3825ba1SMarc Zyngier 1229e3825ba1SMarc Zyngier irq = irq_create_fwspec_mapping(&ppi_fwspec); 1230e3825ba1SMarc Zyngier if (WARN_ON(!irq)) 1231e3825ba1SMarc Zyngier continue; 1232e3825ba1SMarc Zyngier desc = partition_create_desc(gic_data.fwnode, parts, nr_parts, 1233e3825ba1SMarc Zyngier irq, &partition_domain_ops); 1234e3825ba1SMarc Zyngier if (WARN_ON(!desc)) 1235e3825ba1SMarc Zyngier continue; 1236e3825ba1SMarc Zyngier 1237e3825ba1SMarc Zyngier gic_data.ppi_descs[i] = desc; 1238e3825ba1SMarc Zyngier } 123900ee9a1cSJohan Hovold 124000ee9a1cSJohan Hovold out_put_node: 124100ee9a1cSJohan Hovold of_node_put(parts_node); 1242e3825ba1SMarc Zyngier } 1243e3825ba1SMarc Zyngier 12441839e576SJulien Grall static void __init gic_of_setup_kvm_info(struct device_node *node) 12451839e576SJulien Grall { 12461839e576SJulien Grall int ret; 12471839e576SJulien Grall struct resource r; 12481839e576SJulien Grall u32 gicv_idx; 12491839e576SJulien Grall 12501839e576SJulien Grall gic_v3_kvm_info.type = GIC_V3; 12511839e576SJulien Grall 12521839e576SJulien Grall gic_v3_kvm_info.maint_irq = irq_of_parse_and_map(node, 0); 12531839e576SJulien Grall if (!gic_v3_kvm_info.maint_irq) 12541839e576SJulien Grall return; 12551839e576SJulien Grall 12561839e576SJulien Grall if (of_property_read_u32(node, "#redistributor-regions", 12571839e576SJulien Grall &gicv_idx)) 12581839e576SJulien Grall gicv_idx = 1; 12591839e576SJulien Grall 12601839e576SJulien Grall gicv_idx += 3; /* Also skip GICD, GICC, GICH */ 12611839e576SJulien Grall ret = of_address_to_resource(node, gicv_idx, &r); 12621839e576SJulien Grall if (!ret) 12631839e576SJulien Grall gic_v3_kvm_info.vcpu = r; 12641839e576SJulien Grall 12654bdf5025SMarc Zyngier gic_v3_kvm_info.has_v4 = gic_data.rdists.has_vlpis; 12661839e576SJulien Grall gic_set_kvm_info(&gic_v3_kvm_info); 12671839e576SJulien Grall } 12681839e576SJulien Grall 1269021f6537SMarc Zyngier static int __init gic_of_init(struct device_node *node, struct device_node *parent) 1270021f6537SMarc Zyngier { 1271021f6537SMarc Zyngier void __iomem *dist_base; 1272f5c1434cSMarc Zyngier struct redist_region *rdist_regs; 1273021f6537SMarc Zyngier u64 redist_stride; 1274f5c1434cSMarc Zyngier u32 nr_redist_regions; 1275db57d746STomasz Nowicki int err, i; 1276021f6537SMarc Zyngier 1277021f6537SMarc Zyngier dist_base = of_iomap(node, 0); 1278021f6537SMarc Zyngier if (!dist_base) { 1279e81f54c6SRob Herring pr_err("%pOF: unable to map gic dist registers\n", node); 1280021f6537SMarc Zyngier return -ENXIO; 1281021f6537SMarc Zyngier } 1282021f6537SMarc Zyngier 1283db57d746STomasz Nowicki err = gic_validate_dist_version(dist_base); 1284db57d746STomasz Nowicki if (err) { 1285e81f54c6SRob Herring pr_err("%pOF: no distributor detected, giving up\n", node); 1286021f6537SMarc Zyngier goto out_unmap_dist; 1287021f6537SMarc Zyngier } 1288021f6537SMarc Zyngier 1289f5c1434cSMarc Zyngier if (of_property_read_u32(node, "#redistributor-regions", &nr_redist_regions)) 1290f5c1434cSMarc Zyngier nr_redist_regions = 1; 1291021f6537SMarc Zyngier 1292f5c1434cSMarc Zyngier rdist_regs = kzalloc(sizeof(*rdist_regs) * nr_redist_regions, GFP_KERNEL); 1293f5c1434cSMarc Zyngier if (!rdist_regs) { 1294021f6537SMarc Zyngier err = -ENOMEM; 1295021f6537SMarc Zyngier goto out_unmap_dist; 1296021f6537SMarc Zyngier } 1297021f6537SMarc Zyngier 1298f5c1434cSMarc Zyngier for (i = 0; i < nr_redist_regions; i++) { 1299f5c1434cSMarc Zyngier struct resource res; 1300f5c1434cSMarc Zyngier int ret; 1301f5c1434cSMarc Zyngier 1302f5c1434cSMarc Zyngier ret = of_address_to_resource(node, 1 + i, &res); 1303f5c1434cSMarc Zyngier rdist_regs[i].redist_base = of_iomap(node, 1 + i); 1304f5c1434cSMarc Zyngier if (ret || !rdist_regs[i].redist_base) { 1305e81f54c6SRob Herring pr_err("%pOF: couldn't map region %d\n", node, i); 1306021f6537SMarc Zyngier err = -ENODEV; 1307021f6537SMarc Zyngier goto out_unmap_rdist; 1308021f6537SMarc Zyngier } 1309f5c1434cSMarc Zyngier rdist_regs[i].phys_base = res.start; 1310021f6537SMarc Zyngier } 1311021f6537SMarc Zyngier 1312021f6537SMarc Zyngier if (of_property_read_u64(node, "redistributor-stride", &redist_stride)) 1313021f6537SMarc Zyngier redist_stride = 0; 1314021f6537SMarc Zyngier 1315db57d746STomasz Nowicki err = gic_init_bases(dist_base, rdist_regs, nr_redist_regions, 1316db57d746STomasz Nowicki redist_stride, &node->fwnode); 1317e3825ba1SMarc Zyngier if (err) 1318e3825ba1SMarc Zyngier goto out_unmap_rdist; 1319e3825ba1SMarc Zyngier 1320e3825ba1SMarc Zyngier gic_populate_ppi_partitions(node); 1321d33a3c8cSChristoffer Dall 1322d01d3274SDavidlohr Bueso if (static_branch_likely(&supports_deactivate_key)) 13231839e576SJulien Grall gic_of_setup_kvm_info(node); 1324021f6537SMarc Zyngier return 0; 1325021f6537SMarc Zyngier 1326021f6537SMarc Zyngier out_unmap_rdist: 1327f5c1434cSMarc Zyngier for (i = 0; i < nr_redist_regions; i++) 1328f5c1434cSMarc Zyngier if (rdist_regs[i].redist_base) 1329f5c1434cSMarc Zyngier iounmap(rdist_regs[i].redist_base); 1330f5c1434cSMarc Zyngier kfree(rdist_regs); 1331021f6537SMarc Zyngier out_unmap_dist: 1332021f6537SMarc Zyngier iounmap(dist_base); 1333021f6537SMarc Zyngier return err; 1334021f6537SMarc Zyngier } 1335021f6537SMarc Zyngier 1336021f6537SMarc Zyngier IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init); 1337ffa7d616STomasz Nowicki 1338ffa7d616STomasz Nowicki #ifdef CONFIG_ACPI 1339611f039fSJulien Grall static struct 1340611f039fSJulien Grall { 1341611f039fSJulien Grall void __iomem *dist_base; 1342611f039fSJulien Grall struct redist_region *redist_regs; 1343611f039fSJulien Grall u32 nr_redist_regions; 1344611f039fSJulien Grall bool single_redist; 13451839e576SJulien Grall u32 maint_irq; 13461839e576SJulien Grall int maint_irq_mode; 13471839e576SJulien Grall phys_addr_t vcpu_base; 1348611f039fSJulien Grall } acpi_data __initdata; 1349b70fb7afSTomasz Nowicki 1350b70fb7afSTomasz Nowicki static void __init 1351b70fb7afSTomasz Nowicki gic_acpi_register_redist(phys_addr_t phys_base, void __iomem *redist_base) 1352b70fb7afSTomasz Nowicki { 1353b70fb7afSTomasz Nowicki static int count = 0; 1354b70fb7afSTomasz Nowicki 1355611f039fSJulien Grall acpi_data.redist_regs[count].phys_base = phys_base; 1356611f039fSJulien Grall acpi_data.redist_regs[count].redist_base = redist_base; 1357611f039fSJulien Grall acpi_data.redist_regs[count].single_redist = acpi_data.single_redist; 1358b70fb7afSTomasz Nowicki count++; 1359b70fb7afSTomasz Nowicki } 1360ffa7d616STomasz Nowicki 1361ffa7d616STomasz Nowicki static int __init 1362ffa7d616STomasz Nowicki gic_acpi_parse_madt_redist(struct acpi_subtable_header *header, 1363ffa7d616STomasz Nowicki const unsigned long end) 1364ffa7d616STomasz Nowicki { 1365ffa7d616STomasz Nowicki struct acpi_madt_generic_redistributor *redist = 1366ffa7d616STomasz Nowicki (struct acpi_madt_generic_redistributor *)header; 1367ffa7d616STomasz Nowicki void __iomem *redist_base; 1368ffa7d616STomasz Nowicki 1369ffa7d616STomasz Nowicki redist_base = ioremap(redist->base_address, redist->length); 1370ffa7d616STomasz Nowicki if (!redist_base) { 1371ffa7d616STomasz Nowicki pr_err("Couldn't map GICR region @%llx\n", redist->base_address); 1372ffa7d616STomasz Nowicki return -ENOMEM; 1373ffa7d616STomasz Nowicki } 1374ffa7d616STomasz Nowicki 1375b70fb7afSTomasz Nowicki gic_acpi_register_redist(redist->base_address, redist_base); 1376ffa7d616STomasz Nowicki return 0; 1377ffa7d616STomasz Nowicki } 1378ffa7d616STomasz Nowicki 1379b70fb7afSTomasz Nowicki static int __init 1380b70fb7afSTomasz Nowicki gic_acpi_parse_madt_gicc(struct acpi_subtable_header *header, 1381b70fb7afSTomasz Nowicki const unsigned long end) 1382b70fb7afSTomasz Nowicki { 1383b70fb7afSTomasz Nowicki struct acpi_madt_generic_interrupt *gicc = 1384b70fb7afSTomasz Nowicki (struct acpi_madt_generic_interrupt *)header; 1385611f039fSJulien Grall u32 reg = readl_relaxed(acpi_data.dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK; 1386b70fb7afSTomasz Nowicki u32 size = reg == GIC_PIDR2_ARCH_GICv4 ? SZ_64K * 4 : SZ_64K * 2; 1387b70fb7afSTomasz Nowicki void __iomem *redist_base; 1388b70fb7afSTomasz Nowicki 1389ebe2f871SShanker Donthineni /* GICC entry which has !ACPI_MADT_ENABLED is not unusable so skip */ 1390ebe2f871SShanker Donthineni if (!(gicc->flags & ACPI_MADT_ENABLED)) 1391ebe2f871SShanker Donthineni return 0; 1392ebe2f871SShanker Donthineni 1393b70fb7afSTomasz Nowicki redist_base = ioremap(gicc->gicr_base_address, size); 1394b70fb7afSTomasz Nowicki if (!redist_base) 1395b70fb7afSTomasz Nowicki return -ENOMEM; 1396b70fb7afSTomasz Nowicki 1397b70fb7afSTomasz Nowicki gic_acpi_register_redist(gicc->gicr_base_address, redist_base); 1398b70fb7afSTomasz Nowicki return 0; 1399b70fb7afSTomasz Nowicki } 1400b70fb7afSTomasz Nowicki 1401b70fb7afSTomasz Nowicki static int __init gic_acpi_collect_gicr_base(void) 1402b70fb7afSTomasz Nowicki { 1403b70fb7afSTomasz Nowicki acpi_tbl_entry_handler redist_parser; 1404b70fb7afSTomasz Nowicki enum acpi_madt_type type; 1405b70fb7afSTomasz Nowicki 1406611f039fSJulien Grall if (acpi_data.single_redist) { 1407b70fb7afSTomasz Nowicki type = ACPI_MADT_TYPE_GENERIC_INTERRUPT; 1408b70fb7afSTomasz Nowicki redist_parser = gic_acpi_parse_madt_gicc; 1409b70fb7afSTomasz Nowicki } else { 1410b70fb7afSTomasz Nowicki type = ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR; 1411b70fb7afSTomasz Nowicki redist_parser = gic_acpi_parse_madt_redist; 1412b70fb7afSTomasz Nowicki } 1413b70fb7afSTomasz Nowicki 1414b70fb7afSTomasz Nowicki /* Collect redistributor base addresses in GICR entries */ 1415b70fb7afSTomasz Nowicki if (acpi_table_parse_madt(type, redist_parser, 0) > 0) 1416b70fb7afSTomasz Nowicki return 0; 1417b70fb7afSTomasz Nowicki 1418b70fb7afSTomasz Nowicki pr_info("No valid GICR entries exist\n"); 1419b70fb7afSTomasz Nowicki return -ENODEV; 1420b70fb7afSTomasz Nowicki } 1421b70fb7afSTomasz Nowicki 1422ffa7d616STomasz Nowicki static int __init gic_acpi_match_gicr(struct acpi_subtable_header *header, 1423ffa7d616STomasz Nowicki const unsigned long end) 1424ffa7d616STomasz Nowicki { 1425ffa7d616STomasz Nowicki /* Subtable presence means that redist exists, that's it */ 1426ffa7d616STomasz Nowicki return 0; 1427ffa7d616STomasz Nowicki } 1428ffa7d616STomasz Nowicki 1429b70fb7afSTomasz Nowicki static int __init gic_acpi_match_gicc(struct acpi_subtable_header *header, 1430b70fb7afSTomasz Nowicki const unsigned long end) 1431b70fb7afSTomasz Nowicki { 1432b70fb7afSTomasz Nowicki struct acpi_madt_generic_interrupt *gicc = 1433b70fb7afSTomasz Nowicki (struct acpi_madt_generic_interrupt *)header; 1434b70fb7afSTomasz Nowicki 1435b70fb7afSTomasz Nowicki /* 1436b70fb7afSTomasz Nowicki * If GICC is enabled and has valid gicr base address, then it means 1437b70fb7afSTomasz Nowicki * GICR base is presented via GICC 1438b70fb7afSTomasz Nowicki */ 1439b70fb7afSTomasz Nowicki if ((gicc->flags & ACPI_MADT_ENABLED) && gicc->gicr_base_address) 1440b70fb7afSTomasz Nowicki return 0; 1441b70fb7afSTomasz Nowicki 1442ebe2f871SShanker Donthineni /* 1443ebe2f871SShanker Donthineni * It's perfectly valid firmware can pass disabled GICC entry, driver 1444ebe2f871SShanker Donthineni * should not treat as errors, skip the entry instead of probe fail. 1445ebe2f871SShanker Donthineni */ 1446ebe2f871SShanker Donthineni if (!(gicc->flags & ACPI_MADT_ENABLED)) 1447ebe2f871SShanker Donthineni return 0; 1448ebe2f871SShanker Donthineni 1449b70fb7afSTomasz Nowicki return -ENODEV; 1450b70fb7afSTomasz Nowicki } 1451b70fb7afSTomasz Nowicki 1452b70fb7afSTomasz Nowicki static int __init gic_acpi_count_gicr_regions(void) 1453b70fb7afSTomasz Nowicki { 1454b70fb7afSTomasz Nowicki int count; 1455b70fb7afSTomasz Nowicki 1456b70fb7afSTomasz Nowicki /* 1457b70fb7afSTomasz Nowicki * Count how many redistributor regions we have. It is not allowed 1458b70fb7afSTomasz Nowicki * to mix redistributor description, GICR and GICC subtables have to be 1459b70fb7afSTomasz Nowicki * mutually exclusive. 1460b70fb7afSTomasz Nowicki */ 1461b70fb7afSTomasz Nowicki count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR, 1462b70fb7afSTomasz Nowicki gic_acpi_match_gicr, 0); 1463b70fb7afSTomasz Nowicki if (count > 0) { 1464611f039fSJulien Grall acpi_data.single_redist = false; 1465b70fb7afSTomasz Nowicki return count; 1466b70fb7afSTomasz Nowicki } 1467b70fb7afSTomasz Nowicki 1468b70fb7afSTomasz Nowicki count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT, 1469b70fb7afSTomasz Nowicki gic_acpi_match_gicc, 0); 1470b70fb7afSTomasz Nowicki if (count > 0) 1471611f039fSJulien Grall acpi_data.single_redist = true; 1472b70fb7afSTomasz Nowicki 1473b70fb7afSTomasz Nowicki return count; 1474b70fb7afSTomasz Nowicki } 1475b70fb7afSTomasz Nowicki 1476ffa7d616STomasz Nowicki static bool __init acpi_validate_gic_table(struct acpi_subtable_header *header, 1477ffa7d616STomasz Nowicki struct acpi_probe_entry *ape) 1478ffa7d616STomasz Nowicki { 1479ffa7d616STomasz Nowicki struct acpi_madt_generic_distributor *dist; 1480ffa7d616STomasz Nowicki int count; 1481ffa7d616STomasz Nowicki 1482ffa7d616STomasz Nowicki dist = (struct acpi_madt_generic_distributor *)header; 1483ffa7d616STomasz Nowicki if (dist->version != ape->driver_data) 1484ffa7d616STomasz Nowicki return false; 1485ffa7d616STomasz Nowicki 1486ffa7d616STomasz Nowicki /* We need to do that exercise anyway, the sooner the better */ 1487b70fb7afSTomasz Nowicki count = gic_acpi_count_gicr_regions(); 1488ffa7d616STomasz Nowicki if (count <= 0) 1489ffa7d616STomasz Nowicki return false; 1490ffa7d616STomasz Nowicki 1491611f039fSJulien Grall acpi_data.nr_redist_regions = count; 1492ffa7d616STomasz Nowicki return true; 1493ffa7d616STomasz Nowicki } 1494ffa7d616STomasz Nowicki 14951839e576SJulien Grall static int __init gic_acpi_parse_virt_madt_gicc(struct acpi_subtable_header *header, 14961839e576SJulien Grall const unsigned long end) 14971839e576SJulien Grall { 14981839e576SJulien Grall struct acpi_madt_generic_interrupt *gicc = 14991839e576SJulien Grall (struct acpi_madt_generic_interrupt *)header; 15001839e576SJulien Grall int maint_irq_mode; 15011839e576SJulien Grall static int first_madt = true; 15021839e576SJulien Grall 15031839e576SJulien Grall /* Skip unusable CPUs */ 15041839e576SJulien Grall if (!(gicc->flags & ACPI_MADT_ENABLED)) 15051839e576SJulien Grall return 0; 15061839e576SJulien Grall 15071839e576SJulien Grall maint_irq_mode = (gicc->flags & ACPI_MADT_VGIC_IRQ_MODE) ? 15081839e576SJulien Grall ACPI_EDGE_SENSITIVE : ACPI_LEVEL_SENSITIVE; 15091839e576SJulien Grall 15101839e576SJulien Grall if (first_madt) { 15111839e576SJulien Grall first_madt = false; 15121839e576SJulien Grall 15131839e576SJulien Grall acpi_data.maint_irq = gicc->vgic_interrupt; 15141839e576SJulien Grall acpi_data.maint_irq_mode = maint_irq_mode; 15151839e576SJulien Grall acpi_data.vcpu_base = gicc->gicv_base_address; 15161839e576SJulien Grall 15171839e576SJulien Grall return 0; 15181839e576SJulien Grall } 15191839e576SJulien Grall 15201839e576SJulien Grall /* 15211839e576SJulien Grall * The maintenance interrupt and GICV should be the same for every CPU 15221839e576SJulien Grall */ 15231839e576SJulien Grall if ((acpi_data.maint_irq != gicc->vgic_interrupt) || 15241839e576SJulien Grall (acpi_data.maint_irq_mode != maint_irq_mode) || 15251839e576SJulien Grall (acpi_data.vcpu_base != gicc->gicv_base_address)) 15261839e576SJulien Grall return -EINVAL; 15271839e576SJulien Grall 15281839e576SJulien Grall return 0; 15291839e576SJulien Grall } 15301839e576SJulien Grall 15311839e576SJulien Grall static bool __init gic_acpi_collect_virt_info(void) 15321839e576SJulien Grall { 15331839e576SJulien Grall int count; 15341839e576SJulien Grall 15351839e576SJulien Grall count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT, 15361839e576SJulien Grall gic_acpi_parse_virt_madt_gicc, 0); 15371839e576SJulien Grall 15381839e576SJulien Grall return (count > 0); 15391839e576SJulien Grall } 15401839e576SJulien Grall 1541ffa7d616STomasz Nowicki #define ACPI_GICV3_DIST_MEM_SIZE (SZ_64K) 15421839e576SJulien Grall #define ACPI_GICV2_VCTRL_MEM_SIZE (SZ_4K) 15431839e576SJulien Grall #define ACPI_GICV2_VCPU_MEM_SIZE (SZ_8K) 15441839e576SJulien Grall 15451839e576SJulien Grall static void __init gic_acpi_setup_kvm_info(void) 15461839e576SJulien Grall { 15471839e576SJulien Grall int irq; 15481839e576SJulien Grall 15491839e576SJulien Grall if (!gic_acpi_collect_virt_info()) { 15501839e576SJulien Grall pr_warn("Unable to get hardware information used for virtualization\n"); 15511839e576SJulien Grall return; 15521839e576SJulien Grall } 15531839e576SJulien Grall 15541839e576SJulien Grall gic_v3_kvm_info.type = GIC_V3; 15551839e576SJulien Grall 15561839e576SJulien Grall irq = acpi_register_gsi(NULL, acpi_data.maint_irq, 15571839e576SJulien Grall acpi_data.maint_irq_mode, 15581839e576SJulien Grall ACPI_ACTIVE_HIGH); 15591839e576SJulien Grall if (irq <= 0) 15601839e576SJulien Grall return; 15611839e576SJulien Grall 15621839e576SJulien Grall gic_v3_kvm_info.maint_irq = irq; 15631839e576SJulien Grall 15641839e576SJulien Grall if (acpi_data.vcpu_base) { 15651839e576SJulien Grall struct resource *vcpu = &gic_v3_kvm_info.vcpu; 15661839e576SJulien Grall 15671839e576SJulien Grall vcpu->flags = IORESOURCE_MEM; 15681839e576SJulien Grall vcpu->start = acpi_data.vcpu_base; 15691839e576SJulien Grall vcpu->end = vcpu->start + ACPI_GICV2_VCPU_MEM_SIZE - 1; 15701839e576SJulien Grall } 15711839e576SJulien Grall 15724bdf5025SMarc Zyngier gic_v3_kvm_info.has_v4 = gic_data.rdists.has_vlpis; 15731839e576SJulien Grall gic_set_kvm_info(&gic_v3_kvm_info); 15741839e576SJulien Grall } 1575ffa7d616STomasz Nowicki 1576ffa7d616STomasz Nowicki static int __init 1577ffa7d616STomasz Nowicki gic_acpi_init(struct acpi_subtable_header *header, const unsigned long end) 1578ffa7d616STomasz Nowicki { 1579ffa7d616STomasz Nowicki struct acpi_madt_generic_distributor *dist; 1580ffa7d616STomasz Nowicki struct fwnode_handle *domain_handle; 1581611f039fSJulien Grall size_t size; 1582b70fb7afSTomasz Nowicki int i, err; 1583ffa7d616STomasz Nowicki 1584ffa7d616STomasz Nowicki /* Get distributor base address */ 1585ffa7d616STomasz Nowicki dist = (struct acpi_madt_generic_distributor *)header; 1586611f039fSJulien Grall acpi_data.dist_base = ioremap(dist->base_address, 1587611f039fSJulien Grall ACPI_GICV3_DIST_MEM_SIZE); 1588611f039fSJulien Grall if (!acpi_data.dist_base) { 1589ffa7d616STomasz Nowicki pr_err("Unable to map GICD registers\n"); 1590ffa7d616STomasz Nowicki return -ENOMEM; 1591ffa7d616STomasz Nowicki } 1592ffa7d616STomasz Nowicki 1593611f039fSJulien Grall err = gic_validate_dist_version(acpi_data.dist_base); 1594ffa7d616STomasz Nowicki if (err) { 159571192a68SArvind Yadav pr_err("No distributor detected at @%p, giving up\n", 1596611f039fSJulien Grall acpi_data.dist_base); 1597ffa7d616STomasz Nowicki goto out_dist_unmap; 1598ffa7d616STomasz Nowicki } 1599ffa7d616STomasz Nowicki 1600611f039fSJulien Grall size = sizeof(*acpi_data.redist_regs) * acpi_data.nr_redist_regions; 1601611f039fSJulien Grall acpi_data.redist_regs = kzalloc(size, GFP_KERNEL); 1602611f039fSJulien Grall if (!acpi_data.redist_regs) { 1603ffa7d616STomasz Nowicki err = -ENOMEM; 1604ffa7d616STomasz Nowicki goto out_dist_unmap; 1605ffa7d616STomasz Nowicki } 1606ffa7d616STomasz Nowicki 1607b70fb7afSTomasz Nowicki err = gic_acpi_collect_gicr_base(); 1608b70fb7afSTomasz Nowicki if (err) 1609ffa7d616STomasz Nowicki goto out_redist_unmap; 1610ffa7d616STomasz Nowicki 1611611f039fSJulien Grall domain_handle = irq_domain_alloc_fwnode(acpi_data.dist_base); 1612ffa7d616STomasz Nowicki if (!domain_handle) { 1613ffa7d616STomasz Nowicki err = -ENOMEM; 1614ffa7d616STomasz Nowicki goto out_redist_unmap; 1615ffa7d616STomasz Nowicki } 1616ffa7d616STomasz Nowicki 1617611f039fSJulien Grall err = gic_init_bases(acpi_data.dist_base, acpi_data.redist_regs, 1618611f039fSJulien Grall acpi_data.nr_redist_regions, 0, domain_handle); 1619ffa7d616STomasz Nowicki if (err) 1620ffa7d616STomasz Nowicki goto out_fwhandle_free; 1621ffa7d616STomasz Nowicki 1622ffa7d616STomasz Nowicki acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, domain_handle); 1623d33a3c8cSChristoffer Dall 1624d01d3274SDavidlohr Bueso if (static_branch_likely(&supports_deactivate_key)) 16251839e576SJulien Grall gic_acpi_setup_kvm_info(); 16261839e576SJulien Grall 1627ffa7d616STomasz Nowicki return 0; 1628ffa7d616STomasz Nowicki 1629ffa7d616STomasz Nowicki out_fwhandle_free: 1630ffa7d616STomasz Nowicki irq_domain_free_fwnode(domain_handle); 1631ffa7d616STomasz Nowicki out_redist_unmap: 1632611f039fSJulien Grall for (i = 0; i < acpi_data.nr_redist_regions; i++) 1633611f039fSJulien Grall if (acpi_data.redist_regs[i].redist_base) 1634611f039fSJulien Grall iounmap(acpi_data.redist_regs[i].redist_base); 1635611f039fSJulien Grall kfree(acpi_data.redist_regs); 1636ffa7d616STomasz Nowicki out_dist_unmap: 1637611f039fSJulien Grall iounmap(acpi_data.dist_base); 1638ffa7d616STomasz Nowicki return err; 1639ffa7d616STomasz Nowicki } 1640ffa7d616STomasz Nowicki IRQCHIP_ACPI_DECLARE(gic_v3, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 1641ffa7d616STomasz Nowicki acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V3, 1642ffa7d616STomasz Nowicki gic_acpi_init); 1643ffa7d616STomasz Nowicki IRQCHIP_ACPI_DECLARE(gic_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 1644ffa7d616STomasz Nowicki acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V4, 1645ffa7d616STomasz Nowicki gic_acpi_init); 1646ffa7d616STomasz Nowicki IRQCHIP_ACPI_DECLARE(gic_v3_or_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 1647ffa7d616STomasz Nowicki acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_NONE, 1648ffa7d616STomasz Nowicki gic_acpi_init); 1649ffa7d616STomasz Nowicki #endif 1650