1021f6537SMarc Zyngier /* 20edc23eaSMarc Zyngier * Copyright (C) 2013-2017 ARM Limited, All Rights Reserved. 3021f6537SMarc Zyngier * Author: Marc Zyngier <marc.zyngier@arm.com> 4021f6537SMarc Zyngier * 5021f6537SMarc Zyngier * This program is free software; you can redistribute it and/or modify 6021f6537SMarc Zyngier * it under the terms of the GNU General Public License version 2 as 7021f6537SMarc Zyngier * published by the Free Software Foundation. 8021f6537SMarc Zyngier * 9021f6537SMarc Zyngier * This program is distributed in the hope that it will be useful, 10021f6537SMarc Zyngier * but WITHOUT ANY WARRANTY; without even the implied warranty of 11021f6537SMarc Zyngier * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12021f6537SMarc Zyngier * GNU General Public License for more details. 13021f6537SMarc Zyngier * 14021f6537SMarc Zyngier * You should have received a copy of the GNU General Public License 15021f6537SMarc Zyngier * along with this program. If not, see <http://www.gnu.org/licenses/>. 16021f6537SMarc Zyngier */ 17021f6537SMarc Zyngier 1868628bb8SJulien Grall #define pr_fmt(fmt) "GICv3: " fmt 1968628bb8SJulien Grall 20ffa7d616STomasz Nowicki #include <linux/acpi.h> 21021f6537SMarc Zyngier #include <linux/cpu.h> 223708d52fSSudeep Holla #include <linux/cpu_pm.h> 23021f6537SMarc Zyngier #include <linux/delay.h> 24021f6537SMarc Zyngier #include <linux/interrupt.h> 25ffa7d616STomasz Nowicki #include <linux/irqdomain.h> 26021f6537SMarc Zyngier #include <linux/of.h> 27021f6537SMarc Zyngier #include <linux/of_address.h> 28021f6537SMarc Zyngier #include <linux/of_irq.h> 29021f6537SMarc Zyngier #include <linux/percpu.h> 30021f6537SMarc Zyngier #include <linux/slab.h> 31021f6537SMarc Zyngier 3241a83e06SJoel Porquet #include <linux/irqchip.h> 331839e576SJulien Grall #include <linux/irqchip/arm-gic-common.h> 34021f6537SMarc Zyngier #include <linux/irqchip/arm-gic-v3.h> 35e3825ba1SMarc Zyngier #include <linux/irqchip/irq-partition-percpu.h> 36021f6537SMarc Zyngier 37021f6537SMarc Zyngier #include <asm/cputype.h> 38021f6537SMarc Zyngier #include <asm/exception.h> 39021f6537SMarc Zyngier #include <asm/smp_plat.h> 400b6a3da9SMarc Zyngier #include <asm/virt.h> 41021f6537SMarc Zyngier 42021f6537SMarc Zyngier #include "irq-gic-common.h" 43021f6537SMarc Zyngier 44f5c1434cSMarc Zyngier struct redist_region { 45f5c1434cSMarc Zyngier void __iomem *redist_base; 46f5c1434cSMarc Zyngier phys_addr_t phys_base; 47b70fb7afSTomasz Nowicki bool single_redist; 48f5c1434cSMarc Zyngier }; 49f5c1434cSMarc Zyngier 50021f6537SMarc Zyngier struct gic_chip_data { 51e3825ba1SMarc Zyngier struct fwnode_handle *fwnode; 52021f6537SMarc Zyngier void __iomem *dist_base; 53f5c1434cSMarc Zyngier struct redist_region *redist_regions; 54f5c1434cSMarc Zyngier struct rdists rdists; 55021f6537SMarc Zyngier struct irq_domain *domain; 56021f6537SMarc Zyngier u64 redist_stride; 57f5c1434cSMarc Zyngier u32 nr_redist_regions; 58021f6537SMarc Zyngier unsigned int irq_nr; 59e3825ba1SMarc Zyngier struct partition_desc *ppi_descs[16]; 60021f6537SMarc Zyngier }; 61021f6537SMarc Zyngier 62021f6537SMarc Zyngier static struct gic_chip_data gic_data __read_mostly; 630b6a3da9SMarc Zyngier static struct static_key supports_deactivate = STATIC_KEY_INIT_TRUE; 64021f6537SMarc Zyngier 651839e576SJulien Grall static struct gic_kvm_info gic_v3_kvm_info; 661839e576SJulien Grall 67f5c1434cSMarc Zyngier #define gic_data_rdist() (this_cpu_ptr(gic_data.rdists.rdist)) 68f5c1434cSMarc Zyngier #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base) 69021f6537SMarc Zyngier #define gic_data_rdist_sgi_base() (gic_data_rdist_rd_base() + SZ_64K) 70021f6537SMarc Zyngier 71021f6537SMarc Zyngier /* Our default, arbitrary priority value. Linux only uses one anyway. */ 72021f6537SMarc Zyngier #define DEFAULT_PMR_VALUE 0xf0 73021f6537SMarc Zyngier 74021f6537SMarc Zyngier static inline unsigned int gic_irq(struct irq_data *d) 75021f6537SMarc Zyngier { 76021f6537SMarc Zyngier return d->hwirq; 77021f6537SMarc Zyngier } 78021f6537SMarc Zyngier 79021f6537SMarc Zyngier static inline int gic_irq_in_rdist(struct irq_data *d) 80021f6537SMarc Zyngier { 81021f6537SMarc Zyngier return gic_irq(d) < 32; 82021f6537SMarc Zyngier } 83021f6537SMarc Zyngier 84021f6537SMarc Zyngier static inline void __iomem *gic_dist_base(struct irq_data *d) 85021f6537SMarc Zyngier { 86021f6537SMarc Zyngier if (gic_irq_in_rdist(d)) /* SGI+PPI -> SGI_base for this CPU */ 87021f6537SMarc Zyngier return gic_data_rdist_sgi_base(); 88021f6537SMarc Zyngier 89021f6537SMarc Zyngier if (d->hwirq <= 1023) /* SPI -> dist_base */ 90021f6537SMarc Zyngier return gic_data.dist_base; 91021f6537SMarc Zyngier 92021f6537SMarc Zyngier return NULL; 93021f6537SMarc Zyngier } 94021f6537SMarc Zyngier 95021f6537SMarc Zyngier static void gic_do_wait_for_rwp(void __iomem *base) 96021f6537SMarc Zyngier { 97021f6537SMarc Zyngier u32 count = 1000000; /* 1s! */ 98021f6537SMarc Zyngier 99021f6537SMarc Zyngier while (readl_relaxed(base + GICD_CTLR) & GICD_CTLR_RWP) { 100021f6537SMarc Zyngier count--; 101021f6537SMarc Zyngier if (!count) { 102021f6537SMarc Zyngier pr_err_ratelimited("RWP timeout, gone fishing\n"); 103021f6537SMarc Zyngier return; 104021f6537SMarc Zyngier } 105021f6537SMarc Zyngier cpu_relax(); 106021f6537SMarc Zyngier udelay(1); 107021f6537SMarc Zyngier }; 108021f6537SMarc Zyngier } 109021f6537SMarc Zyngier 110021f6537SMarc Zyngier /* Wait for completion of a distributor change */ 111021f6537SMarc Zyngier static void gic_dist_wait_for_rwp(void) 112021f6537SMarc Zyngier { 113021f6537SMarc Zyngier gic_do_wait_for_rwp(gic_data.dist_base); 114021f6537SMarc Zyngier } 115021f6537SMarc Zyngier 116021f6537SMarc Zyngier /* Wait for completion of a redistributor change */ 117021f6537SMarc Zyngier static void gic_redist_wait_for_rwp(void) 118021f6537SMarc Zyngier { 119021f6537SMarc Zyngier gic_do_wait_for_rwp(gic_data_rdist_rd_base()); 120021f6537SMarc Zyngier } 121021f6537SMarc Zyngier 1227936e914SJean-Philippe Brucker #ifdef CONFIG_ARM64 1236d4e11c5SRobert Richter 1246d4e11c5SRobert Richter static u64 __maybe_unused gic_read_iar(void) 1256d4e11c5SRobert Richter { 126a4023f68SSuzuki K Poulose if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_23154)) 1276d4e11c5SRobert Richter return gic_read_iar_cavium_thunderx(); 1286d4e11c5SRobert Richter else 1296d4e11c5SRobert Richter return gic_read_iar_common(); 1306d4e11c5SRobert Richter } 1317936e914SJean-Philippe Brucker #endif 132021f6537SMarc Zyngier 133a2c22510SSudeep Holla static void gic_enable_redist(bool enable) 134021f6537SMarc Zyngier { 135021f6537SMarc Zyngier void __iomem *rbase; 136021f6537SMarc Zyngier u32 count = 1000000; /* 1s! */ 137021f6537SMarc Zyngier u32 val; 138021f6537SMarc Zyngier 139021f6537SMarc Zyngier rbase = gic_data_rdist_rd_base(); 140021f6537SMarc Zyngier 141021f6537SMarc Zyngier val = readl_relaxed(rbase + GICR_WAKER); 142a2c22510SSudeep Holla if (enable) 143a2c22510SSudeep Holla /* Wake up this CPU redistributor */ 144021f6537SMarc Zyngier val &= ~GICR_WAKER_ProcessorSleep; 145a2c22510SSudeep Holla else 146a2c22510SSudeep Holla val |= GICR_WAKER_ProcessorSleep; 147021f6537SMarc Zyngier writel_relaxed(val, rbase + GICR_WAKER); 148021f6537SMarc Zyngier 149a2c22510SSudeep Holla if (!enable) { /* Check that GICR_WAKER is writeable */ 150a2c22510SSudeep Holla val = readl_relaxed(rbase + GICR_WAKER); 151a2c22510SSudeep Holla if (!(val & GICR_WAKER_ProcessorSleep)) 152a2c22510SSudeep Holla return; /* No PM support in this redistributor */ 153021f6537SMarc Zyngier } 154a2c22510SSudeep Holla 155d102eb5cSDan Carpenter while (--count) { 156a2c22510SSudeep Holla val = readl_relaxed(rbase + GICR_WAKER); 157cf1d9d11SAndrew Jones if (enable ^ (bool)(val & GICR_WAKER_ChildrenAsleep)) 158a2c22510SSudeep Holla break; 159021f6537SMarc Zyngier cpu_relax(); 160021f6537SMarc Zyngier udelay(1); 161021f6537SMarc Zyngier }; 162a2c22510SSudeep Holla if (!count) 163a2c22510SSudeep Holla pr_err_ratelimited("redistributor failed to %s...\n", 164a2c22510SSudeep Holla enable ? "wakeup" : "sleep"); 165021f6537SMarc Zyngier } 166021f6537SMarc Zyngier 167021f6537SMarc Zyngier /* 168021f6537SMarc Zyngier * Routines to disable, enable, EOI and route interrupts 169021f6537SMarc Zyngier */ 170b594c6e2SMarc Zyngier static int gic_peek_irq(struct irq_data *d, u32 offset) 171b594c6e2SMarc Zyngier { 172b594c6e2SMarc Zyngier u32 mask = 1 << (gic_irq(d) % 32); 173b594c6e2SMarc Zyngier void __iomem *base; 174b594c6e2SMarc Zyngier 175b594c6e2SMarc Zyngier if (gic_irq_in_rdist(d)) 176b594c6e2SMarc Zyngier base = gic_data_rdist_sgi_base(); 177b594c6e2SMarc Zyngier else 178b594c6e2SMarc Zyngier base = gic_data.dist_base; 179b594c6e2SMarc Zyngier 180b594c6e2SMarc Zyngier return !!(readl_relaxed(base + offset + (gic_irq(d) / 32) * 4) & mask); 181b594c6e2SMarc Zyngier } 182b594c6e2SMarc Zyngier 183021f6537SMarc Zyngier static void gic_poke_irq(struct irq_data *d, u32 offset) 184021f6537SMarc Zyngier { 185021f6537SMarc Zyngier u32 mask = 1 << (gic_irq(d) % 32); 186021f6537SMarc Zyngier void (*rwp_wait)(void); 187021f6537SMarc Zyngier void __iomem *base; 188021f6537SMarc Zyngier 189021f6537SMarc Zyngier if (gic_irq_in_rdist(d)) { 190021f6537SMarc Zyngier base = gic_data_rdist_sgi_base(); 191021f6537SMarc Zyngier rwp_wait = gic_redist_wait_for_rwp; 192021f6537SMarc Zyngier } else { 193021f6537SMarc Zyngier base = gic_data.dist_base; 194021f6537SMarc Zyngier rwp_wait = gic_dist_wait_for_rwp; 195021f6537SMarc Zyngier } 196021f6537SMarc Zyngier 197021f6537SMarc Zyngier writel_relaxed(mask, base + offset + (gic_irq(d) / 32) * 4); 198021f6537SMarc Zyngier rwp_wait(); 199021f6537SMarc Zyngier } 200021f6537SMarc Zyngier 201021f6537SMarc Zyngier static void gic_mask_irq(struct irq_data *d) 202021f6537SMarc Zyngier { 203021f6537SMarc Zyngier gic_poke_irq(d, GICD_ICENABLER); 204021f6537SMarc Zyngier } 205021f6537SMarc Zyngier 2060b6a3da9SMarc Zyngier static void gic_eoimode1_mask_irq(struct irq_data *d) 2070b6a3da9SMarc Zyngier { 2080b6a3da9SMarc Zyngier gic_mask_irq(d); 209530bf353SMarc Zyngier /* 210530bf353SMarc Zyngier * When masking a forwarded interrupt, make sure it is 211530bf353SMarc Zyngier * deactivated as well. 212530bf353SMarc Zyngier * 213530bf353SMarc Zyngier * This ensures that an interrupt that is getting 214530bf353SMarc Zyngier * disabled/masked will not get "stuck", because there is 215530bf353SMarc Zyngier * noone to deactivate it (guest is being terminated). 216530bf353SMarc Zyngier */ 2174df7f54dSThomas Gleixner if (irqd_is_forwarded_to_vcpu(d)) 218530bf353SMarc Zyngier gic_poke_irq(d, GICD_ICACTIVER); 2190b6a3da9SMarc Zyngier } 2200b6a3da9SMarc Zyngier 221021f6537SMarc Zyngier static void gic_unmask_irq(struct irq_data *d) 222021f6537SMarc Zyngier { 223021f6537SMarc Zyngier gic_poke_irq(d, GICD_ISENABLER); 224021f6537SMarc Zyngier } 225021f6537SMarc Zyngier 226b594c6e2SMarc Zyngier static int gic_irq_set_irqchip_state(struct irq_data *d, 227b594c6e2SMarc Zyngier enum irqchip_irq_state which, bool val) 228b594c6e2SMarc Zyngier { 229b594c6e2SMarc Zyngier u32 reg; 230b594c6e2SMarc Zyngier 231b594c6e2SMarc Zyngier if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */ 232b594c6e2SMarc Zyngier return -EINVAL; 233b594c6e2SMarc Zyngier 234b594c6e2SMarc Zyngier switch (which) { 235b594c6e2SMarc Zyngier case IRQCHIP_STATE_PENDING: 236b594c6e2SMarc Zyngier reg = val ? GICD_ISPENDR : GICD_ICPENDR; 237b594c6e2SMarc Zyngier break; 238b594c6e2SMarc Zyngier 239b594c6e2SMarc Zyngier case IRQCHIP_STATE_ACTIVE: 240b594c6e2SMarc Zyngier reg = val ? GICD_ISACTIVER : GICD_ICACTIVER; 241b594c6e2SMarc Zyngier break; 242b594c6e2SMarc Zyngier 243b594c6e2SMarc Zyngier case IRQCHIP_STATE_MASKED: 244b594c6e2SMarc Zyngier reg = val ? GICD_ICENABLER : GICD_ISENABLER; 245b594c6e2SMarc Zyngier break; 246b594c6e2SMarc Zyngier 247b594c6e2SMarc Zyngier default: 248b594c6e2SMarc Zyngier return -EINVAL; 249b594c6e2SMarc Zyngier } 250b594c6e2SMarc Zyngier 251b594c6e2SMarc Zyngier gic_poke_irq(d, reg); 252b594c6e2SMarc Zyngier return 0; 253b594c6e2SMarc Zyngier } 254b594c6e2SMarc Zyngier 255b594c6e2SMarc Zyngier static int gic_irq_get_irqchip_state(struct irq_data *d, 256b594c6e2SMarc Zyngier enum irqchip_irq_state which, bool *val) 257b594c6e2SMarc Zyngier { 258b594c6e2SMarc Zyngier if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */ 259b594c6e2SMarc Zyngier return -EINVAL; 260b594c6e2SMarc Zyngier 261b594c6e2SMarc Zyngier switch (which) { 262b594c6e2SMarc Zyngier case IRQCHIP_STATE_PENDING: 263b594c6e2SMarc Zyngier *val = gic_peek_irq(d, GICD_ISPENDR); 264b594c6e2SMarc Zyngier break; 265b594c6e2SMarc Zyngier 266b594c6e2SMarc Zyngier case IRQCHIP_STATE_ACTIVE: 267b594c6e2SMarc Zyngier *val = gic_peek_irq(d, GICD_ISACTIVER); 268b594c6e2SMarc Zyngier break; 269b594c6e2SMarc Zyngier 270b594c6e2SMarc Zyngier case IRQCHIP_STATE_MASKED: 271b594c6e2SMarc Zyngier *val = !gic_peek_irq(d, GICD_ISENABLER); 272b594c6e2SMarc Zyngier break; 273b594c6e2SMarc Zyngier 274b594c6e2SMarc Zyngier default: 275b594c6e2SMarc Zyngier return -EINVAL; 276b594c6e2SMarc Zyngier } 277b594c6e2SMarc Zyngier 278b594c6e2SMarc Zyngier return 0; 279b594c6e2SMarc Zyngier } 280b594c6e2SMarc Zyngier 281021f6537SMarc Zyngier static void gic_eoi_irq(struct irq_data *d) 282021f6537SMarc Zyngier { 283021f6537SMarc Zyngier gic_write_eoir(gic_irq(d)); 284021f6537SMarc Zyngier } 285021f6537SMarc Zyngier 2860b6a3da9SMarc Zyngier static void gic_eoimode1_eoi_irq(struct irq_data *d) 2870b6a3da9SMarc Zyngier { 2880b6a3da9SMarc Zyngier /* 289530bf353SMarc Zyngier * No need to deactivate an LPI, or an interrupt that 290530bf353SMarc Zyngier * is is getting forwarded to a vcpu. 2910b6a3da9SMarc Zyngier */ 2924df7f54dSThomas Gleixner if (gic_irq(d) >= 8192 || irqd_is_forwarded_to_vcpu(d)) 2930b6a3da9SMarc Zyngier return; 2940b6a3da9SMarc Zyngier gic_write_dir(gic_irq(d)); 2950b6a3da9SMarc Zyngier } 2960b6a3da9SMarc Zyngier 297021f6537SMarc Zyngier static int gic_set_type(struct irq_data *d, unsigned int type) 298021f6537SMarc Zyngier { 299021f6537SMarc Zyngier unsigned int irq = gic_irq(d); 300021f6537SMarc Zyngier void (*rwp_wait)(void); 301021f6537SMarc Zyngier void __iomem *base; 302021f6537SMarc Zyngier 303021f6537SMarc Zyngier /* Interrupt configuration for SGIs can't be changed */ 304021f6537SMarc Zyngier if (irq < 16) 305021f6537SMarc Zyngier return -EINVAL; 306021f6537SMarc Zyngier 307fb7e7debSLiviu Dudau /* SPIs have restrictions on the supported types */ 308fb7e7debSLiviu Dudau if (irq >= 32 && type != IRQ_TYPE_LEVEL_HIGH && 309fb7e7debSLiviu Dudau type != IRQ_TYPE_EDGE_RISING) 310021f6537SMarc Zyngier return -EINVAL; 311021f6537SMarc Zyngier 312021f6537SMarc Zyngier if (gic_irq_in_rdist(d)) { 313021f6537SMarc Zyngier base = gic_data_rdist_sgi_base(); 314021f6537SMarc Zyngier rwp_wait = gic_redist_wait_for_rwp; 315021f6537SMarc Zyngier } else { 316021f6537SMarc Zyngier base = gic_data.dist_base; 317021f6537SMarc Zyngier rwp_wait = gic_dist_wait_for_rwp; 318021f6537SMarc Zyngier } 319021f6537SMarc Zyngier 320fb7e7debSLiviu Dudau return gic_configure_irq(irq, type, base, rwp_wait); 321021f6537SMarc Zyngier } 322021f6537SMarc Zyngier 323530bf353SMarc Zyngier static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu) 324530bf353SMarc Zyngier { 3254df7f54dSThomas Gleixner if (vcpu) 3264df7f54dSThomas Gleixner irqd_set_forwarded_to_vcpu(d); 3274df7f54dSThomas Gleixner else 3284df7f54dSThomas Gleixner irqd_clr_forwarded_to_vcpu(d); 329530bf353SMarc Zyngier return 0; 330530bf353SMarc Zyngier } 331530bf353SMarc Zyngier 332f6c86a41SJean-Philippe Brucker static u64 gic_mpidr_to_affinity(unsigned long mpidr) 333021f6537SMarc Zyngier { 334021f6537SMarc Zyngier u64 aff; 335021f6537SMarc Zyngier 336f6c86a41SJean-Philippe Brucker aff = ((u64)MPIDR_AFFINITY_LEVEL(mpidr, 3) << 32 | 337021f6537SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 | 338021f6537SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | 339021f6537SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 0)); 340021f6537SMarc Zyngier 341021f6537SMarc Zyngier return aff; 342021f6537SMarc Zyngier } 343021f6537SMarc Zyngier 344021f6537SMarc Zyngier static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) 345021f6537SMarc Zyngier { 346f6c86a41SJean-Philippe Brucker u32 irqnr; 347021f6537SMarc Zyngier 348021f6537SMarc Zyngier do { 349021f6537SMarc Zyngier irqnr = gic_read_iar(); 350021f6537SMarc Zyngier 351da33f31dSMarc Zyngier if (likely(irqnr > 15 && irqnr < 1020) || irqnr >= 8192) { 352ebc6de00SMarc Zyngier int err; 3530b6a3da9SMarc Zyngier 3540b6a3da9SMarc Zyngier if (static_key_true(&supports_deactivate)) 3550b6a3da9SMarc Zyngier gic_write_eoir(irqnr); 35639a06b67SWill Deacon else 35739a06b67SWill Deacon isb(); 3580b6a3da9SMarc Zyngier 359ebc6de00SMarc Zyngier err = handle_domain_irq(gic_data.domain, irqnr, regs); 360ebc6de00SMarc Zyngier if (err) { 361da33f31dSMarc Zyngier WARN_ONCE(true, "Unexpected interrupt received!\n"); 3620b6a3da9SMarc Zyngier if (static_key_true(&supports_deactivate)) { 3630b6a3da9SMarc Zyngier if (irqnr < 8192) 3640b6a3da9SMarc Zyngier gic_write_dir(irqnr); 3650b6a3da9SMarc Zyngier } else { 366021f6537SMarc Zyngier gic_write_eoir(irqnr); 367021f6537SMarc Zyngier } 3680b6a3da9SMarc Zyngier } 369ebc6de00SMarc Zyngier continue; 370ebc6de00SMarc Zyngier } 371021f6537SMarc Zyngier if (irqnr < 16) { 372021f6537SMarc Zyngier gic_write_eoir(irqnr); 3730b6a3da9SMarc Zyngier if (static_key_true(&supports_deactivate)) 3740b6a3da9SMarc Zyngier gic_write_dir(irqnr); 375021f6537SMarc Zyngier #ifdef CONFIG_SMP 376f86c4fbdSWill Deacon /* 377f86c4fbdSWill Deacon * Unlike GICv2, we don't need an smp_rmb() here. 378f86c4fbdSWill Deacon * The control dependency from gic_read_iar to 379f86c4fbdSWill Deacon * the ISB in gic_write_eoir is enough to ensure 380f86c4fbdSWill Deacon * that any shared data read by handle_IPI will 381f86c4fbdSWill Deacon * be read after the ACK. 382f86c4fbdSWill Deacon */ 383021f6537SMarc Zyngier handle_IPI(irqnr, regs); 384021f6537SMarc Zyngier #else 385021f6537SMarc Zyngier WARN_ONCE(true, "Unexpected SGI received!\n"); 386021f6537SMarc Zyngier #endif 387021f6537SMarc Zyngier continue; 388021f6537SMarc Zyngier } 389021f6537SMarc Zyngier } while (irqnr != ICC_IAR1_EL1_SPURIOUS); 390021f6537SMarc Zyngier } 391021f6537SMarc Zyngier 392021f6537SMarc Zyngier static void __init gic_dist_init(void) 393021f6537SMarc Zyngier { 394021f6537SMarc Zyngier unsigned int i; 395021f6537SMarc Zyngier u64 affinity; 396021f6537SMarc Zyngier void __iomem *base = gic_data.dist_base; 397021f6537SMarc Zyngier 398021f6537SMarc Zyngier /* Disable the distributor */ 399021f6537SMarc Zyngier writel_relaxed(0, base + GICD_CTLR); 400021f6537SMarc Zyngier gic_dist_wait_for_rwp(); 401021f6537SMarc Zyngier 4027c9b9730SMarc Zyngier /* 4037c9b9730SMarc Zyngier * Configure SPIs as non-secure Group-1. This will only matter 4047c9b9730SMarc Zyngier * if the GIC only has a single security state. This will not 4057c9b9730SMarc Zyngier * do the right thing if the kernel is running in secure mode, 4067c9b9730SMarc Zyngier * but that's not the intended use case anyway. 4077c9b9730SMarc Zyngier */ 4087c9b9730SMarc Zyngier for (i = 32; i < gic_data.irq_nr; i += 32) 4097c9b9730SMarc Zyngier writel_relaxed(~0, base + GICD_IGROUPR + i / 8); 4107c9b9730SMarc Zyngier 411021f6537SMarc Zyngier gic_dist_config(base, gic_data.irq_nr, gic_dist_wait_for_rwp); 412021f6537SMarc Zyngier 413021f6537SMarc Zyngier /* Enable distributor with ARE, Group1 */ 414021f6537SMarc Zyngier writel_relaxed(GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G1A | GICD_CTLR_ENABLE_G1, 415021f6537SMarc Zyngier base + GICD_CTLR); 416021f6537SMarc Zyngier 417021f6537SMarc Zyngier /* 418021f6537SMarc Zyngier * Set all global interrupts to the boot CPU only. ARE must be 419021f6537SMarc Zyngier * enabled. 420021f6537SMarc Zyngier */ 421021f6537SMarc Zyngier affinity = gic_mpidr_to_affinity(cpu_logical_map(smp_processor_id())); 422021f6537SMarc Zyngier for (i = 32; i < gic_data.irq_nr; i++) 42372c97126SJean-Philippe Brucker gic_write_irouter(affinity, base + GICD_IROUTER + i * 8); 424021f6537SMarc Zyngier } 425021f6537SMarc Zyngier 4260d94ded2SMarc Zyngier static int gic_iterate_rdists(int (*fn)(struct redist_region *, void __iomem *)) 427021f6537SMarc Zyngier { 4280d94ded2SMarc Zyngier int ret = -ENODEV; 429021f6537SMarc Zyngier int i; 430021f6537SMarc Zyngier 431f5c1434cSMarc Zyngier for (i = 0; i < gic_data.nr_redist_regions; i++) { 432f5c1434cSMarc Zyngier void __iomem *ptr = gic_data.redist_regions[i].redist_base; 4330d94ded2SMarc Zyngier u64 typer; 434021f6537SMarc Zyngier u32 reg; 435021f6537SMarc Zyngier 436021f6537SMarc Zyngier reg = readl_relaxed(ptr + GICR_PIDR2) & GIC_PIDR2_ARCH_MASK; 437021f6537SMarc Zyngier if (reg != GIC_PIDR2_ARCH_GICv3 && 438021f6537SMarc Zyngier reg != GIC_PIDR2_ARCH_GICv4) { /* We're in trouble... */ 439021f6537SMarc Zyngier pr_warn("No redistributor present @%p\n", ptr); 440021f6537SMarc Zyngier break; 441021f6537SMarc Zyngier } 442021f6537SMarc Zyngier 443021f6537SMarc Zyngier do { 44472c97126SJean-Philippe Brucker typer = gic_read_typer(ptr + GICR_TYPER); 4450d94ded2SMarc Zyngier ret = fn(gic_data.redist_regions + i, ptr); 4460d94ded2SMarc Zyngier if (!ret) 447021f6537SMarc Zyngier return 0; 448021f6537SMarc Zyngier 449b70fb7afSTomasz Nowicki if (gic_data.redist_regions[i].single_redist) 450b70fb7afSTomasz Nowicki break; 451b70fb7afSTomasz Nowicki 452021f6537SMarc Zyngier if (gic_data.redist_stride) { 453021f6537SMarc Zyngier ptr += gic_data.redist_stride; 454021f6537SMarc Zyngier } else { 455021f6537SMarc Zyngier ptr += SZ_64K * 2; /* Skip RD_base + SGI_base */ 456021f6537SMarc Zyngier if (typer & GICR_TYPER_VLPIS) 457021f6537SMarc Zyngier ptr += SZ_64K * 2; /* Skip VLPI_base + reserved page */ 458021f6537SMarc Zyngier } 459021f6537SMarc Zyngier } while (!(typer & GICR_TYPER_LAST)); 460021f6537SMarc Zyngier } 461021f6537SMarc Zyngier 4620d94ded2SMarc Zyngier return ret ? -ENODEV : 0; 4630d94ded2SMarc Zyngier } 4640d94ded2SMarc Zyngier 4650d94ded2SMarc Zyngier static int __gic_populate_rdist(struct redist_region *region, void __iomem *ptr) 4660d94ded2SMarc Zyngier { 4670d94ded2SMarc Zyngier unsigned long mpidr = cpu_logical_map(smp_processor_id()); 4680d94ded2SMarc Zyngier u64 typer; 4690d94ded2SMarc Zyngier u32 aff; 4700d94ded2SMarc Zyngier 4710d94ded2SMarc Zyngier /* 4720d94ded2SMarc Zyngier * Convert affinity to a 32bit value that can be matched to 4730d94ded2SMarc Zyngier * GICR_TYPER bits [63:32]. 4740d94ded2SMarc Zyngier */ 4750d94ded2SMarc Zyngier aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 24 | 4760d94ded2SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 | 4770d94ded2SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | 4780d94ded2SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 0)); 4790d94ded2SMarc Zyngier 4800d94ded2SMarc Zyngier typer = gic_read_typer(ptr + GICR_TYPER); 4810d94ded2SMarc Zyngier if ((typer >> 32) == aff) { 4820d94ded2SMarc Zyngier u64 offset = ptr - region->redist_base; 4830d94ded2SMarc Zyngier gic_data_rdist_rd_base() = ptr; 4840d94ded2SMarc Zyngier gic_data_rdist()->phys_base = region->phys_base + offset; 4850d94ded2SMarc Zyngier 4860d94ded2SMarc Zyngier pr_info("CPU%d: found redistributor %lx region %d:%pa\n", 4870d94ded2SMarc Zyngier smp_processor_id(), mpidr, 4880d94ded2SMarc Zyngier (int)(region - gic_data.redist_regions), 4890d94ded2SMarc Zyngier &gic_data_rdist()->phys_base); 4900d94ded2SMarc Zyngier return 0; 4910d94ded2SMarc Zyngier } 4920d94ded2SMarc Zyngier 4930d94ded2SMarc Zyngier /* Try next one */ 4940d94ded2SMarc Zyngier return 1; 4950d94ded2SMarc Zyngier } 4960d94ded2SMarc Zyngier 4970d94ded2SMarc Zyngier static int gic_populate_rdist(void) 4980d94ded2SMarc Zyngier { 4990d94ded2SMarc Zyngier if (gic_iterate_rdists(__gic_populate_rdist) == 0) 5000d94ded2SMarc Zyngier return 0; 5010d94ded2SMarc Zyngier 502021f6537SMarc Zyngier /* We couldn't even deal with ourselves... */ 503f6c86a41SJean-Philippe Brucker WARN(true, "CPU%d: mpidr %lx has no re-distributor!\n", 5040d94ded2SMarc Zyngier smp_processor_id(), 5050d94ded2SMarc Zyngier (unsigned long)cpu_logical_map(smp_processor_id())); 506021f6537SMarc Zyngier return -ENODEV; 507021f6537SMarc Zyngier } 508021f6537SMarc Zyngier 5090edc23eaSMarc Zyngier static int __gic_update_vlpi_properties(struct redist_region *region, 5100edc23eaSMarc Zyngier void __iomem *ptr) 5110edc23eaSMarc Zyngier { 5120edc23eaSMarc Zyngier u64 typer = gic_read_typer(ptr + GICR_TYPER); 5130edc23eaSMarc Zyngier gic_data.rdists.has_vlpis &= !!(typer & GICR_TYPER_VLPIS); 5140edc23eaSMarc Zyngier gic_data.rdists.has_direct_lpi &= !!(typer & GICR_TYPER_DirectLPIS); 5150edc23eaSMarc Zyngier 5160edc23eaSMarc Zyngier return 1; 5170edc23eaSMarc Zyngier } 5180edc23eaSMarc Zyngier 5190edc23eaSMarc Zyngier static void gic_update_vlpi_properties(void) 5200edc23eaSMarc Zyngier { 5210edc23eaSMarc Zyngier gic_iterate_rdists(__gic_update_vlpi_properties); 5220edc23eaSMarc Zyngier pr_info("%sVLPI support, %sdirect LPI support\n", 5230edc23eaSMarc Zyngier !gic_data.rdists.has_vlpis ? "no " : "", 5240edc23eaSMarc Zyngier !gic_data.rdists.has_direct_lpi ? "no " : ""); 5250edc23eaSMarc Zyngier } 5260edc23eaSMarc Zyngier 5273708d52fSSudeep Holla static void gic_cpu_sys_reg_init(void) 528021f6537SMarc Zyngier { 5297cabd008SMarc Zyngier /* 5307cabd008SMarc Zyngier * Need to check that the SRE bit has actually been set. If 5317cabd008SMarc Zyngier * not, it means that SRE is disabled at EL2. We're going to 5327cabd008SMarc Zyngier * die painfully, and there is nothing we can do about it. 5337cabd008SMarc Zyngier * 5347cabd008SMarc Zyngier * Kindly inform the luser. 5357cabd008SMarc Zyngier */ 5367cabd008SMarc Zyngier if (!gic_enable_sre()) 5377cabd008SMarc Zyngier pr_err("GIC: unable to set SRE (disabled at EL2), panic ahead\n"); 538021f6537SMarc Zyngier 539021f6537SMarc Zyngier /* Set priority mask register */ 540021f6537SMarc Zyngier gic_write_pmr(DEFAULT_PMR_VALUE); 541021f6537SMarc Zyngier 54291ef8442SDaniel Thompson /* 54391ef8442SDaniel Thompson * Some firmwares hand over to the kernel with the BPR changed from 54491ef8442SDaniel Thompson * its reset value (and with a value large enough to prevent 54591ef8442SDaniel Thompson * any pre-emptive interrupts from working at all). Writing a zero 54691ef8442SDaniel Thompson * to BPR restores is reset value. 54791ef8442SDaniel Thompson */ 54891ef8442SDaniel Thompson gic_write_bpr1(0); 54991ef8442SDaniel Thompson 5500b6a3da9SMarc Zyngier if (static_key_true(&supports_deactivate)) { 5510b6a3da9SMarc Zyngier /* EOI drops priority only (mode 1) */ 5520b6a3da9SMarc Zyngier gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop); 5530b6a3da9SMarc Zyngier } else { 554021f6537SMarc Zyngier /* EOI deactivates interrupt too (mode 0) */ 555021f6537SMarc Zyngier gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop_dir); 5560b6a3da9SMarc Zyngier } 557021f6537SMarc Zyngier 558021f6537SMarc Zyngier /* ... and let's hit the road... */ 559021f6537SMarc Zyngier gic_write_grpen1(1); 560021f6537SMarc Zyngier } 561021f6537SMarc Zyngier 562da33f31dSMarc Zyngier static int gic_dist_supports_lpis(void) 563da33f31dSMarc Zyngier { 564da33f31dSMarc Zyngier return !!(readl_relaxed(gic_data.dist_base + GICD_TYPER) & GICD_TYPER_LPIS); 565da33f31dSMarc Zyngier } 566da33f31dSMarc Zyngier 567021f6537SMarc Zyngier static void gic_cpu_init(void) 568021f6537SMarc Zyngier { 569021f6537SMarc Zyngier void __iomem *rbase; 570021f6537SMarc Zyngier 571021f6537SMarc Zyngier /* Register ourselves with the rest of the world */ 572021f6537SMarc Zyngier if (gic_populate_rdist()) 573021f6537SMarc Zyngier return; 574021f6537SMarc Zyngier 575a2c22510SSudeep Holla gic_enable_redist(true); 576021f6537SMarc Zyngier 577021f6537SMarc Zyngier rbase = gic_data_rdist_sgi_base(); 578021f6537SMarc Zyngier 5797c9b9730SMarc Zyngier /* Configure SGIs/PPIs as non-secure Group-1 */ 5807c9b9730SMarc Zyngier writel_relaxed(~0, rbase + GICR_IGROUPR0); 5817c9b9730SMarc Zyngier 582021f6537SMarc Zyngier gic_cpu_config(rbase, gic_redist_wait_for_rwp); 583021f6537SMarc Zyngier 584da33f31dSMarc Zyngier /* Give LPIs a spin */ 585da33f31dSMarc Zyngier if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis()) 586da33f31dSMarc Zyngier its_cpu_init(); 587da33f31dSMarc Zyngier 5883708d52fSSudeep Holla /* initialise system registers */ 5893708d52fSSudeep Holla gic_cpu_sys_reg_init(); 590021f6537SMarc Zyngier } 591021f6537SMarc Zyngier 592021f6537SMarc Zyngier #ifdef CONFIG_SMP 593021f6537SMarc Zyngier 5946670a6d8SRichard Cochran static int gic_starting_cpu(unsigned int cpu) 5956670a6d8SRichard Cochran { 5966670a6d8SRichard Cochran gic_cpu_init(); 5976670a6d8SRichard Cochran return 0; 5986670a6d8SRichard Cochran } 599021f6537SMarc Zyngier 600021f6537SMarc Zyngier static u16 gic_compute_target_list(int *base_cpu, const struct cpumask *mask, 601f6c86a41SJean-Philippe Brucker unsigned long cluster_id) 602021f6537SMarc Zyngier { 603727653d6SJames Morse int next_cpu, cpu = *base_cpu; 604f6c86a41SJean-Philippe Brucker unsigned long mpidr = cpu_logical_map(cpu); 605021f6537SMarc Zyngier u16 tlist = 0; 606021f6537SMarc Zyngier 607021f6537SMarc Zyngier while (cpu < nr_cpu_ids) { 608021f6537SMarc Zyngier /* 609021f6537SMarc Zyngier * If we ever get a cluster of more than 16 CPUs, just 610021f6537SMarc Zyngier * scream and skip that CPU. 611021f6537SMarc Zyngier */ 612021f6537SMarc Zyngier if (WARN_ON((mpidr & 0xff) >= 16)) 613021f6537SMarc Zyngier goto out; 614021f6537SMarc Zyngier 615021f6537SMarc Zyngier tlist |= 1 << (mpidr & 0xf); 616021f6537SMarc Zyngier 617727653d6SJames Morse next_cpu = cpumask_next(cpu, mask); 618727653d6SJames Morse if (next_cpu >= nr_cpu_ids) 619021f6537SMarc Zyngier goto out; 620727653d6SJames Morse cpu = next_cpu; 621021f6537SMarc Zyngier 622021f6537SMarc Zyngier mpidr = cpu_logical_map(cpu); 623021f6537SMarc Zyngier 624021f6537SMarc Zyngier if (cluster_id != (mpidr & ~0xffUL)) { 625021f6537SMarc Zyngier cpu--; 626021f6537SMarc Zyngier goto out; 627021f6537SMarc Zyngier } 628021f6537SMarc Zyngier } 629021f6537SMarc Zyngier out: 630021f6537SMarc Zyngier *base_cpu = cpu; 631021f6537SMarc Zyngier return tlist; 632021f6537SMarc Zyngier } 633021f6537SMarc Zyngier 6347e580278SAndre Przywara #define MPIDR_TO_SGI_AFFINITY(cluster_id, level) \ 6357e580278SAndre Przywara (MPIDR_AFFINITY_LEVEL(cluster_id, level) \ 6367e580278SAndre Przywara << ICC_SGI1R_AFFINITY_## level ##_SHIFT) 6377e580278SAndre Przywara 638021f6537SMarc Zyngier static void gic_send_sgi(u64 cluster_id, u16 tlist, unsigned int irq) 639021f6537SMarc Zyngier { 640021f6537SMarc Zyngier u64 val; 641021f6537SMarc Zyngier 6427e580278SAndre Przywara val = (MPIDR_TO_SGI_AFFINITY(cluster_id, 3) | 6437e580278SAndre Przywara MPIDR_TO_SGI_AFFINITY(cluster_id, 2) | 6447e580278SAndre Przywara irq << ICC_SGI1R_SGI_ID_SHIFT | 6457e580278SAndre Przywara MPIDR_TO_SGI_AFFINITY(cluster_id, 1) | 6467e580278SAndre Przywara tlist << ICC_SGI1R_TARGET_LIST_SHIFT); 647021f6537SMarc Zyngier 648021f6537SMarc Zyngier pr_debug("CPU%d: ICC_SGI1R_EL1 %llx\n", smp_processor_id(), val); 649021f6537SMarc Zyngier gic_write_sgi1r(val); 650021f6537SMarc Zyngier } 651021f6537SMarc Zyngier 652021f6537SMarc Zyngier static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) 653021f6537SMarc Zyngier { 654021f6537SMarc Zyngier int cpu; 655021f6537SMarc Zyngier 656021f6537SMarc Zyngier if (WARN_ON(irq >= 16)) 657021f6537SMarc Zyngier return; 658021f6537SMarc Zyngier 659021f6537SMarc Zyngier /* 660021f6537SMarc Zyngier * Ensure that stores to Normal memory are visible to the 661021f6537SMarc Zyngier * other CPUs before issuing the IPI. 662021f6537SMarc Zyngier */ 663021f6537SMarc Zyngier smp_wmb(); 664021f6537SMarc Zyngier 665f9b531feSRusty Russell for_each_cpu(cpu, mask) { 666f6c86a41SJean-Philippe Brucker unsigned long cluster_id = cpu_logical_map(cpu) & ~0xffUL; 667021f6537SMarc Zyngier u16 tlist; 668021f6537SMarc Zyngier 669021f6537SMarc Zyngier tlist = gic_compute_target_list(&cpu, mask, cluster_id); 670021f6537SMarc Zyngier gic_send_sgi(cluster_id, tlist, irq); 671021f6537SMarc Zyngier } 672021f6537SMarc Zyngier 673021f6537SMarc Zyngier /* Force the above writes to ICC_SGI1R_EL1 to be executed */ 674021f6537SMarc Zyngier isb(); 675021f6537SMarc Zyngier } 676021f6537SMarc Zyngier 677021f6537SMarc Zyngier static void gic_smp_init(void) 678021f6537SMarc Zyngier { 679021f6537SMarc Zyngier set_smp_cross_call(gic_raise_softirq); 6806896bcd1SThomas Gleixner cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_GIC_STARTING, 68173c1b41eSThomas Gleixner "irqchip/arm/gicv3:starting", 68273c1b41eSThomas Gleixner gic_starting_cpu, NULL); 683021f6537SMarc Zyngier } 684021f6537SMarc Zyngier 685021f6537SMarc Zyngier static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, 686021f6537SMarc Zyngier bool force) 687021f6537SMarc Zyngier { 68865a30f8bSSuzuki K Poulose unsigned int cpu; 689021f6537SMarc Zyngier void __iomem *reg; 690021f6537SMarc Zyngier int enabled; 691021f6537SMarc Zyngier u64 val; 692021f6537SMarc Zyngier 69365a30f8bSSuzuki K Poulose if (force) 69465a30f8bSSuzuki K Poulose cpu = cpumask_first(mask_val); 69565a30f8bSSuzuki K Poulose else 69665a30f8bSSuzuki K Poulose cpu = cpumask_any_and(mask_val, cpu_online_mask); 69765a30f8bSSuzuki K Poulose 698866d7c1bSSuzuki K Poulose if (cpu >= nr_cpu_ids) 699866d7c1bSSuzuki K Poulose return -EINVAL; 700866d7c1bSSuzuki K Poulose 701021f6537SMarc Zyngier if (gic_irq_in_rdist(d)) 702021f6537SMarc Zyngier return -EINVAL; 703021f6537SMarc Zyngier 704021f6537SMarc Zyngier /* If interrupt was enabled, disable it first */ 705021f6537SMarc Zyngier enabled = gic_peek_irq(d, GICD_ISENABLER); 706021f6537SMarc Zyngier if (enabled) 707021f6537SMarc Zyngier gic_mask_irq(d); 708021f6537SMarc Zyngier 709021f6537SMarc Zyngier reg = gic_dist_base(d) + GICD_IROUTER + (gic_irq(d) * 8); 710021f6537SMarc Zyngier val = gic_mpidr_to_affinity(cpu_logical_map(cpu)); 711021f6537SMarc Zyngier 71272c97126SJean-Philippe Brucker gic_write_irouter(val, reg); 713021f6537SMarc Zyngier 714021f6537SMarc Zyngier /* 715021f6537SMarc Zyngier * If the interrupt was enabled, enabled it again. Otherwise, 716021f6537SMarc Zyngier * just wait for the distributor to have digested our changes. 717021f6537SMarc Zyngier */ 718021f6537SMarc Zyngier if (enabled) 719021f6537SMarc Zyngier gic_unmask_irq(d); 720021f6537SMarc Zyngier else 721021f6537SMarc Zyngier gic_dist_wait_for_rwp(); 722021f6537SMarc Zyngier 723956ae91aSMarc Zyngier irq_data_update_effective_affinity(d, cpumask_of(cpu)); 724956ae91aSMarc Zyngier 7250fc6fa29SAntoine Tenart return IRQ_SET_MASK_OK_DONE; 726021f6537SMarc Zyngier } 727021f6537SMarc Zyngier #else 728021f6537SMarc Zyngier #define gic_set_affinity NULL 729021f6537SMarc Zyngier #define gic_smp_init() do { } while(0) 730021f6537SMarc Zyngier #endif 731021f6537SMarc Zyngier 7323708d52fSSudeep Holla #ifdef CONFIG_CPU_PM 733ccd9432aSSudeep Holla /* Check whether it's single security state view */ 734ccd9432aSSudeep Holla static bool gic_dist_security_disabled(void) 735ccd9432aSSudeep Holla { 736ccd9432aSSudeep Holla return readl_relaxed(gic_data.dist_base + GICD_CTLR) & GICD_CTLR_DS; 737ccd9432aSSudeep Holla } 738ccd9432aSSudeep Holla 7393708d52fSSudeep Holla static int gic_cpu_pm_notifier(struct notifier_block *self, 7403708d52fSSudeep Holla unsigned long cmd, void *v) 7413708d52fSSudeep Holla { 7423708d52fSSudeep Holla if (cmd == CPU_PM_EXIT) { 743ccd9432aSSudeep Holla if (gic_dist_security_disabled()) 7443708d52fSSudeep Holla gic_enable_redist(true); 7453708d52fSSudeep Holla gic_cpu_sys_reg_init(); 746ccd9432aSSudeep Holla } else if (cmd == CPU_PM_ENTER && gic_dist_security_disabled()) { 7473708d52fSSudeep Holla gic_write_grpen1(0); 7483708d52fSSudeep Holla gic_enable_redist(false); 7493708d52fSSudeep Holla } 7503708d52fSSudeep Holla return NOTIFY_OK; 7513708d52fSSudeep Holla } 7523708d52fSSudeep Holla 7533708d52fSSudeep Holla static struct notifier_block gic_cpu_pm_notifier_block = { 7543708d52fSSudeep Holla .notifier_call = gic_cpu_pm_notifier, 7553708d52fSSudeep Holla }; 7563708d52fSSudeep Holla 7573708d52fSSudeep Holla static void gic_cpu_pm_init(void) 7583708d52fSSudeep Holla { 7593708d52fSSudeep Holla cpu_pm_register_notifier(&gic_cpu_pm_notifier_block); 7603708d52fSSudeep Holla } 7613708d52fSSudeep Holla 7623708d52fSSudeep Holla #else 7633708d52fSSudeep Holla static inline void gic_cpu_pm_init(void) { } 7643708d52fSSudeep Holla #endif /* CONFIG_CPU_PM */ 7653708d52fSSudeep Holla 766021f6537SMarc Zyngier static struct irq_chip gic_chip = { 767021f6537SMarc Zyngier .name = "GICv3", 768021f6537SMarc Zyngier .irq_mask = gic_mask_irq, 769021f6537SMarc Zyngier .irq_unmask = gic_unmask_irq, 770021f6537SMarc Zyngier .irq_eoi = gic_eoi_irq, 771021f6537SMarc Zyngier .irq_set_type = gic_set_type, 772021f6537SMarc Zyngier .irq_set_affinity = gic_set_affinity, 773b594c6e2SMarc Zyngier .irq_get_irqchip_state = gic_irq_get_irqchip_state, 774b594c6e2SMarc Zyngier .irq_set_irqchip_state = gic_irq_set_irqchip_state, 77555963c9fSSudeep Holla .flags = IRQCHIP_SET_TYPE_MASKED, 776021f6537SMarc Zyngier }; 777021f6537SMarc Zyngier 7780b6a3da9SMarc Zyngier static struct irq_chip gic_eoimode1_chip = { 7790b6a3da9SMarc Zyngier .name = "GICv3", 7800b6a3da9SMarc Zyngier .irq_mask = gic_eoimode1_mask_irq, 7810b6a3da9SMarc Zyngier .irq_unmask = gic_unmask_irq, 7820b6a3da9SMarc Zyngier .irq_eoi = gic_eoimode1_eoi_irq, 7830b6a3da9SMarc Zyngier .irq_set_type = gic_set_type, 7840b6a3da9SMarc Zyngier .irq_set_affinity = gic_set_affinity, 7850b6a3da9SMarc Zyngier .irq_get_irqchip_state = gic_irq_get_irqchip_state, 7860b6a3da9SMarc Zyngier .irq_set_irqchip_state = gic_irq_set_irqchip_state, 787530bf353SMarc Zyngier .irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity, 7880b6a3da9SMarc Zyngier .flags = IRQCHIP_SET_TYPE_MASKED, 7890b6a3da9SMarc Zyngier }; 7900b6a3da9SMarc Zyngier 791da33f31dSMarc Zyngier #define GIC_ID_NR (1U << gic_data.rdists.id_bits) 792da33f31dSMarc Zyngier 793021f6537SMarc Zyngier static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq, 794021f6537SMarc Zyngier irq_hw_number_t hw) 795021f6537SMarc Zyngier { 7960b6a3da9SMarc Zyngier struct irq_chip *chip = &gic_chip; 7970b6a3da9SMarc Zyngier 7980b6a3da9SMarc Zyngier if (static_key_true(&supports_deactivate)) 7990b6a3da9SMarc Zyngier chip = &gic_eoimode1_chip; 8000b6a3da9SMarc Zyngier 801021f6537SMarc Zyngier /* SGIs are private to the core kernel */ 802021f6537SMarc Zyngier if (hw < 16) 803021f6537SMarc Zyngier return -EPERM; 804da33f31dSMarc Zyngier /* Nothing here */ 805da33f31dSMarc Zyngier if (hw >= gic_data.irq_nr && hw < 8192) 806da33f31dSMarc Zyngier return -EPERM; 807da33f31dSMarc Zyngier /* Off limits */ 808da33f31dSMarc Zyngier if (hw >= GIC_ID_NR) 809da33f31dSMarc Zyngier return -EPERM; 810da33f31dSMarc Zyngier 811021f6537SMarc Zyngier /* PPIs */ 812021f6537SMarc Zyngier if (hw < 32) { 813021f6537SMarc Zyngier irq_set_percpu_devid(irq); 8140b6a3da9SMarc Zyngier irq_domain_set_info(d, irq, hw, chip, d->host_data, 815443acc4fSMarc Zyngier handle_percpu_devid_irq, NULL, NULL); 816d17cab44SRob Herring irq_set_status_flags(irq, IRQ_NOAUTOEN); 817021f6537SMarc Zyngier } 818021f6537SMarc Zyngier /* SPIs */ 819021f6537SMarc Zyngier if (hw >= 32 && hw < gic_data.irq_nr) { 8200b6a3da9SMarc Zyngier irq_domain_set_info(d, irq, hw, chip, d->host_data, 821443acc4fSMarc Zyngier handle_fasteoi_irq, NULL, NULL); 822d17cab44SRob Herring irq_set_probe(irq); 823956ae91aSMarc Zyngier irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(irq))); 824021f6537SMarc Zyngier } 825da33f31dSMarc Zyngier /* LPIs */ 826da33f31dSMarc Zyngier if (hw >= 8192 && hw < GIC_ID_NR) { 827da33f31dSMarc Zyngier if (!gic_dist_supports_lpis()) 828da33f31dSMarc Zyngier return -EPERM; 8290b6a3da9SMarc Zyngier irq_domain_set_info(d, irq, hw, chip, d->host_data, 830da33f31dSMarc Zyngier handle_fasteoi_irq, NULL, NULL); 831da33f31dSMarc Zyngier } 832da33f31dSMarc Zyngier 833021f6537SMarc Zyngier return 0; 834021f6537SMarc Zyngier } 835021f6537SMarc Zyngier 836f833f57fSMarc Zyngier static int gic_irq_domain_translate(struct irq_domain *d, 837f833f57fSMarc Zyngier struct irq_fwspec *fwspec, 838f833f57fSMarc Zyngier unsigned long *hwirq, 839f833f57fSMarc Zyngier unsigned int *type) 840021f6537SMarc Zyngier { 841f833f57fSMarc Zyngier if (is_of_node(fwspec->fwnode)) { 842f833f57fSMarc Zyngier if (fwspec->param_count < 3) 843021f6537SMarc Zyngier return -EINVAL; 844021f6537SMarc Zyngier 845db8c70ecSMarc Zyngier switch (fwspec->param[0]) { 846db8c70ecSMarc Zyngier case 0: /* SPI */ 847db8c70ecSMarc Zyngier *hwirq = fwspec->param[1] + 32; 848db8c70ecSMarc Zyngier break; 849db8c70ecSMarc Zyngier case 1: /* PPI */ 850f833f57fSMarc Zyngier *hwirq = fwspec->param[1] + 16; 851db8c70ecSMarc Zyngier break; 852db8c70ecSMarc Zyngier case GIC_IRQ_TYPE_LPI: /* LPI */ 853db8c70ecSMarc Zyngier *hwirq = fwspec->param[1]; 854db8c70ecSMarc Zyngier break; 855db8c70ecSMarc Zyngier default: 856db8c70ecSMarc Zyngier return -EINVAL; 857db8c70ecSMarc Zyngier } 858f833f57fSMarc Zyngier 859f833f57fSMarc Zyngier *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; 860f833f57fSMarc Zyngier return 0; 861021f6537SMarc Zyngier } 862021f6537SMarc Zyngier 863ffa7d616STomasz Nowicki if (is_fwnode_irqchip(fwspec->fwnode)) { 864ffa7d616STomasz Nowicki if(fwspec->param_count != 2) 865ffa7d616STomasz Nowicki return -EINVAL; 866ffa7d616STomasz Nowicki 867ffa7d616STomasz Nowicki *hwirq = fwspec->param[0]; 868ffa7d616STomasz Nowicki *type = fwspec->param[1]; 869ffa7d616STomasz Nowicki return 0; 870ffa7d616STomasz Nowicki } 871ffa7d616STomasz Nowicki 872f833f57fSMarc Zyngier return -EINVAL; 873021f6537SMarc Zyngier } 874021f6537SMarc Zyngier 875443acc4fSMarc Zyngier static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, 876443acc4fSMarc Zyngier unsigned int nr_irqs, void *arg) 877443acc4fSMarc Zyngier { 878443acc4fSMarc Zyngier int i, ret; 879443acc4fSMarc Zyngier irq_hw_number_t hwirq; 880443acc4fSMarc Zyngier unsigned int type = IRQ_TYPE_NONE; 881f833f57fSMarc Zyngier struct irq_fwspec *fwspec = arg; 882443acc4fSMarc Zyngier 883f833f57fSMarc Zyngier ret = gic_irq_domain_translate(domain, fwspec, &hwirq, &type); 884443acc4fSMarc Zyngier if (ret) 885443acc4fSMarc Zyngier return ret; 886443acc4fSMarc Zyngier 88763c16c6eSSuzuki K Poulose for (i = 0; i < nr_irqs; i++) { 88863c16c6eSSuzuki K Poulose ret = gic_irq_domain_map(domain, virq + i, hwirq + i); 88963c16c6eSSuzuki K Poulose if (ret) 89063c16c6eSSuzuki K Poulose return ret; 89163c16c6eSSuzuki K Poulose } 892443acc4fSMarc Zyngier 893443acc4fSMarc Zyngier return 0; 894443acc4fSMarc Zyngier } 895443acc4fSMarc Zyngier 896443acc4fSMarc Zyngier static void gic_irq_domain_free(struct irq_domain *domain, unsigned int virq, 897443acc4fSMarc Zyngier unsigned int nr_irqs) 898443acc4fSMarc Zyngier { 899443acc4fSMarc Zyngier int i; 900443acc4fSMarc Zyngier 901443acc4fSMarc Zyngier for (i = 0; i < nr_irqs; i++) { 902443acc4fSMarc Zyngier struct irq_data *d = irq_domain_get_irq_data(domain, virq + i); 903443acc4fSMarc Zyngier irq_set_handler(virq + i, NULL); 904443acc4fSMarc Zyngier irq_domain_reset_irq_data(d); 905443acc4fSMarc Zyngier } 906443acc4fSMarc Zyngier } 907443acc4fSMarc Zyngier 908e3825ba1SMarc Zyngier static int gic_irq_domain_select(struct irq_domain *d, 909e3825ba1SMarc Zyngier struct irq_fwspec *fwspec, 910e3825ba1SMarc Zyngier enum irq_domain_bus_token bus_token) 911e3825ba1SMarc Zyngier { 912e3825ba1SMarc Zyngier /* Not for us */ 913e3825ba1SMarc Zyngier if (fwspec->fwnode != d->fwnode) 914e3825ba1SMarc Zyngier return 0; 915e3825ba1SMarc Zyngier 916e3825ba1SMarc Zyngier /* If this is not DT, then we have a single domain */ 917e3825ba1SMarc Zyngier if (!is_of_node(fwspec->fwnode)) 918e3825ba1SMarc Zyngier return 1; 919e3825ba1SMarc Zyngier 920e3825ba1SMarc Zyngier /* 921e3825ba1SMarc Zyngier * If this is a PPI and we have a 4th (non-null) parameter, 922e3825ba1SMarc Zyngier * then we need to match the partition domain. 923e3825ba1SMarc Zyngier */ 924e3825ba1SMarc Zyngier if (fwspec->param_count >= 4 && 925e3825ba1SMarc Zyngier fwspec->param[0] == 1 && fwspec->param[3] != 0) 926e3825ba1SMarc Zyngier return d == partition_get_domain(gic_data.ppi_descs[fwspec->param[1]]); 927e3825ba1SMarc Zyngier 928e3825ba1SMarc Zyngier return d == gic_data.domain; 929e3825ba1SMarc Zyngier } 930e3825ba1SMarc Zyngier 931021f6537SMarc Zyngier static const struct irq_domain_ops gic_irq_domain_ops = { 932f833f57fSMarc Zyngier .translate = gic_irq_domain_translate, 933443acc4fSMarc Zyngier .alloc = gic_irq_domain_alloc, 934443acc4fSMarc Zyngier .free = gic_irq_domain_free, 935e3825ba1SMarc Zyngier .select = gic_irq_domain_select, 936e3825ba1SMarc Zyngier }; 937e3825ba1SMarc Zyngier 938e3825ba1SMarc Zyngier static int partition_domain_translate(struct irq_domain *d, 939e3825ba1SMarc Zyngier struct irq_fwspec *fwspec, 940e3825ba1SMarc Zyngier unsigned long *hwirq, 941e3825ba1SMarc Zyngier unsigned int *type) 942e3825ba1SMarc Zyngier { 943e3825ba1SMarc Zyngier struct device_node *np; 944e3825ba1SMarc Zyngier int ret; 945e3825ba1SMarc Zyngier 946e3825ba1SMarc Zyngier np = of_find_node_by_phandle(fwspec->param[3]); 947e3825ba1SMarc Zyngier if (WARN_ON(!np)) 948e3825ba1SMarc Zyngier return -EINVAL; 949e3825ba1SMarc Zyngier 950e3825ba1SMarc Zyngier ret = partition_translate_id(gic_data.ppi_descs[fwspec->param[1]], 951e3825ba1SMarc Zyngier of_node_to_fwnode(np)); 952e3825ba1SMarc Zyngier if (ret < 0) 953e3825ba1SMarc Zyngier return ret; 954e3825ba1SMarc Zyngier 955e3825ba1SMarc Zyngier *hwirq = ret; 956e3825ba1SMarc Zyngier *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; 957e3825ba1SMarc Zyngier 958e3825ba1SMarc Zyngier return 0; 959e3825ba1SMarc Zyngier } 960e3825ba1SMarc Zyngier 961e3825ba1SMarc Zyngier static const struct irq_domain_ops partition_domain_ops = { 962e3825ba1SMarc Zyngier .translate = partition_domain_translate, 963e3825ba1SMarc Zyngier .select = gic_irq_domain_select, 964021f6537SMarc Zyngier }; 965021f6537SMarc Zyngier 966db57d746STomasz Nowicki static int __init gic_init_bases(void __iomem *dist_base, 967db57d746STomasz Nowicki struct redist_region *rdist_regs, 968db57d746STomasz Nowicki u32 nr_redist_regions, 969db57d746STomasz Nowicki u64 redist_stride, 970db57d746STomasz Nowicki struct fwnode_handle *handle) 971db57d746STomasz Nowicki { 972db57d746STomasz Nowicki u32 typer; 973db57d746STomasz Nowicki int gic_irqs; 974db57d746STomasz Nowicki int err; 975db57d746STomasz Nowicki 976db57d746STomasz Nowicki if (!is_hyp_mode_available()) 977db57d746STomasz Nowicki static_key_slow_dec(&supports_deactivate); 978db57d746STomasz Nowicki 979db57d746STomasz Nowicki if (static_key_true(&supports_deactivate)) 980db57d746STomasz Nowicki pr_info("GIC: Using split EOI/Deactivate mode\n"); 981db57d746STomasz Nowicki 982e3825ba1SMarc Zyngier gic_data.fwnode = handle; 983db57d746STomasz Nowicki gic_data.dist_base = dist_base; 984db57d746STomasz Nowicki gic_data.redist_regions = rdist_regs; 985db57d746STomasz Nowicki gic_data.nr_redist_regions = nr_redist_regions; 986db57d746STomasz Nowicki gic_data.redist_stride = redist_stride; 987db57d746STomasz Nowicki 988db57d746STomasz Nowicki /* 989db57d746STomasz Nowicki * Find out how many interrupts are supported. 990db57d746STomasz Nowicki * The GIC only supports up to 1020 interrupt sources (SGI+PPI+SPI) 991db57d746STomasz Nowicki */ 992db57d746STomasz Nowicki typer = readl_relaxed(gic_data.dist_base + GICD_TYPER); 993db57d746STomasz Nowicki gic_data.rdists.id_bits = GICD_TYPER_ID_BITS(typer); 994db57d746STomasz Nowicki gic_irqs = GICD_TYPER_IRQS(typer); 995db57d746STomasz Nowicki if (gic_irqs > 1020) 996db57d746STomasz Nowicki gic_irqs = 1020; 997db57d746STomasz Nowicki gic_data.irq_nr = gic_irqs; 998db57d746STomasz Nowicki 999db57d746STomasz Nowicki gic_data.domain = irq_domain_create_tree(handle, &gic_irq_domain_ops, 1000db57d746STomasz Nowicki &gic_data); 1001db57d746STomasz Nowicki gic_data.rdists.rdist = alloc_percpu(typeof(*gic_data.rdists.rdist)); 10020edc23eaSMarc Zyngier gic_data.rdists.has_vlpis = true; 10030edc23eaSMarc Zyngier gic_data.rdists.has_direct_lpi = true; 1004db57d746STomasz Nowicki 1005db57d746STomasz Nowicki if (WARN_ON(!gic_data.domain) || WARN_ON(!gic_data.rdists.rdist)) { 1006db57d746STomasz Nowicki err = -ENOMEM; 1007db57d746STomasz Nowicki goto out_free; 1008db57d746STomasz Nowicki } 1009db57d746STomasz Nowicki 1010db57d746STomasz Nowicki set_handle_irq(gic_handle_irq); 1011db57d746STomasz Nowicki 10120edc23eaSMarc Zyngier gic_update_vlpi_properties(); 10130edc23eaSMarc Zyngier 1014db40f0a7STomasz Nowicki if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis()) 1015db40f0a7STomasz Nowicki its_init(handle, &gic_data.rdists, gic_data.domain); 1016db57d746STomasz Nowicki 1017db57d746STomasz Nowicki gic_smp_init(); 1018db57d746STomasz Nowicki gic_dist_init(); 1019db57d746STomasz Nowicki gic_cpu_init(); 1020db57d746STomasz Nowicki gic_cpu_pm_init(); 1021db57d746STomasz Nowicki 1022db57d746STomasz Nowicki return 0; 1023db57d746STomasz Nowicki 1024db57d746STomasz Nowicki out_free: 1025db57d746STomasz Nowicki if (gic_data.domain) 1026db57d746STomasz Nowicki irq_domain_remove(gic_data.domain); 1027db57d746STomasz Nowicki free_percpu(gic_data.rdists.rdist); 1028db57d746STomasz Nowicki return err; 1029db57d746STomasz Nowicki } 1030db57d746STomasz Nowicki 1031db57d746STomasz Nowicki static int __init gic_validate_dist_version(void __iomem *dist_base) 1032db57d746STomasz Nowicki { 1033db57d746STomasz Nowicki u32 reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK; 1034db57d746STomasz Nowicki 1035db57d746STomasz Nowicki if (reg != GIC_PIDR2_ARCH_GICv3 && reg != GIC_PIDR2_ARCH_GICv4) 1036db57d746STomasz Nowicki return -ENODEV; 1037db57d746STomasz Nowicki 1038db57d746STomasz Nowicki return 0; 1039db57d746STomasz Nowicki } 1040db57d746STomasz Nowicki 1041e3825ba1SMarc Zyngier static int get_cpu_number(struct device_node *dn) 1042e3825ba1SMarc Zyngier { 1043e3825ba1SMarc Zyngier const __be32 *cell; 1044e3825ba1SMarc Zyngier u64 hwid; 10453fad4cdaSzijun_hu int cpu; 1046e3825ba1SMarc Zyngier 1047e3825ba1SMarc Zyngier cell = of_get_property(dn, "reg", NULL); 1048e3825ba1SMarc Zyngier if (!cell) 1049e3825ba1SMarc Zyngier return -1; 1050e3825ba1SMarc Zyngier 1051e3825ba1SMarc Zyngier hwid = of_read_number(cell, of_n_addr_cells(dn)); 1052e3825ba1SMarc Zyngier 1053e3825ba1SMarc Zyngier /* 1054e3825ba1SMarc Zyngier * Non affinity bits must be set to 0 in the DT 1055e3825ba1SMarc Zyngier */ 1056e3825ba1SMarc Zyngier if (hwid & ~MPIDR_HWID_BITMASK) 1057e3825ba1SMarc Zyngier return -1; 1058e3825ba1SMarc Zyngier 10593fad4cdaSzijun_hu for_each_possible_cpu(cpu) 10603fad4cdaSzijun_hu if (cpu_logical_map(cpu) == hwid) 10613fad4cdaSzijun_hu return cpu; 1062e3825ba1SMarc Zyngier 1063e3825ba1SMarc Zyngier return -1; 1064e3825ba1SMarc Zyngier } 1065e3825ba1SMarc Zyngier 1066e3825ba1SMarc Zyngier /* Create all possible partitions at boot time */ 10677beaa24bSLinus Torvalds static void __init gic_populate_ppi_partitions(struct device_node *gic_node) 1068e3825ba1SMarc Zyngier { 1069e3825ba1SMarc Zyngier struct device_node *parts_node, *child_part; 1070e3825ba1SMarc Zyngier int part_idx = 0, i; 1071e3825ba1SMarc Zyngier int nr_parts; 1072e3825ba1SMarc Zyngier struct partition_affinity *parts; 1073e3825ba1SMarc Zyngier 1074e3825ba1SMarc Zyngier parts_node = of_find_node_by_name(gic_node, "ppi-partitions"); 1075e3825ba1SMarc Zyngier if (!parts_node) 1076e3825ba1SMarc Zyngier return; 1077e3825ba1SMarc Zyngier 1078e3825ba1SMarc Zyngier nr_parts = of_get_child_count(parts_node); 1079e3825ba1SMarc Zyngier 1080e3825ba1SMarc Zyngier if (!nr_parts) 1081e3825ba1SMarc Zyngier return; 1082e3825ba1SMarc Zyngier 1083e3825ba1SMarc Zyngier parts = kzalloc(sizeof(*parts) * nr_parts, GFP_KERNEL); 1084e3825ba1SMarc Zyngier if (WARN_ON(!parts)) 1085e3825ba1SMarc Zyngier return; 1086e3825ba1SMarc Zyngier 1087e3825ba1SMarc Zyngier for_each_child_of_node(parts_node, child_part) { 1088e3825ba1SMarc Zyngier struct partition_affinity *part; 1089e3825ba1SMarc Zyngier int n; 1090e3825ba1SMarc Zyngier 1091e3825ba1SMarc Zyngier part = &parts[part_idx]; 1092e3825ba1SMarc Zyngier 1093e3825ba1SMarc Zyngier part->partition_id = of_node_to_fwnode(child_part); 1094e3825ba1SMarc Zyngier 1095e3825ba1SMarc Zyngier pr_info("GIC: PPI partition %s[%d] { ", 1096e3825ba1SMarc Zyngier child_part->name, part_idx); 1097e3825ba1SMarc Zyngier 1098e3825ba1SMarc Zyngier n = of_property_count_elems_of_size(child_part, "affinity", 1099e3825ba1SMarc Zyngier sizeof(u32)); 1100e3825ba1SMarc Zyngier WARN_ON(n <= 0); 1101e3825ba1SMarc Zyngier 1102e3825ba1SMarc Zyngier for (i = 0; i < n; i++) { 1103e3825ba1SMarc Zyngier int err, cpu; 1104e3825ba1SMarc Zyngier u32 cpu_phandle; 1105e3825ba1SMarc Zyngier struct device_node *cpu_node; 1106e3825ba1SMarc Zyngier 1107e3825ba1SMarc Zyngier err = of_property_read_u32_index(child_part, "affinity", 1108e3825ba1SMarc Zyngier i, &cpu_phandle); 1109e3825ba1SMarc Zyngier if (WARN_ON(err)) 1110e3825ba1SMarc Zyngier continue; 1111e3825ba1SMarc Zyngier 1112e3825ba1SMarc Zyngier cpu_node = of_find_node_by_phandle(cpu_phandle); 1113e3825ba1SMarc Zyngier if (WARN_ON(!cpu_node)) 1114e3825ba1SMarc Zyngier continue; 1115e3825ba1SMarc Zyngier 1116e3825ba1SMarc Zyngier cpu = get_cpu_number(cpu_node); 1117e3825ba1SMarc Zyngier if (WARN_ON(cpu == -1)) 1118e3825ba1SMarc Zyngier continue; 1119e3825ba1SMarc Zyngier 1120e81f54c6SRob Herring pr_cont("%pOF[%d] ", cpu_node, cpu); 1121e3825ba1SMarc Zyngier 1122e3825ba1SMarc Zyngier cpumask_set_cpu(cpu, &part->mask); 1123e3825ba1SMarc Zyngier } 1124e3825ba1SMarc Zyngier 1125e3825ba1SMarc Zyngier pr_cont("}\n"); 1126e3825ba1SMarc Zyngier part_idx++; 1127e3825ba1SMarc Zyngier } 1128e3825ba1SMarc Zyngier 1129e3825ba1SMarc Zyngier for (i = 0; i < 16; i++) { 1130e3825ba1SMarc Zyngier unsigned int irq; 1131e3825ba1SMarc Zyngier struct partition_desc *desc; 1132e3825ba1SMarc Zyngier struct irq_fwspec ppi_fwspec = { 1133e3825ba1SMarc Zyngier .fwnode = gic_data.fwnode, 1134e3825ba1SMarc Zyngier .param_count = 3, 1135e3825ba1SMarc Zyngier .param = { 1136e3825ba1SMarc Zyngier [0] = 1, 1137e3825ba1SMarc Zyngier [1] = i, 1138e3825ba1SMarc Zyngier [2] = IRQ_TYPE_NONE, 1139e3825ba1SMarc Zyngier }, 1140e3825ba1SMarc Zyngier }; 1141e3825ba1SMarc Zyngier 1142e3825ba1SMarc Zyngier irq = irq_create_fwspec_mapping(&ppi_fwspec); 1143e3825ba1SMarc Zyngier if (WARN_ON(!irq)) 1144e3825ba1SMarc Zyngier continue; 1145e3825ba1SMarc Zyngier desc = partition_create_desc(gic_data.fwnode, parts, nr_parts, 1146e3825ba1SMarc Zyngier irq, &partition_domain_ops); 1147e3825ba1SMarc Zyngier if (WARN_ON(!desc)) 1148e3825ba1SMarc Zyngier continue; 1149e3825ba1SMarc Zyngier 1150e3825ba1SMarc Zyngier gic_data.ppi_descs[i] = desc; 1151e3825ba1SMarc Zyngier } 1152e3825ba1SMarc Zyngier } 1153e3825ba1SMarc Zyngier 11541839e576SJulien Grall static void __init gic_of_setup_kvm_info(struct device_node *node) 11551839e576SJulien Grall { 11561839e576SJulien Grall int ret; 11571839e576SJulien Grall struct resource r; 11581839e576SJulien Grall u32 gicv_idx; 11591839e576SJulien Grall 11601839e576SJulien Grall gic_v3_kvm_info.type = GIC_V3; 11611839e576SJulien Grall 11621839e576SJulien Grall gic_v3_kvm_info.maint_irq = irq_of_parse_and_map(node, 0); 11631839e576SJulien Grall if (!gic_v3_kvm_info.maint_irq) 11641839e576SJulien Grall return; 11651839e576SJulien Grall 11661839e576SJulien Grall if (of_property_read_u32(node, "#redistributor-regions", 11671839e576SJulien Grall &gicv_idx)) 11681839e576SJulien Grall gicv_idx = 1; 11691839e576SJulien Grall 11701839e576SJulien Grall gicv_idx += 3; /* Also skip GICD, GICC, GICH */ 11711839e576SJulien Grall ret = of_address_to_resource(node, gicv_idx, &r); 11721839e576SJulien Grall if (!ret) 11731839e576SJulien Grall gic_v3_kvm_info.vcpu = r; 11741839e576SJulien Grall 11754bdf5025SMarc Zyngier gic_v3_kvm_info.has_v4 = gic_data.rdists.has_vlpis; 11761839e576SJulien Grall gic_set_kvm_info(&gic_v3_kvm_info); 11771839e576SJulien Grall } 11781839e576SJulien Grall 1179021f6537SMarc Zyngier static int __init gic_of_init(struct device_node *node, struct device_node *parent) 1180021f6537SMarc Zyngier { 1181021f6537SMarc Zyngier void __iomem *dist_base; 1182f5c1434cSMarc Zyngier struct redist_region *rdist_regs; 1183021f6537SMarc Zyngier u64 redist_stride; 1184f5c1434cSMarc Zyngier u32 nr_redist_regions; 1185db57d746STomasz Nowicki int err, i; 1186021f6537SMarc Zyngier 1187021f6537SMarc Zyngier dist_base = of_iomap(node, 0); 1188021f6537SMarc Zyngier if (!dist_base) { 1189e81f54c6SRob Herring pr_err("%pOF: unable to map gic dist registers\n", node); 1190021f6537SMarc Zyngier return -ENXIO; 1191021f6537SMarc Zyngier } 1192021f6537SMarc Zyngier 1193db57d746STomasz Nowicki err = gic_validate_dist_version(dist_base); 1194db57d746STomasz Nowicki if (err) { 1195e81f54c6SRob Herring pr_err("%pOF: no distributor detected, giving up\n", node); 1196021f6537SMarc Zyngier goto out_unmap_dist; 1197021f6537SMarc Zyngier } 1198021f6537SMarc Zyngier 1199f5c1434cSMarc Zyngier if (of_property_read_u32(node, "#redistributor-regions", &nr_redist_regions)) 1200f5c1434cSMarc Zyngier nr_redist_regions = 1; 1201021f6537SMarc Zyngier 1202f5c1434cSMarc Zyngier rdist_regs = kzalloc(sizeof(*rdist_regs) * nr_redist_regions, GFP_KERNEL); 1203f5c1434cSMarc Zyngier if (!rdist_regs) { 1204021f6537SMarc Zyngier err = -ENOMEM; 1205021f6537SMarc Zyngier goto out_unmap_dist; 1206021f6537SMarc Zyngier } 1207021f6537SMarc Zyngier 1208f5c1434cSMarc Zyngier for (i = 0; i < nr_redist_regions; i++) { 1209f5c1434cSMarc Zyngier struct resource res; 1210f5c1434cSMarc Zyngier int ret; 1211f5c1434cSMarc Zyngier 1212f5c1434cSMarc Zyngier ret = of_address_to_resource(node, 1 + i, &res); 1213f5c1434cSMarc Zyngier rdist_regs[i].redist_base = of_iomap(node, 1 + i); 1214f5c1434cSMarc Zyngier if (ret || !rdist_regs[i].redist_base) { 1215e81f54c6SRob Herring pr_err("%pOF: couldn't map region %d\n", node, i); 1216021f6537SMarc Zyngier err = -ENODEV; 1217021f6537SMarc Zyngier goto out_unmap_rdist; 1218021f6537SMarc Zyngier } 1219f5c1434cSMarc Zyngier rdist_regs[i].phys_base = res.start; 1220021f6537SMarc Zyngier } 1221021f6537SMarc Zyngier 1222021f6537SMarc Zyngier if (of_property_read_u64(node, "redistributor-stride", &redist_stride)) 1223021f6537SMarc Zyngier redist_stride = 0; 1224021f6537SMarc Zyngier 1225db57d746STomasz Nowicki err = gic_init_bases(dist_base, rdist_regs, nr_redist_regions, 1226db57d746STomasz Nowicki redist_stride, &node->fwnode); 1227e3825ba1SMarc Zyngier if (err) 1228e3825ba1SMarc Zyngier goto out_unmap_rdist; 1229e3825ba1SMarc Zyngier 1230e3825ba1SMarc Zyngier gic_populate_ppi_partitions(node); 12311839e576SJulien Grall gic_of_setup_kvm_info(node); 1232021f6537SMarc Zyngier return 0; 1233021f6537SMarc Zyngier 1234021f6537SMarc Zyngier out_unmap_rdist: 1235f5c1434cSMarc Zyngier for (i = 0; i < nr_redist_regions; i++) 1236f5c1434cSMarc Zyngier if (rdist_regs[i].redist_base) 1237f5c1434cSMarc Zyngier iounmap(rdist_regs[i].redist_base); 1238f5c1434cSMarc Zyngier kfree(rdist_regs); 1239021f6537SMarc Zyngier out_unmap_dist: 1240021f6537SMarc Zyngier iounmap(dist_base); 1241021f6537SMarc Zyngier return err; 1242021f6537SMarc Zyngier } 1243021f6537SMarc Zyngier 1244021f6537SMarc Zyngier IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init); 1245ffa7d616STomasz Nowicki 1246ffa7d616STomasz Nowicki #ifdef CONFIG_ACPI 1247611f039fSJulien Grall static struct 1248611f039fSJulien Grall { 1249611f039fSJulien Grall void __iomem *dist_base; 1250611f039fSJulien Grall struct redist_region *redist_regs; 1251611f039fSJulien Grall u32 nr_redist_regions; 1252611f039fSJulien Grall bool single_redist; 12531839e576SJulien Grall u32 maint_irq; 12541839e576SJulien Grall int maint_irq_mode; 12551839e576SJulien Grall phys_addr_t vcpu_base; 1256611f039fSJulien Grall } acpi_data __initdata; 1257b70fb7afSTomasz Nowicki 1258b70fb7afSTomasz Nowicki static void __init 1259b70fb7afSTomasz Nowicki gic_acpi_register_redist(phys_addr_t phys_base, void __iomem *redist_base) 1260b70fb7afSTomasz Nowicki { 1261b70fb7afSTomasz Nowicki static int count = 0; 1262b70fb7afSTomasz Nowicki 1263611f039fSJulien Grall acpi_data.redist_regs[count].phys_base = phys_base; 1264611f039fSJulien Grall acpi_data.redist_regs[count].redist_base = redist_base; 1265611f039fSJulien Grall acpi_data.redist_regs[count].single_redist = acpi_data.single_redist; 1266b70fb7afSTomasz Nowicki count++; 1267b70fb7afSTomasz Nowicki } 1268ffa7d616STomasz Nowicki 1269ffa7d616STomasz Nowicki static int __init 1270ffa7d616STomasz Nowicki gic_acpi_parse_madt_redist(struct acpi_subtable_header *header, 1271ffa7d616STomasz Nowicki const unsigned long end) 1272ffa7d616STomasz Nowicki { 1273ffa7d616STomasz Nowicki struct acpi_madt_generic_redistributor *redist = 1274ffa7d616STomasz Nowicki (struct acpi_madt_generic_redistributor *)header; 1275ffa7d616STomasz Nowicki void __iomem *redist_base; 1276ffa7d616STomasz Nowicki 1277ffa7d616STomasz Nowicki redist_base = ioremap(redist->base_address, redist->length); 1278ffa7d616STomasz Nowicki if (!redist_base) { 1279ffa7d616STomasz Nowicki pr_err("Couldn't map GICR region @%llx\n", redist->base_address); 1280ffa7d616STomasz Nowicki return -ENOMEM; 1281ffa7d616STomasz Nowicki } 1282ffa7d616STomasz Nowicki 1283b70fb7afSTomasz Nowicki gic_acpi_register_redist(redist->base_address, redist_base); 1284ffa7d616STomasz Nowicki return 0; 1285ffa7d616STomasz Nowicki } 1286ffa7d616STomasz Nowicki 1287b70fb7afSTomasz Nowicki static int __init 1288b70fb7afSTomasz Nowicki gic_acpi_parse_madt_gicc(struct acpi_subtable_header *header, 1289b70fb7afSTomasz Nowicki const unsigned long end) 1290b70fb7afSTomasz Nowicki { 1291b70fb7afSTomasz Nowicki struct acpi_madt_generic_interrupt *gicc = 1292b70fb7afSTomasz Nowicki (struct acpi_madt_generic_interrupt *)header; 1293611f039fSJulien Grall u32 reg = readl_relaxed(acpi_data.dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK; 1294b70fb7afSTomasz Nowicki u32 size = reg == GIC_PIDR2_ARCH_GICv4 ? SZ_64K * 4 : SZ_64K * 2; 1295b70fb7afSTomasz Nowicki void __iomem *redist_base; 1296b70fb7afSTomasz Nowicki 1297b70fb7afSTomasz Nowicki redist_base = ioremap(gicc->gicr_base_address, size); 1298b70fb7afSTomasz Nowicki if (!redist_base) 1299b70fb7afSTomasz Nowicki return -ENOMEM; 1300b70fb7afSTomasz Nowicki 1301b70fb7afSTomasz Nowicki gic_acpi_register_redist(gicc->gicr_base_address, redist_base); 1302b70fb7afSTomasz Nowicki return 0; 1303b70fb7afSTomasz Nowicki } 1304b70fb7afSTomasz Nowicki 1305b70fb7afSTomasz Nowicki static int __init gic_acpi_collect_gicr_base(void) 1306b70fb7afSTomasz Nowicki { 1307b70fb7afSTomasz Nowicki acpi_tbl_entry_handler redist_parser; 1308b70fb7afSTomasz Nowicki enum acpi_madt_type type; 1309b70fb7afSTomasz Nowicki 1310611f039fSJulien Grall if (acpi_data.single_redist) { 1311b70fb7afSTomasz Nowicki type = ACPI_MADT_TYPE_GENERIC_INTERRUPT; 1312b70fb7afSTomasz Nowicki redist_parser = gic_acpi_parse_madt_gicc; 1313b70fb7afSTomasz Nowicki } else { 1314b70fb7afSTomasz Nowicki type = ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR; 1315b70fb7afSTomasz Nowicki redist_parser = gic_acpi_parse_madt_redist; 1316b70fb7afSTomasz Nowicki } 1317b70fb7afSTomasz Nowicki 1318b70fb7afSTomasz Nowicki /* Collect redistributor base addresses in GICR entries */ 1319b70fb7afSTomasz Nowicki if (acpi_table_parse_madt(type, redist_parser, 0) > 0) 1320b70fb7afSTomasz Nowicki return 0; 1321b70fb7afSTomasz Nowicki 1322b70fb7afSTomasz Nowicki pr_info("No valid GICR entries exist\n"); 1323b70fb7afSTomasz Nowicki return -ENODEV; 1324b70fb7afSTomasz Nowicki } 1325b70fb7afSTomasz Nowicki 1326ffa7d616STomasz Nowicki static int __init gic_acpi_match_gicr(struct acpi_subtable_header *header, 1327ffa7d616STomasz Nowicki const unsigned long end) 1328ffa7d616STomasz Nowicki { 1329ffa7d616STomasz Nowicki /* Subtable presence means that redist exists, that's it */ 1330ffa7d616STomasz Nowicki return 0; 1331ffa7d616STomasz Nowicki } 1332ffa7d616STomasz Nowicki 1333b70fb7afSTomasz Nowicki static int __init gic_acpi_match_gicc(struct acpi_subtable_header *header, 1334b70fb7afSTomasz Nowicki const unsigned long end) 1335b70fb7afSTomasz Nowicki { 1336b70fb7afSTomasz Nowicki struct acpi_madt_generic_interrupt *gicc = 1337b70fb7afSTomasz Nowicki (struct acpi_madt_generic_interrupt *)header; 1338b70fb7afSTomasz Nowicki 1339b70fb7afSTomasz Nowicki /* 1340b70fb7afSTomasz Nowicki * If GICC is enabled and has valid gicr base address, then it means 1341b70fb7afSTomasz Nowicki * GICR base is presented via GICC 1342b70fb7afSTomasz Nowicki */ 1343b70fb7afSTomasz Nowicki if ((gicc->flags & ACPI_MADT_ENABLED) && gicc->gicr_base_address) 1344b70fb7afSTomasz Nowicki return 0; 1345b70fb7afSTomasz Nowicki 1346b70fb7afSTomasz Nowicki return -ENODEV; 1347b70fb7afSTomasz Nowicki } 1348b70fb7afSTomasz Nowicki 1349b70fb7afSTomasz Nowicki static int __init gic_acpi_count_gicr_regions(void) 1350b70fb7afSTomasz Nowicki { 1351b70fb7afSTomasz Nowicki int count; 1352b70fb7afSTomasz Nowicki 1353b70fb7afSTomasz Nowicki /* 1354b70fb7afSTomasz Nowicki * Count how many redistributor regions we have. It is not allowed 1355b70fb7afSTomasz Nowicki * to mix redistributor description, GICR and GICC subtables have to be 1356b70fb7afSTomasz Nowicki * mutually exclusive. 1357b70fb7afSTomasz Nowicki */ 1358b70fb7afSTomasz Nowicki count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR, 1359b70fb7afSTomasz Nowicki gic_acpi_match_gicr, 0); 1360b70fb7afSTomasz Nowicki if (count > 0) { 1361611f039fSJulien Grall acpi_data.single_redist = false; 1362b70fb7afSTomasz Nowicki return count; 1363b70fb7afSTomasz Nowicki } 1364b70fb7afSTomasz Nowicki 1365b70fb7afSTomasz Nowicki count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT, 1366b70fb7afSTomasz Nowicki gic_acpi_match_gicc, 0); 1367b70fb7afSTomasz Nowicki if (count > 0) 1368611f039fSJulien Grall acpi_data.single_redist = true; 1369b70fb7afSTomasz Nowicki 1370b70fb7afSTomasz Nowicki return count; 1371b70fb7afSTomasz Nowicki } 1372b70fb7afSTomasz Nowicki 1373ffa7d616STomasz Nowicki static bool __init acpi_validate_gic_table(struct acpi_subtable_header *header, 1374ffa7d616STomasz Nowicki struct acpi_probe_entry *ape) 1375ffa7d616STomasz Nowicki { 1376ffa7d616STomasz Nowicki struct acpi_madt_generic_distributor *dist; 1377ffa7d616STomasz Nowicki int count; 1378ffa7d616STomasz Nowicki 1379ffa7d616STomasz Nowicki dist = (struct acpi_madt_generic_distributor *)header; 1380ffa7d616STomasz Nowicki if (dist->version != ape->driver_data) 1381ffa7d616STomasz Nowicki return false; 1382ffa7d616STomasz Nowicki 1383ffa7d616STomasz Nowicki /* We need to do that exercise anyway, the sooner the better */ 1384b70fb7afSTomasz Nowicki count = gic_acpi_count_gicr_regions(); 1385ffa7d616STomasz Nowicki if (count <= 0) 1386ffa7d616STomasz Nowicki return false; 1387ffa7d616STomasz Nowicki 1388611f039fSJulien Grall acpi_data.nr_redist_regions = count; 1389ffa7d616STomasz Nowicki return true; 1390ffa7d616STomasz Nowicki } 1391ffa7d616STomasz Nowicki 13921839e576SJulien Grall static int __init gic_acpi_parse_virt_madt_gicc(struct acpi_subtable_header *header, 13931839e576SJulien Grall const unsigned long end) 13941839e576SJulien Grall { 13951839e576SJulien Grall struct acpi_madt_generic_interrupt *gicc = 13961839e576SJulien Grall (struct acpi_madt_generic_interrupt *)header; 13971839e576SJulien Grall int maint_irq_mode; 13981839e576SJulien Grall static int first_madt = true; 13991839e576SJulien Grall 14001839e576SJulien Grall /* Skip unusable CPUs */ 14011839e576SJulien Grall if (!(gicc->flags & ACPI_MADT_ENABLED)) 14021839e576SJulien Grall return 0; 14031839e576SJulien Grall 14041839e576SJulien Grall maint_irq_mode = (gicc->flags & ACPI_MADT_VGIC_IRQ_MODE) ? 14051839e576SJulien Grall ACPI_EDGE_SENSITIVE : ACPI_LEVEL_SENSITIVE; 14061839e576SJulien Grall 14071839e576SJulien Grall if (first_madt) { 14081839e576SJulien Grall first_madt = false; 14091839e576SJulien Grall 14101839e576SJulien Grall acpi_data.maint_irq = gicc->vgic_interrupt; 14111839e576SJulien Grall acpi_data.maint_irq_mode = maint_irq_mode; 14121839e576SJulien Grall acpi_data.vcpu_base = gicc->gicv_base_address; 14131839e576SJulien Grall 14141839e576SJulien Grall return 0; 14151839e576SJulien Grall } 14161839e576SJulien Grall 14171839e576SJulien Grall /* 14181839e576SJulien Grall * The maintenance interrupt and GICV should be the same for every CPU 14191839e576SJulien Grall */ 14201839e576SJulien Grall if ((acpi_data.maint_irq != gicc->vgic_interrupt) || 14211839e576SJulien Grall (acpi_data.maint_irq_mode != maint_irq_mode) || 14221839e576SJulien Grall (acpi_data.vcpu_base != gicc->gicv_base_address)) 14231839e576SJulien Grall return -EINVAL; 14241839e576SJulien Grall 14251839e576SJulien Grall return 0; 14261839e576SJulien Grall } 14271839e576SJulien Grall 14281839e576SJulien Grall static bool __init gic_acpi_collect_virt_info(void) 14291839e576SJulien Grall { 14301839e576SJulien Grall int count; 14311839e576SJulien Grall 14321839e576SJulien Grall count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT, 14331839e576SJulien Grall gic_acpi_parse_virt_madt_gicc, 0); 14341839e576SJulien Grall 14351839e576SJulien Grall return (count > 0); 14361839e576SJulien Grall } 14371839e576SJulien Grall 1438ffa7d616STomasz Nowicki #define ACPI_GICV3_DIST_MEM_SIZE (SZ_64K) 14391839e576SJulien Grall #define ACPI_GICV2_VCTRL_MEM_SIZE (SZ_4K) 14401839e576SJulien Grall #define ACPI_GICV2_VCPU_MEM_SIZE (SZ_8K) 14411839e576SJulien Grall 14421839e576SJulien Grall static void __init gic_acpi_setup_kvm_info(void) 14431839e576SJulien Grall { 14441839e576SJulien Grall int irq; 14451839e576SJulien Grall 14461839e576SJulien Grall if (!gic_acpi_collect_virt_info()) { 14471839e576SJulien Grall pr_warn("Unable to get hardware information used for virtualization\n"); 14481839e576SJulien Grall return; 14491839e576SJulien Grall } 14501839e576SJulien Grall 14511839e576SJulien Grall gic_v3_kvm_info.type = GIC_V3; 14521839e576SJulien Grall 14531839e576SJulien Grall irq = acpi_register_gsi(NULL, acpi_data.maint_irq, 14541839e576SJulien Grall acpi_data.maint_irq_mode, 14551839e576SJulien Grall ACPI_ACTIVE_HIGH); 14561839e576SJulien Grall if (irq <= 0) 14571839e576SJulien Grall return; 14581839e576SJulien Grall 14591839e576SJulien Grall gic_v3_kvm_info.maint_irq = irq; 14601839e576SJulien Grall 14611839e576SJulien Grall if (acpi_data.vcpu_base) { 14621839e576SJulien Grall struct resource *vcpu = &gic_v3_kvm_info.vcpu; 14631839e576SJulien Grall 14641839e576SJulien Grall vcpu->flags = IORESOURCE_MEM; 14651839e576SJulien Grall vcpu->start = acpi_data.vcpu_base; 14661839e576SJulien Grall vcpu->end = vcpu->start + ACPI_GICV2_VCPU_MEM_SIZE - 1; 14671839e576SJulien Grall } 14681839e576SJulien Grall 14694bdf5025SMarc Zyngier gic_v3_kvm_info.has_v4 = gic_data.rdists.has_vlpis; 14701839e576SJulien Grall gic_set_kvm_info(&gic_v3_kvm_info); 14711839e576SJulien Grall } 1472ffa7d616STomasz Nowicki 1473ffa7d616STomasz Nowicki static int __init 1474ffa7d616STomasz Nowicki gic_acpi_init(struct acpi_subtable_header *header, const unsigned long end) 1475ffa7d616STomasz Nowicki { 1476ffa7d616STomasz Nowicki struct acpi_madt_generic_distributor *dist; 1477ffa7d616STomasz Nowicki struct fwnode_handle *domain_handle; 1478611f039fSJulien Grall size_t size; 1479b70fb7afSTomasz Nowicki int i, err; 1480ffa7d616STomasz Nowicki 1481ffa7d616STomasz Nowicki /* Get distributor base address */ 1482ffa7d616STomasz Nowicki dist = (struct acpi_madt_generic_distributor *)header; 1483611f039fSJulien Grall acpi_data.dist_base = ioremap(dist->base_address, 1484611f039fSJulien Grall ACPI_GICV3_DIST_MEM_SIZE); 1485611f039fSJulien Grall if (!acpi_data.dist_base) { 1486ffa7d616STomasz Nowicki pr_err("Unable to map GICD registers\n"); 1487ffa7d616STomasz Nowicki return -ENOMEM; 1488ffa7d616STomasz Nowicki } 1489ffa7d616STomasz Nowicki 1490611f039fSJulien Grall err = gic_validate_dist_version(acpi_data.dist_base); 1491ffa7d616STomasz Nowicki if (err) { 1492611f039fSJulien Grall pr_err("No distributor detected at @%p, giving up", 1493611f039fSJulien Grall acpi_data.dist_base); 1494ffa7d616STomasz Nowicki goto out_dist_unmap; 1495ffa7d616STomasz Nowicki } 1496ffa7d616STomasz Nowicki 1497611f039fSJulien Grall size = sizeof(*acpi_data.redist_regs) * acpi_data.nr_redist_regions; 1498611f039fSJulien Grall acpi_data.redist_regs = kzalloc(size, GFP_KERNEL); 1499611f039fSJulien Grall if (!acpi_data.redist_regs) { 1500ffa7d616STomasz Nowicki err = -ENOMEM; 1501ffa7d616STomasz Nowicki goto out_dist_unmap; 1502ffa7d616STomasz Nowicki } 1503ffa7d616STomasz Nowicki 1504b70fb7afSTomasz Nowicki err = gic_acpi_collect_gicr_base(); 1505b70fb7afSTomasz Nowicki if (err) 1506ffa7d616STomasz Nowicki goto out_redist_unmap; 1507ffa7d616STomasz Nowicki 1508611f039fSJulien Grall domain_handle = irq_domain_alloc_fwnode(acpi_data.dist_base); 1509ffa7d616STomasz Nowicki if (!domain_handle) { 1510ffa7d616STomasz Nowicki err = -ENOMEM; 1511ffa7d616STomasz Nowicki goto out_redist_unmap; 1512ffa7d616STomasz Nowicki } 1513ffa7d616STomasz Nowicki 1514611f039fSJulien Grall err = gic_init_bases(acpi_data.dist_base, acpi_data.redist_regs, 1515611f039fSJulien Grall acpi_data.nr_redist_regions, 0, domain_handle); 1516ffa7d616STomasz Nowicki if (err) 1517ffa7d616STomasz Nowicki goto out_fwhandle_free; 1518ffa7d616STomasz Nowicki 1519ffa7d616STomasz Nowicki acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, domain_handle); 15201839e576SJulien Grall gic_acpi_setup_kvm_info(); 15211839e576SJulien Grall 1522ffa7d616STomasz Nowicki return 0; 1523ffa7d616STomasz Nowicki 1524ffa7d616STomasz Nowicki out_fwhandle_free: 1525ffa7d616STomasz Nowicki irq_domain_free_fwnode(domain_handle); 1526ffa7d616STomasz Nowicki out_redist_unmap: 1527611f039fSJulien Grall for (i = 0; i < acpi_data.nr_redist_regions; i++) 1528611f039fSJulien Grall if (acpi_data.redist_regs[i].redist_base) 1529611f039fSJulien Grall iounmap(acpi_data.redist_regs[i].redist_base); 1530611f039fSJulien Grall kfree(acpi_data.redist_regs); 1531ffa7d616STomasz Nowicki out_dist_unmap: 1532611f039fSJulien Grall iounmap(acpi_data.dist_base); 1533ffa7d616STomasz Nowicki return err; 1534ffa7d616STomasz Nowicki } 1535ffa7d616STomasz Nowicki IRQCHIP_ACPI_DECLARE(gic_v3, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 1536ffa7d616STomasz Nowicki acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V3, 1537ffa7d616STomasz Nowicki gic_acpi_init); 1538ffa7d616STomasz Nowicki IRQCHIP_ACPI_DECLARE(gic_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 1539ffa7d616STomasz Nowicki acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V4, 1540ffa7d616STomasz Nowicki gic_acpi_init); 1541ffa7d616STomasz Nowicki IRQCHIP_ACPI_DECLARE(gic_v3_or_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 1542ffa7d616STomasz Nowicki acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_NONE, 1543ffa7d616STomasz Nowicki gic_acpi_init); 1544ffa7d616STomasz Nowicki #endif 1545