1caab277bSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 2021f6537SMarc Zyngier /* 30edc23eaSMarc Zyngier * Copyright (C) 2013-2017 ARM Limited, All Rights Reserved. 4021f6537SMarc Zyngier * Author: Marc Zyngier <marc.zyngier@arm.com> 5021f6537SMarc Zyngier */ 6021f6537SMarc Zyngier 768628bb8SJulien Grall #define pr_fmt(fmt) "GICv3: " fmt 868628bb8SJulien Grall 9ffa7d616STomasz Nowicki #include <linux/acpi.h> 10021f6537SMarc Zyngier #include <linux/cpu.h> 113708d52fSSudeep Holla #include <linux/cpu_pm.h> 12021f6537SMarc Zyngier #include <linux/delay.h> 13021f6537SMarc Zyngier #include <linux/interrupt.h> 14ffa7d616STomasz Nowicki #include <linux/irqdomain.h> 15021f6537SMarc Zyngier #include <linux/of.h> 16021f6537SMarc Zyngier #include <linux/of_address.h> 17021f6537SMarc Zyngier #include <linux/of_irq.h> 18021f6537SMarc Zyngier #include <linux/percpu.h> 19101b35f7SJulien Thierry #include <linux/refcount.h> 20021f6537SMarc Zyngier #include <linux/slab.h> 21021f6537SMarc Zyngier 2241a83e06SJoel Porquet #include <linux/irqchip.h> 231839e576SJulien Grall #include <linux/irqchip/arm-gic-common.h> 24021f6537SMarc Zyngier #include <linux/irqchip/arm-gic-v3.h> 25e3825ba1SMarc Zyngier #include <linux/irqchip/irq-partition-percpu.h> 26021f6537SMarc Zyngier 27021f6537SMarc Zyngier #include <asm/cputype.h> 28021f6537SMarc Zyngier #include <asm/exception.h> 29021f6537SMarc Zyngier #include <asm/smp_plat.h> 300b6a3da9SMarc Zyngier #include <asm/virt.h> 31021f6537SMarc Zyngier 32021f6537SMarc Zyngier #include "irq-gic-common.h" 33021f6537SMarc Zyngier 34f32c9266SJulien Thierry #define GICD_INT_NMI_PRI (GICD_INT_DEF_PRI & ~0x80) 35f32c9266SJulien Thierry 369c8114c2SSrinivas Kandagatla #define FLAGS_WORKAROUND_GICR_WAKER_MSM8996 (1ULL << 0) 37d01fd161SMarc Zyngier #define FLAGS_WORKAROUND_CAVIUM_ERRATUM_38539 (1ULL << 1) 389c8114c2SSrinivas Kandagatla 3964b499d8SMarc Zyngier #define GIC_IRQ_TYPE_PARTITION (GIC_IRQ_TYPE_LPI + 1) 4064b499d8SMarc Zyngier 41f5c1434cSMarc Zyngier struct redist_region { 42f5c1434cSMarc Zyngier void __iomem *redist_base; 43f5c1434cSMarc Zyngier phys_addr_t phys_base; 44b70fb7afSTomasz Nowicki bool single_redist; 45f5c1434cSMarc Zyngier }; 46f5c1434cSMarc Zyngier 47021f6537SMarc Zyngier struct gic_chip_data { 48e3825ba1SMarc Zyngier struct fwnode_handle *fwnode; 49021f6537SMarc Zyngier void __iomem *dist_base; 50f5c1434cSMarc Zyngier struct redist_region *redist_regions; 51f5c1434cSMarc Zyngier struct rdists rdists; 52021f6537SMarc Zyngier struct irq_domain *domain; 53021f6537SMarc Zyngier u64 redist_stride; 54f5c1434cSMarc Zyngier u32 nr_redist_regions; 559c8114c2SSrinivas Kandagatla u64 flags; 56eda0d04aSShanker Donthineni bool has_rss; 571a60e1e6SMarc Zyngier unsigned int ppi_nr; 5852085d3fSMarc Zyngier struct partition_desc **ppi_descs; 59021f6537SMarc Zyngier }; 60021f6537SMarc Zyngier 61021f6537SMarc Zyngier static struct gic_chip_data gic_data __read_mostly; 62d01d3274SDavidlohr Bueso static DEFINE_STATIC_KEY_TRUE(supports_deactivate_key); 63021f6537SMarc Zyngier 64211bddd2SMarc Zyngier #define GIC_ID_NR (1U << GICD_TYPER_ID_BITS(gic_data.rdists.gicd_typer)) 65c107d613SZenghui Yu #define GIC_LINE_NR min(GICD_TYPER_SPIS(gic_data.rdists.gicd_typer), 1020U) 66211bddd2SMarc Zyngier #define GIC_ESPI_NR GICD_TYPER_ESPIS(gic_data.rdists.gicd_typer) 67211bddd2SMarc Zyngier 68d98d0a99SJulien Thierry /* 69d98d0a99SJulien Thierry * The behaviours of RPR and PMR registers differ depending on the value of 70d98d0a99SJulien Thierry * SCR_EL3.FIQ, and the behaviour of non-secure priority registers of the 71d98d0a99SJulien Thierry * distributor and redistributors depends on whether security is enabled in the 72d98d0a99SJulien Thierry * GIC. 73d98d0a99SJulien Thierry * 74d98d0a99SJulien Thierry * When security is enabled, non-secure priority values from the (re)distributor 75d98d0a99SJulien Thierry * are presented to the GIC CPUIF as follow: 76d98d0a99SJulien Thierry * (GIC_(R)DIST_PRI[irq] >> 1) | 0x80; 77d98d0a99SJulien Thierry * 78d4034114SLorenzo Pieralisi * If SCR_EL3.FIQ == 1, the values written to/read from PMR and RPR at non-secure 79d98d0a99SJulien Thierry * EL1 are subject to a similar operation thus matching the priorities presented 8033678059SAlexandru Elisei * from the (re)distributor when security is enabled. When SCR_EL3.FIQ == 0, 81d4034114SLorenzo Pieralisi * these values are unchanged by the GIC. 82d98d0a99SJulien Thierry * 83d98d0a99SJulien Thierry * see GICv3/GICv4 Architecture Specification (IHI0069D): 84d98d0a99SJulien Thierry * - section 4.8.1 Non-secure accesses to register fields for Secure interrupt 85d98d0a99SJulien Thierry * priorities. 86d98d0a99SJulien Thierry * - Figure 4-7 Secure read of the priority field for a Non-secure Group 1 87d98d0a99SJulien Thierry * interrupt. 88d98d0a99SJulien Thierry */ 89d98d0a99SJulien Thierry static DEFINE_STATIC_KEY_FALSE(supports_pseudo_nmis); 90d98d0a99SJulien Thierry 91f2266504SMarc Zyngier /* 92f2266504SMarc Zyngier * Global static key controlling whether an update to PMR allowing more 93f2266504SMarc Zyngier * interrupts requires to be propagated to the redistributor (DSB SY). 94f2266504SMarc Zyngier * And this needs to be exported for modules to be able to enable 95f2266504SMarc Zyngier * interrupts... 96f2266504SMarc Zyngier */ 97f2266504SMarc Zyngier DEFINE_STATIC_KEY_FALSE(gic_pmr_sync); 98f2266504SMarc Zyngier EXPORT_SYMBOL(gic_pmr_sync); 99f2266504SMarc Zyngier 10033678059SAlexandru Elisei DEFINE_STATIC_KEY_FALSE(gic_nonsecure_priorities); 10133678059SAlexandru Elisei EXPORT_SYMBOL(gic_nonsecure_priorities); 10233678059SAlexandru Elisei 1038d474deaSChen-Yu Tsai /* 1048d474deaSChen-Yu Tsai * When the Non-secure world has access to group 0 interrupts (as a 1058d474deaSChen-Yu Tsai * consequence of SCR_EL3.FIQ == 0), reading the ICC_RPR_EL1 register will 1068d474deaSChen-Yu Tsai * return the Distributor's view of the interrupt priority. 1078d474deaSChen-Yu Tsai * 1088d474deaSChen-Yu Tsai * When GIC security is enabled (GICD_CTLR.DS == 0), the interrupt priority 1098d474deaSChen-Yu Tsai * written by software is moved to the Non-secure range by the Distributor. 1108d474deaSChen-Yu Tsai * 1118d474deaSChen-Yu Tsai * If both are true (which is when gic_nonsecure_priorities gets enabled), 1128d474deaSChen-Yu Tsai * we need to shift down the priority programmed by software to match it 1138d474deaSChen-Yu Tsai * against the value returned by ICC_RPR_EL1. 1148d474deaSChen-Yu Tsai */ 1158d474deaSChen-Yu Tsai #define GICD_INT_RPR_PRI(priority) \ 1168d474deaSChen-Yu Tsai ({ \ 1178d474deaSChen-Yu Tsai u32 __priority = (priority); \ 1188d474deaSChen-Yu Tsai if (static_branch_unlikely(&gic_nonsecure_priorities)) \ 1198d474deaSChen-Yu Tsai __priority = 0x80 | (__priority >> 1); \ 1208d474deaSChen-Yu Tsai \ 1218d474deaSChen-Yu Tsai __priority; \ 1228d474deaSChen-Yu Tsai }) 1238d474deaSChen-Yu Tsai 124101b35f7SJulien Thierry /* ppi_nmi_refs[n] == number of cpus having ppi[n + 16] set as NMI */ 12581a43273SMarc Zyngier static refcount_t *ppi_nmi_refs; 126101b35f7SJulien Thierry 1270e5cb777SMarc Zyngier static struct gic_kvm_info gic_v3_kvm_info __initdata; 128eda0d04aSShanker Donthineni static DEFINE_PER_CPU(bool, has_rss); 1291839e576SJulien Grall 130eda0d04aSShanker Donthineni #define MPIDR_RS(mpidr) (((mpidr) & 0xF0UL) >> 4) 131f5c1434cSMarc Zyngier #define gic_data_rdist() (this_cpu_ptr(gic_data.rdists.rdist)) 132f5c1434cSMarc Zyngier #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base) 133021f6537SMarc Zyngier #define gic_data_rdist_sgi_base() (gic_data_rdist_rd_base() + SZ_64K) 134021f6537SMarc Zyngier 135021f6537SMarc Zyngier /* Our default, arbitrary priority value. Linux only uses one anyway. */ 136021f6537SMarc Zyngier #define DEFAULT_PMR_VALUE 0xf0 137021f6537SMarc Zyngier 138e91b036eSMarc Zyngier enum gic_intid_range { 13970a29c32SMarc Zyngier SGI_RANGE, 140e91b036eSMarc Zyngier PPI_RANGE, 141e91b036eSMarc Zyngier SPI_RANGE, 1425f51f803SMarc Zyngier EPPI_RANGE, 143211bddd2SMarc Zyngier ESPI_RANGE, 144e91b036eSMarc Zyngier LPI_RANGE, 145e91b036eSMarc Zyngier __INVALID_RANGE__ 146e91b036eSMarc Zyngier }; 147e91b036eSMarc Zyngier 148e91b036eSMarc Zyngier static enum gic_intid_range __get_intid_range(irq_hw_number_t hwirq) 149e91b036eSMarc Zyngier { 150e91b036eSMarc Zyngier switch (hwirq) { 15170a29c32SMarc Zyngier case 0 ... 15: 15270a29c32SMarc Zyngier return SGI_RANGE; 153e91b036eSMarc Zyngier case 16 ... 31: 154e91b036eSMarc Zyngier return PPI_RANGE; 155e91b036eSMarc Zyngier case 32 ... 1019: 156e91b036eSMarc Zyngier return SPI_RANGE; 1575f51f803SMarc Zyngier case EPPI_BASE_INTID ... (EPPI_BASE_INTID + 63): 1585f51f803SMarc Zyngier return EPPI_RANGE; 159211bddd2SMarc Zyngier case ESPI_BASE_INTID ... (ESPI_BASE_INTID + 1023): 160211bddd2SMarc Zyngier return ESPI_RANGE; 161e91b036eSMarc Zyngier case 8192 ... GENMASK(23, 0): 162e91b036eSMarc Zyngier return LPI_RANGE; 163e91b036eSMarc Zyngier default: 164e91b036eSMarc Zyngier return __INVALID_RANGE__; 165e91b036eSMarc Zyngier } 166e91b036eSMarc Zyngier } 167e91b036eSMarc Zyngier 168e91b036eSMarc Zyngier static enum gic_intid_range get_intid_range(struct irq_data *d) 169e91b036eSMarc Zyngier { 170e91b036eSMarc Zyngier return __get_intid_range(d->hwirq); 171e91b036eSMarc Zyngier } 172e91b036eSMarc Zyngier 173021f6537SMarc Zyngier static inline unsigned int gic_irq(struct irq_data *d) 174021f6537SMarc Zyngier { 175021f6537SMarc Zyngier return d->hwirq; 176021f6537SMarc Zyngier } 177021f6537SMarc Zyngier 17870a29c32SMarc Zyngier static inline bool gic_irq_in_rdist(struct irq_data *d) 179021f6537SMarc Zyngier { 18070a29c32SMarc Zyngier switch (get_intid_range(d)) { 18170a29c32SMarc Zyngier case SGI_RANGE: 18270a29c32SMarc Zyngier case PPI_RANGE: 18370a29c32SMarc Zyngier case EPPI_RANGE: 18470a29c32SMarc Zyngier return true; 18570a29c32SMarc Zyngier default: 18670a29c32SMarc Zyngier return false; 18770a29c32SMarc Zyngier } 188021f6537SMarc Zyngier } 189021f6537SMarc Zyngier 190021f6537SMarc Zyngier static inline void __iomem *gic_dist_base(struct irq_data *d) 191021f6537SMarc Zyngier { 192e91b036eSMarc Zyngier switch (get_intid_range(d)) { 19370a29c32SMarc Zyngier case SGI_RANGE: 194e91b036eSMarc Zyngier case PPI_RANGE: 1955f51f803SMarc Zyngier case EPPI_RANGE: 196e91b036eSMarc Zyngier /* SGI+PPI -> SGI_base for this CPU */ 197021f6537SMarc Zyngier return gic_data_rdist_sgi_base(); 198021f6537SMarc Zyngier 199e91b036eSMarc Zyngier case SPI_RANGE: 200211bddd2SMarc Zyngier case ESPI_RANGE: 201e91b036eSMarc Zyngier /* SPI -> dist_base */ 202021f6537SMarc Zyngier return gic_data.dist_base; 203021f6537SMarc Zyngier 204e91b036eSMarc Zyngier default: 205021f6537SMarc Zyngier return NULL; 206021f6537SMarc Zyngier } 207e91b036eSMarc Zyngier } 208021f6537SMarc Zyngier 209021f6537SMarc Zyngier static void gic_do_wait_for_rwp(void __iomem *base) 210021f6537SMarc Zyngier { 211021f6537SMarc Zyngier u32 count = 1000000; /* 1s! */ 212021f6537SMarc Zyngier 213021f6537SMarc Zyngier while (readl_relaxed(base + GICD_CTLR) & GICD_CTLR_RWP) { 214021f6537SMarc Zyngier count--; 215021f6537SMarc Zyngier if (!count) { 216021f6537SMarc Zyngier pr_err_ratelimited("RWP timeout, gone fishing\n"); 217021f6537SMarc Zyngier return; 218021f6537SMarc Zyngier } 219021f6537SMarc Zyngier cpu_relax(); 220021f6537SMarc Zyngier udelay(1); 2212c542426SDaode Huang } 222021f6537SMarc Zyngier } 223021f6537SMarc Zyngier 224021f6537SMarc Zyngier /* Wait for completion of a distributor change */ 225021f6537SMarc Zyngier static void gic_dist_wait_for_rwp(void) 226021f6537SMarc Zyngier { 227021f6537SMarc Zyngier gic_do_wait_for_rwp(gic_data.dist_base); 228021f6537SMarc Zyngier } 229021f6537SMarc Zyngier 230021f6537SMarc Zyngier /* Wait for completion of a redistributor change */ 231021f6537SMarc Zyngier static void gic_redist_wait_for_rwp(void) 232021f6537SMarc Zyngier { 233021f6537SMarc Zyngier gic_do_wait_for_rwp(gic_data_rdist_rd_base()); 234021f6537SMarc Zyngier } 235021f6537SMarc Zyngier 2367936e914SJean-Philippe Brucker #ifdef CONFIG_ARM64 2376d4e11c5SRobert Richter 2386d4e11c5SRobert Richter static u64 __maybe_unused gic_read_iar(void) 2396d4e11c5SRobert Richter { 240a4023f68SSuzuki K Poulose if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_23154)) 2416d4e11c5SRobert Richter return gic_read_iar_cavium_thunderx(); 2426d4e11c5SRobert Richter else 2436d4e11c5SRobert Richter return gic_read_iar_common(); 2446d4e11c5SRobert Richter } 2457936e914SJean-Philippe Brucker #endif 246021f6537SMarc Zyngier 247a2c22510SSudeep Holla static void gic_enable_redist(bool enable) 248021f6537SMarc Zyngier { 249021f6537SMarc Zyngier void __iomem *rbase; 250021f6537SMarc Zyngier u32 count = 1000000; /* 1s! */ 251021f6537SMarc Zyngier u32 val; 252021f6537SMarc Zyngier 2539c8114c2SSrinivas Kandagatla if (gic_data.flags & FLAGS_WORKAROUND_GICR_WAKER_MSM8996) 2549c8114c2SSrinivas Kandagatla return; 2559c8114c2SSrinivas Kandagatla 256021f6537SMarc Zyngier rbase = gic_data_rdist_rd_base(); 257021f6537SMarc Zyngier 258021f6537SMarc Zyngier val = readl_relaxed(rbase + GICR_WAKER); 259a2c22510SSudeep Holla if (enable) 260a2c22510SSudeep Holla /* Wake up this CPU redistributor */ 261021f6537SMarc Zyngier val &= ~GICR_WAKER_ProcessorSleep; 262a2c22510SSudeep Holla else 263a2c22510SSudeep Holla val |= GICR_WAKER_ProcessorSleep; 264021f6537SMarc Zyngier writel_relaxed(val, rbase + GICR_WAKER); 265021f6537SMarc Zyngier 266a2c22510SSudeep Holla if (!enable) { /* Check that GICR_WAKER is writeable */ 267a2c22510SSudeep Holla val = readl_relaxed(rbase + GICR_WAKER); 268a2c22510SSudeep Holla if (!(val & GICR_WAKER_ProcessorSleep)) 269a2c22510SSudeep Holla return; /* No PM support in this redistributor */ 270021f6537SMarc Zyngier } 271a2c22510SSudeep Holla 272d102eb5cSDan Carpenter while (--count) { 273a2c22510SSudeep Holla val = readl_relaxed(rbase + GICR_WAKER); 274cf1d9d11SAndrew Jones if (enable ^ (bool)(val & GICR_WAKER_ChildrenAsleep)) 275a2c22510SSudeep Holla break; 276021f6537SMarc Zyngier cpu_relax(); 277021f6537SMarc Zyngier udelay(1); 2782c542426SDaode Huang } 279a2c22510SSudeep Holla if (!count) 280a2c22510SSudeep Holla pr_err_ratelimited("redistributor failed to %s...\n", 281a2c22510SSudeep Holla enable ? "wakeup" : "sleep"); 282021f6537SMarc Zyngier } 283021f6537SMarc Zyngier 284021f6537SMarc Zyngier /* 285021f6537SMarc Zyngier * Routines to disable, enable, EOI and route interrupts 286021f6537SMarc Zyngier */ 287e91b036eSMarc Zyngier static u32 convert_offset_index(struct irq_data *d, u32 offset, u32 *index) 288e91b036eSMarc Zyngier { 289e91b036eSMarc Zyngier switch (get_intid_range(d)) { 29070a29c32SMarc Zyngier case SGI_RANGE: 291e91b036eSMarc Zyngier case PPI_RANGE: 292e91b036eSMarc Zyngier case SPI_RANGE: 293e91b036eSMarc Zyngier *index = d->hwirq; 294e91b036eSMarc Zyngier return offset; 2955f51f803SMarc Zyngier case EPPI_RANGE: 2965f51f803SMarc Zyngier /* 2975f51f803SMarc Zyngier * Contrary to the ESPI range, the EPPI range is contiguous 2985f51f803SMarc Zyngier * to the PPI range in the registers, so let's adjust the 2995f51f803SMarc Zyngier * displacement accordingly. Consistency is overrated. 3005f51f803SMarc Zyngier */ 3015f51f803SMarc Zyngier *index = d->hwirq - EPPI_BASE_INTID + 32; 3025f51f803SMarc Zyngier return offset; 303211bddd2SMarc Zyngier case ESPI_RANGE: 304211bddd2SMarc Zyngier *index = d->hwirq - ESPI_BASE_INTID; 305211bddd2SMarc Zyngier switch (offset) { 306211bddd2SMarc Zyngier case GICD_ISENABLER: 307211bddd2SMarc Zyngier return GICD_ISENABLERnE; 308211bddd2SMarc Zyngier case GICD_ICENABLER: 309211bddd2SMarc Zyngier return GICD_ICENABLERnE; 310211bddd2SMarc Zyngier case GICD_ISPENDR: 311211bddd2SMarc Zyngier return GICD_ISPENDRnE; 312211bddd2SMarc Zyngier case GICD_ICPENDR: 313211bddd2SMarc Zyngier return GICD_ICPENDRnE; 314211bddd2SMarc Zyngier case GICD_ISACTIVER: 315211bddd2SMarc Zyngier return GICD_ISACTIVERnE; 316211bddd2SMarc Zyngier case GICD_ICACTIVER: 317211bddd2SMarc Zyngier return GICD_ICACTIVERnE; 318211bddd2SMarc Zyngier case GICD_IPRIORITYR: 319211bddd2SMarc Zyngier return GICD_IPRIORITYRnE; 320211bddd2SMarc Zyngier case GICD_ICFGR: 321211bddd2SMarc Zyngier return GICD_ICFGRnE; 322211bddd2SMarc Zyngier case GICD_IROUTER: 323211bddd2SMarc Zyngier return GICD_IROUTERnE; 324211bddd2SMarc Zyngier default: 325211bddd2SMarc Zyngier break; 326211bddd2SMarc Zyngier } 327211bddd2SMarc Zyngier break; 328e91b036eSMarc Zyngier default: 329e91b036eSMarc Zyngier break; 330e91b036eSMarc Zyngier } 331e91b036eSMarc Zyngier 332e91b036eSMarc Zyngier WARN_ON(1); 333e91b036eSMarc Zyngier *index = d->hwirq; 334e91b036eSMarc Zyngier return offset; 335e91b036eSMarc Zyngier } 336e91b036eSMarc Zyngier 337b594c6e2SMarc Zyngier static int gic_peek_irq(struct irq_data *d, u32 offset) 338b594c6e2SMarc Zyngier { 339b594c6e2SMarc Zyngier void __iomem *base; 340e91b036eSMarc Zyngier u32 index, mask; 341e91b036eSMarc Zyngier 342e91b036eSMarc Zyngier offset = convert_offset_index(d, offset, &index); 343e91b036eSMarc Zyngier mask = 1 << (index % 32); 344b594c6e2SMarc Zyngier 345b594c6e2SMarc Zyngier if (gic_irq_in_rdist(d)) 346b594c6e2SMarc Zyngier base = gic_data_rdist_sgi_base(); 347b594c6e2SMarc Zyngier else 348b594c6e2SMarc Zyngier base = gic_data.dist_base; 349b594c6e2SMarc Zyngier 350e91b036eSMarc Zyngier return !!(readl_relaxed(base + offset + (index / 32) * 4) & mask); 351b594c6e2SMarc Zyngier } 352b594c6e2SMarc Zyngier 353021f6537SMarc Zyngier static void gic_poke_irq(struct irq_data *d, u32 offset) 354021f6537SMarc Zyngier { 355021f6537SMarc Zyngier void (*rwp_wait)(void); 356021f6537SMarc Zyngier void __iomem *base; 357e91b036eSMarc Zyngier u32 index, mask; 358e91b036eSMarc Zyngier 359e91b036eSMarc Zyngier offset = convert_offset_index(d, offset, &index); 360e91b036eSMarc Zyngier mask = 1 << (index % 32); 361021f6537SMarc Zyngier 362021f6537SMarc Zyngier if (gic_irq_in_rdist(d)) { 363021f6537SMarc Zyngier base = gic_data_rdist_sgi_base(); 364021f6537SMarc Zyngier rwp_wait = gic_redist_wait_for_rwp; 365021f6537SMarc Zyngier } else { 366021f6537SMarc Zyngier base = gic_data.dist_base; 367021f6537SMarc Zyngier rwp_wait = gic_dist_wait_for_rwp; 368021f6537SMarc Zyngier } 369021f6537SMarc Zyngier 370e91b036eSMarc Zyngier writel_relaxed(mask, base + offset + (index / 32) * 4); 371021f6537SMarc Zyngier rwp_wait(); 372021f6537SMarc Zyngier } 373021f6537SMarc Zyngier 374021f6537SMarc Zyngier static void gic_mask_irq(struct irq_data *d) 375021f6537SMarc Zyngier { 376021f6537SMarc Zyngier gic_poke_irq(d, GICD_ICENABLER); 377021f6537SMarc Zyngier } 378021f6537SMarc Zyngier 3790b6a3da9SMarc Zyngier static void gic_eoimode1_mask_irq(struct irq_data *d) 3800b6a3da9SMarc Zyngier { 3810b6a3da9SMarc Zyngier gic_mask_irq(d); 382530bf353SMarc Zyngier /* 383530bf353SMarc Zyngier * When masking a forwarded interrupt, make sure it is 384530bf353SMarc Zyngier * deactivated as well. 385530bf353SMarc Zyngier * 386530bf353SMarc Zyngier * This ensures that an interrupt that is getting 387530bf353SMarc Zyngier * disabled/masked will not get "stuck", because there is 388530bf353SMarc Zyngier * noone to deactivate it (guest is being terminated). 389530bf353SMarc Zyngier */ 3904df7f54dSThomas Gleixner if (irqd_is_forwarded_to_vcpu(d)) 391530bf353SMarc Zyngier gic_poke_irq(d, GICD_ICACTIVER); 3920b6a3da9SMarc Zyngier } 3930b6a3da9SMarc Zyngier 394021f6537SMarc Zyngier static void gic_unmask_irq(struct irq_data *d) 395021f6537SMarc Zyngier { 396021f6537SMarc Zyngier gic_poke_irq(d, GICD_ISENABLER); 397021f6537SMarc Zyngier } 398021f6537SMarc Zyngier 399d98d0a99SJulien Thierry static inline bool gic_supports_nmi(void) 400d98d0a99SJulien Thierry { 401d98d0a99SJulien Thierry return IS_ENABLED(CONFIG_ARM64_PSEUDO_NMI) && 402d98d0a99SJulien Thierry static_branch_likely(&supports_pseudo_nmis); 403d98d0a99SJulien Thierry } 404d98d0a99SJulien Thierry 405b594c6e2SMarc Zyngier static int gic_irq_set_irqchip_state(struct irq_data *d, 406b594c6e2SMarc Zyngier enum irqchip_irq_state which, bool val) 407b594c6e2SMarc Zyngier { 408b594c6e2SMarc Zyngier u32 reg; 409b594c6e2SMarc Zyngier 41064b499d8SMarc Zyngier if (d->hwirq >= 8192) /* SGI/PPI/SPI only */ 411b594c6e2SMarc Zyngier return -EINVAL; 412b594c6e2SMarc Zyngier 413b594c6e2SMarc Zyngier switch (which) { 414b594c6e2SMarc Zyngier case IRQCHIP_STATE_PENDING: 415b594c6e2SMarc Zyngier reg = val ? GICD_ISPENDR : GICD_ICPENDR; 416b594c6e2SMarc Zyngier break; 417b594c6e2SMarc Zyngier 418b594c6e2SMarc Zyngier case IRQCHIP_STATE_ACTIVE: 419b594c6e2SMarc Zyngier reg = val ? GICD_ISACTIVER : GICD_ICACTIVER; 420b594c6e2SMarc Zyngier break; 421b594c6e2SMarc Zyngier 422b594c6e2SMarc Zyngier case IRQCHIP_STATE_MASKED: 423b594c6e2SMarc Zyngier reg = val ? GICD_ICENABLER : GICD_ISENABLER; 424b594c6e2SMarc Zyngier break; 425b594c6e2SMarc Zyngier 426b594c6e2SMarc Zyngier default: 427b594c6e2SMarc Zyngier return -EINVAL; 428b594c6e2SMarc Zyngier } 429b594c6e2SMarc Zyngier 430b594c6e2SMarc Zyngier gic_poke_irq(d, reg); 431b594c6e2SMarc Zyngier return 0; 432b594c6e2SMarc Zyngier } 433b594c6e2SMarc Zyngier 434b594c6e2SMarc Zyngier static int gic_irq_get_irqchip_state(struct irq_data *d, 435b594c6e2SMarc Zyngier enum irqchip_irq_state which, bool *val) 436b594c6e2SMarc Zyngier { 437211bddd2SMarc Zyngier if (d->hwirq >= 8192) /* PPI/SPI only */ 438b594c6e2SMarc Zyngier return -EINVAL; 439b594c6e2SMarc Zyngier 440b594c6e2SMarc Zyngier switch (which) { 441b594c6e2SMarc Zyngier case IRQCHIP_STATE_PENDING: 442b594c6e2SMarc Zyngier *val = gic_peek_irq(d, GICD_ISPENDR); 443b594c6e2SMarc Zyngier break; 444b594c6e2SMarc Zyngier 445b594c6e2SMarc Zyngier case IRQCHIP_STATE_ACTIVE: 446b594c6e2SMarc Zyngier *val = gic_peek_irq(d, GICD_ISACTIVER); 447b594c6e2SMarc Zyngier break; 448b594c6e2SMarc Zyngier 449b594c6e2SMarc Zyngier case IRQCHIP_STATE_MASKED: 450b594c6e2SMarc Zyngier *val = !gic_peek_irq(d, GICD_ISENABLER); 451b594c6e2SMarc Zyngier break; 452b594c6e2SMarc Zyngier 453b594c6e2SMarc Zyngier default: 454b594c6e2SMarc Zyngier return -EINVAL; 455b594c6e2SMarc Zyngier } 456b594c6e2SMarc Zyngier 457b594c6e2SMarc Zyngier return 0; 458b594c6e2SMarc Zyngier } 459b594c6e2SMarc Zyngier 460101b35f7SJulien Thierry static void gic_irq_set_prio(struct irq_data *d, u8 prio) 461101b35f7SJulien Thierry { 462101b35f7SJulien Thierry void __iomem *base = gic_dist_base(d); 463e91b036eSMarc Zyngier u32 offset, index; 464101b35f7SJulien Thierry 465e91b036eSMarc Zyngier offset = convert_offset_index(d, GICD_IPRIORITYR, &index); 466e91b036eSMarc Zyngier 467e91b036eSMarc Zyngier writeb_relaxed(prio, base + offset + index); 468101b35f7SJulien Thierry } 469101b35f7SJulien Thierry 470bfa80ee9SJames Morse static u32 __gic_get_ppi_index(irq_hw_number_t hwirq) 47181a43273SMarc Zyngier { 472bfa80ee9SJames Morse switch (__get_intid_range(hwirq)) { 47381a43273SMarc Zyngier case PPI_RANGE: 474bfa80ee9SJames Morse return hwirq - 16; 4755f51f803SMarc Zyngier case EPPI_RANGE: 476bfa80ee9SJames Morse return hwirq - EPPI_BASE_INTID + 16; 47781a43273SMarc Zyngier default: 47881a43273SMarc Zyngier unreachable(); 47981a43273SMarc Zyngier } 48081a43273SMarc Zyngier } 48181a43273SMarc Zyngier 482bfa80ee9SJames Morse static u32 gic_get_ppi_index(struct irq_data *d) 483bfa80ee9SJames Morse { 484bfa80ee9SJames Morse return __gic_get_ppi_index(d->hwirq); 485bfa80ee9SJames Morse } 486bfa80ee9SJames Morse 487101b35f7SJulien Thierry static int gic_irq_nmi_setup(struct irq_data *d) 488101b35f7SJulien Thierry { 489101b35f7SJulien Thierry struct irq_desc *desc = irq_to_desc(d->irq); 490101b35f7SJulien Thierry 491101b35f7SJulien Thierry if (!gic_supports_nmi()) 492101b35f7SJulien Thierry return -EINVAL; 493101b35f7SJulien Thierry 494101b35f7SJulien Thierry if (gic_peek_irq(d, GICD_ISENABLER)) { 495101b35f7SJulien Thierry pr_err("Cannot set NMI property of enabled IRQ %u\n", d->irq); 496101b35f7SJulien Thierry return -EINVAL; 497101b35f7SJulien Thierry } 498101b35f7SJulien Thierry 499101b35f7SJulien Thierry /* 500101b35f7SJulien Thierry * A secondary irq_chip should be in charge of LPI request, 501101b35f7SJulien Thierry * it should not be possible to get there 502101b35f7SJulien Thierry */ 503101b35f7SJulien Thierry if (WARN_ON(gic_irq(d) >= 8192)) 504101b35f7SJulien Thierry return -EINVAL; 505101b35f7SJulien Thierry 506101b35f7SJulien Thierry /* desc lock should already be held */ 50781a43273SMarc Zyngier if (gic_irq_in_rdist(d)) { 50881a43273SMarc Zyngier u32 idx = gic_get_ppi_index(d); 50981a43273SMarc Zyngier 510101b35f7SJulien Thierry /* Setting up PPI as NMI, only switch handler for first NMI */ 51181a43273SMarc Zyngier if (!refcount_inc_not_zero(&ppi_nmi_refs[idx])) { 51281a43273SMarc Zyngier refcount_set(&ppi_nmi_refs[idx], 1); 513101b35f7SJulien Thierry desc->handle_irq = handle_percpu_devid_fasteoi_nmi; 514101b35f7SJulien Thierry } 515101b35f7SJulien Thierry } else { 516101b35f7SJulien Thierry desc->handle_irq = handle_fasteoi_nmi; 517101b35f7SJulien Thierry } 518101b35f7SJulien Thierry 519101b35f7SJulien Thierry gic_irq_set_prio(d, GICD_INT_NMI_PRI); 520101b35f7SJulien Thierry 521101b35f7SJulien Thierry return 0; 522101b35f7SJulien Thierry } 523101b35f7SJulien Thierry 524101b35f7SJulien Thierry static void gic_irq_nmi_teardown(struct irq_data *d) 525101b35f7SJulien Thierry { 526101b35f7SJulien Thierry struct irq_desc *desc = irq_to_desc(d->irq); 527101b35f7SJulien Thierry 528101b35f7SJulien Thierry if (WARN_ON(!gic_supports_nmi())) 529101b35f7SJulien Thierry return; 530101b35f7SJulien Thierry 531101b35f7SJulien Thierry if (gic_peek_irq(d, GICD_ISENABLER)) { 532101b35f7SJulien Thierry pr_err("Cannot set NMI property of enabled IRQ %u\n", d->irq); 533101b35f7SJulien Thierry return; 534101b35f7SJulien Thierry } 535101b35f7SJulien Thierry 536101b35f7SJulien Thierry /* 537101b35f7SJulien Thierry * A secondary irq_chip should be in charge of LPI request, 538101b35f7SJulien Thierry * it should not be possible to get there 539101b35f7SJulien Thierry */ 540101b35f7SJulien Thierry if (WARN_ON(gic_irq(d) >= 8192)) 541101b35f7SJulien Thierry return; 542101b35f7SJulien Thierry 543101b35f7SJulien Thierry /* desc lock should already be held */ 54481a43273SMarc Zyngier if (gic_irq_in_rdist(d)) { 54581a43273SMarc Zyngier u32 idx = gic_get_ppi_index(d); 54681a43273SMarc Zyngier 547101b35f7SJulien Thierry /* Tearing down NMI, only switch handler for last NMI */ 54881a43273SMarc Zyngier if (refcount_dec_and_test(&ppi_nmi_refs[idx])) 549101b35f7SJulien Thierry desc->handle_irq = handle_percpu_devid_irq; 550101b35f7SJulien Thierry } else { 551101b35f7SJulien Thierry desc->handle_irq = handle_fasteoi_irq; 552101b35f7SJulien Thierry } 553101b35f7SJulien Thierry 554101b35f7SJulien Thierry gic_irq_set_prio(d, GICD_INT_DEF_PRI); 555101b35f7SJulien Thierry } 556101b35f7SJulien Thierry 557021f6537SMarc Zyngier static void gic_eoi_irq(struct irq_data *d) 558021f6537SMarc Zyngier { 559021f6537SMarc Zyngier gic_write_eoir(gic_irq(d)); 560021f6537SMarc Zyngier } 561021f6537SMarc Zyngier 5620b6a3da9SMarc Zyngier static void gic_eoimode1_eoi_irq(struct irq_data *d) 5630b6a3da9SMarc Zyngier { 5640b6a3da9SMarc Zyngier /* 565530bf353SMarc Zyngier * No need to deactivate an LPI, or an interrupt that 566530bf353SMarc Zyngier * is is getting forwarded to a vcpu. 5670b6a3da9SMarc Zyngier */ 5684df7f54dSThomas Gleixner if (gic_irq(d) >= 8192 || irqd_is_forwarded_to_vcpu(d)) 5690b6a3da9SMarc Zyngier return; 5700b6a3da9SMarc Zyngier gic_write_dir(gic_irq(d)); 5710b6a3da9SMarc Zyngier } 5720b6a3da9SMarc Zyngier 573021f6537SMarc Zyngier static int gic_set_type(struct irq_data *d, unsigned int type) 574021f6537SMarc Zyngier { 5755f51f803SMarc Zyngier enum gic_intid_range range; 576021f6537SMarc Zyngier unsigned int irq = gic_irq(d); 577021f6537SMarc Zyngier void (*rwp_wait)(void); 578021f6537SMarc Zyngier void __iomem *base; 579e91b036eSMarc Zyngier u32 offset, index; 58013d22e2eSMarc Zyngier int ret; 581021f6537SMarc Zyngier 5825f51f803SMarc Zyngier range = get_intid_range(d); 5835f51f803SMarc Zyngier 58464b499d8SMarc Zyngier /* Interrupt configuration for SGIs can't be changed */ 58564b499d8SMarc Zyngier if (range == SGI_RANGE) 58664b499d8SMarc Zyngier return type != IRQ_TYPE_EDGE_RISING ? -EINVAL : 0; 58764b499d8SMarc Zyngier 588fb7e7debSLiviu Dudau /* SPIs have restrictions on the supported types */ 5895f51f803SMarc Zyngier if ((range == SPI_RANGE || range == ESPI_RANGE) && 5905f51f803SMarc Zyngier type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING) 591021f6537SMarc Zyngier return -EINVAL; 592021f6537SMarc Zyngier 593021f6537SMarc Zyngier if (gic_irq_in_rdist(d)) { 594021f6537SMarc Zyngier base = gic_data_rdist_sgi_base(); 595021f6537SMarc Zyngier rwp_wait = gic_redist_wait_for_rwp; 596021f6537SMarc Zyngier } else { 597021f6537SMarc Zyngier base = gic_data.dist_base; 598021f6537SMarc Zyngier rwp_wait = gic_dist_wait_for_rwp; 599021f6537SMarc Zyngier } 600021f6537SMarc Zyngier 601e91b036eSMarc Zyngier offset = convert_offset_index(d, GICD_ICFGR, &index); 60213d22e2eSMarc Zyngier 603e91b036eSMarc Zyngier ret = gic_configure_irq(index, type, base + offset, rwp_wait); 6045f51f803SMarc Zyngier if (ret && (range == PPI_RANGE || range == EPPI_RANGE)) { 60513d22e2eSMarc Zyngier /* Misconfigured PPIs are usually not fatal */ 6065f51f803SMarc Zyngier pr_warn("GIC: PPI INTID%d is secure or misconfigured\n", irq); 60713d22e2eSMarc Zyngier ret = 0; 60813d22e2eSMarc Zyngier } 60913d22e2eSMarc Zyngier 61013d22e2eSMarc Zyngier return ret; 611021f6537SMarc Zyngier } 612021f6537SMarc Zyngier 613530bf353SMarc Zyngier static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu) 614530bf353SMarc Zyngier { 61564b499d8SMarc Zyngier if (get_intid_range(d) == SGI_RANGE) 61664b499d8SMarc Zyngier return -EINVAL; 61764b499d8SMarc Zyngier 6184df7f54dSThomas Gleixner if (vcpu) 6194df7f54dSThomas Gleixner irqd_set_forwarded_to_vcpu(d); 6204df7f54dSThomas Gleixner else 6214df7f54dSThomas Gleixner irqd_clr_forwarded_to_vcpu(d); 622530bf353SMarc Zyngier return 0; 623530bf353SMarc Zyngier } 624530bf353SMarc Zyngier 625f6c86a41SJean-Philippe Brucker static u64 gic_mpidr_to_affinity(unsigned long mpidr) 626021f6537SMarc Zyngier { 627021f6537SMarc Zyngier u64 aff; 628021f6537SMarc Zyngier 629f6c86a41SJean-Philippe Brucker aff = ((u64)MPIDR_AFFINITY_LEVEL(mpidr, 3) << 32 | 630021f6537SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 | 631021f6537SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | 632021f6537SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 0)); 633021f6537SMarc Zyngier 634021f6537SMarc Zyngier return aff; 635021f6537SMarc Zyngier } 636021f6537SMarc Zyngier 637f32c9266SJulien Thierry static void gic_deactivate_unhandled(u32 irqnr) 638f32c9266SJulien Thierry { 639f32c9266SJulien Thierry if (static_branch_likely(&supports_deactivate_key)) { 640f32c9266SJulien Thierry if (irqnr < 8192) 641f32c9266SJulien Thierry gic_write_dir(irqnr); 642f32c9266SJulien Thierry } else { 643f32c9266SJulien Thierry gic_write_eoir(irqnr); 644f32c9266SJulien Thierry } 645f32c9266SJulien Thierry } 646f32c9266SJulien Thierry 647f32c9266SJulien Thierry static inline void gic_handle_nmi(u32 irqnr, struct pt_regs *regs) 648f32c9266SJulien Thierry { 64917ce302fSJulien Thierry bool irqs_enabled = interrupts_enabled(regs); 650f32c9266SJulien Thierry int err; 651f32c9266SJulien Thierry 65217ce302fSJulien Thierry if (irqs_enabled) 65317ce302fSJulien Thierry nmi_enter(); 65417ce302fSJulien Thierry 655f32c9266SJulien Thierry if (static_branch_likely(&supports_deactivate_key)) 656f32c9266SJulien Thierry gic_write_eoir(irqnr); 657f32c9266SJulien Thierry /* 658f32c9266SJulien Thierry * Leave the PSR.I bit set to prevent other NMIs to be 659f32c9266SJulien Thierry * received while handling this one. 660f32c9266SJulien Thierry * PSR.I will be restored when we ERET to the 661f32c9266SJulien Thierry * interrupted context. 662f32c9266SJulien Thierry */ 663*0953fb26SMark Rutland err = generic_handle_domain_nmi(gic_data.domain, irqnr); 664f32c9266SJulien Thierry if (err) 665f32c9266SJulien Thierry gic_deactivate_unhandled(irqnr); 66617ce302fSJulien Thierry 66717ce302fSJulien Thierry if (irqs_enabled) 66817ce302fSJulien Thierry nmi_exit(); 669f32c9266SJulien Thierry } 670f32c9266SJulien Thierry 671382e6e17SMarc Zyngier static u32 do_read_iar(struct pt_regs *regs) 672382e6e17SMarc Zyngier { 673382e6e17SMarc Zyngier u32 iar; 674382e6e17SMarc Zyngier 675382e6e17SMarc Zyngier if (gic_supports_nmi() && unlikely(!interrupts_enabled(regs))) { 676382e6e17SMarc Zyngier u64 pmr; 677382e6e17SMarc Zyngier 678382e6e17SMarc Zyngier /* 679382e6e17SMarc Zyngier * We were in a context with IRQs disabled. However, the 680382e6e17SMarc Zyngier * entry code has set PMR to a value that allows any 681382e6e17SMarc Zyngier * interrupt to be acknowledged, and not just NMIs. This can 682382e6e17SMarc Zyngier * lead to surprising effects if the NMI has been retired in 683382e6e17SMarc Zyngier * the meantime, and that there is an IRQ pending. The IRQ 684382e6e17SMarc Zyngier * would then be taken in NMI context, something that nobody 685382e6e17SMarc Zyngier * wants to debug twice. 686382e6e17SMarc Zyngier * 687382e6e17SMarc Zyngier * Until we sort this, drop PMR again to a level that will 688382e6e17SMarc Zyngier * actually only allow NMIs before reading IAR, and then 689382e6e17SMarc Zyngier * restore it to what it was. 690382e6e17SMarc Zyngier */ 691382e6e17SMarc Zyngier pmr = gic_read_pmr(); 692382e6e17SMarc Zyngier gic_pmr_mask_irqs(); 693382e6e17SMarc Zyngier isb(); 694382e6e17SMarc Zyngier 695382e6e17SMarc Zyngier iar = gic_read_iar(); 696382e6e17SMarc Zyngier 697382e6e17SMarc Zyngier gic_write_pmr(pmr); 698382e6e17SMarc Zyngier } else { 699382e6e17SMarc Zyngier iar = gic_read_iar(); 700382e6e17SMarc Zyngier } 701382e6e17SMarc Zyngier 702382e6e17SMarc Zyngier return iar; 703382e6e17SMarc Zyngier } 704382e6e17SMarc Zyngier 705021f6537SMarc Zyngier static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) 706021f6537SMarc Zyngier { 707f6c86a41SJean-Philippe Brucker u32 irqnr; 708021f6537SMarc Zyngier 709382e6e17SMarc Zyngier irqnr = do_read_iar(regs); 710021f6537SMarc Zyngier 711a97709f5SHe Ying /* Check for special IDs first */ 712a97709f5SHe Ying if ((irqnr >= 1020 && irqnr <= 1023)) 713a97709f5SHe Ying return; 714a97709f5SHe Ying 715f32c9266SJulien Thierry if (gic_supports_nmi() && 7168d474deaSChen-Yu Tsai unlikely(gic_read_rpr() == GICD_INT_RPR_PRI(GICD_INT_NMI_PRI))) { 717f32c9266SJulien Thierry gic_handle_nmi(irqnr, regs); 718f32c9266SJulien Thierry return; 719f32c9266SJulien Thierry } 720f32c9266SJulien Thierry 7213f1f3234SJulien Thierry if (gic_prio_masking_enabled()) { 7223f1f3234SJulien Thierry gic_pmr_mask_irqs(); 7233f1f3234SJulien Thierry gic_arch_enable_irqs(); 7243f1f3234SJulien Thierry } 7253f1f3234SJulien Thierry 726d01d3274SDavidlohr Bueso if (static_branch_likely(&supports_deactivate_key)) 7270b6a3da9SMarc Zyngier gic_write_eoir(irqnr); 72839a06b67SWill Deacon else 72939a06b67SWill Deacon isb(); 7300b6a3da9SMarc Zyngier 731*0953fb26SMark Rutland if (generic_handle_domain_irq(gic_data.domain, irqnr)) { 732da33f31dSMarc Zyngier WARN_ONCE(true, "Unexpected interrupt received!\n"); 733f32c9266SJulien Thierry gic_deactivate_unhandled(irqnr); 7340b6a3da9SMarc Zyngier } 735021f6537SMarc Zyngier } 736021f6537SMarc Zyngier 737b5cf6073SJulien Thierry static u32 gic_get_pribits(void) 738b5cf6073SJulien Thierry { 739b5cf6073SJulien Thierry u32 pribits; 740b5cf6073SJulien Thierry 741b5cf6073SJulien Thierry pribits = gic_read_ctlr(); 742b5cf6073SJulien Thierry pribits &= ICC_CTLR_EL1_PRI_BITS_MASK; 743b5cf6073SJulien Thierry pribits >>= ICC_CTLR_EL1_PRI_BITS_SHIFT; 744b5cf6073SJulien Thierry pribits++; 745b5cf6073SJulien Thierry 746b5cf6073SJulien Thierry return pribits; 747b5cf6073SJulien Thierry } 748b5cf6073SJulien Thierry 749b5cf6073SJulien Thierry static bool gic_has_group0(void) 750b5cf6073SJulien Thierry { 751b5cf6073SJulien Thierry u32 val; 752e7932188SJulien Thierry u32 old_pmr; 753e7932188SJulien Thierry 754e7932188SJulien Thierry old_pmr = gic_read_pmr(); 755b5cf6073SJulien Thierry 756b5cf6073SJulien Thierry /* 757b5cf6073SJulien Thierry * Let's find out if Group0 is under control of EL3 or not by 758b5cf6073SJulien Thierry * setting the highest possible, non-zero priority in PMR. 759b5cf6073SJulien Thierry * 760b5cf6073SJulien Thierry * If SCR_EL3.FIQ is set, the priority gets shifted down in 761b5cf6073SJulien Thierry * order for the CPU interface to set bit 7, and keep the 762b5cf6073SJulien Thierry * actual priority in the non-secure range. In the process, it 763b5cf6073SJulien Thierry * looses the least significant bit and the actual priority 764b5cf6073SJulien Thierry * becomes 0x80. Reading it back returns 0, indicating that 765b5cf6073SJulien Thierry * we're don't have access to Group0. 766b5cf6073SJulien Thierry */ 767b5cf6073SJulien Thierry gic_write_pmr(BIT(8 - gic_get_pribits())); 768b5cf6073SJulien Thierry val = gic_read_pmr(); 769b5cf6073SJulien Thierry 770e7932188SJulien Thierry gic_write_pmr(old_pmr); 771e7932188SJulien Thierry 772b5cf6073SJulien Thierry return val != 0; 773b5cf6073SJulien Thierry } 774b5cf6073SJulien Thierry 775021f6537SMarc Zyngier static void __init gic_dist_init(void) 776021f6537SMarc Zyngier { 777021f6537SMarc Zyngier unsigned int i; 778021f6537SMarc Zyngier u64 affinity; 779021f6537SMarc Zyngier void __iomem *base = gic_data.dist_base; 7800b04758bSMarc Zyngier u32 val; 781021f6537SMarc Zyngier 782021f6537SMarc Zyngier /* Disable the distributor */ 783021f6537SMarc Zyngier writel_relaxed(0, base + GICD_CTLR); 784021f6537SMarc Zyngier gic_dist_wait_for_rwp(); 785021f6537SMarc Zyngier 7867c9b9730SMarc Zyngier /* 7877c9b9730SMarc Zyngier * Configure SPIs as non-secure Group-1. This will only matter 7887c9b9730SMarc Zyngier * if the GIC only has a single security state. This will not 7897c9b9730SMarc Zyngier * do the right thing if the kernel is running in secure mode, 7907c9b9730SMarc Zyngier * but that's not the intended use case anyway. 7917c9b9730SMarc Zyngier */ 792211bddd2SMarc Zyngier for (i = 32; i < GIC_LINE_NR; i += 32) 7937c9b9730SMarc Zyngier writel_relaxed(~0, base + GICD_IGROUPR + i / 8); 7947c9b9730SMarc Zyngier 795211bddd2SMarc Zyngier /* Extended SPI range, not handled by the GICv2/GICv3 common code */ 796211bddd2SMarc Zyngier for (i = 0; i < GIC_ESPI_NR; i += 32) { 797211bddd2SMarc Zyngier writel_relaxed(~0U, base + GICD_ICENABLERnE + i / 8); 798211bddd2SMarc Zyngier writel_relaxed(~0U, base + GICD_ICACTIVERnE + i / 8); 799211bddd2SMarc Zyngier } 800211bddd2SMarc Zyngier 801211bddd2SMarc Zyngier for (i = 0; i < GIC_ESPI_NR; i += 32) 802211bddd2SMarc Zyngier writel_relaxed(~0U, base + GICD_IGROUPRnE + i / 8); 803211bddd2SMarc Zyngier 804211bddd2SMarc Zyngier for (i = 0; i < GIC_ESPI_NR; i += 16) 805211bddd2SMarc Zyngier writel_relaxed(0, base + GICD_ICFGRnE + i / 4); 806211bddd2SMarc Zyngier 807211bddd2SMarc Zyngier for (i = 0; i < GIC_ESPI_NR; i += 4) 808211bddd2SMarc Zyngier writel_relaxed(GICD_INT_DEF_PRI_X4, base + GICD_IPRIORITYRnE + i); 809211bddd2SMarc Zyngier 810211bddd2SMarc Zyngier /* Now do the common stuff, and wait for the distributor to drain */ 811211bddd2SMarc Zyngier gic_dist_config(base, GIC_LINE_NR, gic_dist_wait_for_rwp); 812021f6537SMarc Zyngier 8130b04758bSMarc Zyngier val = GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G1A | GICD_CTLR_ENABLE_G1; 8140b04758bSMarc Zyngier if (gic_data.rdists.gicd_typer2 & GICD_TYPER2_nASSGIcap) { 8150b04758bSMarc Zyngier pr_info("Enabling SGIs without active state\n"); 8160b04758bSMarc Zyngier val |= GICD_CTLR_nASSGIreq; 8170b04758bSMarc Zyngier } 8180b04758bSMarc Zyngier 819021f6537SMarc Zyngier /* Enable distributor with ARE, Group1 */ 8200b04758bSMarc Zyngier writel_relaxed(val, base + GICD_CTLR); 821021f6537SMarc Zyngier 822021f6537SMarc Zyngier /* 823021f6537SMarc Zyngier * Set all global interrupts to the boot CPU only. ARE must be 824021f6537SMarc Zyngier * enabled. 825021f6537SMarc Zyngier */ 826021f6537SMarc Zyngier affinity = gic_mpidr_to_affinity(cpu_logical_map(smp_processor_id())); 827211bddd2SMarc Zyngier for (i = 32; i < GIC_LINE_NR; i++) 82872c97126SJean-Philippe Brucker gic_write_irouter(affinity, base + GICD_IROUTER + i * 8); 829211bddd2SMarc Zyngier 830211bddd2SMarc Zyngier for (i = 0; i < GIC_ESPI_NR; i++) 831211bddd2SMarc Zyngier gic_write_irouter(affinity, base + GICD_IROUTERnE + i * 8); 832021f6537SMarc Zyngier } 833021f6537SMarc Zyngier 8340d94ded2SMarc Zyngier static int gic_iterate_rdists(int (*fn)(struct redist_region *, void __iomem *)) 835021f6537SMarc Zyngier { 8360d94ded2SMarc Zyngier int ret = -ENODEV; 837021f6537SMarc Zyngier int i; 838021f6537SMarc Zyngier 839f5c1434cSMarc Zyngier for (i = 0; i < gic_data.nr_redist_regions; i++) { 840f5c1434cSMarc Zyngier void __iomem *ptr = gic_data.redist_regions[i].redist_base; 8410d94ded2SMarc Zyngier u64 typer; 842021f6537SMarc Zyngier u32 reg; 843021f6537SMarc Zyngier 844021f6537SMarc Zyngier reg = readl_relaxed(ptr + GICR_PIDR2) & GIC_PIDR2_ARCH_MASK; 845021f6537SMarc Zyngier if (reg != GIC_PIDR2_ARCH_GICv3 && 846021f6537SMarc Zyngier reg != GIC_PIDR2_ARCH_GICv4) { /* We're in trouble... */ 847021f6537SMarc Zyngier pr_warn("No redistributor present @%p\n", ptr); 848021f6537SMarc Zyngier break; 849021f6537SMarc Zyngier } 850021f6537SMarc Zyngier 851021f6537SMarc Zyngier do { 85272c97126SJean-Philippe Brucker typer = gic_read_typer(ptr + GICR_TYPER); 8530d94ded2SMarc Zyngier ret = fn(gic_data.redist_regions + i, ptr); 8540d94ded2SMarc Zyngier if (!ret) 855021f6537SMarc Zyngier return 0; 856021f6537SMarc Zyngier 857b70fb7afSTomasz Nowicki if (gic_data.redist_regions[i].single_redist) 858b70fb7afSTomasz Nowicki break; 859b70fb7afSTomasz Nowicki 860021f6537SMarc Zyngier if (gic_data.redist_stride) { 861021f6537SMarc Zyngier ptr += gic_data.redist_stride; 862021f6537SMarc Zyngier } else { 863021f6537SMarc Zyngier ptr += SZ_64K * 2; /* Skip RD_base + SGI_base */ 864021f6537SMarc Zyngier if (typer & GICR_TYPER_VLPIS) 865021f6537SMarc Zyngier ptr += SZ_64K * 2; /* Skip VLPI_base + reserved page */ 866021f6537SMarc Zyngier } 867021f6537SMarc Zyngier } while (!(typer & GICR_TYPER_LAST)); 868021f6537SMarc Zyngier } 869021f6537SMarc Zyngier 8700d94ded2SMarc Zyngier return ret ? -ENODEV : 0; 8710d94ded2SMarc Zyngier } 8720d94ded2SMarc Zyngier 8730d94ded2SMarc Zyngier static int __gic_populate_rdist(struct redist_region *region, void __iomem *ptr) 8740d94ded2SMarc Zyngier { 8750d94ded2SMarc Zyngier unsigned long mpidr = cpu_logical_map(smp_processor_id()); 8760d94ded2SMarc Zyngier u64 typer; 8770d94ded2SMarc Zyngier u32 aff; 8780d94ded2SMarc Zyngier 8790d94ded2SMarc Zyngier /* 8800d94ded2SMarc Zyngier * Convert affinity to a 32bit value that can be matched to 8810d94ded2SMarc Zyngier * GICR_TYPER bits [63:32]. 8820d94ded2SMarc Zyngier */ 8830d94ded2SMarc Zyngier aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 24 | 8840d94ded2SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 | 8850d94ded2SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | 8860d94ded2SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 0)); 8870d94ded2SMarc Zyngier 8880d94ded2SMarc Zyngier typer = gic_read_typer(ptr + GICR_TYPER); 8890d94ded2SMarc Zyngier if ((typer >> 32) == aff) { 8900d94ded2SMarc Zyngier u64 offset = ptr - region->redist_base; 8919058a4e9SMarc Zyngier raw_spin_lock_init(&gic_data_rdist()->rd_lock); 8920d94ded2SMarc Zyngier gic_data_rdist_rd_base() = ptr; 8930d94ded2SMarc Zyngier gic_data_rdist()->phys_base = region->phys_base + offset; 8940d94ded2SMarc Zyngier 8950d94ded2SMarc Zyngier pr_info("CPU%d: found redistributor %lx region %d:%pa\n", 8960d94ded2SMarc Zyngier smp_processor_id(), mpidr, 8970d94ded2SMarc Zyngier (int)(region - gic_data.redist_regions), 8980d94ded2SMarc Zyngier &gic_data_rdist()->phys_base); 8990d94ded2SMarc Zyngier return 0; 9000d94ded2SMarc Zyngier } 9010d94ded2SMarc Zyngier 9020d94ded2SMarc Zyngier /* Try next one */ 9030d94ded2SMarc Zyngier return 1; 9040d94ded2SMarc Zyngier } 9050d94ded2SMarc Zyngier 9060d94ded2SMarc Zyngier static int gic_populate_rdist(void) 9070d94ded2SMarc Zyngier { 9080d94ded2SMarc Zyngier if (gic_iterate_rdists(__gic_populate_rdist) == 0) 9090d94ded2SMarc Zyngier return 0; 9100d94ded2SMarc Zyngier 911021f6537SMarc Zyngier /* We couldn't even deal with ourselves... */ 912f6c86a41SJean-Philippe Brucker WARN(true, "CPU%d: mpidr %lx has no re-distributor!\n", 9130d94ded2SMarc Zyngier smp_processor_id(), 9140d94ded2SMarc Zyngier (unsigned long)cpu_logical_map(smp_processor_id())); 915021f6537SMarc Zyngier return -ENODEV; 916021f6537SMarc Zyngier } 917021f6537SMarc Zyngier 9181a60e1e6SMarc Zyngier static int __gic_update_rdist_properties(struct redist_region *region, 9190edc23eaSMarc Zyngier void __iomem *ptr) 9200edc23eaSMarc Zyngier { 9210edc23eaSMarc Zyngier u64 typer = gic_read_typer(ptr + GICR_TYPER); 922b25319d2SMarc Zyngier 9230edc23eaSMarc Zyngier gic_data.rdists.has_vlpis &= !!(typer & GICR_TYPER_VLPIS); 924b25319d2SMarc Zyngier 925b25319d2SMarc Zyngier /* RVPEID implies some form of DirectLPI, no matter what the doc says... :-/ */ 926b25319d2SMarc Zyngier gic_data.rdists.has_rvpeid &= !!(typer & GICR_TYPER_RVPEID); 927b25319d2SMarc Zyngier gic_data.rdists.has_direct_lpi &= (!!(typer & GICR_TYPER_DirectLPIS) | 928b25319d2SMarc Zyngier gic_data.rdists.has_rvpeid); 92996806229SMarc Zyngier gic_data.rdists.has_vpend_valid_dirty &= !!(typer & GICR_TYPER_DIRTY); 930b25319d2SMarc Zyngier 931b25319d2SMarc Zyngier /* Detect non-sensical configurations */ 932b25319d2SMarc Zyngier if (WARN_ON_ONCE(gic_data.rdists.has_rvpeid && !gic_data.rdists.has_vlpis)) { 933b25319d2SMarc Zyngier gic_data.rdists.has_direct_lpi = false; 934b25319d2SMarc Zyngier gic_data.rdists.has_vlpis = false; 935b25319d2SMarc Zyngier gic_data.rdists.has_rvpeid = false; 936b25319d2SMarc Zyngier } 937b25319d2SMarc Zyngier 9385f51f803SMarc Zyngier gic_data.ppi_nr = min(GICR_TYPER_NR_PPIS(typer), gic_data.ppi_nr); 9390edc23eaSMarc Zyngier 9400edc23eaSMarc Zyngier return 1; 9410edc23eaSMarc Zyngier } 9420edc23eaSMarc Zyngier 9431a60e1e6SMarc Zyngier static void gic_update_rdist_properties(void) 9440edc23eaSMarc Zyngier { 9451a60e1e6SMarc Zyngier gic_data.ppi_nr = UINT_MAX; 9461a60e1e6SMarc Zyngier gic_iterate_rdists(__gic_update_rdist_properties); 9471a60e1e6SMarc Zyngier if (WARN_ON(gic_data.ppi_nr == UINT_MAX)) 9481a60e1e6SMarc Zyngier gic_data.ppi_nr = 0; 9491a60e1e6SMarc Zyngier pr_info("%d PPIs implemented\n", gic_data.ppi_nr); 95096806229SMarc Zyngier if (gic_data.rdists.has_vlpis) 95196806229SMarc Zyngier pr_info("GICv4 features: %s%s%s\n", 95296806229SMarc Zyngier gic_data.rdists.has_direct_lpi ? "DirectLPI " : "", 95396806229SMarc Zyngier gic_data.rdists.has_rvpeid ? "RVPEID " : "", 95496806229SMarc Zyngier gic_data.rdists.has_vpend_valid_dirty ? "Valid+Dirty " : ""); 9550edc23eaSMarc Zyngier } 9560edc23eaSMarc Zyngier 957d98d0a99SJulien Thierry /* Check whether it's single security state view */ 958d98d0a99SJulien Thierry static inline bool gic_dist_security_disabled(void) 959d98d0a99SJulien Thierry { 960d98d0a99SJulien Thierry return readl_relaxed(gic_data.dist_base + GICD_CTLR) & GICD_CTLR_DS; 961d98d0a99SJulien Thierry } 962d98d0a99SJulien Thierry 9633708d52fSSudeep Holla static void gic_cpu_sys_reg_init(void) 964021f6537SMarc Zyngier { 965eda0d04aSShanker Donthineni int i, cpu = smp_processor_id(); 966eda0d04aSShanker Donthineni u64 mpidr = cpu_logical_map(cpu); 967eda0d04aSShanker Donthineni u64 need_rss = MPIDR_RS(mpidr); 96833625282SMarc Zyngier bool group0; 969b5cf6073SJulien Thierry u32 pribits; 970eda0d04aSShanker Donthineni 9717cabd008SMarc Zyngier /* 9727cabd008SMarc Zyngier * Need to check that the SRE bit has actually been set. If 9737cabd008SMarc Zyngier * not, it means that SRE is disabled at EL2. We're going to 9747cabd008SMarc Zyngier * die painfully, and there is nothing we can do about it. 9757cabd008SMarc Zyngier * 9767cabd008SMarc Zyngier * Kindly inform the luser. 9777cabd008SMarc Zyngier */ 9787cabd008SMarc Zyngier if (!gic_enable_sre()) 9797cabd008SMarc Zyngier pr_err("GIC: unable to set SRE (disabled at EL2), panic ahead\n"); 980021f6537SMarc Zyngier 981b5cf6073SJulien Thierry pribits = gic_get_pribits(); 98233625282SMarc Zyngier 983b5cf6073SJulien Thierry group0 = gic_has_group0(); 98433625282SMarc Zyngier 985021f6537SMarc Zyngier /* Set priority mask register */ 986d98d0a99SJulien Thierry if (!gic_prio_masking_enabled()) { 98733625282SMarc Zyngier write_gicreg(DEFAULT_PMR_VALUE, ICC_PMR_EL1); 98833678059SAlexandru Elisei } else if (gic_supports_nmi()) { 989d98d0a99SJulien Thierry /* 990d98d0a99SJulien Thierry * Mismatch configuration with boot CPU, the system is likely 991d98d0a99SJulien Thierry * to die as interrupt masking will not work properly on all 992d98d0a99SJulien Thierry * CPUs 99333678059SAlexandru Elisei * 99433678059SAlexandru Elisei * The boot CPU calls this function before enabling NMI support, 99533678059SAlexandru Elisei * and as a result we'll never see this warning in the boot path 99633678059SAlexandru Elisei * for that CPU. 997d98d0a99SJulien Thierry */ 99833678059SAlexandru Elisei if (static_branch_unlikely(&gic_nonsecure_priorities)) 99933678059SAlexandru Elisei WARN_ON(!group0 || gic_dist_security_disabled()); 100033678059SAlexandru Elisei else 100133678059SAlexandru Elisei WARN_ON(group0 && !gic_dist_security_disabled()); 1002d98d0a99SJulien Thierry } 1003021f6537SMarc Zyngier 100491ef8442SDaniel Thompson /* 100591ef8442SDaniel Thompson * Some firmwares hand over to the kernel with the BPR changed from 100691ef8442SDaniel Thompson * its reset value (and with a value large enough to prevent 100791ef8442SDaniel Thompson * any pre-emptive interrupts from working at all). Writing a zero 100891ef8442SDaniel Thompson * to BPR restores is reset value. 100991ef8442SDaniel Thompson */ 101091ef8442SDaniel Thompson gic_write_bpr1(0); 101191ef8442SDaniel Thompson 1012d01d3274SDavidlohr Bueso if (static_branch_likely(&supports_deactivate_key)) { 10130b6a3da9SMarc Zyngier /* EOI drops priority only (mode 1) */ 10140b6a3da9SMarc Zyngier gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop); 10150b6a3da9SMarc Zyngier } else { 1016021f6537SMarc Zyngier /* EOI deactivates interrupt too (mode 0) */ 1017021f6537SMarc Zyngier gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop_dir); 10180b6a3da9SMarc Zyngier } 1019021f6537SMarc Zyngier 102033625282SMarc Zyngier /* Always whack Group0 before Group1 */ 102133625282SMarc Zyngier if (group0) { 102233625282SMarc Zyngier switch(pribits) { 102333625282SMarc Zyngier case 8: 102433625282SMarc Zyngier case 7: 102533625282SMarc Zyngier write_gicreg(0, ICC_AP0R3_EL1); 102633625282SMarc Zyngier write_gicreg(0, ICC_AP0R2_EL1); 1027df561f66SGustavo A. R. Silva fallthrough; 102833625282SMarc Zyngier case 6: 102933625282SMarc Zyngier write_gicreg(0, ICC_AP0R1_EL1); 1030df561f66SGustavo A. R. Silva fallthrough; 103133625282SMarc Zyngier case 5: 103233625282SMarc Zyngier case 4: 103333625282SMarc Zyngier write_gicreg(0, ICC_AP0R0_EL1); 103433625282SMarc Zyngier } 1035d6062a6dSMarc Zyngier 103633625282SMarc Zyngier isb(); 103733625282SMarc Zyngier } 103833625282SMarc Zyngier 103933625282SMarc Zyngier switch(pribits) { 1040d6062a6dSMarc Zyngier case 8: 1041d6062a6dSMarc Zyngier case 7: 1042d6062a6dSMarc Zyngier write_gicreg(0, ICC_AP1R3_EL1); 1043d6062a6dSMarc Zyngier write_gicreg(0, ICC_AP1R2_EL1); 1044df561f66SGustavo A. R. Silva fallthrough; 1045d6062a6dSMarc Zyngier case 6: 1046d6062a6dSMarc Zyngier write_gicreg(0, ICC_AP1R1_EL1); 1047df561f66SGustavo A. R. Silva fallthrough; 1048d6062a6dSMarc Zyngier case 5: 1049d6062a6dSMarc Zyngier case 4: 1050d6062a6dSMarc Zyngier write_gicreg(0, ICC_AP1R0_EL1); 1051d6062a6dSMarc Zyngier } 1052d6062a6dSMarc Zyngier 1053d6062a6dSMarc Zyngier isb(); 1054d6062a6dSMarc Zyngier 1055021f6537SMarc Zyngier /* ... and let's hit the road... */ 1056021f6537SMarc Zyngier gic_write_grpen1(1); 1057eda0d04aSShanker Donthineni 1058eda0d04aSShanker Donthineni /* Keep the RSS capability status in per_cpu variable */ 1059eda0d04aSShanker Donthineni per_cpu(has_rss, cpu) = !!(gic_read_ctlr() & ICC_CTLR_EL1_RSS); 1060eda0d04aSShanker Donthineni 1061eda0d04aSShanker Donthineni /* Check all the CPUs have capable of sending SGIs to other CPUs */ 1062eda0d04aSShanker Donthineni for_each_online_cpu(i) { 1063eda0d04aSShanker Donthineni bool have_rss = per_cpu(has_rss, i) && per_cpu(has_rss, cpu); 1064eda0d04aSShanker Donthineni 1065eda0d04aSShanker Donthineni need_rss |= MPIDR_RS(cpu_logical_map(i)); 1066eda0d04aSShanker Donthineni if (need_rss && (!have_rss)) 1067eda0d04aSShanker Donthineni pr_crit("CPU%d (%lx) can't SGI CPU%d (%lx), no RSS\n", 1068eda0d04aSShanker Donthineni cpu, (unsigned long)mpidr, 1069eda0d04aSShanker Donthineni i, (unsigned long)cpu_logical_map(i)); 1070eda0d04aSShanker Donthineni } 1071eda0d04aSShanker Donthineni 1072eda0d04aSShanker Donthineni /** 1073eda0d04aSShanker Donthineni * GIC spec says, when ICC_CTLR_EL1.RSS==1 and GICD_TYPER.RSS==0, 1074eda0d04aSShanker Donthineni * writing ICC_ASGI1R_EL1 register with RS != 0 is a CONSTRAINED 1075eda0d04aSShanker Donthineni * UNPREDICTABLE choice of : 1076eda0d04aSShanker Donthineni * - The write is ignored. 1077eda0d04aSShanker Donthineni * - The RS field is treated as 0. 1078eda0d04aSShanker Donthineni */ 1079eda0d04aSShanker Donthineni if (need_rss && (!gic_data.has_rss)) 1080eda0d04aSShanker Donthineni pr_crit_once("RSS is required but GICD doesn't support it\n"); 1081021f6537SMarc Zyngier } 1082021f6537SMarc Zyngier 1083f736d65dSMarc Zyngier static bool gicv3_nolpi; 1084f736d65dSMarc Zyngier 1085f736d65dSMarc Zyngier static int __init gicv3_nolpi_cfg(char *buf) 1086f736d65dSMarc Zyngier { 1087f736d65dSMarc Zyngier return strtobool(buf, &gicv3_nolpi); 1088f736d65dSMarc Zyngier } 1089f736d65dSMarc Zyngier early_param("irqchip.gicv3_nolpi", gicv3_nolpi_cfg); 1090f736d65dSMarc Zyngier 1091da33f31dSMarc Zyngier static int gic_dist_supports_lpis(void) 1092da33f31dSMarc Zyngier { 1093d38a71c5SMarc Zyngier return (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && 1094d38a71c5SMarc Zyngier !!(readl_relaxed(gic_data.dist_base + GICD_TYPER) & GICD_TYPER_LPIS) && 1095d38a71c5SMarc Zyngier !gicv3_nolpi); 1096da33f31dSMarc Zyngier } 1097da33f31dSMarc Zyngier 1098021f6537SMarc Zyngier static void gic_cpu_init(void) 1099021f6537SMarc Zyngier { 1100021f6537SMarc Zyngier void __iomem *rbase; 11011a60e1e6SMarc Zyngier int i; 1102021f6537SMarc Zyngier 1103021f6537SMarc Zyngier /* Register ourselves with the rest of the world */ 1104021f6537SMarc Zyngier if (gic_populate_rdist()) 1105021f6537SMarc Zyngier return; 1106021f6537SMarc Zyngier 1107a2c22510SSudeep Holla gic_enable_redist(true); 1108021f6537SMarc Zyngier 1109ad5a78d3SMarc Zyngier WARN((gic_data.ppi_nr > 16 || GIC_ESPI_NR != 0) && 1110ad5a78d3SMarc Zyngier !(gic_read_ctlr() & ICC_CTLR_EL1_ExtRange), 1111ad5a78d3SMarc Zyngier "Distributor has extended ranges, but CPU%d doesn't\n", 1112ad5a78d3SMarc Zyngier smp_processor_id()); 1113ad5a78d3SMarc Zyngier 1114021f6537SMarc Zyngier rbase = gic_data_rdist_sgi_base(); 1115021f6537SMarc Zyngier 11167c9b9730SMarc Zyngier /* Configure SGIs/PPIs as non-secure Group-1 */ 11171a60e1e6SMarc Zyngier for (i = 0; i < gic_data.ppi_nr + 16; i += 32) 11181a60e1e6SMarc Zyngier writel_relaxed(~0, rbase + GICR_IGROUPR0 + i / 8); 11197c9b9730SMarc Zyngier 11201a60e1e6SMarc Zyngier gic_cpu_config(rbase, gic_data.ppi_nr + 16, gic_redist_wait_for_rwp); 1121021f6537SMarc Zyngier 11223708d52fSSudeep Holla /* initialise system registers */ 11233708d52fSSudeep Holla gic_cpu_sys_reg_init(); 1124021f6537SMarc Zyngier } 1125021f6537SMarc Zyngier 1126021f6537SMarc Zyngier #ifdef CONFIG_SMP 1127021f6537SMarc Zyngier 1128eda0d04aSShanker Donthineni #define MPIDR_TO_SGI_RS(mpidr) (MPIDR_RS(mpidr) << ICC_SGI1R_RS_SHIFT) 1129eda0d04aSShanker Donthineni #define MPIDR_TO_SGI_CLUSTER_ID(mpidr) ((mpidr) & ~0xFUL) 1130eda0d04aSShanker Donthineni 11316670a6d8SRichard Cochran static int gic_starting_cpu(unsigned int cpu) 11326670a6d8SRichard Cochran { 11336670a6d8SRichard Cochran gic_cpu_init(); 1134d38a71c5SMarc Zyngier 1135d38a71c5SMarc Zyngier if (gic_dist_supports_lpis()) 1136d38a71c5SMarc Zyngier its_cpu_init(); 1137d38a71c5SMarc Zyngier 11386670a6d8SRichard Cochran return 0; 11396670a6d8SRichard Cochran } 1140021f6537SMarc Zyngier 1141021f6537SMarc Zyngier static u16 gic_compute_target_list(int *base_cpu, const struct cpumask *mask, 1142f6c86a41SJean-Philippe Brucker unsigned long cluster_id) 1143021f6537SMarc Zyngier { 1144727653d6SJames Morse int next_cpu, cpu = *base_cpu; 1145f6c86a41SJean-Philippe Brucker unsigned long mpidr = cpu_logical_map(cpu); 1146021f6537SMarc Zyngier u16 tlist = 0; 1147021f6537SMarc Zyngier 1148021f6537SMarc Zyngier while (cpu < nr_cpu_ids) { 1149021f6537SMarc Zyngier tlist |= 1 << (mpidr & 0xf); 1150021f6537SMarc Zyngier 1151727653d6SJames Morse next_cpu = cpumask_next(cpu, mask); 1152727653d6SJames Morse if (next_cpu >= nr_cpu_ids) 1153021f6537SMarc Zyngier goto out; 1154727653d6SJames Morse cpu = next_cpu; 1155021f6537SMarc Zyngier 1156021f6537SMarc Zyngier mpidr = cpu_logical_map(cpu); 1157021f6537SMarc Zyngier 1158eda0d04aSShanker Donthineni if (cluster_id != MPIDR_TO_SGI_CLUSTER_ID(mpidr)) { 1159021f6537SMarc Zyngier cpu--; 1160021f6537SMarc Zyngier goto out; 1161021f6537SMarc Zyngier } 1162021f6537SMarc Zyngier } 1163021f6537SMarc Zyngier out: 1164021f6537SMarc Zyngier *base_cpu = cpu; 1165021f6537SMarc Zyngier return tlist; 1166021f6537SMarc Zyngier } 1167021f6537SMarc Zyngier 11687e580278SAndre Przywara #define MPIDR_TO_SGI_AFFINITY(cluster_id, level) \ 11697e580278SAndre Przywara (MPIDR_AFFINITY_LEVEL(cluster_id, level) \ 11707e580278SAndre Przywara << ICC_SGI1R_AFFINITY_## level ##_SHIFT) 11717e580278SAndre Przywara 1172021f6537SMarc Zyngier static void gic_send_sgi(u64 cluster_id, u16 tlist, unsigned int irq) 1173021f6537SMarc Zyngier { 1174021f6537SMarc Zyngier u64 val; 1175021f6537SMarc Zyngier 11767e580278SAndre Przywara val = (MPIDR_TO_SGI_AFFINITY(cluster_id, 3) | 11777e580278SAndre Przywara MPIDR_TO_SGI_AFFINITY(cluster_id, 2) | 11787e580278SAndre Przywara irq << ICC_SGI1R_SGI_ID_SHIFT | 11797e580278SAndre Przywara MPIDR_TO_SGI_AFFINITY(cluster_id, 1) | 1180eda0d04aSShanker Donthineni MPIDR_TO_SGI_RS(cluster_id) | 11817e580278SAndre Przywara tlist << ICC_SGI1R_TARGET_LIST_SHIFT); 1182021f6537SMarc Zyngier 1183b6dd4d83SMark Salter pr_devel("CPU%d: ICC_SGI1R_EL1 %llx\n", smp_processor_id(), val); 1184021f6537SMarc Zyngier gic_write_sgi1r(val); 1185021f6537SMarc Zyngier } 1186021f6537SMarc Zyngier 118764b499d8SMarc Zyngier static void gic_ipi_send_mask(struct irq_data *d, const struct cpumask *mask) 1188021f6537SMarc Zyngier { 1189021f6537SMarc Zyngier int cpu; 1190021f6537SMarc Zyngier 119164b499d8SMarc Zyngier if (WARN_ON(d->hwirq >= 16)) 1192021f6537SMarc Zyngier return; 1193021f6537SMarc Zyngier 1194021f6537SMarc Zyngier /* 1195021f6537SMarc Zyngier * Ensure that stores to Normal memory are visible to the 1196021f6537SMarc Zyngier * other CPUs before issuing the IPI. 1197021f6537SMarc Zyngier */ 119821ec30c0SShanker Donthineni wmb(); 1199021f6537SMarc Zyngier 1200f9b531feSRusty Russell for_each_cpu(cpu, mask) { 1201eda0d04aSShanker Donthineni u64 cluster_id = MPIDR_TO_SGI_CLUSTER_ID(cpu_logical_map(cpu)); 1202021f6537SMarc Zyngier u16 tlist; 1203021f6537SMarc Zyngier 1204021f6537SMarc Zyngier tlist = gic_compute_target_list(&cpu, mask, cluster_id); 120564b499d8SMarc Zyngier gic_send_sgi(cluster_id, tlist, d->hwirq); 1206021f6537SMarc Zyngier } 1207021f6537SMarc Zyngier 1208021f6537SMarc Zyngier /* Force the above writes to ICC_SGI1R_EL1 to be executed */ 1209021f6537SMarc Zyngier isb(); 1210021f6537SMarc Zyngier } 1211021f6537SMarc Zyngier 12128a94c1abSIngo Rohloff static void __init gic_smp_init(void) 1213021f6537SMarc Zyngier { 121464b499d8SMarc Zyngier struct irq_fwspec sgi_fwspec = { 121564b499d8SMarc Zyngier .fwnode = gic_data.fwnode, 121664b499d8SMarc Zyngier .param_count = 1, 121764b499d8SMarc Zyngier }; 121864b499d8SMarc Zyngier int base_sgi; 121964b499d8SMarc Zyngier 12206896bcd1SThomas Gleixner cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_GIC_STARTING, 122173c1b41eSThomas Gleixner "irqchip/arm/gicv3:starting", 122273c1b41eSThomas Gleixner gic_starting_cpu, NULL); 122364b499d8SMarc Zyngier 122464b499d8SMarc Zyngier /* Register all 8 non-secure SGIs */ 122564b499d8SMarc Zyngier base_sgi = __irq_domain_alloc_irqs(gic_data.domain, -1, 8, 122664b499d8SMarc Zyngier NUMA_NO_NODE, &sgi_fwspec, 122764b499d8SMarc Zyngier false, NULL); 122864b499d8SMarc Zyngier if (WARN_ON(base_sgi <= 0)) 122964b499d8SMarc Zyngier return; 123064b499d8SMarc Zyngier 123164b499d8SMarc Zyngier set_smp_ipi_range(base_sgi, 8); 1232021f6537SMarc Zyngier } 1233021f6537SMarc Zyngier 1234021f6537SMarc Zyngier static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, 1235021f6537SMarc Zyngier bool force) 1236021f6537SMarc Zyngier { 123765a30f8bSSuzuki K Poulose unsigned int cpu; 1238e91b036eSMarc Zyngier u32 offset, index; 1239021f6537SMarc Zyngier void __iomem *reg; 1240021f6537SMarc Zyngier int enabled; 1241021f6537SMarc Zyngier u64 val; 1242021f6537SMarc Zyngier 124365a30f8bSSuzuki K Poulose if (force) 124465a30f8bSSuzuki K Poulose cpu = cpumask_first(mask_val); 124565a30f8bSSuzuki K Poulose else 124665a30f8bSSuzuki K Poulose cpu = cpumask_any_and(mask_val, cpu_online_mask); 124765a30f8bSSuzuki K Poulose 1248866d7c1bSSuzuki K Poulose if (cpu >= nr_cpu_ids) 1249866d7c1bSSuzuki K Poulose return -EINVAL; 1250866d7c1bSSuzuki K Poulose 1251021f6537SMarc Zyngier if (gic_irq_in_rdist(d)) 1252021f6537SMarc Zyngier return -EINVAL; 1253021f6537SMarc Zyngier 1254021f6537SMarc Zyngier /* If interrupt was enabled, disable it first */ 1255021f6537SMarc Zyngier enabled = gic_peek_irq(d, GICD_ISENABLER); 1256021f6537SMarc Zyngier if (enabled) 1257021f6537SMarc Zyngier gic_mask_irq(d); 1258021f6537SMarc Zyngier 1259e91b036eSMarc Zyngier offset = convert_offset_index(d, GICD_IROUTER, &index); 1260e91b036eSMarc Zyngier reg = gic_dist_base(d) + offset + (index * 8); 1261021f6537SMarc Zyngier val = gic_mpidr_to_affinity(cpu_logical_map(cpu)); 1262021f6537SMarc Zyngier 126372c97126SJean-Philippe Brucker gic_write_irouter(val, reg); 1264021f6537SMarc Zyngier 1265021f6537SMarc Zyngier /* 1266021f6537SMarc Zyngier * If the interrupt was enabled, enabled it again. Otherwise, 1267021f6537SMarc Zyngier * just wait for the distributor to have digested our changes. 1268021f6537SMarc Zyngier */ 1269021f6537SMarc Zyngier if (enabled) 1270021f6537SMarc Zyngier gic_unmask_irq(d); 1271021f6537SMarc Zyngier else 1272021f6537SMarc Zyngier gic_dist_wait_for_rwp(); 1273021f6537SMarc Zyngier 1274956ae91aSMarc Zyngier irq_data_update_effective_affinity(d, cpumask_of(cpu)); 1275956ae91aSMarc Zyngier 12760fc6fa29SAntoine Tenart return IRQ_SET_MASK_OK_DONE; 1277021f6537SMarc Zyngier } 1278021f6537SMarc Zyngier #else 1279021f6537SMarc Zyngier #define gic_set_affinity NULL 128064b499d8SMarc Zyngier #define gic_ipi_send_mask NULL 1281021f6537SMarc Zyngier #define gic_smp_init() do { } while(0) 1282021f6537SMarc Zyngier #endif 1283021f6537SMarc Zyngier 128417f644e9SValentin Schneider static int gic_retrigger(struct irq_data *data) 128517f644e9SValentin Schneider { 128617f644e9SValentin Schneider return !gic_irq_set_irqchip_state(data, IRQCHIP_STATE_PENDING, true); 128717f644e9SValentin Schneider } 128817f644e9SValentin Schneider 12893708d52fSSudeep Holla #ifdef CONFIG_CPU_PM 12903708d52fSSudeep Holla static int gic_cpu_pm_notifier(struct notifier_block *self, 12913708d52fSSudeep Holla unsigned long cmd, void *v) 12923708d52fSSudeep Holla { 12933708d52fSSudeep Holla if (cmd == CPU_PM_EXIT) { 1294ccd9432aSSudeep Holla if (gic_dist_security_disabled()) 12953708d52fSSudeep Holla gic_enable_redist(true); 12963708d52fSSudeep Holla gic_cpu_sys_reg_init(); 1297ccd9432aSSudeep Holla } else if (cmd == CPU_PM_ENTER && gic_dist_security_disabled()) { 12983708d52fSSudeep Holla gic_write_grpen1(0); 12993708d52fSSudeep Holla gic_enable_redist(false); 13003708d52fSSudeep Holla } 13013708d52fSSudeep Holla return NOTIFY_OK; 13023708d52fSSudeep Holla } 13033708d52fSSudeep Holla 13043708d52fSSudeep Holla static struct notifier_block gic_cpu_pm_notifier_block = { 13053708d52fSSudeep Holla .notifier_call = gic_cpu_pm_notifier, 13063708d52fSSudeep Holla }; 13073708d52fSSudeep Holla 13083708d52fSSudeep Holla static void gic_cpu_pm_init(void) 13093708d52fSSudeep Holla { 13103708d52fSSudeep Holla cpu_pm_register_notifier(&gic_cpu_pm_notifier_block); 13113708d52fSSudeep Holla } 13123708d52fSSudeep Holla 13133708d52fSSudeep Holla #else 13143708d52fSSudeep Holla static inline void gic_cpu_pm_init(void) { } 13153708d52fSSudeep Holla #endif /* CONFIG_CPU_PM */ 13163708d52fSSudeep Holla 1317021f6537SMarc Zyngier static struct irq_chip gic_chip = { 1318021f6537SMarc Zyngier .name = "GICv3", 1319021f6537SMarc Zyngier .irq_mask = gic_mask_irq, 1320021f6537SMarc Zyngier .irq_unmask = gic_unmask_irq, 1321021f6537SMarc Zyngier .irq_eoi = gic_eoi_irq, 1322021f6537SMarc Zyngier .irq_set_type = gic_set_type, 1323021f6537SMarc Zyngier .irq_set_affinity = gic_set_affinity, 132417f644e9SValentin Schneider .irq_retrigger = gic_retrigger, 1325b594c6e2SMarc Zyngier .irq_get_irqchip_state = gic_irq_get_irqchip_state, 1326b594c6e2SMarc Zyngier .irq_set_irqchip_state = gic_irq_set_irqchip_state, 1327101b35f7SJulien Thierry .irq_nmi_setup = gic_irq_nmi_setup, 1328101b35f7SJulien Thierry .irq_nmi_teardown = gic_irq_nmi_teardown, 132964b499d8SMarc Zyngier .ipi_send_mask = gic_ipi_send_mask, 13304110b5cbSMarc Zyngier .flags = IRQCHIP_SET_TYPE_MASKED | 13314110b5cbSMarc Zyngier IRQCHIP_SKIP_SET_WAKE | 13324110b5cbSMarc Zyngier IRQCHIP_MASK_ON_SUSPEND, 1333021f6537SMarc Zyngier }; 1334021f6537SMarc Zyngier 13350b6a3da9SMarc Zyngier static struct irq_chip gic_eoimode1_chip = { 13360b6a3da9SMarc Zyngier .name = "GICv3", 13370b6a3da9SMarc Zyngier .irq_mask = gic_eoimode1_mask_irq, 13380b6a3da9SMarc Zyngier .irq_unmask = gic_unmask_irq, 13390b6a3da9SMarc Zyngier .irq_eoi = gic_eoimode1_eoi_irq, 13400b6a3da9SMarc Zyngier .irq_set_type = gic_set_type, 13410b6a3da9SMarc Zyngier .irq_set_affinity = gic_set_affinity, 134217f644e9SValentin Schneider .irq_retrigger = gic_retrigger, 13430b6a3da9SMarc Zyngier .irq_get_irqchip_state = gic_irq_get_irqchip_state, 13440b6a3da9SMarc Zyngier .irq_set_irqchip_state = gic_irq_set_irqchip_state, 1345530bf353SMarc Zyngier .irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity, 1346101b35f7SJulien Thierry .irq_nmi_setup = gic_irq_nmi_setup, 1347101b35f7SJulien Thierry .irq_nmi_teardown = gic_irq_nmi_teardown, 134864b499d8SMarc Zyngier .ipi_send_mask = gic_ipi_send_mask, 13494110b5cbSMarc Zyngier .flags = IRQCHIP_SET_TYPE_MASKED | 13504110b5cbSMarc Zyngier IRQCHIP_SKIP_SET_WAKE | 13514110b5cbSMarc Zyngier IRQCHIP_MASK_ON_SUSPEND, 13520b6a3da9SMarc Zyngier }; 13530b6a3da9SMarc Zyngier 1354021f6537SMarc Zyngier static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq, 1355021f6537SMarc Zyngier irq_hw_number_t hw) 1356021f6537SMarc Zyngier { 13570b6a3da9SMarc Zyngier struct irq_chip *chip = &gic_chip; 13581b57d91bSValentin Schneider struct irq_data *irqd = irq_desc_get_irq_data(irq_to_desc(irq)); 13590b6a3da9SMarc Zyngier 1360d01d3274SDavidlohr Bueso if (static_branch_likely(&supports_deactivate_key)) 13610b6a3da9SMarc Zyngier chip = &gic_eoimode1_chip; 13620b6a3da9SMarc Zyngier 1363e91b036eSMarc Zyngier switch (__get_intid_range(hw)) { 136470a29c32SMarc Zyngier case SGI_RANGE: 1365e91b036eSMarc Zyngier case PPI_RANGE: 13665f51f803SMarc Zyngier case EPPI_RANGE: 1367021f6537SMarc Zyngier irq_set_percpu_devid(irq); 13680b6a3da9SMarc Zyngier irq_domain_set_info(d, irq, hw, chip, d->host_data, 1369443acc4fSMarc Zyngier handle_percpu_devid_irq, NULL, NULL); 1370e91b036eSMarc Zyngier break; 1371e91b036eSMarc Zyngier 1372e91b036eSMarc Zyngier case SPI_RANGE: 1373211bddd2SMarc Zyngier case ESPI_RANGE: 13740b6a3da9SMarc Zyngier irq_domain_set_info(d, irq, hw, chip, d->host_data, 1375443acc4fSMarc Zyngier handle_fasteoi_irq, NULL, NULL); 1376d17cab44SRob Herring irq_set_probe(irq); 13771b57d91bSValentin Schneider irqd_set_single_target(irqd); 1378e91b036eSMarc Zyngier break; 1379e91b036eSMarc Zyngier 1380e91b036eSMarc Zyngier case LPI_RANGE: 1381da33f31dSMarc Zyngier if (!gic_dist_supports_lpis()) 1382da33f31dSMarc Zyngier return -EPERM; 13830b6a3da9SMarc Zyngier irq_domain_set_info(d, irq, hw, chip, d->host_data, 1384da33f31dSMarc Zyngier handle_fasteoi_irq, NULL, NULL); 1385e91b036eSMarc Zyngier break; 1386e91b036eSMarc Zyngier 1387e91b036eSMarc Zyngier default: 1388e91b036eSMarc Zyngier return -EPERM; 1389da33f31dSMarc Zyngier } 1390da33f31dSMarc Zyngier 13911b57d91bSValentin Schneider /* Prevents SW retriggers which mess up the ACK/EOI ordering */ 13921b57d91bSValentin Schneider irqd_set_handle_enforce_irqctx(irqd); 1393021f6537SMarc Zyngier return 0; 1394021f6537SMarc Zyngier } 1395021f6537SMarc Zyngier 1396f833f57fSMarc Zyngier static int gic_irq_domain_translate(struct irq_domain *d, 1397f833f57fSMarc Zyngier struct irq_fwspec *fwspec, 1398f833f57fSMarc Zyngier unsigned long *hwirq, 1399f833f57fSMarc Zyngier unsigned int *type) 1400021f6537SMarc Zyngier { 140164b499d8SMarc Zyngier if (fwspec->param_count == 1 && fwspec->param[0] < 16) { 140264b499d8SMarc Zyngier *hwirq = fwspec->param[0]; 140364b499d8SMarc Zyngier *type = IRQ_TYPE_EDGE_RISING; 140464b499d8SMarc Zyngier return 0; 140564b499d8SMarc Zyngier } 140664b499d8SMarc Zyngier 1407f833f57fSMarc Zyngier if (is_of_node(fwspec->fwnode)) { 1408f833f57fSMarc Zyngier if (fwspec->param_count < 3) 1409021f6537SMarc Zyngier return -EINVAL; 1410021f6537SMarc Zyngier 1411db8c70ecSMarc Zyngier switch (fwspec->param[0]) { 1412db8c70ecSMarc Zyngier case 0: /* SPI */ 1413db8c70ecSMarc Zyngier *hwirq = fwspec->param[1] + 32; 1414db8c70ecSMarc Zyngier break; 1415db8c70ecSMarc Zyngier case 1: /* PPI */ 1416f833f57fSMarc Zyngier *hwirq = fwspec->param[1] + 16; 1417db8c70ecSMarc Zyngier break; 1418211bddd2SMarc Zyngier case 2: /* ESPI */ 1419211bddd2SMarc Zyngier *hwirq = fwspec->param[1] + ESPI_BASE_INTID; 1420211bddd2SMarc Zyngier break; 14215f51f803SMarc Zyngier case 3: /* EPPI */ 14225f51f803SMarc Zyngier *hwirq = fwspec->param[1] + EPPI_BASE_INTID; 14235f51f803SMarc Zyngier break; 1424db8c70ecSMarc Zyngier case GIC_IRQ_TYPE_LPI: /* LPI */ 1425db8c70ecSMarc Zyngier *hwirq = fwspec->param[1]; 1426db8c70ecSMarc Zyngier break; 14275f51f803SMarc Zyngier case GIC_IRQ_TYPE_PARTITION: 14285f51f803SMarc Zyngier *hwirq = fwspec->param[1]; 14295f51f803SMarc Zyngier if (fwspec->param[1] >= 16) 14305f51f803SMarc Zyngier *hwirq += EPPI_BASE_INTID - 16; 14315f51f803SMarc Zyngier else 14325f51f803SMarc Zyngier *hwirq += 16; 14335f51f803SMarc Zyngier break; 1434db8c70ecSMarc Zyngier default: 1435db8c70ecSMarc Zyngier return -EINVAL; 1436db8c70ecSMarc Zyngier } 1437f833f57fSMarc Zyngier 1438f833f57fSMarc Zyngier *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; 14396ef6386eSMarc Zyngier 144065da7d19SMarc Zyngier /* 144165da7d19SMarc Zyngier * Make it clear that broken DTs are... broken. 1442a359f757SIngo Molnar * Partitioned PPIs are an unfortunate exception. 144365da7d19SMarc Zyngier */ 144465da7d19SMarc Zyngier WARN_ON(*type == IRQ_TYPE_NONE && 144565da7d19SMarc Zyngier fwspec->param[0] != GIC_IRQ_TYPE_PARTITION); 1446f833f57fSMarc Zyngier return 0; 1447021f6537SMarc Zyngier } 1448021f6537SMarc Zyngier 1449ffa7d616STomasz Nowicki if (is_fwnode_irqchip(fwspec->fwnode)) { 1450ffa7d616STomasz Nowicki if(fwspec->param_count != 2) 1451ffa7d616STomasz Nowicki return -EINVAL; 1452ffa7d616STomasz Nowicki 1453ffa7d616STomasz Nowicki *hwirq = fwspec->param[0]; 1454ffa7d616STomasz Nowicki *type = fwspec->param[1]; 14556ef6386eSMarc Zyngier 14566ef6386eSMarc Zyngier WARN_ON(*type == IRQ_TYPE_NONE); 1457ffa7d616STomasz Nowicki return 0; 1458ffa7d616STomasz Nowicki } 1459ffa7d616STomasz Nowicki 1460f833f57fSMarc Zyngier return -EINVAL; 1461021f6537SMarc Zyngier } 1462021f6537SMarc Zyngier 1463443acc4fSMarc Zyngier static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, 1464443acc4fSMarc Zyngier unsigned int nr_irqs, void *arg) 1465443acc4fSMarc Zyngier { 1466443acc4fSMarc Zyngier int i, ret; 1467443acc4fSMarc Zyngier irq_hw_number_t hwirq; 1468443acc4fSMarc Zyngier unsigned int type = IRQ_TYPE_NONE; 1469f833f57fSMarc Zyngier struct irq_fwspec *fwspec = arg; 1470443acc4fSMarc Zyngier 1471f833f57fSMarc Zyngier ret = gic_irq_domain_translate(domain, fwspec, &hwirq, &type); 1472443acc4fSMarc Zyngier if (ret) 1473443acc4fSMarc Zyngier return ret; 1474443acc4fSMarc Zyngier 147563c16c6eSSuzuki K Poulose for (i = 0; i < nr_irqs; i++) { 147663c16c6eSSuzuki K Poulose ret = gic_irq_domain_map(domain, virq + i, hwirq + i); 147763c16c6eSSuzuki K Poulose if (ret) 147863c16c6eSSuzuki K Poulose return ret; 147963c16c6eSSuzuki K Poulose } 1480443acc4fSMarc Zyngier 1481443acc4fSMarc Zyngier return 0; 1482443acc4fSMarc Zyngier } 1483443acc4fSMarc Zyngier 1484443acc4fSMarc Zyngier static void gic_irq_domain_free(struct irq_domain *domain, unsigned int virq, 1485443acc4fSMarc Zyngier unsigned int nr_irqs) 1486443acc4fSMarc Zyngier { 1487443acc4fSMarc Zyngier int i; 1488443acc4fSMarc Zyngier 1489443acc4fSMarc Zyngier for (i = 0; i < nr_irqs; i++) { 1490443acc4fSMarc Zyngier struct irq_data *d = irq_domain_get_irq_data(domain, virq + i); 1491443acc4fSMarc Zyngier irq_set_handler(virq + i, NULL); 1492443acc4fSMarc Zyngier irq_domain_reset_irq_data(d); 1493443acc4fSMarc Zyngier } 1494443acc4fSMarc Zyngier } 1495443acc4fSMarc Zyngier 1496d753f849SJames Morse static bool fwspec_is_partitioned_ppi(struct irq_fwspec *fwspec, 1497d753f849SJames Morse irq_hw_number_t hwirq) 1498d753f849SJames Morse { 1499d753f849SJames Morse enum gic_intid_range range; 1500d753f849SJames Morse 1501d753f849SJames Morse if (!gic_data.ppi_descs) 1502d753f849SJames Morse return false; 1503d753f849SJames Morse 1504d753f849SJames Morse if (!is_of_node(fwspec->fwnode)) 1505d753f849SJames Morse return false; 1506d753f849SJames Morse 1507d753f849SJames Morse if (fwspec->param_count < 4 || !fwspec->param[3]) 1508d753f849SJames Morse return false; 1509d753f849SJames Morse 1510d753f849SJames Morse range = __get_intid_range(hwirq); 1511d753f849SJames Morse if (range != PPI_RANGE && range != EPPI_RANGE) 1512d753f849SJames Morse return false; 1513d753f849SJames Morse 1514d753f849SJames Morse return true; 1515d753f849SJames Morse } 1516d753f849SJames Morse 1517e3825ba1SMarc Zyngier static int gic_irq_domain_select(struct irq_domain *d, 1518e3825ba1SMarc Zyngier struct irq_fwspec *fwspec, 1519e3825ba1SMarc Zyngier enum irq_domain_bus_token bus_token) 1520e3825ba1SMarc Zyngier { 1521d753f849SJames Morse unsigned int type, ret, ppi_idx; 1522d753f849SJames Morse irq_hw_number_t hwirq; 1523d753f849SJames Morse 1524e3825ba1SMarc Zyngier /* Not for us */ 1525e3825ba1SMarc Zyngier if (fwspec->fwnode != d->fwnode) 1526e3825ba1SMarc Zyngier return 0; 1527e3825ba1SMarc Zyngier 1528e3825ba1SMarc Zyngier /* If this is not DT, then we have a single domain */ 1529e3825ba1SMarc Zyngier if (!is_of_node(fwspec->fwnode)) 1530e3825ba1SMarc Zyngier return 1; 1531e3825ba1SMarc Zyngier 1532d753f849SJames Morse ret = gic_irq_domain_translate(d, fwspec, &hwirq, &type); 1533d753f849SJames Morse if (WARN_ON_ONCE(ret)) 1534d753f849SJames Morse return 0; 1535d753f849SJames Morse 1536d753f849SJames Morse if (!fwspec_is_partitioned_ppi(fwspec, hwirq)) 1537d753f849SJames Morse return d == gic_data.domain; 1538d753f849SJames Morse 1539e3825ba1SMarc Zyngier /* 1540e3825ba1SMarc Zyngier * If this is a PPI and we have a 4th (non-null) parameter, 1541e3825ba1SMarc Zyngier * then we need to match the partition domain. 1542e3825ba1SMarc Zyngier */ 1543d753f849SJames Morse ppi_idx = __gic_get_ppi_index(hwirq); 1544d753f849SJames Morse return d == partition_get_domain(gic_data.ppi_descs[ppi_idx]); 1545e3825ba1SMarc Zyngier } 1546e3825ba1SMarc Zyngier 1547021f6537SMarc Zyngier static const struct irq_domain_ops gic_irq_domain_ops = { 1548f833f57fSMarc Zyngier .translate = gic_irq_domain_translate, 1549443acc4fSMarc Zyngier .alloc = gic_irq_domain_alloc, 1550443acc4fSMarc Zyngier .free = gic_irq_domain_free, 1551e3825ba1SMarc Zyngier .select = gic_irq_domain_select, 1552e3825ba1SMarc Zyngier }; 1553e3825ba1SMarc Zyngier 1554e3825ba1SMarc Zyngier static int partition_domain_translate(struct irq_domain *d, 1555e3825ba1SMarc Zyngier struct irq_fwspec *fwspec, 1556e3825ba1SMarc Zyngier unsigned long *hwirq, 1557e3825ba1SMarc Zyngier unsigned int *type) 1558e3825ba1SMarc Zyngier { 1559d753f849SJames Morse unsigned long ppi_intid; 1560e3825ba1SMarc Zyngier struct device_node *np; 1561d753f849SJames Morse unsigned int ppi_idx; 1562e3825ba1SMarc Zyngier int ret; 1563e3825ba1SMarc Zyngier 156452085d3fSMarc Zyngier if (!gic_data.ppi_descs) 156552085d3fSMarc Zyngier return -ENOMEM; 156652085d3fSMarc Zyngier 1567e3825ba1SMarc Zyngier np = of_find_node_by_phandle(fwspec->param[3]); 1568e3825ba1SMarc Zyngier if (WARN_ON(!np)) 1569e3825ba1SMarc Zyngier return -EINVAL; 1570e3825ba1SMarc Zyngier 1571d753f849SJames Morse ret = gic_irq_domain_translate(d, fwspec, &ppi_intid, type); 1572d753f849SJames Morse if (WARN_ON_ONCE(ret)) 1573d753f849SJames Morse return 0; 1574d753f849SJames Morse 1575d753f849SJames Morse ppi_idx = __gic_get_ppi_index(ppi_intid); 1576d753f849SJames Morse ret = partition_translate_id(gic_data.ppi_descs[ppi_idx], 1577e3825ba1SMarc Zyngier of_node_to_fwnode(np)); 1578e3825ba1SMarc Zyngier if (ret < 0) 1579e3825ba1SMarc Zyngier return ret; 1580e3825ba1SMarc Zyngier 1581e3825ba1SMarc Zyngier *hwirq = ret; 1582e3825ba1SMarc Zyngier *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; 1583e3825ba1SMarc Zyngier 1584e3825ba1SMarc Zyngier return 0; 1585e3825ba1SMarc Zyngier } 1586e3825ba1SMarc Zyngier 1587e3825ba1SMarc Zyngier static const struct irq_domain_ops partition_domain_ops = { 1588e3825ba1SMarc Zyngier .translate = partition_domain_translate, 1589e3825ba1SMarc Zyngier .select = gic_irq_domain_select, 1590021f6537SMarc Zyngier }; 1591021f6537SMarc Zyngier 15929c8114c2SSrinivas Kandagatla static bool gic_enable_quirk_msm8996(void *data) 15939c8114c2SSrinivas Kandagatla { 15949c8114c2SSrinivas Kandagatla struct gic_chip_data *d = data; 15959c8114c2SSrinivas Kandagatla 15969c8114c2SSrinivas Kandagatla d->flags |= FLAGS_WORKAROUND_GICR_WAKER_MSM8996; 15979c8114c2SSrinivas Kandagatla 15989c8114c2SSrinivas Kandagatla return true; 15999c8114c2SSrinivas Kandagatla } 16009c8114c2SSrinivas Kandagatla 1601d01fd161SMarc Zyngier static bool gic_enable_quirk_cavium_38539(void *data) 1602d01fd161SMarc Zyngier { 1603d01fd161SMarc Zyngier struct gic_chip_data *d = data; 1604d01fd161SMarc Zyngier 1605d01fd161SMarc Zyngier d->flags |= FLAGS_WORKAROUND_CAVIUM_ERRATUM_38539; 1606d01fd161SMarc Zyngier 1607d01fd161SMarc Zyngier return true; 1608d01fd161SMarc Zyngier } 1609d01fd161SMarc Zyngier 16107f2481b3SMarc Zyngier static bool gic_enable_quirk_hip06_07(void *data) 16117f2481b3SMarc Zyngier { 16127f2481b3SMarc Zyngier struct gic_chip_data *d = data; 16137f2481b3SMarc Zyngier 16147f2481b3SMarc Zyngier /* 16157f2481b3SMarc Zyngier * HIP06 GICD_IIDR clashes with GIC-600 product number (despite 16167f2481b3SMarc Zyngier * not being an actual ARM implementation). The saving grace is 16177f2481b3SMarc Zyngier * that GIC-600 doesn't have ESPI, so nothing to do in that case. 16187f2481b3SMarc Zyngier * HIP07 doesn't even have a proper IIDR, and still pretends to 16197f2481b3SMarc Zyngier * have ESPI. In both cases, put them right. 16207f2481b3SMarc Zyngier */ 16217f2481b3SMarc Zyngier if (d->rdists.gicd_typer & GICD_TYPER_ESPI) { 16227f2481b3SMarc Zyngier /* Zero both ESPI and the RES0 field next to it... */ 16237f2481b3SMarc Zyngier d->rdists.gicd_typer &= ~GENMASK(9, 8); 16247f2481b3SMarc Zyngier return true; 16257f2481b3SMarc Zyngier } 16267f2481b3SMarc Zyngier 16277f2481b3SMarc Zyngier return false; 16287f2481b3SMarc Zyngier } 16297f2481b3SMarc Zyngier 16307f2481b3SMarc Zyngier static const struct gic_quirk gic_quirks[] = { 16317f2481b3SMarc Zyngier { 16327f2481b3SMarc Zyngier .desc = "GICv3: Qualcomm MSM8996 broken firmware", 16337f2481b3SMarc Zyngier .compatible = "qcom,msm8996-gic-v3", 16347f2481b3SMarc Zyngier .init = gic_enable_quirk_msm8996, 16357f2481b3SMarc Zyngier }, 16367f2481b3SMarc Zyngier { 16377f2481b3SMarc Zyngier .desc = "GICv3: HIP06 erratum 161010803", 16387f2481b3SMarc Zyngier .iidr = 0x0204043b, 16397f2481b3SMarc Zyngier .mask = 0xffffffff, 16407f2481b3SMarc Zyngier .init = gic_enable_quirk_hip06_07, 16417f2481b3SMarc Zyngier }, 16427f2481b3SMarc Zyngier { 16437f2481b3SMarc Zyngier .desc = "GICv3: HIP07 erratum 161010803", 16447f2481b3SMarc Zyngier .iidr = 0x00000000, 16457f2481b3SMarc Zyngier .mask = 0xffffffff, 16467f2481b3SMarc Zyngier .init = gic_enable_quirk_hip06_07, 16477f2481b3SMarc Zyngier }, 16487f2481b3SMarc Zyngier { 1649d01fd161SMarc Zyngier /* 1650d01fd161SMarc Zyngier * Reserved register accesses generate a Synchronous 1651d01fd161SMarc Zyngier * External Abort. This erratum applies to: 1652d01fd161SMarc Zyngier * - ThunderX: CN88xx 1653d01fd161SMarc Zyngier * - OCTEON TX: CN83xx, CN81xx 1654d01fd161SMarc Zyngier * - OCTEON TX2: CN93xx, CN96xx, CN98xx, CNF95xx* 1655d01fd161SMarc Zyngier */ 1656d01fd161SMarc Zyngier .desc = "GICv3: Cavium erratum 38539", 1657d01fd161SMarc Zyngier .iidr = 0xa000034c, 1658d01fd161SMarc Zyngier .mask = 0xe8f00fff, 1659d01fd161SMarc Zyngier .init = gic_enable_quirk_cavium_38539, 1660d01fd161SMarc Zyngier }, 1661d01fd161SMarc Zyngier { 16627f2481b3SMarc Zyngier } 16637f2481b3SMarc Zyngier }; 16647f2481b3SMarc Zyngier 1665d98d0a99SJulien Thierry static void gic_enable_nmi_support(void) 1666d98d0a99SJulien Thierry { 1667101b35f7SJulien Thierry int i; 1668101b35f7SJulien Thierry 166981a43273SMarc Zyngier if (!gic_prio_masking_enabled()) 167081a43273SMarc Zyngier return; 167181a43273SMarc Zyngier 167281a43273SMarc Zyngier ppi_nmi_refs = kcalloc(gic_data.ppi_nr, sizeof(*ppi_nmi_refs), GFP_KERNEL); 167381a43273SMarc Zyngier if (!ppi_nmi_refs) 167481a43273SMarc Zyngier return; 167581a43273SMarc Zyngier 167681a43273SMarc Zyngier for (i = 0; i < gic_data.ppi_nr; i++) 1677101b35f7SJulien Thierry refcount_set(&ppi_nmi_refs[i], 0); 1678101b35f7SJulien Thierry 1679f2266504SMarc Zyngier /* 1680f2266504SMarc Zyngier * Linux itself doesn't use 1:N distribution, so has no need to 1681f2266504SMarc Zyngier * set PMHE. The only reason to have it set is if EL3 requires it 1682f2266504SMarc Zyngier * (and we can't change it). 1683f2266504SMarc Zyngier */ 1684f2266504SMarc Zyngier if (gic_read_ctlr() & ICC_CTLR_EL1_PMHE_MASK) 1685f2266504SMarc Zyngier static_branch_enable(&gic_pmr_sync); 1686f2266504SMarc Zyngier 16874e594ad1SAlexandru Elisei pr_info("Pseudo-NMIs enabled using %s ICC_PMR_EL1 synchronisation\n", 16884e594ad1SAlexandru Elisei static_branch_unlikely(&gic_pmr_sync) ? "forced" : "relaxed"); 1689f2266504SMarc Zyngier 169033678059SAlexandru Elisei /* 169133678059SAlexandru Elisei * How priority values are used by the GIC depends on two things: 169233678059SAlexandru Elisei * the security state of the GIC (controlled by the GICD_CTRL.DS bit) 169333678059SAlexandru Elisei * and if Group 0 interrupts can be delivered to Linux in the non-secure 169433678059SAlexandru Elisei * world as FIQs (controlled by the SCR_EL3.FIQ bit). These affect the 169533678059SAlexandru Elisei * the ICC_PMR_EL1 register and the priority that software assigns to 169633678059SAlexandru Elisei * interrupts: 169733678059SAlexandru Elisei * 169833678059SAlexandru Elisei * GICD_CTRL.DS | SCR_EL3.FIQ | ICC_PMR_EL1 | Group 1 priority 169933678059SAlexandru Elisei * ----------------------------------------------------------- 170033678059SAlexandru Elisei * 1 | - | unchanged | unchanged 170133678059SAlexandru Elisei * ----------------------------------------------------------- 170233678059SAlexandru Elisei * 0 | 1 | non-secure | non-secure 170333678059SAlexandru Elisei * ----------------------------------------------------------- 170433678059SAlexandru Elisei * 0 | 0 | unchanged | non-secure 170533678059SAlexandru Elisei * 170633678059SAlexandru Elisei * where non-secure means that the value is right-shifted by one and the 170733678059SAlexandru Elisei * MSB bit set, to make it fit in the non-secure priority range. 170833678059SAlexandru Elisei * 170933678059SAlexandru Elisei * In the first two cases, where ICC_PMR_EL1 and the interrupt priority 171033678059SAlexandru Elisei * are both either modified or unchanged, we can use the same set of 171133678059SAlexandru Elisei * priorities. 171233678059SAlexandru Elisei * 171333678059SAlexandru Elisei * In the last case, where only the interrupt priorities are modified to 171433678059SAlexandru Elisei * be in the non-secure range, we use a different PMR value to mask IRQs 171533678059SAlexandru Elisei * and the rest of the values that we use remain unchanged. 171633678059SAlexandru Elisei */ 171733678059SAlexandru Elisei if (gic_has_group0() && !gic_dist_security_disabled()) 171833678059SAlexandru Elisei static_branch_enable(&gic_nonsecure_priorities); 171933678059SAlexandru Elisei 1720d98d0a99SJulien Thierry static_branch_enable(&supports_pseudo_nmis); 1721101b35f7SJulien Thierry 1722101b35f7SJulien Thierry if (static_branch_likely(&supports_deactivate_key)) 1723101b35f7SJulien Thierry gic_eoimode1_chip.flags |= IRQCHIP_SUPPORTS_NMI; 1724101b35f7SJulien Thierry else 1725101b35f7SJulien Thierry gic_chip.flags |= IRQCHIP_SUPPORTS_NMI; 1726d98d0a99SJulien Thierry } 1727d98d0a99SJulien Thierry 1728db57d746STomasz Nowicki static int __init gic_init_bases(void __iomem *dist_base, 1729db57d746STomasz Nowicki struct redist_region *rdist_regs, 1730db57d746STomasz Nowicki u32 nr_redist_regions, 1731db57d746STomasz Nowicki u64 redist_stride, 1732db57d746STomasz Nowicki struct fwnode_handle *handle) 1733db57d746STomasz Nowicki { 1734db57d746STomasz Nowicki u32 typer; 1735db57d746STomasz Nowicki int err; 1736db57d746STomasz Nowicki 1737db57d746STomasz Nowicki if (!is_hyp_mode_available()) 1738d01d3274SDavidlohr Bueso static_branch_disable(&supports_deactivate_key); 1739db57d746STomasz Nowicki 1740d01d3274SDavidlohr Bueso if (static_branch_likely(&supports_deactivate_key)) 1741db57d746STomasz Nowicki pr_info("GIC: Using split EOI/Deactivate mode\n"); 1742db57d746STomasz Nowicki 1743e3825ba1SMarc Zyngier gic_data.fwnode = handle; 1744db57d746STomasz Nowicki gic_data.dist_base = dist_base; 1745db57d746STomasz Nowicki gic_data.redist_regions = rdist_regs; 1746db57d746STomasz Nowicki gic_data.nr_redist_regions = nr_redist_regions; 1747db57d746STomasz Nowicki gic_data.redist_stride = redist_stride; 1748db57d746STomasz Nowicki 1749db57d746STomasz Nowicki /* 1750db57d746STomasz Nowicki * Find out how many interrupts are supported. 1751db57d746STomasz Nowicki */ 1752db57d746STomasz Nowicki typer = readl_relaxed(gic_data.dist_base + GICD_TYPER); 1753a4f9edb2SMarc Zyngier gic_data.rdists.gicd_typer = typer; 17547f2481b3SMarc Zyngier 17557f2481b3SMarc Zyngier gic_enable_quirks(readl_relaxed(gic_data.dist_base + GICD_IIDR), 17567f2481b3SMarc Zyngier gic_quirks, &gic_data); 17577f2481b3SMarc Zyngier 1758211bddd2SMarc Zyngier pr_info("%d SPIs implemented\n", GIC_LINE_NR - 32); 1759211bddd2SMarc Zyngier pr_info("%d Extended SPIs implemented\n", GIC_ESPI_NR); 1760f2d83409SMarc Zyngier 1761d01fd161SMarc Zyngier /* 1762d01fd161SMarc Zyngier * ThunderX1 explodes on reading GICD_TYPER2, in violation of the 1763d01fd161SMarc Zyngier * architecture spec (which says that reserved registers are RES0). 1764d01fd161SMarc Zyngier */ 1765d01fd161SMarc Zyngier if (!(gic_data.flags & FLAGS_WORKAROUND_CAVIUM_ERRATUM_38539)) 1766f2d83409SMarc Zyngier gic_data.rdists.gicd_typer2 = readl_relaxed(gic_data.dist_base + GICD_TYPER2); 1767f2d83409SMarc Zyngier 1768db57d746STomasz Nowicki gic_data.domain = irq_domain_create_tree(handle, &gic_irq_domain_ops, 1769db57d746STomasz Nowicki &gic_data); 1770db57d746STomasz Nowicki gic_data.rdists.rdist = alloc_percpu(typeof(*gic_data.rdists.rdist)); 1771b25319d2SMarc Zyngier gic_data.rdists.has_rvpeid = true; 17720edc23eaSMarc Zyngier gic_data.rdists.has_vlpis = true; 17730edc23eaSMarc Zyngier gic_data.rdists.has_direct_lpi = true; 177496806229SMarc Zyngier gic_data.rdists.has_vpend_valid_dirty = true; 1775db57d746STomasz Nowicki 1776db57d746STomasz Nowicki if (WARN_ON(!gic_data.domain) || WARN_ON(!gic_data.rdists.rdist)) { 1777db57d746STomasz Nowicki err = -ENOMEM; 1778db57d746STomasz Nowicki goto out_free; 1779db57d746STomasz Nowicki } 1780db57d746STomasz Nowicki 1781eeaa4b24Sluanshi irq_domain_update_bus_token(gic_data.domain, DOMAIN_BUS_WIRED); 1782eeaa4b24Sluanshi 1783eda0d04aSShanker Donthineni gic_data.has_rss = !!(typer & GICD_TYPER_RSS); 1784eda0d04aSShanker Donthineni pr_info("Distributor has %sRange Selector support\n", 1785eda0d04aSShanker Donthineni gic_data.has_rss ? "" : "no "); 1786eda0d04aSShanker Donthineni 178750528752SMarc Zyngier if (typer & GICD_TYPER_MBIS) { 178850528752SMarc Zyngier err = mbi_init(handle, gic_data.domain); 178950528752SMarc Zyngier if (err) 179050528752SMarc Zyngier pr_err("Failed to initialize MBIs\n"); 179150528752SMarc Zyngier } 179250528752SMarc Zyngier 1793db57d746STomasz Nowicki set_handle_irq(gic_handle_irq); 1794db57d746STomasz Nowicki 17951a60e1e6SMarc Zyngier gic_update_rdist_properties(); 17960edc23eaSMarc Zyngier 1797db57d746STomasz Nowicki gic_dist_init(); 1798db57d746STomasz Nowicki gic_cpu_init(); 179964b499d8SMarc Zyngier gic_smp_init(); 1800db57d746STomasz Nowicki gic_cpu_pm_init(); 1801db57d746STomasz Nowicki 1802d38a71c5SMarc Zyngier if (gic_dist_supports_lpis()) { 1803d38a71c5SMarc Zyngier its_init(handle, &gic_data.rdists, gic_data.domain); 1804d38a71c5SMarc Zyngier its_cpu_init(); 180590b4c555SZeev Zilberman } else { 180690b4c555SZeev Zilberman if (IS_ENABLED(CONFIG_ARM_GIC_V2M)) 180790b4c555SZeev Zilberman gicv2m_init(handle, gic_data.domain); 1808d38a71c5SMarc Zyngier } 1809d38a71c5SMarc Zyngier 1810d98d0a99SJulien Thierry gic_enable_nmi_support(); 1811d98d0a99SJulien Thierry 1812db57d746STomasz Nowicki return 0; 1813db57d746STomasz Nowicki 1814db57d746STomasz Nowicki out_free: 1815db57d746STomasz Nowicki if (gic_data.domain) 1816db57d746STomasz Nowicki irq_domain_remove(gic_data.domain); 1817db57d746STomasz Nowicki free_percpu(gic_data.rdists.rdist); 1818db57d746STomasz Nowicki return err; 1819db57d746STomasz Nowicki } 1820db57d746STomasz Nowicki 1821db57d746STomasz Nowicki static int __init gic_validate_dist_version(void __iomem *dist_base) 1822db57d746STomasz Nowicki { 1823db57d746STomasz Nowicki u32 reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK; 1824db57d746STomasz Nowicki 1825db57d746STomasz Nowicki if (reg != GIC_PIDR2_ARCH_GICv3 && reg != GIC_PIDR2_ARCH_GICv4) 1826db57d746STomasz Nowicki return -ENODEV; 1827db57d746STomasz Nowicki 1828db57d746STomasz Nowicki return 0; 1829db57d746STomasz Nowicki } 1830db57d746STomasz Nowicki 1831e3825ba1SMarc Zyngier /* Create all possible partitions at boot time */ 18327beaa24bSLinus Torvalds static void __init gic_populate_ppi_partitions(struct device_node *gic_node) 1833e3825ba1SMarc Zyngier { 1834e3825ba1SMarc Zyngier struct device_node *parts_node, *child_part; 1835e3825ba1SMarc Zyngier int part_idx = 0, i; 1836e3825ba1SMarc Zyngier int nr_parts; 1837e3825ba1SMarc Zyngier struct partition_affinity *parts; 1838e3825ba1SMarc Zyngier 183900ee9a1cSJohan Hovold parts_node = of_get_child_by_name(gic_node, "ppi-partitions"); 1840e3825ba1SMarc Zyngier if (!parts_node) 1841e3825ba1SMarc Zyngier return; 1842e3825ba1SMarc Zyngier 184352085d3fSMarc Zyngier gic_data.ppi_descs = kcalloc(gic_data.ppi_nr, sizeof(*gic_data.ppi_descs), GFP_KERNEL); 184452085d3fSMarc Zyngier if (!gic_data.ppi_descs) 184552085d3fSMarc Zyngier return; 184652085d3fSMarc Zyngier 1847e3825ba1SMarc Zyngier nr_parts = of_get_child_count(parts_node); 1848e3825ba1SMarc Zyngier 1849e3825ba1SMarc Zyngier if (!nr_parts) 185000ee9a1cSJohan Hovold goto out_put_node; 1851e3825ba1SMarc Zyngier 18526396bb22SKees Cook parts = kcalloc(nr_parts, sizeof(*parts), GFP_KERNEL); 1853e3825ba1SMarc Zyngier if (WARN_ON(!parts)) 185400ee9a1cSJohan Hovold goto out_put_node; 1855e3825ba1SMarc Zyngier 1856e3825ba1SMarc Zyngier for_each_child_of_node(parts_node, child_part) { 1857e3825ba1SMarc Zyngier struct partition_affinity *part; 1858e3825ba1SMarc Zyngier int n; 1859e3825ba1SMarc Zyngier 1860e3825ba1SMarc Zyngier part = &parts[part_idx]; 1861e3825ba1SMarc Zyngier 1862e3825ba1SMarc Zyngier part->partition_id = of_node_to_fwnode(child_part); 1863e3825ba1SMarc Zyngier 18642ef790dcSRob Herring pr_info("GIC: PPI partition %pOFn[%d] { ", 18652ef790dcSRob Herring child_part, part_idx); 1866e3825ba1SMarc Zyngier 1867e3825ba1SMarc Zyngier n = of_property_count_elems_of_size(child_part, "affinity", 1868e3825ba1SMarc Zyngier sizeof(u32)); 1869e3825ba1SMarc Zyngier WARN_ON(n <= 0); 1870e3825ba1SMarc Zyngier 1871e3825ba1SMarc Zyngier for (i = 0; i < n; i++) { 1872e3825ba1SMarc Zyngier int err, cpu; 1873e3825ba1SMarc Zyngier u32 cpu_phandle; 1874e3825ba1SMarc Zyngier struct device_node *cpu_node; 1875e3825ba1SMarc Zyngier 1876e3825ba1SMarc Zyngier err = of_property_read_u32_index(child_part, "affinity", 1877e3825ba1SMarc Zyngier i, &cpu_phandle); 1878e3825ba1SMarc Zyngier if (WARN_ON(err)) 1879e3825ba1SMarc Zyngier continue; 1880e3825ba1SMarc Zyngier 1881e3825ba1SMarc Zyngier cpu_node = of_find_node_by_phandle(cpu_phandle); 1882e3825ba1SMarc Zyngier if (WARN_ON(!cpu_node)) 1883e3825ba1SMarc Zyngier continue; 1884e3825ba1SMarc Zyngier 1885c08ec7daSSuzuki K Poulose cpu = of_cpu_node_to_id(cpu_node); 1886c08ec7daSSuzuki K Poulose if (WARN_ON(cpu < 0)) 1887e3825ba1SMarc Zyngier continue; 1888e3825ba1SMarc Zyngier 1889e81f54c6SRob Herring pr_cont("%pOF[%d] ", cpu_node, cpu); 1890e3825ba1SMarc Zyngier 1891e3825ba1SMarc Zyngier cpumask_set_cpu(cpu, &part->mask); 1892e3825ba1SMarc Zyngier } 1893e3825ba1SMarc Zyngier 1894e3825ba1SMarc Zyngier pr_cont("}\n"); 1895e3825ba1SMarc Zyngier part_idx++; 1896e3825ba1SMarc Zyngier } 1897e3825ba1SMarc Zyngier 189852085d3fSMarc Zyngier for (i = 0; i < gic_data.ppi_nr; i++) { 1899e3825ba1SMarc Zyngier unsigned int irq; 1900e3825ba1SMarc Zyngier struct partition_desc *desc; 1901e3825ba1SMarc Zyngier struct irq_fwspec ppi_fwspec = { 1902e3825ba1SMarc Zyngier .fwnode = gic_data.fwnode, 1903e3825ba1SMarc Zyngier .param_count = 3, 1904e3825ba1SMarc Zyngier .param = { 190565da7d19SMarc Zyngier [0] = GIC_IRQ_TYPE_PARTITION, 1906e3825ba1SMarc Zyngier [1] = i, 1907e3825ba1SMarc Zyngier [2] = IRQ_TYPE_NONE, 1908e3825ba1SMarc Zyngier }, 1909e3825ba1SMarc Zyngier }; 1910e3825ba1SMarc Zyngier 1911e3825ba1SMarc Zyngier irq = irq_create_fwspec_mapping(&ppi_fwspec); 1912e3825ba1SMarc Zyngier if (WARN_ON(!irq)) 1913e3825ba1SMarc Zyngier continue; 1914e3825ba1SMarc Zyngier desc = partition_create_desc(gic_data.fwnode, parts, nr_parts, 1915e3825ba1SMarc Zyngier irq, &partition_domain_ops); 1916e3825ba1SMarc Zyngier if (WARN_ON(!desc)) 1917e3825ba1SMarc Zyngier continue; 1918e3825ba1SMarc Zyngier 1919e3825ba1SMarc Zyngier gic_data.ppi_descs[i] = desc; 1920e3825ba1SMarc Zyngier } 192100ee9a1cSJohan Hovold 192200ee9a1cSJohan Hovold out_put_node: 192300ee9a1cSJohan Hovold of_node_put(parts_node); 1924e3825ba1SMarc Zyngier } 1925e3825ba1SMarc Zyngier 19261839e576SJulien Grall static void __init gic_of_setup_kvm_info(struct device_node *node) 19271839e576SJulien Grall { 19281839e576SJulien Grall int ret; 19291839e576SJulien Grall struct resource r; 19301839e576SJulien Grall u32 gicv_idx; 19311839e576SJulien Grall 19321839e576SJulien Grall gic_v3_kvm_info.type = GIC_V3; 19331839e576SJulien Grall 19341839e576SJulien Grall gic_v3_kvm_info.maint_irq = irq_of_parse_and_map(node, 0); 19351839e576SJulien Grall if (!gic_v3_kvm_info.maint_irq) 19361839e576SJulien Grall return; 19371839e576SJulien Grall 19381839e576SJulien Grall if (of_property_read_u32(node, "#redistributor-regions", 19391839e576SJulien Grall &gicv_idx)) 19401839e576SJulien Grall gicv_idx = 1; 19411839e576SJulien Grall 19421839e576SJulien Grall gicv_idx += 3; /* Also skip GICD, GICC, GICH */ 19431839e576SJulien Grall ret = of_address_to_resource(node, gicv_idx, &r); 19441839e576SJulien Grall if (!ret) 19451839e576SJulien Grall gic_v3_kvm_info.vcpu = r; 19461839e576SJulien Grall 19474bdf5025SMarc Zyngier gic_v3_kvm_info.has_v4 = gic_data.rdists.has_vlpis; 19483c40706dSMarc Zyngier gic_v3_kvm_info.has_v4_1 = gic_data.rdists.has_rvpeid; 19490e5cb777SMarc Zyngier vgic_set_kvm_info(&gic_v3_kvm_info); 19501839e576SJulien Grall } 19511839e576SJulien Grall 1952021f6537SMarc Zyngier static int __init gic_of_init(struct device_node *node, struct device_node *parent) 1953021f6537SMarc Zyngier { 1954021f6537SMarc Zyngier void __iomem *dist_base; 1955f5c1434cSMarc Zyngier struct redist_region *rdist_regs; 1956021f6537SMarc Zyngier u64 redist_stride; 1957f5c1434cSMarc Zyngier u32 nr_redist_regions; 1958db57d746STomasz Nowicki int err, i; 1959021f6537SMarc Zyngier 1960021f6537SMarc Zyngier dist_base = of_iomap(node, 0); 1961021f6537SMarc Zyngier if (!dist_base) { 1962e81f54c6SRob Herring pr_err("%pOF: unable to map gic dist registers\n", node); 1963021f6537SMarc Zyngier return -ENXIO; 1964021f6537SMarc Zyngier } 1965021f6537SMarc Zyngier 1966db57d746STomasz Nowicki err = gic_validate_dist_version(dist_base); 1967db57d746STomasz Nowicki if (err) { 1968e81f54c6SRob Herring pr_err("%pOF: no distributor detected, giving up\n", node); 1969021f6537SMarc Zyngier goto out_unmap_dist; 1970021f6537SMarc Zyngier } 1971021f6537SMarc Zyngier 1972f5c1434cSMarc Zyngier if (of_property_read_u32(node, "#redistributor-regions", &nr_redist_regions)) 1973f5c1434cSMarc Zyngier nr_redist_regions = 1; 1974021f6537SMarc Zyngier 19756396bb22SKees Cook rdist_regs = kcalloc(nr_redist_regions, sizeof(*rdist_regs), 19766396bb22SKees Cook GFP_KERNEL); 1977f5c1434cSMarc Zyngier if (!rdist_regs) { 1978021f6537SMarc Zyngier err = -ENOMEM; 1979021f6537SMarc Zyngier goto out_unmap_dist; 1980021f6537SMarc Zyngier } 1981021f6537SMarc Zyngier 1982f5c1434cSMarc Zyngier for (i = 0; i < nr_redist_regions; i++) { 1983f5c1434cSMarc Zyngier struct resource res; 1984f5c1434cSMarc Zyngier int ret; 1985f5c1434cSMarc Zyngier 1986f5c1434cSMarc Zyngier ret = of_address_to_resource(node, 1 + i, &res); 1987f5c1434cSMarc Zyngier rdist_regs[i].redist_base = of_iomap(node, 1 + i); 1988f5c1434cSMarc Zyngier if (ret || !rdist_regs[i].redist_base) { 1989e81f54c6SRob Herring pr_err("%pOF: couldn't map region %d\n", node, i); 1990021f6537SMarc Zyngier err = -ENODEV; 1991021f6537SMarc Zyngier goto out_unmap_rdist; 1992021f6537SMarc Zyngier } 1993f5c1434cSMarc Zyngier rdist_regs[i].phys_base = res.start; 1994021f6537SMarc Zyngier } 1995021f6537SMarc Zyngier 1996021f6537SMarc Zyngier if (of_property_read_u64(node, "redistributor-stride", &redist_stride)) 1997021f6537SMarc Zyngier redist_stride = 0; 1998021f6537SMarc Zyngier 1999f70fdb42SSrinivas Kandagatla gic_enable_of_quirks(node, gic_quirks, &gic_data); 2000f70fdb42SSrinivas Kandagatla 2001db57d746STomasz Nowicki err = gic_init_bases(dist_base, rdist_regs, nr_redist_regions, 2002db57d746STomasz Nowicki redist_stride, &node->fwnode); 2003e3825ba1SMarc Zyngier if (err) 2004e3825ba1SMarc Zyngier goto out_unmap_rdist; 2005e3825ba1SMarc Zyngier 2006e3825ba1SMarc Zyngier gic_populate_ppi_partitions(node); 2007d33a3c8cSChristoffer Dall 2008d01d3274SDavidlohr Bueso if (static_branch_likely(&supports_deactivate_key)) 20091839e576SJulien Grall gic_of_setup_kvm_info(node); 2010021f6537SMarc Zyngier return 0; 2011021f6537SMarc Zyngier 2012021f6537SMarc Zyngier out_unmap_rdist: 2013f5c1434cSMarc Zyngier for (i = 0; i < nr_redist_regions; i++) 2014f5c1434cSMarc Zyngier if (rdist_regs[i].redist_base) 2015f5c1434cSMarc Zyngier iounmap(rdist_regs[i].redist_base); 2016f5c1434cSMarc Zyngier kfree(rdist_regs); 2017021f6537SMarc Zyngier out_unmap_dist: 2018021f6537SMarc Zyngier iounmap(dist_base); 2019021f6537SMarc Zyngier return err; 2020021f6537SMarc Zyngier } 2021021f6537SMarc Zyngier 2022021f6537SMarc Zyngier IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init); 2023ffa7d616STomasz Nowicki 2024ffa7d616STomasz Nowicki #ifdef CONFIG_ACPI 2025611f039fSJulien Grall static struct 2026611f039fSJulien Grall { 2027611f039fSJulien Grall void __iomem *dist_base; 2028611f039fSJulien Grall struct redist_region *redist_regs; 2029611f039fSJulien Grall u32 nr_redist_regions; 2030611f039fSJulien Grall bool single_redist; 2031926b5dfaSMarc Zyngier int enabled_rdists; 20321839e576SJulien Grall u32 maint_irq; 20331839e576SJulien Grall int maint_irq_mode; 20341839e576SJulien Grall phys_addr_t vcpu_base; 2035611f039fSJulien Grall } acpi_data __initdata; 2036b70fb7afSTomasz Nowicki 2037b70fb7afSTomasz Nowicki static void __init 2038b70fb7afSTomasz Nowicki gic_acpi_register_redist(phys_addr_t phys_base, void __iomem *redist_base) 2039b70fb7afSTomasz Nowicki { 2040b70fb7afSTomasz Nowicki static int count = 0; 2041b70fb7afSTomasz Nowicki 2042611f039fSJulien Grall acpi_data.redist_regs[count].phys_base = phys_base; 2043611f039fSJulien Grall acpi_data.redist_regs[count].redist_base = redist_base; 2044611f039fSJulien Grall acpi_data.redist_regs[count].single_redist = acpi_data.single_redist; 2045b70fb7afSTomasz Nowicki count++; 2046b70fb7afSTomasz Nowicki } 2047ffa7d616STomasz Nowicki 2048ffa7d616STomasz Nowicki static int __init 204960574d1eSKeith Busch gic_acpi_parse_madt_redist(union acpi_subtable_headers *header, 2050ffa7d616STomasz Nowicki const unsigned long end) 2051ffa7d616STomasz Nowicki { 2052ffa7d616STomasz Nowicki struct acpi_madt_generic_redistributor *redist = 2053ffa7d616STomasz Nowicki (struct acpi_madt_generic_redistributor *)header; 2054ffa7d616STomasz Nowicki void __iomem *redist_base; 2055ffa7d616STomasz Nowicki 2056ffa7d616STomasz Nowicki redist_base = ioremap(redist->base_address, redist->length); 2057ffa7d616STomasz Nowicki if (!redist_base) { 2058ffa7d616STomasz Nowicki pr_err("Couldn't map GICR region @%llx\n", redist->base_address); 2059ffa7d616STomasz Nowicki return -ENOMEM; 2060ffa7d616STomasz Nowicki } 2061ffa7d616STomasz Nowicki 2062b70fb7afSTomasz Nowicki gic_acpi_register_redist(redist->base_address, redist_base); 2063ffa7d616STomasz Nowicki return 0; 2064ffa7d616STomasz Nowicki } 2065ffa7d616STomasz Nowicki 2066b70fb7afSTomasz Nowicki static int __init 206760574d1eSKeith Busch gic_acpi_parse_madt_gicc(union acpi_subtable_headers *header, 2068b70fb7afSTomasz Nowicki const unsigned long end) 2069b70fb7afSTomasz Nowicki { 2070b70fb7afSTomasz Nowicki struct acpi_madt_generic_interrupt *gicc = 2071b70fb7afSTomasz Nowicki (struct acpi_madt_generic_interrupt *)header; 2072611f039fSJulien Grall u32 reg = readl_relaxed(acpi_data.dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK; 2073b70fb7afSTomasz Nowicki u32 size = reg == GIC_PIDR2_ARCH_GICv4 ? SZ_64K * 4 : SZ_64K * 2; 2074b70fb7afSTomasz Nowicki void __iomem *redist_base; 2075b70fb7afSTomasz Nowicki 2076ebe2f871SShanker Donthineni /* GICC entry which has !ACPI_MADT_ENABLED is not unusable so skip */ 2077ebe2f871SShanker Donthineni if (!(gicc->flags & ACPI_MADT_ENABLED)) 2078ebe2f871SShanker Donthineni return 0; 2079ebe2f871SShanker Donthineni 2080b70fb7afSTomasz Nowicki redist_base = ioremap(gicc->gicr_base_address, size); 2081b70fb7afSTomasz Nowicki if (!redist_base) 2082b70fb7afSTomasz Nowicki return -ENOMEM; 2083b70fb7afSTomasz Nowicki 2084b70fb7afSTomasz Nowicki gic_acpi_register_redist(gicc->gicr_base_address, redist_base); 2085b70fb7afSTomasz Nowicki return 0; 2086b70fb7afSTomasz Nowicki } 2087b70fb7afSTomasz Nowicki 2088b70fb7afSTomasz Nowicki static int __init gic_acpi_collect_gicr_base(void) 2089b70fb7afSTomasz Nowicki { 2090b70fb7afSTomasz Nowicki acpi_tbl_entry_handler redist_parser; 2091b70fb7afSTomasz Nowicki enum acpi_madt_type type; 2092b70fb7afSTomasz Nowicki 2093611f039fSJulien Grall if (acpi_data.single_redist) { 2094b70fb7afSTomasz Nowicki type = ACPI_MADT_TYPE_GENERIC_INTERRUPT; 2095b70fb7afSTomasz Nowicki redist_parser = gic_acpi_parse_madt_gicc; 2096b70fb7afSTomasz Nowicki } else { 2097b70fb7afSTomasz Nowicki type = ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR; 2098b70fb7afSTomasz Nowicki redist_parser = gic_acpi_parse_madt_redist; 2099b70fb7afSTomasz Nowicki } 2100b70fb7afSTomasz Nowicki 2101b70fb7afSTomasz Nowicki /* Collect redistributor base addresses in GICR entries */ 2102b70fb7afSTomasz Nowicki if (acpi_table_parse_madt(type, redist_parser, 0) > 0) 2103b70fb7afSTomasz Nowicki return 0; 2104b70fb7afSTomasz Nowicki 2105b70fb7afSTomasz Nowicki pr_info("No valid GICR entries exist\n"); 2106b70fb7afSTomasz Nowicki return -ENODEV; 2107b70fb7afSTomasz Nowicki } 2108b70fb7afSTomasz Nowicki 210960574d1eSKeith Busch static int __init gic_acpi_match_gicr(union acpi_subtable_headers *header, 2110ffa7d616STomasz Nowicki const unsigned long end) 2111ffa7d616STomasz Nowicki { 2112ffa7d616STomasz Nowicki /* Subtable presence means that redist exists, that's it */ 2113ffa7d616STomasz Nowicki return 0; 2114ffa7d616STomasz Nowicki } 2115ffa7d616STomasz Nowicki 211660574d1eSKeith Busch static int __init gic_acpi_match_gicc(union acpi_subtable_headers *header, 2117b70fb7afSTomasz Nowicki const unsigned long end) 2118b70fb7afSTomasz Nowicki { 2119b70fb7afSTomasz Nowicki struct acpi_madt_generic_interrupt *gicc = 2120b70fb7afSTomasz Nowicki (struct acpi_madt_generic_interrupt *)header; 2121b70fb7afSTomasz Nowicki 2122b70fb7afSTomasz Nowicki /* 2123b70fb7afSTomasz Nowicki * If GICC is enabled and has valid gicr base address, then it means 2124b70fb7afSTomasz Nowicki * GICR base is presented via GICC 2125b70fb7afSTomasz Nowicki */ 2126926b5dfaSMarc Zyngier if ((gicc->flags & ACPI_MADT_ENABLED) && gicc->gicr_base_address) { 2127926b5dfaSMarc Zyngier acpi_data.enabled_rdists++; 2128b70fb7afSTomasz Nowicki return 0; 2129926b5dfaSMarc Zyngier } 2130b70fb7afSTomasz Nowicki 2131ebe2f871SShanker Donthineni /* 2132ebe2f871SShanker Donthineni * It's perfectly valid firmware can pass disabled GICC entry, driver 2133ebe2f871SShanker Donthineni * should not treat as errors, skip the entry instead of probe fail. 2134ebe2f871SShanker Donthineni */ 2135ebe2f871SShanker Donthineni if (!(gicc->flags & ACPI_MADT_ENABLED)) 2136ebe2f871SShanker Donthineni return 0; 2137ebe2f871SShanker Donthineni 2138b70fb7afSTomasz Nowicki return -ENODEV; 2139b70fb7afSTomasz Nowicki } 2140b70fb7afSTomasz Nowicki 2141b70fb7afSTomasz Nowicki static int __init gic_acpi_count_gicr_regions(void) 2142b70fb7afSTomasz Nowicki { 2143b70fb7afSTomasz Nowicki int count; 2144b70fb7afSTomasz Nowicki 2145b70fb7afSTomasz Nowicki /* 2146b70fb7afSTomasz Nowicki * Count how many redistributor regions we have. It is not allowed 2147b70fb7afSTomasz Nowicki * to mix redistributor description, GICR and GICC subtables have to be 2148b70fb7afSTomasz Nowicki * mutually exclusive. 2149b70fb7afSTomasz Nowicki */ 2150b70fb7afSTomasz Nowicki count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR, 2151b70fb7afSTomasz Nowicki gic_acpi_match_gicr, 0); 2152b70fb7afSTomasz Nowicki if (count > 0) { 2153611f039fSJulien Grall acpi_data.single_redist = false; 2154b70fb7afSTomasz Nowicki return count; 2155b70fb7afSTomasz Nowicki } 2156b70fb7afSTomasz Nowicki 2157b70fb7afSTomasz Nowicki count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT, 2158b70fb7afSTomasz Nowicki gic_acpi_match_gicc, 0); 2159926b5dfaSMarc Zyngier if (count > 0) { 2160611f039fSJulien Grall acpi_data.single_redist = true; 2161926b5dfaSMarc Zyngier count = acpi_data.enabled_rdists; 2162926b5dfaSMarc Zyngier } 2163b70fb7afSTomasz Nowicki 2164b70fb7afSTomasz Nowicki return count; 2165b70fb7afSTomasz Nowicki } 2166b70fb7afSTomasz Nowicki 2167ffa7d616STomasz Nowicki static bool __init acpi_validate_gic_table(struct acpi_subtable_header *header, 2168ffa7d616STomasz Nowicki struct acpi_probe_entry *ape) 2169ffa7d616STomasz Nowicki { 2170ffa7d616STomasz Nowicki struct acpi_madt_generic_distributor *dist; 2171ffa7d616STomasz Nowicki int count; 2172ffa7d616STomasz Nowicki 2173ffa7d616STomasz Nowicki dist = (struct acpi_madt_generic_distributor *)header; 2174ffa7d616STomasz Nowicki if (dist->version != ape->driver_data) 2175ffa7d616STomasz Nowicki return false; 2176ffa7d616STomasz Nowicki 2177ffa7d616STomasz Nowicki /* We need to do that exercise anyway, the sooner the better */ 2178b70fb7afSTomasz Nowicki count = gic_acpi_count_gicr_regions(); 2179ffa7d616STomasz Nowicki if (count <= 0) 2180ffa7d616STomasz Nowicki return false; 2181ffa7d616STomasz Nowicki 2182611f039fSJulien Grall acpi_data.nr_redist_regions = count; 2183ffa7d616STomasz Nowicki return true; 2184ffa7d616STomasz Nowicki } 2185ffa7d616STomasz Nowicki 218660574d1eSKeith Busch static int __init gic_acpi_parse_virt_madt_gicc(union acpi_subtable_headers *header, 21871839e576SJulien Grall const unsigned long end) 21881839e576SJulien Grall { 21891839e576SJulien Grall struct acpi_madt_generic_interrupt *gicc = 21901839e576SJulien Grall (struct acpi_madt_generic_interrupt *)header; 21911839e576SJulien Grall int maint_irq_mode; 21921839e576SJulien Grall static int first_madt = true; 21931839e576SJulien Grall 21941839e576SJulien Grall /* Skip unusable CPUs */ 21951839e576SJulien Grall if (!(gicc->flags & ACPI_MADT_ENABLED)) 21961839e576SJulien Grall return 0; 21971839e576SJulien Grall 21981839e576SJulien Grall maint_irq_mode = (gicc->flags & ACPI_MADT_VGIC_IRQ_MODE) ? 21991839e576SJulien Grall ACPI_EDGE_SENSITIVE : ACPI_LEVEL_SENSITIVE; 22001839e576SJulien Grall 22011839e576SJulien Grall if (first_madt) { 22021839e576SJulien Grall first_madt = false; 22031839e576SJulien Grall 22041839e576SJulien Grall acpi_data.maint_irq = gicc->vgic_interrupt; 22051839e576SJulien Grall acpi_data.maint_irq_mode = maint_irq_mode; 22061839e576SJulien Grall acpi_data.vcpu_base = gicc->gicv_base_address; 22071839e576SJulien Grall 22081839e576SJulien Grall return 0; 22091839e576SJulien Grall } 22101839e576SJulien Grall 22111839e576SJulien Grall /* 22121839e576SJulien Grall * The maintenance interrupt and GICV should be the same for every CPU 22131839e576SJulien Grall */ 22141839e576SJulien Grall if ((acpi_data.maint_irq != gicc->vgic_interrupt) || 22151839e576SJulien Grall (acpi_data.maint_irq_mode != maint_irq_mode) || 22161839e576SJulien Grall (acpi_data.vcpu_base != gicc->gicv_base_address)) 22171839e576SJulien Grall return -EINVAL; 22181839e576SJulien Grall 22191839e576SJulien Grall return 0; 22201839e576SJulien Grall } 22211839e576SJulien Grall 22221839e576SJulien Grall static bool __init gic_acpi_collect_virt_info(void) 22231839e576SJulien Grall { 22241839e576SJulien Grall int count; 22251839e576SJulien Grall 22261839e576SJulien Grall count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT, 22271839e576SJulien Grall gic_acpi_parse_virt_madt_gicc, 0); 22281839e576SJulien Grall 22291839e576SJulien Grall return (count > 0); 22301839e576SJulien Grall } 22311839e576SJulien Grall 2232ffa7d616STomasz Nowicki #define ACPI_GICV3_DIST_MEM_SIZE (SZ_64K) 22331839e576SJulien Grall #define ACPI_GICV2_VCTRL_MEM_SIZE (SZ_4K) 22341839e576SJulien Grall #define ACPI_GICV2_VCPU_MEM_SIZE (SZ_8K) 22351839e576SJulien Grall 22361839e576SJulien Grall static void __init gic_acpi_setup_kvm_info(void) 22371839e576SJulien Grall { 22381839e576SJulien Grall int irq; 22391839e576SJulien Grall 22401839e576SJulien Grall if (!gic_acpi_collect_virt_info()) { 22411839e576SJulien Grall pr_warn("Unable to get hardware information used for virtualization\n"); 22421839e576SJulien Grall return; 22431839e576SJulien Grall } 22441839e576SJulien Grall 22451839e576SJulien Grall gic_v3_kvm_info.type = GIC_V3; 22461839e576SJulien Grall 22471839e576SJulien Grall irq = acpi_register_gsi(NULL, acpi_data.maint_irq, 22481839e576SJulien Grall acpi_data.maint_irq_mode, 22491839e576SJulien Grall ACPI_ACTIVE_HIGH); 22501839e576SJulien Grall if (irq <= 0) 22511839e576SJulien Grall return; 22521839e576SJulien Grall 22531839e576SJulien Grall gic_v3_kvm_info.maint_irq = irq; 22541839e576SJulien Grall 22551839e576SJulien Grall if (acpi_data.vcpu_base) { 22561839e576SJulien Grall struct resource *vcpu = &gic_v3_kvm_info.vcpu; 22571839e576SJulien Grall 22581839e576SJulien Grall vcpu->flags = IORESOURCE_MEM; 22591839e576SJulien Grall vcpu->start = acpi_data.vcpu_base; 22601839e576SJulien Grall vcpu->end = vcpu->start + ACPI_GICV2_VCPU_MEM_SIZE - 1; 22611839e576SJulien Grall } 22621839e576SJulien Grall 22634bdf5025SMarc Zyngier gic_v3_kvm_info.has_v4 = gic_data.rdists.has_vlpis; 22643c40706dSMarc Zyngier gic_v3_kvm_info.has_v4_1 = gic_data.rdists.has_rvpeid; 22650e5cb777SMarc Zyngier vgic_set_kvm_info(&gic_v3_kvm_info); 22661839e576SJulien Grall } 2267ffa7d616STomasz Nowicki 2268ffa7d616STomasz Nowicki static int __init 2269aba3c7edSOscar Carter gic_acpi_init(union acpi_subtable_headers *header, const unsigned long end) 2270ffa7d616STomasz Nowicki { 2271ffa7d616STomasz Nowicki struct acpi_madt_generic_distributor *dist; 2272ffa7d616STomasz Nowicki struct fwnode_handle *domain_handle; 2273611f039fSJulien Grall size_t size; 2274b70fb7afSTomasz Nowicki int i, err; 2275ffa7d616STomasz Nowicki 2276ffa7d616STomasz Nowicki /* Get distributor base address */ 2277ffa7d616STomasz Nowicki dist = (struct acpi_madt_generic_distributor *)header; 2278611f039fSJulien Grall acpi_data.dist_base = ioremap(dist->base_address, 2279611f039fSJulien Grall ACPI_GICV3_DIST_MEM_SIZE); 2280611f039fSJulien Grall if (!acpi_data.dist_base) { 2281ffa7d616STomasz Nowicki pr_err("Unable to map GICD registers\n"); 2282ffa7d616STomasz Nowicki return -ENOMEM; 2283ffa7d616STomasz Nowicki } 2284ffa7d616STomasz Nowicki 2285611f039fSJulien Grall err = gic_validate_dist_version(acpi_data.dist_base); 2286ffa7d616STomasz Nowicki if (err) { 228771192a68SArvind Yadav pr_err("No distributor detected at @%p, giving up\n", 2288611f039fSJulien Grall acpi_data.dist_base); 2289ffa7d616STomasz Nowicki goto out_dist_unmap; 2290ffa7d616STomasz Nowicki } 2291ffa7d616STomasz Nowicki 2292611f039fSJulien Grall size = sizeof(*acpi_data.redist_regs) * acpi_data.nr_redist_regions; 2293611f039fSJulien Grall acpi_data.redist_regs = kzalloc(size, GFP_KERNEL); 2294611f039fSJulien Grall if (!acpi_data.redist_regs) { 2295ffa7d616STomasz Nowicki err = -ENOMEM; 2296ffa7d616STomasz Nowicki goto out_dist_unmap; 2297ffa7d616STomasz Nowicki } 2298ffa7d616STomasz Nowicki 2299b70fb7afSTomasz Nowicki err = gic_acpi_collect_gicr_base(); 2300b70fb7afSTomasz Nowicki if (err) 2301ffa7d616STomasz Nowicki goto out_redist_unmap; 2302ffa7d616STomasz Nowicki 2303eeee0d09SMarc Zyngier domain_handle = irq_domain_alloc_fwnode(&dist->base_address); 2304ffa7d616STomasz Nowicki if (!domain_handle) { 2305ffa7d616STomasz Nowicki err = -ENOMEM; 2306ffa7d616STomasz Nowicki goto out_redist_unmap; 2307ffa7d616STomasz Nowicki } 2308ffa7d616STomasz Nowicki 2309611f039fSJulien Grall err = gic_init_bases(acpi_data.dist_base, acpi_data.redist_regs, 2310611f039fSJulien Grall acpi_data.nr_redist_regions, 0, domain_handle); 2311ffa7d616STomasz Nowicki if (err) 2312ffa7d616STomasz Nowicki goto out_fwhandle_free; 2313ffa7d616STomasz Nowicki 2314ffa7d616STomasz Nowicki acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, domain_handle); 2315d33a3c8cSChristoffer Dall 2316d01d3274SDavidlohr Bueso if (static_branch_likely(&supports_deactivate_key)) 23171839e576SJulien Grall gic_acpi_setup_kvm_info(); 23181839e576SJulien Grall 2319ffa7d616STomasz Nowicki return 0; 2320ffa7d616STomasz Nowicki 2321ffa7d616STomasz Nowicki out_fwhandle_free: 2322ffa7d616STomasz Nowicki irq_domain_free_fwnode(domain_handle); 2323ffa7d616STomasz Nowicki out_redist_unmap: 2324611f039fSJulien Grall for (i = 0; i < acpi_data.nr_redist_regions; i++) 2325611f039fSJulien Grall if (acpi_data.redist_regs[i].redist_base) 2326611f039fSJulien Grall iounmap(acpi_data.redist_regs[i].redist_base); 2327611f039fSJulien Grall kfree(acpi_data.redist_regs); 2328ffa7d616STomasz Nowicki out_dist_unmap: 2329611f039fSJulien Grall iounmap(acpi_data.dist_base); 2330ffa7d616STomasz Nowicki return err; 2331ffa7d616STomasz Nowicki } 2332ffa7d616STomasz Nowicki IRQCHIP_ACPI_DECLARE(gic_v3, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 2333ffa7d616STomasz Nowicki acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V3, 2334ffa7d616STomasz Nowicki gic_acpi_init); 2335ffa7d616STomasz Nowicki IRQCHIP_ACPI_DECLARE(gic_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 2336ffa7d616STomasz Nowicki acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V4, 2337ffa7d616STomasz Nowicki gic_acpi_init); 2338ffa7d616STomasz Nowicki IRQCHIP_ACPI_DECLARE(gic_v3_or_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 2339ffa7d616STomasz Nowicki acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_NONE, 2340ffa7d616STomasz Nowicki gic_acpi_init); 2341ffa7d616STomasz Nowicki #endif 2342