1021f6537SMarc Zyngier /* 2021f6537SMarc Zyngier * Copyright (C) 2013, 2014 ARM Limited, All Rights Reserved. 3021f6537SMarc Zyngier * Author: Marc Zyngier <marc.zyngier@arm.com> 4021f6537SMarc Zyngier * 5021f6537SMarc Zyngier * This program is free software; you can redistribute it and/or modify 6021f6537SMarc Zyngier * it under the terms of the GNU General Public License version 2 as 7021f6537SMarc Zyngier * published by the Free Software Foundation. 8021f6537SMarc Zyngier * 9021f6537SMarc Zyngier * This program is distributed in the hope that it will be useful, 10021f6537SMarc Zyngier * but WITHOUT ANY WARRANTY; without even the implied warranty of 11021f6537SMarc Zyngier * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12021f6537SMarc Zyngier * GNU General Public License for more details. 13021f6537SMarc Zyngier * 14021f6537SMarc Zyngier * You should have received a copy of the GNU General Public License 15021f6537SMarc Zyngier * along with this program. If not, see <http://www.gnu.org/licenses/>. 16021f6537SMarc Zyngier */ 17021f6537SMarc Zyngier 18021f6537SMarc Zyngier #include <linux/cpu.h> 19021f6537SMarc Zyngier #include <linux/delay.h> 20021f6537SMarc Zyngier #include <linux/interrupt.h> 21021f6537SMarc Zyngier #include <linux/of.h> 22021f6537SMarc Zyngier #include <linux/of_address.h> 23021f6537SMarc Zyngier #include <linux/of_irq.h> 24021f6537SMarc Zyngier #include <linux/percpu.h> 25021f6537SMarc Zyngier #include <linux/slab.h> 26021f6537SMarc Zyngier 27021f6537SMarc Zyngier #include <linux/irqchip/arm-gic-v3.h> 28021f6537SMarc Zyngier 29021f6537SMarc Zyngier #include <asm/cputype.h> 30021f6537SMarc Zyngier #include <asm/exception.h> 31021f6537SMarc Zyngier #include <asm/smp_plat.h> 32021f6537SMarc Zyngier 33021f6537SMarc Zyngier #include "irq-gic-common.h" 34021f6537SMarc Zyngier #include "irqchip.h" 35021f6537SMarc Zyngier 36021f6537SMarc Zyngier struct gic_chip_data { 37021f6537SMarc Zyngier void __iomem *dist_base; 38021f6537SMarc Zyngier void __iomem **redist_base; 39021f6537SMarc Zyngier void __percpu __iomem **rdist; 40021f6537SMarc Zyngier struct irq_domain *domain; 41021f6537SMarc Zyngier u64 redist_stride; 42021f6537SMarc Zyngier u32 redist_regions; 43021f6537SMarc Zyngier unsigned int irq_nr; 44021f6537SMarc Zyngier }; 45021f6537SMarc Zyngier 46021f6537SMarc Zyngier static struct gic_chip_data gic_data __read_mostly; 47021f6537SMarc Zyngier 48021f6537SMarc Zyngier #define gic_data_rdist() (this_cpu_ptr(gic_data.rdist)) 49021f6537SMarc Zyngier #define gic_data_rdist_rd_base() (*gic_data_rdist()) 50021f6537SMarc Zyngier #define gic_data_rdist_sgi_base() (gic_data_rdist_rd_base() + SZ_64K) 51021f6537SMarc Zyngier 52021f6537SMarc Zyngier /* Our default, arbitrary priority value. Linux only uses one anyway. */ 53021f6537SMarc Zyngier #define DEFAULT_PMR_VALUE 0xf0 54021f6537SMarc Zyngier 55021f6537SMarc Zyngier static inline unsigned int gic_irq(struct irq_data *d) 56021f6537SMarc Zyngier { 57021f6537SMarc Zyngier return d->hwirq; 58021f6537SMarc Zyngier } 59021f6537SMarc Zyngier 60021f6537SMarc Zyngier static inline int gic_irq_in_rdist(struct irq_data *d) 61021f6537SMarc Zyngier { 62021f6537SMarc Zyngier return gic_irq(d) < 32; 63021f6537SMarc Zyngier } 64021f6537SMarc Zyngier 65021f6537SMarc Zyngier static inline void __iomem *gic_dist_base(struct irq_data *d) 66021f6537SMarc Zyngier { 67021f6537SMarc Zyngier if (gic_irq_in_rdist(d)) /* SGI+PPI -> SGI_base for this CPU */ 68021f6537SMarc Zyngier return gic_data_rdist_sgi_base(); 69021f6537SMarc Zyngier 70021f6537SMarc Zyngier if (d->hwirq <= 1023) /* SPI -> dist_base */ 71021f6537SMarc Zyngier return gic_data.dist_base; 72021f6537SMarc Zyngier 73021f6537SMarc Zyngier if (d->hwirq >= 8192) 74021f6537SMarc Zyngier BUG(); /* LPI Detected!!! */ 75021f6537SMarc Zyngier 76021f6537SMarc Zyngier return NULL; 77021f6537SMarc Zyngier } 78021f6537SMarc Zyngier 79021f6537SMarc Zyngier static void gic_do_wait_for_rwp(void __iomem *base) 80021f6537SMarc Zyngier { 81021f6537SMarc Zyngier u32 count = 1000000; /* 1s! */ 82021f6537SMarc Zyngier 83021f6537SMarc Zyngier while (readl_relaxed(base + GICD_CTLR) & GICD_CTLR_RWP) { 84021f6537SMarc Zyngier count--; 85021f6537SMarc Zyngier if (!count) { 86021f6537SMarc Zyngier pr_err_ratelimited("RWP timeout, gone fishing\n"); 87021f6537SMarc Zyngier return; 88021f6537SMarc Zyngier } 89021f6537SMarc Zyngier cpu_relax(); 90021f6537SMarc Zyngier udelay(1); 91021f6537SMarc Zyngier }; 92021f6537SMarc Zyngier } 93021f6537SMarc Zyngier 94021f6537SMarc Zyngier /* Wait for completion of a distributor change */ 95021f6537SMarc Zyngier static void gic_dist_wait_for_rwp(void) 96021f6537SMarc Zyngier { 97021f6537SMarc Zyngier gic_do_wait_for_rwp(gic_data.dist_base); 98021f6537SMarc Zyngier } 99021f6537SMarc Zyngier 100021f6537SMarc Zyngier /* Wait for completion of a redistributor change */ 101021f6537SMarc Zyngier static void gic_redist_wait_for_rwp(void) 102021f6537SMarc Zyngier { 103021f6537SMarc Zyngier gic_do_wait_for_rwp(gic_data_rdist_rd_base()); 104021f6537SMarc Zyngier } 105021f6537SMarc Zyngier 106021f6537SMarc Zyngier /* Low level accessors */ 107021f6537SMarc Zyngier static u64 gic_read_iar(void) 108021f6537SMarc Zyngier { 109021f6537SMarc Zyngier u64 irqstat; 110021f6537SMarc Zyngier 111021f6537SMarc Zyngier asm volatile("mrs %0, " __stringify(ICC_IAR1_EL1) : "=r" (irqstat)); 112021f6537SMarc Zyngier return irqstat; 113021f6537SMarc Zyngier } 114021f6537SMarc Zyngier 115021f6537SMarc Zyngier static void gic_write_pmr(u64 val) 116021f6537SMarc Zyngier { 117021f6537SMarc Zyngier asm volatile("msr " __stringify(ICC_PMR_EL1) ", %0" : : "r" (val)); 118021f6537SMarc Zyngier } 119021f6537SMarc Zyngier 120021f6537SMarc Zyngier static void gic_write_ctlr(u64 val) 121021f6537SMarc Zyngier { 122021f6537SMarc Zyngier asm volatile("msr " __stringify(ICC_CTLR_EL1) ", %0" : : "r" (val)); 123021f6537SMarc Zyngier isb(); 124021f6537SMarc Zyngier } 125021f6537SMarc Zyngier 126021f6537SMarc Zyngier static void gic_write_grpen1(u64 val) 127021f6537SMarc Zyngier { 128021f6537SMarc Zyngier asm volatile("msr " __stringify(ICC_GRPEN1_EL1) ", %0" : : "r" (val)); 129021f6537SMarc Zyngier isb(); 130021f6537SMarc Zyngier } 131021f6537SMarc Zyngier 132021f6537SMarc Zyngier static void gic_write_sgi1r(u64 val) 133021f6537SMarc Zyngier { 134021f6537SMarc Zyngier asm volatile("msr " __stringify(ICC_SGI1R_EL1) ", %0" : : "r" (val)); 135021f6537SMarc Zyngier } 136021f6537SMarc Zyngier 137021f6537SMarc Zyngier static void gic_enable_sre(void) 138021f6537SMarc Zyngier { 139021f6537SMarc Zyngier u64 val; 140021f6537SMarc Zyngier 141021f6537SMarc Zyngier asm volatile("mrs %0, " __stringify(ICC_SRE_EL1) : "=r" (val)); 142021f6537SMarc Zyngier val |= ICC_SRE_EL1_SRE; 143021f6537SMarc Zyngier asm volatile("msr " __stringify(ICC_SRE_EL1) ", %0" : : "r" (val)); 144021f6537SMarc Zyngier isb(); 145021f6537SMarc Zyngier 146021f6537SMarc Zyngier /* 147021f6537SMarc Zyngier * Need to check that the SRE bit has actually been set. If 148021f6537SMarc Zyngier * not, it means that SRE is disabled at EL2. We're going to 149021f6537SMarc Zyngier * die painfully, and there is nothing we can do about it. 150021f6537SMarc Zyngier * 151021f6537SMarc Zyngier * Kindly inform the luser. 152021f6537SMarc Zyngier */ 153021f6537SMarc Zyngier asm volatile("mrs %0, " __stringify(ICC_SRE_EL1) : "=r" (val)); 154021f6537SMarc Zyngier if (!(val & ICC_SRE_EL1_SRE)) 155021f6537SMarc Zyngier pr_err("GIC: unable to set SRE (disabled at EL2), panic ahead\n"); 156021f6537SMarc Zyngier } 157021f6537SMarc Zyngier 158021f6537SMarc Zyngier static void gic_enable_redist(void) 159021f6537SMarc Zyngier { 160021f6537SMarc Zyngier void __iomem *rbase; 161021f6537SMarc Zyngier u32 count = 1000000; /* 1s! */ 162021f6537SMarc Zyngier u32 val; 163021f6537SMarc Zyngier 164021f6537SMarc Zyngier rbase = gic_data_rdist_rd_base(); 165021f6537SMarc Zyngier 166021f6537SMarc Zyngier /* Wake up this CPU redistributor */ 167021f6537SMarc Zyngier val = readl_relaxed(rbase + GICR_WAKER); 168021f6537SMarc Zyngier val &= ~GICR_WAKER_ProcessorSleep; 169021f6537SMarc Zyngier writel_relaxed(val, rbase + GICR_WAKER); 170021f6537SMarc Zyngier 171021f6537SMarc Zyngier while (readl_relaxed(rbase + GICR_WAKER) & GICR_WAKER_ChildrenAsleep) { 172021f6537SMarc Zyngier count--; 173021f6537SMarc Zyngier if (!count) { 174021f6537SMarc Zyngier pr_err_ratelimited("redist didn't wake up...\n"); 175021f6537SMarc Zyngier return; 176021f6537SMarc Zyngier } 177021f6537SMarc Zyngier cpu_relax(); 178021f6537SMarc Zyngier udelay(1); 179021f6537SMarc Zyngier }; 180021f6537SMarc Zyngier } 181021f6537SMarc Zyngier 182021f6537SMarc Zyngier /* 183021f6537SMarc Zyngier * Routines to disable, enable, EOI and route interrupts 184021f6537SMarc Zyngier */ 185021f6537SMarc Zyngier static void gic_poke_irq(struct irq_data *d, u32 offset) 186021f6537SMarc Zyngier { 187021f6537SMarc Zyngier u32 mask = 1 << (gic_irq(d) % 32); 188021f6537SMarc Zyngier void (*rwp_wait)(void); 189021f6537SMarc Zyngier void __iomem *base; 190021f6537SMarc Zyngier 191021f6537SMarc Zyngier if (gic_irq_in_rdist(d)) { 192021f6537SMarc Zyngier base = gic_data_rdist_sgi_base(); 193021f6537SMarc Zyngier rwp_wait = gic_redist_wait_for_rwp; 194021f6537SMarc Zyngier } else { 195021f6537SMarc Zyngier base = gic_data.dist_base; 196021f6537SMarc Zyngier rwp_wait = gic_dist_wait_for_rwp; 197021f6537SMarc Zyngier } 198021f6537SMarc Zyngier 199021f6537SMarc Zyngier writel_relaxed(mask, base + offset + (gic_irq(d) / 32) * 4); 200021f6537SMarc Zyngier rwp_wait(); 201021f6537SMarc Zyngier } 202021f6537SMarc Zyngier 203021f6537SMarc Zyngier static int gic_peek_irq(struct irq_data *d, u32 offset) 204021f6537SMarc Zyngier { 205021f6537SMarc Zyngier u32 mask = 1 << (gic_irq(d) % 32); 206021f6537SMarc Zyngier void __iomem *base; 207021f6537SMarc Zyngier 208021f6537SMarc Zyngier if (gic_irq_in_rdist(d)) 209021f6537SMarc Zyngier base = gic_data_rdist_sgi_base(); 210021f6537SMarc Zyngier else 211021f6537SMarc Zyngier base = gic_data.dist_base; 212021f6537SMarc Zyngier 213021f6537SMarc Zyngier return !!(readl_relaxed(base + offset + (gic_irq(d) / 32) * 4) & mask); 214021f6537SMarc Zyngier } 215021f6537SMarc Zyngier 216021f6537SMarc Zyngier static void gic_mask_irq(struct irq_data *d) 217021f6537SMarc Zyngier { 218021f6537SMarc Zyngier gic_poke_irq(d, GICD_ICENABLER); 219021f6537SMarc Zyngier } 220021f6537SMarc Zyngier 221021f6537SMarc Zyngier static void gic_unmask_irq(struct irq_data *d) 222021f6537SMarc Zyngier { 223021f6537SMarc Zyngier gic_poke_irq(d, GICD_ISENABLER); 224021f6537SMarc Zyngier } 225021f6537SMarc Zyngier 226021f6537SMarc Zyngier static void gic_eoi_irq(struct irq_data *d) 227021f6537SMarc Zyngier { 228021f6537SMarc Zyngier gic_write_eoir(gic_irq(d)); 229021f6537SMarc Zyngier } 230021f6537SMarc Zyngier 231021f6537SMarc Zyngier static int gic_set_type(struct irq_data *d, unsigned int type) 232021f6537SMarc Zyngier { 233021f6537SMarc Zyngier unsigned int irq = gic_irq(d); 234021f6537SMarc Zyngier void (*rwp_wait)(void); 235021f6537SMarc Zyngier void __iomem *base; 236021f6537SMarc Zyngier 237021f6537SMarc Zyngier /* Interrupt configuration for SGIs can't be changed */ 238021f6537SMarc Zyngier if (irq < 16) 239021f6537SMarc Zyngier return -EINVAL; 240021f6537SMarc Zyngier 241021f6537SMarc Zyngier if (type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING) 242021f6537SMarc Zyngier return -EINVAL; 243021f6537SMarc Zyngier 244021f6537SMarc Zyngier if (gic_irq_in_rdist(d)) { 245021f6537SMarc Zyngier base = gic_data_rdist_sgi_base(); 246021f6537SMarc Zyngier rwp_wait = gic_redist_wait_for_rwp; 247021f6537SMarc Zyngier } else { 248021f6537SMarc Zyngier base = gic_data.dist_base; 249021f6537SMarc Zyngier rwp_wait = gic_dist_wait_for_rwp; 250021f6537SMarc Zyngier } 251021f6537SMarc Zyngier 252021f6537SMarc Zyngier gic_configure_irq(irq, type, base, rwp_wait); 253021f6537SMarc Zyngier 254021f6537SMarc Zyngier return 0; 255021f6537SMarc Zyngier } 256021f6537SMarc Zyngier 257021f6537SMarc Zyngier static u64 gic_mpidr_to_affinity(u64 mpidr) 258021f6537SMarc Zyngier { 259021f6537SMarc Zyngier u64 aff; 260021f6537SMarc Zyngier 261021f6537SMarc Zyngier aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 32 | 262021f6537SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 | 263021f6537SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | 264021f6537SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 0)); 265021f6537SMarc Zyngier 266021f6537SMarc Zyngier return aff; 267021f6537SMarc Zyngier } 268021f6537SMarc Zyngier 269021f6537SMarc Zyngier static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) 270021f6537SMarc Zyngier { 271021f6537SMarc Zyngier u64 irqnr; 272021f6537SMarc Zyngier 273021f6537SMarc Zyngier do { 274021f6537SMarc Zyngier irqnr = gic_read_iar(); 275021f6537SMarc Zyngier 276021f6537SMarc Zyngier if (likely(irqnr > 15 && irqnr < 1020)) { 277021f6537SMarc Zyngier u64 irq = irq_find_mapping(gic_data.domain, irqnr); 278021f6537SMarc Zyngier if (likely(irq)) { 279021f6537SMarc Zyngier handle_IRQ(irq, regs); 280021f6537SMarc Zyngier continue; 281021f6537SMarc Zyngier } 282021f6537SMarc Zyngier 283021f6537SMarc Zyngier WARN_ONCE(true, "Unexpected SPI received!\n"); 284021f6537SMarc Zyngier gic_write_eoir(irqnr); 285021f6537SMarc Zyngier } 286021f6537SMarc Zyngier if (irqnr < 16) { 287021f6537SMarc Zyngier gic_write_eoir(irqnr); 288021f6537SMarc Zyngier #ifdef CONFIG_SMP 289021f6537SMarc Zyngier handle_IPI(irqnr, regs); 290021f6537SMarc Zyngier #else 291021f6537SMarc Zyngier WARN_ONCE(true, "Unexpected SGI received!\n"); 292021f6537SMarc Zyngier #endif 293021f6537SMarc Zyngier continue; 294021f6537SMarc Zyngier } 295021f6537SMarc Zyngier } while (irqnr != ICC_IAR1_EL1_SPURIOUS); 296021f6537SMarc Zyngier } 297021f6537SMarc Zyngier 298021f6537SMarc Zyngier static void __init gic_dist_init(void) 299021f6537SMarc Zyngier { 300021f6537SMarc Zyngier unsigned int i; 301021f6537SMarc Zyngier u64 affinity; 302021f6537SMarc Zyngier void __iomem *base = gic_data.dist_base; 303021f6537SMarc Zyngier 304021f6537SMarc Zyngier /* Disable the distributor */ 305021f6537SMarc Zyngier writel_relaxed(0, base + GICD_CTLR); 306021f6537SMarc Zyngier gic_dist_wait_for_rwp(); 307021f6537SMarc Zyngier 308021f6537SMarc Zyngier gic_dist_config(base, gic_data.irq_nr, gic_dist_wait_for_rwp); 309021f6537SMarc Zyngier 310021f6537SMarc Zyngier /* Enable distributor with ARE, Group1 */ 311021f6537SMarc Zyngier writel_relaxed(GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G1A | GICD_CTLR_ENABLE_G1, 312021f6537SMarc Zyngier base + GICD_CTLR); 313021f6537SMarc Zyngier 314021f6537SMarc Zyngier /* 315021f6537SMarc Zyngier * Set all global interrupts to the boot CPU only. ARE must be 316021f6537SMarc Zyngier * enabled. 317021f6537SMarc Zyngier */ 318021f6537SMarc Zyngier affinity = gic_mpidr_to_affinity(cpu_logical_map(smp_processor_id())); 319021f6537SMarc Zyngier for (i = 32; i < gic_data.irq_nr; i++) 320021f6537SMarc Zyngier writeq_relaxed(affinity, base + GICD_IROUTER + i * 8); 321021f6537SMarc Zyngier } 322021f6537SMarc Zyngier 323021f6537SMarc Zyngier static int gic_populate_rdist(void) 324021f6537SMarc Zyngier { 325021f6537SMarc Zyngier u64 mpidr = cpu_logical_map(smp_processor_id()); 326021f6537SMarc Zyngier u64 typer; 327021f6537SMarc Zyngier u32 aff; 328021f6537SMarc Zyngier int i; 329021f6537SMarc Zyngier 330021f6537SMarc Zyngier /* 331021f6537SMarc Zyngier * Convert affinity to a 32bit value that can be matched to 332021f6537SMarc Zyngier * GICR_TYPER bits [63:32]. 333021f6537SMarc Zyngier */ 334021f6537SMarc Zyngier aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 24 | 335021f6537SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 | 336021f6537SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | 337021f6537SMarc Zyngier MPIDR_AFFINITY_LEVEL(mpidr, 0)); 338021f6537SMarc Zyngier 339021f6537SMarc Zyngier for (i = 0; i < gic_data.redist_regions; i++) { 340021f6537SMarc Zyngier void __iomem *ptr = gic_data.redist_base[i]; 341021f6537SMarc Zyngier u32 reg; 342021f6537SMarc Zyngier 343021f6537SMarc Zyngier reg = readl_relaxed(ptr + GICR_PIDR2) & GIC_PIDR2_ARCH_MASK; 344021f6537SMarc Zyngier if (reg != GIC_PIDR2_ARCH_GICv3 && 345021f6537SMarc Zyngier reg != GIC_PIDR2_ARCH_GICv4) { /* We're in trouble... */ 346021f6537SMarc Zyngier pr_warn("No redistributor present @%p\n", ptr); 347021f6537SMarc Zyngier break; 348021f6537SMarc Zyngier } 349021f6537SMarc Zyngier 350021f6537SMarc Zyngier do { 351021f6537SMarc Zyngier typer = readq_relaxed(ptr + GICR_TYPER); 352021f6537SMarc Zyngier if ((typer >> 32) == aff) { 353021f6537SMarc Zyngier gic_data_rdist_rd_base() = ptr; 354021f6537SMarc Zyngier pr_info("CPU%d: found redistributor %llx @%p\n", 355021f6537SMarc Zyngier smp_processor_id(), 356021f6537SMarc Zyngier (unsigned long long)mpidr, ptr); 357021f6537SMarc Zyngier return 0; 358021f6537SMarc Zyngier } 359021f6537SMarc Zyngier 360021f6537SMarc Zyngier if (gic_data.redist_stride) { 361021f6537SMarc Zyngier ptr += gic_data.redist_stride; 362021f6537SMarc Zyngier } else { 363021f6537SMarc Zyngier ptr += SZ_64K * 2; /* Skip RD_base + SGI_base */ 364021f6537SMarc Zyngier if (typer & GICR_TYPER_VLPIS) 365021f6537SMarc Zyngier ptr += SZ_64K * 2; /* Skip VLPI_base + reserved page */ 366021f6537SMarc Zyngier } 367021f6537SMarc Zyngier } while (!(typer & GICR_TYPER_LAST)); 368021f6537SMarc Zyngier } 369021f6537SMarc Zyngier 370021f6537SMarc Zyngier /* We couldn't even deal with ourselves... */ 371021f6537SMarc Zyngier WARN(true, "CPU%d: mpidr %llx has no re-distributor!\n", 372021f6537SMarc Zyngier smp_processor_id(), (unsigned long long)mpidr); 373021f6537SMarc Zyngier return -ENODEV; 374021f6537SMarc Zyngier } 375021f6537SMarc Zyngier 376021f6537SMarc Zyngier static void gic_cpu_init(void) 377021f6537SMarc Zyngier { 378021f6537SMarc Zyngier void __iomem *rbase; 379021f6537SMarc Zyngier 380021f6537SMarc Zyngier /* Register ourselves with the rest of the world */ 381021f6537SMarc Zyngier if (gic_populate_rdist()) 382021f6537SMarc Zyngier return; 383021f6537SMarc Zyngier 384021f6537SMarc Zyngier gic_enable_redist(); 385021f6537SMarc Zyngier 386021f6537SMarc Zyngier rbase = gic_data_rdist_sgi_base(); 387021f6537SMarc Zyngier 388021f6537SMarc Zyngier gic_cpu_config(rbase, gic_redist_wait_for_rwp); 389021f6537SMarc Zyngier 390021f6537SMarc Zyngier /* Enable system registers */ 391021f6537SMarc Zyngier gic_enable_sre(); 392021f6537SMarc Zyngier 393021f6537SMarc Zyngier /* Set priority mask register */ 394021f6537SMarc Zyngier gic_write_pmr(DEFAULT_PMR_VALUE); 395021f6537SMarc Zyngier 396021f6537SMarc Zyngier /* EOI deactivates interrupt too (mode 0) */ 397021f6537SMarc Zyngier gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop_dir); 398021f6537SMarc Zyngier 399021f6537SMarc Zyngier /* ... and let's hit the road... */ 400021f6537SMarc Zyngier gic_write_grpen1(1); 401021f6537SMarc Zyngier } 402021f6537SMarc Zyngier 403021f6537SMarc Zyngier #ifdef CONFIG_SMP 404021f6537SMarc Zyngier static int gic_secondary_init(struct notifier_block *nfb, 405021f6537SMarc Zyngier unsigned long action, void *hcpu) 406021f6537SMarc Zyngier { 407021f6537SMarc Zyngier if (action == CPU_STARTING || action == CPU_STARTING_FROZEN) 408021f6537SMarc Zyngier gic_cpu_init(); 409021f6537SMarc Zyngier return NOTIFY_OK; 410021f6537SMarc Zyngier } 411021f6537SMarc Zyngier 412021f6537SMarc Zyngier /* 413021f6537SMarc Zyngier * Notifier for enabling the GIC CPU interface. Set an arbitrarily high 414021f6537SMarc Zyngier * priority because the GIC needs to be up before the ARM generic timers. 415021f6537SMarc Zyngier */ 416021f6537SMarc Zyngier static struct notifier_block gic_cpu_notifier = { 417021f6537SMarc Zyngier .notifier_call = gic_secondary_init, 418021f6537SMarc Zyngier .priority = 100, 419021f6537SMarc Zyngier }; 420021f6537SMarc Zyngier 421021f6537SMarc Zyngier static u16 gic_compute_target_list(int *base_cpu, const struct cpumask *mask, 422021f6537SMarc Zyngier u64 cluster_id) 423021f6537SMarc Zyngier { 424021f6537SMarc Zyngier int cpu = *base_cpu; 425021f6537SMarc Zyngier u64 mpidr = cpu_logical_map(cpu); 426021f6537SMarc Zyngier u16 tlist = 0; 427021f6537SMarc Zyngier 428021f6537SMarc Zyngier while (cpu < nr_cpu_ids) { 429021f6537SMarc Zyngier /* 430021f6537SMarc Zyngier * If we ever get a cluster of more than 16 CPUs, just 431021f6537SMarc Zyngier * scream and skip that CPU. 432021f6537SMarc Zyngier */ 433021f6537SMarc Zyngier if (WARN_ON((mpidr & 0xff) >= 16)) 434021f6537SMarc Zyngier goto out; 435021f6537SMarc Zyngier 436021f6537SMarc Zyngier tlist |= 1 << (mpidr & 0xf); 437021f6537SMarc Zyngier 438021f6537SMarc Zyngier cpu = cpumask_next(cpu, mask); 439021f6537SMarc Zyngier if (cpu == nr_cpu_ids) 440021f6537SMarc Zyngier goto out; 441021f6537SMarc Zyngier 442021f6537SMarc Zyngier mpidr = cpu_logical_map(cpu); 443021f6537SMarc Zyngier 444021f6537SMarc Zyngier if (cluster_id != (mpidr & ~0xffUL)) { 445021f6537SMarc Zyngier cpu--; 446021f6537SMarc Zyngier goto out; 447021f6537SMarc Zyngier } 448021f6537SMarc Zyngier } 449021f6537SMarc Zyngier out: 450021f6537SMarc Zyngier *base_cpu = cpu; 451021f6537SMarc Zyngier return tlist; 452021f6537SMarc Zyngier } 453021f6537SMarc Zyngier 454021f6537SMarc Zyngier static void gic_send_sgi(u64 cluster_id, u16 tlist, unsigned int irq) 455021f6537SMarc Zyngier { 456021f6537SMarc Zyngier u64 val; 457021f6537SMarc Zyngier 458021f6537SMarc Zyngier val = (MPIDR_AFFINITY_LEVEL(cluster_id, 3) << 48 | 459021f6537SMarc Zyngier MPIDR_AFFINITY_LEVEL(cluster_id, 2) << 32 | 460021f6537SMarc Zyngier irq << 24 | 461021f6537SMarc Zyngier MPIDR_AFFINITY_LEVEL(cluster_id, 1) << 16 | 462021f6537SMarc Zyngier tlist); 463021f6537SMarc Zyngier 464021f6537SMarc Zyngier pr_debug("CPU%d: ICC_SGI1R_EL1 %llx\n", smp_processor_id(), val); 465021f6537SMarc Zyngier gic_write_sgi1r(val); 466021f6537SMarc Zyngier } 467021f6537SMarc Zyngier 468021f6537SMarc Zyngier static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) 469021f6537SMarc Zyngier { 470021f6537SMarc Zyngier int cpu; 471021f6537SMarc Zyngier 472021f6537SMarc Zyngier if (WARN_ON(irq >= 16)) 473021f6537SMarc Zyngier return; 474021f6537SMarc Zyngier 475021f6537SMarc Zyngier /* 476021f6537SMarc Zyngier * Ensure that stores to Normal memory are visible to the 477021f6537SMarc Zyngier * other CPUs before issuing the IPI. 478021f6537SMarc Zyngier */ 479021f6537SMarc Zyngier smp_wmb(); 480021f6537SMarc Zyngier 481021f6537SMarc Zyngier for_each_cpu_mask(cpu, *mask) { 482021f6537SMarc Zyngier u64 cluster_id = cpu_logical_map(cpu) & ~0xffUL; 483021f6537SMarc Zyngier u16 tlist; 484021f6537SMarc Zyngier 485021f6537SMarc Zyngier tlist = gic_compute_target_list(&cpu, mask, cluster_id); 486021f6537SMarc Zyngier gic_send_sgi(cluster_id, tlist, irq); 487021f6537SMarc Zyngier } 488021f6537SMarc Zyngier 489021f6537SMarc Zyngier /* Force the above writes to ICC_SGI1R_EL1 to be executed */ 490021f6537SMarc Zyngier isb(); 491021f6537SMarc Zyngier } 492021f6537SMarc Zyngier 493021f6537SMarc Zyngier static void gic_smp_init(void) 494021f6537SMarc Zyngier { 495021f6537SMarc Zyngier set_smp_cross_call(gic_raise_softirq); 496021f6537SMarc Zyngier register_cpu_notifier(&gic_cpu_notifier); 497021f6537SMarc Zyngier } 498021f6537SMarc Zyngier 499021f6537SMarc Zyngier static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, 500021f6537SMarc Zyngier bool force) 501021f6537SMarc Zyngier { 502021f6537SMarc Zyngier unsigned int cpu = cpumask_any_and(mask_val, cpu_online_mask); 503021f6537SMarc Zyngier void __iomem *reg; 504021f6537SMarc Zyngier int enabled; 505021f6537SMarc Zyngier u64 val; 506021f6537SMarc Zyngier 507021f6537SMarc Zyngier if (gic_irq_in_rdist(d)) 508021f6537SMarc Zyngier return -EINVAL; 509021f6537SMarc Zyngier 510021f6537SMarc Zyngier /* If interrupt was enabled, disable it first */ 511021f6537SMarc Zyngier enabled = gic_peek_irq(d, GICD_ISENABLER); 512021f6537SMarc Zyngier if (enabled) 513021f6537SMarc Zyngier gic_mask_irq(d); 514021f6537SMarc Zyngier 515021f6537SMarc Zyngier reg = gic_dist_base(d) + GICD_IROUTER + (gic_irq(d) * 8); 516021f6537SMarc Zyngier val = gic_mpidr_to_affinity(cpu_logical_map(cpu)); 517021f6537SMarc Zyngier 518021f6537SMarc Zyngier writeq_relaxed(val, reg); 519021f6537SMarc Zyngier 520021f6537SMarc Zyngier /* 521021f6537SMarc Zyngier * If the interrupt was enabled, enabled it again. Otherwise, 522021f6537SMarc Zyngier * just wait for the distributor to have digested our changes. 523021f6537SMarc Zyngier */ 524021f6537SMarc Zyngier if (enabled) 525021f6537SMarc Zyngier gic_unmask_irq(d); 526021f6537SMarc Zyngier else 527021f6537SMarc Zyngier gic_dist_wait_for_rwp(); 528021f6537SMarc Zyngier 529021f6537SMarc Zyngier return IRQ_SET_MASK_OK; 530021f6537SMarc Zyngier } 531021f6537SMarc Zyngier #else 532021f6537SMarc Zyngier #define gic_set_affinity NULL 533021f6537SMarc Zyngier #define gic_smp_init() do { } while(0) 534021f6537SMarc Zyngier #endif 535021f6537SMarc Zyngier 536021f6537SMarc Zyngier static struct irq_chip gic_chip = { 537021f6537SMarc Zyngier .name = "GICv3", 538021f6537SMarc Zyngier .irq_mask = gic_mask_irq, 539021f6537SMarc Zyngier .irq_unmask = gic_unmask_irq, 540021f6537SMarc Zyngier .irq_eoi = gic_eoi_irq, 541021f6537SMarc Zyngier .irq_set_type = gic_set_type, 542021f6537SMarc Zyngier .irq_set_affinity = gic_set_affinity, 543021f6537SMarc Zyngier }; 544021f6537SMarc Zyngier 545021f6537SMarc Zyngier static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq, 546021f6537SMarc Zyngier irq_hw_number_t hw) 547021f6537SMarc Zyngier { 548021f6537SMarc Zyngier /* SGIs are private to the core kernel */ 549021f6537SMarc Zyngier if (hw < 16) 550021f6537SMarc Zyngier return -EPERM; 551021f6537SMarc Zyngier /* PPIs */ 552021f6537SMarc Zyngier if (hw < 32) { 553021f6537SMarc Zyngier irq_set_percpu_devid(irq); 554021f6537SMarc Zyngier irq_set_chip_and_handler(irq, &gic_chip, 555021f6537SMarc Zyngier handle_percpu_devid_irq); 556021f6537SMarc Zyngier set_irq_flags(irq, IRQF_VALID | IRQF_NOAUTOEN); 557021f6537SMarc Zyngier } 558021f6537SMarc Zyngier /* SPIs */ 559021f6537SMarc Zyngier if (hw >= 32 && hw < gic_data.irq_nr) { 560021f6537SMarc Zyngier irq_set_chip_and_handler(irq, &gic_chip, 561021f6537SMarc Zyngier handle_fasteoi_irq); 562021f6537SMarc Zyngier set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 563021f6537SMarc Zyngier } 564021f6537SMarc Zyngier irq_set_chip_data(irq, d->host_data); 565021f6537SMarc Zyngier return 0; 566021f6537SMarc Zyngier } 567021f6537SMarc Zyngier 568021f6537SMarc Zyngier static int gic_irq_domain_xlate(struct irq_domain *d, 569021f6537SMarc Zyngier struct device_node *controller, 570021f6537SMarc Zyngier const u32 *intspec, unsigned int intsize, 571021f6537SMarc Zyngier unsigned long *out_hwirq, unsigned int *out_type) 572021f6537SMarc Zyngier { 573021f6537SMarc Zyngier if (d->of_node != controller) 574021f6537SMarc Zyngier return -EINVAL; 575021f6537SMarc Zyngier if (intsize < 3) 576021f6537SMarc Zyngier return -EINVAL; 577021f6537SMarc Zyngier 578021f6537SMarc Zyngier switch(intspec[0]) { 579021f6537SMarc Zyngier case 0: /* SPI */ 580021f6537SMarc Zyngier *out_hwirq = intspec[1] + 32; 581021f6537SMarc Zyngier break; 582021f6537SMarc Zyngier case 1: /* PPI */ 583021f6537SMarc Zyngier *out_hwirq = intspec[1] + 16; 584021f6537SMarc Zyngier break; 585021f6537SMarc Zyngier default: 586021f6537SMarc Zyngier return -EINVAL; 587021f6537SMarc Zyngier } 588021f6537SMarc Zyngier 589021f6537SMarc Zyngier *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK; 590021f6537SMarc Zyngier return 0; 591021f6537SMarc Zyngier } 592021f6537SMarc Zyngier 593021f6537SMarc Zyngier static const struct irq_domain_ops gic_irq_domain_ops = { 594021f6537SMarc Zyngier .map = gic_irq_domain_map, 595021f6537SMarc Zyngier .xlate = gic_irq_domain_xlate, 596021f6537SMarc Zyngier }; 597021f6537SMarc Zyngier 598021f6537SMarc Zyngier static int __init gic_of_init(struct device_node *node, struct device_node *parent) 599021f6537SMarc Zyngier { 600021f6537SMarc Zyngier void __iomem *dist_base; 601021f6537SMarc Zyngier void __iomem **redist_base; 602021f6537SMarc Zyngier u64 redist_stride; 603021f6537SMarc Zyngier u32 redist_regions; 604021f6537SMarc Zyngier u32 reg; 605021f6537SMarc Zyngier int gic_irqs; 606021f6537SMarc Zyngier int err; 607021f6537SMarc Zyngier int i; 608021f6537SMarc Zyngier 609021f6537SMarc Zyngier dist_base = of_iomap(node, 0); 610021f6537SMarc Zyngier if (!dist_base) { 611021f6537SMarc Zyngier pr_err("%s: unable to map gic dist registers\n", 612021f6537SMarc Zyngier node->full_name); 613021f6537SMarc Zyngier return -ENXIO; 614021f6537SMarc Zyngier } 615021f6537SMarc Zyngier 616021f6537SMarc Zyngier reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK; 617021f6537SMarc Zyngier if (reg != GIC_PIDR2_ARCH_GICv3 && reg != GIC_PIDR2_ARCH_GICv4) { 618021f6537SMarc Zyngier pr_err("%s: no distributor detected, giving up\n", 619021f6537SMarc Zyngier node->full_name); 620021f6537SMarc Zyngier err = -ENODEV; 621021f6537SMarc Zyngier goto out_unmap_dist; 622021f6537SMarc Zyngier } 623021f6537SMarc Zyngier 624021f6537SMarc Zyngier if (of_property_read_u32(node, "#redistributor-regions", &redist_regions)) 625021f6537SMarc Zyngier redist_regions = 1; 626021f6537SMarc Zyngier 627021f6537SMarc Zyngier redist_base = kzalloc(sizeof(*redist_base) * redist_regions, GFP_KERNEL); 628021f6537SMarc Zyngier if (!redist_base) { 629021f6537SMarc Zyngier err = -ENOMEM; 630021f6537SMarc Zyngier goto out_unmap_dist; 631021f6537SMarc Zyngier } 632021f6537SMarc Zyngier 633021f6537SMarc Zyngier for (i = 0; i < redist_regions; i++) { 634021f6537SMarc Zyngier redist_base[i] = of_iomap(node, 1 + i); 635021f6537SMarc Zyngier if (!redist_base[i]) { 636021f6537SMarc Zyngier pr_err("%s: couldn't map region %d\n", 637021f6537SMarc Zyngier node->full_name, i); 638021f6537SMarc Zyngier err = -ENODEV; 639021f6537SMarc Zyngier goto out_unmap_rdist; 640021f6537SMarc Zyngier } 641021f6537SMarc Zyngier } 642021f6537SMarc Zyngier 643021f6537SMarc Zyngier if (of_property_read_u64(node, "redistributor-stride", &redist_stride)) 644021f6537SMarc Zyngier redist_stride = 0; 645021f6537SMarc Zyngier 646021f6537SMarc Zyngier gic_data.dist_base = dist_base; 647021f6537SMarc Zyngier gic_data.redist_base = redist_base; 648021f6537SMarc Zyngier gic_data.redist_regions = redist_regions; 649021f6537SMarc Zyngier gic_data.redist_stride = redist_stride; 650021f6537SMarc Zyngier 651021f6537SMarc Zyngier /* 652021f6537SMarc Zyngier * Find out how many interrupts are supported. 653021f6537SMarc Zyngier * The GIC only supports up to 1020 interrupt sources (SGI+PPI+SPI) 654021f6537SMarc Zyngier */ 655021f6537SMarc Zyngier gic_irqs = readl_relaxed(gic_data.dist_base + GICD_TYPER) & 0x1f; 656021f6537SMarc Zyngier gic_irqs = (gic_irqs + 1) * 32; 657021f6537SMarc Zyngier if (gic_irqs > 1020) 658021f6537SMarc Zyngier gic_irqs = 1020; 659021f6537SMarc Zyngier gic_data.irq_nr = gic_irqs; 660021f6537SMarc Zyngier 661021f6537SMarc Zyngier gic_data.domain = irq_domain_add_tree(node, &gic_irq_domain_ops, 662021f6537SMarc Zyngier &gic_data); 663021f6537SMarc Zyngier gic_data.rdist = alloc_percpu(typeof(*gic_data.rdist)); 664021f6537SMarc Zyngier 665021f6537SMarc Zyngier if (WARN_ON(!gic_data.domain) || WARN_ON(!gic_data.rdist)) { 666021f6537SMarc Zyngier err = -ENOMEM; 667021f6537SMarc Zyngier goto out_free; 668021f6537SMarc Zyngier } 669021f6537SMarc Zyngier 670021f6537SMarc Zyngier set_handle_irq(gic_handle_irq); 671021f6537SMarc Zyngier 672021f6537SMarc Zyngier gic_smp_init(); 673021f6537SMarc Zyngier gic_dist_init(); 674021f6537SMarc Zyngier gic_cpu_init(); 675021f6537SMarc Zyngier 676021f6537SMarc Zyngier return 0; 677021f6537SMarc Zyngier 678021f6537SMarc Zyngier out_free: 679021f6537SMarc Zyngier if (gic_data.domain) 680021f6537SMarc Zyngier irq_domain_remove(gic_data.domain); 681021f6537SMarc Zyngier free_percpu(gic_data.rdist); 682021f6537SMarc Zyngier out_unmap_rdist: 683021f6537SMarc Zyngier for (i = 0; i < redist_regions; i++) 684021f6537SMarc Zyngier if (redist_base[i]) 685021f6537SMarc Zyngier iounmap(redist_base[i]); 686021f6537SMarc Zyngier kfree(redist_base); 687021f6537SMarc Zyngier out_unmap_dist: 688021f6537SMarc Zyngier iounmap(dist_base); 689021f6537SMarc Zyngier return err; 690021f6537SMarc Zyngier } 691021f6537SMarc Zyngier 692021f6537SMarc Zyngier IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init); 693