1 /* 2 * Copyright (C) 2013, 2014 ARM Limited, All Rights Reserved. 3 * Author: Marc Zyngier <marc.zyngier@arm.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program. If not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #include <linux/acpi.h> 19 #include <linux/acpi_iort.h> 20 #include <linux/bitmap.h> 21 #include <linux/cpu.h> 22 #include <linux/delay.h> 23 #include <linux/dma-iommu.h> 24 #include <linux/interrupt.h> 25 #include <linux/irqdomain.h> 26 #include <linux/log2.h> 27 #include <linux/mm.h> 28 #include <linux/msi.h> 29 #include <linux/of.h> 30 #include <linux/of_address.h> 31 #include <linux/of_irq.h> 32 #include <linux/of_pci.h> 33 #include <linux/of_platform.h> 34 #include <linux/percpu.h> 35 #include <linux/slab.h> 36 37 #include <linux/irqchip.h> 38 #include <linux/irqchip/arm-gic-v3.h> 39 40 #include <asm/cputype.h> 41 #include <asm/exception.h> 42 43 #include "irq-gic-common.h" 44 45 #define ITS_FLAGS_CMDQ_NEEDS_FLUSHING (1ULL << 0) 46 #define ITS_FLAGS_WORKAROUND_CAVIUM_22375 (1ULL << 1) 47 #define ITS_FLAGS_WORKAROUND_CAVIUM_23144 (1ULL << 2) 48 49 #define RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING (1 << 0) 50 51 /* 52 * Collection structure - just an ID, and a redistributor address to 53 * ping. We use one per CPU as a bag of interrupts assigned to this 54 * CPU. 55 */ 56 struct its_collection { 57 u64 target_address; 58 u16 col_id; 59 }; 60 61 /* 62 * The ITS_BASER structure - contains memory information, cached 63 * value of BASER register configuration and ITS page size. 64 */ 65 struct its_baser { 66 void *base; 67 u64 val; 68 u32 order; 69 u32 psz; 70 }; 71 72 /* 73 * The ITS structure - contains most of the infrastructure, with the 74 * top-level MSI domain, the command queue, the collections, and the 75 * list of devices writing to it. 76 */ 77 struct its_node { 78 raw_spinlock_t lock; 79 struct list_head entry; 80 void __iomem *base; 81 phys_addr_t phys_base; 82 struct its_cmd_block *cmd_base; 83 struct its_cmd_block *cmd_write; 84 struct its_baser tables[GITS_BASER_NR_REGS]; 85 struct its_collection *collections; 86 struct list_head its_device_list; 87 u64 flags; 88 u32 ite_size; 89 u32 device_ids; 90 int numa_node; 91 }; 92 93 #define ITS_ITT_ALIGN SZ_256 94 95 /* Convert page order to size in bytes */ 96 #define PAGE_ORDER_TO_SIZE(o) (PAGE_SIZE << (o)) 97 98 struct event_lpi_map { 99 unsigned long *lpi_map; 100 u16 *col_map; 101 irq_hw_number_t lpi_base; 102 int nr_lpis; 103 }; 104 105 /* 106 * The ITS view of a device - belongs to an ITS, a collection, owns an 107 * interrupt translation table, and a list of interrupts. 108 */ 109 struct its_device { 110 struct list_head entry; 111 struct its_node *its; 112 struct event_lpi_map event_map; 113 void *itt; 114 u32 nr_ites; 115 u32 device_id; 116 }; 117 118 static LIST_HEAD(its_nodes); 119 static DEFINE_SPINLOCK(its_lock); 120 static struct rdists *gic_rdists; 121 static struct irq_domain *its_parent; 122 123 #define gic_data_rdist() (raw_cpu_ptr(gic_rdists->rdist)) 124 #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base) 125 126 static struct its_collection *dev_event_to_col(struct its_device *its_dev, 127 u32 event) 128 { 129 struct its_node *its = its_dev->its; 130 131 return its->collections + its_dev->event_map.col_map[event]; 132 } 133 134 /* 135 * ITS command descriptors - parameters to be encoded in a command 136 * block. 137 */ 138 struct its_cmd_desc { 139 union { 140 struct { 141 struct its_device *dev; 142 u32 event_id; 143 } its_inv_cmd; 144 145 struct { 146 struct its_device *dev; 147 u32 event_id; 148 } its_int_cmd; 149 150 struct { 151 struct its_device *dev; 152 int valid; 153 } its_mapd_cmd; 154 155 struct { 156 struct its_collection *col; 157 int valid; 158 } its_mapc_cmd; 159 160 struct { 161 struct its_device *dev; 162 u32 phys_id; 163 u32 event_id; 164 } its_mapti_cmd; 165 166 struct { 167 struct its_device *dev; 168 struct its_collection *col; 169 u32 event_id; 170 } its_movi_cmd; 171 172 struct { 173 struct its_device *dev; 174 u32 event_id; 175 } its_discard_cmd; 176 177 struct { 178 struct its_collection *col; 179 } its_invall_cmd; 180 }; 181 }; 182 183 /* 184 * The ITS command block, which is what the ITS actually parses. 185 */ 186 struct its_cmd_block { 187 u64 raw_cmd[4]; 188 }; 189 190 #define ITS_CMD_QUEUE_SZ SZ_64K 191 #define ITS_CMD_QUEUE_NR_ENTRIES (ITS_CMD_QUEUE_SZ / sizeof(struct its_cmd_block)) 192 193 typedef struct its_collection *(*its_cmd_builder_t)(struct its_cmd_block *, 194 struct its_cmd_desc *); 195 196 static void its_mask_encode(u64 *raw_cmd, u64 val, int h, int l) 197 { 198 u64 mask = GENMASK_ULL(h, l); 199 *raw_cmd &= ~mask; 200 *raw_cmd |= (val << l) & mask; 201 } 202 203 static void its_encode_cmd(struct its_cmd_block *cmd, u8 cmd_nr) 204 { 205 its_mask_encode(&cmd->raw_cmd[0], cmd_nr, 7, 0); 206 } 207 208 static void its_encode_devid(struct its_cmd_block *cmd, u32 devid) 209 { 210 its_mask_encode(&cmd->raw_cmd[0], devid, 63, 32); 211 } 212 213 static void its_encode_event_id(struct its_cmd_block *cmd, u32 id) 214 { 215 its_mask_encode(&cmd->raw_cmd[1], id, 31, 0); 216 } 217 218 static void its_encode_phys_id(struct its_cmd_block *cmd, u32 phys_id) 219 { 220 its_mask_encode(&cmd->raw_cmd[1], phys_id, 63, 32); 221 } 222 223 static void its_encode_size(struct its_cmd_block *cmd, u8 size) 224 { 225 its_mask_encode(&cmd->raw_cmd[1], size, 4, 0); 226 } 227 228 static void its_encode_itt(struct its_cmd_block *cmd, u64 itt_addr) 229 { 230 its_mask_encode(&cmd->raw_cmd[2], itt_addr >> 8, 50, 8); 231 } 232 233 static void its_encode_valid(struct its_cmd_block *cmd, int valid) 234 { 235 its_mask_encode(&cmd->raw_cmd[2], !!valid, 63, 63); 236 } 237 238 static void its_encode_target(struct its_cmd_block *cmd, u64 target_addr) 239 { 240 its_mask_encode(&cmd->raw_cmd[2], target_addr >> 16, 50, 16); 241 } 242 243 static void its_encode_collection(struct its_cmd_block *cmd, u16 col) 244 { 245 its_mask_encode(&cmd->raw_cmd[2], col, 15, 0); 246 } 247 248 static inline void its_fixup_cmd(struct its_cmd_block *cmd) 249 { 250 /* Let's fixup BE commands */ 251 cmd->raw_cmd[0] = cpu_to_le64(cmd->raw_cmd[0]); 252 cmd->raw_cmd[1] = cpu_to_le64(cmd->raw_cmd[1]); 253 cmd->raw_cmd[2] = cpu_to_le64(cmd->raw_cmd[2]); 254 cmd->raw_cmd[3] = cpu_to_le64(cmd->raw_cmd[3]); 255 } 256 257 static struct its_collection *its_build_mapd_cmd(struct its_cmd_block *cmd, 258 struct its_cmd_desc *desc) 259 { 260 unsigned long itt_addr; 261 u8 size = ilog2(desc->its_mapd_cmd.dev->nr_ites); 262 263 itt_addr = virt_to_phys(desc->its_mapd_cmd.dev->itt); 264 itt_addr = ALIGN(itt_addr, ITS_ITT_ALIGN); 265 266 its_encode_cmd(cmd, GITS_CMD_MAPD); 267 its_encode_devid(cmd, desc->its_mapd_cmd.dev->device_id); 268 its_encode_size(cmd, size - 1); 269 its_encode_itt(cmd, itt_addr); 270 its_encode_valid(cmd, desc->its_mapd_cmd.valid); 271 272 its_fixup_cmd(cmd); 273 274 return NULL; 275 } 276 277 static struct its_collection *its_build_mapc_cmd(struct its_cmd_block *cmd, 278 struct its_cmd_desc *desc) 279 { 280 its_encode_cmd(cmd, GITS_CMD_MAPC); 281 its_encode_collection(cmd, desc->its_mapc_cmd.col->col_id); 282 its_encode_target(cmd, desc->its_mapc_cmd.col->target_address); 283 its_encode_valid(cmd, desc->its_mapc_cmd.valid); 284 285 its_fixup_cmd(cmd); 286 287 return desc->its_mapc_cmd.col; 288 } 289 290 static struct its_collection *its_build_mapti_cmd(struct its_cmd_block *cmd, 291 struct its_cmd_desc *desc) 292 { 293 struct its_collection *col; 294 295 col = dev_event_to_col(desc->its_mapti_cmd.dev, 296 desc->its_mapti_cmd.event_id); 297 298 its_encode_cmd(cmd, GITS_CMD_MAPTI); 299 its_encode_devid(cmd, desc->its_mapti_cmd.dev->device_id); 300 its_encode_event_id(cmd, desc->its_mapti_cmd.event_id); 301 its_encode_phys_id(cmd, desc->its_mapti_cmd.phys_id); 302 its_encode_collection(cmd, col->col_id); 303 304 its_fixup_cmd(cmd); 305 306 return col; 307 } 308 309 static struct its_collection *its_build_movi_cmd(struct its_cmd_block *cmd, 310 struct its_cmd_desc *desc) 311 { 312 struct its_collection *col; 313 314 col = dev_event_to_col(desc->its_movi_cmd.dev, 315 desc->its_movi_cmd.event_id); 316 317 its_encode_cmd(cmd, GITS_CMD_MOVI); 318 its_encode_devid(cmd, desc->its_movi_cmd.dev->device_id); 319 its_encode_event_id(cmd, desc->its_movi_cmd.event_id); 320 its_encode_collection(cmd, desc->its_movi_cmd.col->col_id); 321 322 its_fixup_cmd(cmd); 323 324 return col; 325 } 326 327 static struct its_collection *its_build_discard_cmd(struct its_cmd_block *cmd, 328 struct its_cmd_desc *desc) 329 { 330 struct its_collection *col; 331 332 col = dev_event_to_col(desc->its_discard_cmd.dev, 333 desc->its_discard_cmd.event_id); 334 335 its_encode_cmd(cmd, GITS_CMD_DISCARD); 336 its_encode_devid(cmd, desc->its_discard_cmd.dev->device_id); 337 its_encode_event_id(cmd, desc->its_discard_cmd.event_id); 338 339 its_fixup_cmd(cmd); 340 341 return col; 342 } 343 344 static struct its_collection *its_build_inv_cmd(struct its_cmd_block *cmd, 345 struct its_cmd_desc *desc) 346 { 347 struct its_collection *col; 348 349 col = dev_event_to_col(desc->its_inv_cmd.dev, 350 desc->its_inv_cmd.event_id); 351 352 its_encode_cmd(cmd, GITS_CMD_INV); 353 its_encode_devid(cmd, desc->its_inv_cmd.dev->device_id); 354 its_encode_event_id(cmd, desc->its_inv_cmd.event_id); 355 356 its_fixup_cmd(cmd); 357 358 return col; 359 } 360 361 static struct its_collection *its_build_invall_cmd(struct its_cmd_block *cmd, 362 struct its_cmd_desc *desc) 363 { 364 its_encode_cmd(cmd, GITS_CMD_INVALL); 365 its_encode_collection(cmd, desc->its_mapc_cmd.col->col_id); 366 367 its_fixup_cmd(cmd); 368 369 return NULL; 370 } 371 372 static u64 its_cmd_ptr_to_offset(struct its_node *its, 373 struct its_cmd_block *ptr) 374 { 375 return (ptr - its->cmd_base) * sizeof(*ptr); 376 } 377 378 static int its_queue_full(struct its_node *its) 379 { 380 int widx; 381 int ridx; 382 383 widx = its->cmd_write - its->cmd_base; 384 ridx = readl_relaxed(its->base + GITS_CREADR) / sizeof(struct its_cmd_block); 385 386 /* This is incredibly unlikely to happen, unless the ITS locks up. */ 387 if (((widx + 1) % ITS_CMD_QUEUE_NR_ENTRIES) == ridx) 388 return 1; 389 390 return 0; 391 } 392 393 static struct its_cmd_block *its_allocate_entry(struct its_node *its) 394 { 395 struct its_cmd_block *cmd; 396 u32 count = 1000000; /* 1s! */ 397 398 while (its_queue_full(its)) { 399 count--; 400 if (!count) { 401 pr_err_ratelimited("ITS queue not draining\n"); 402 return NULL; 403 } 404 cpu_relax(); 405 udelay(1); 406 } 407 408 cmd = its->cmd_write++; 409 410 /* Handle queue wrapping */ 411 if (its->cmd_write == (its->cmd_base + ITS_CMD_QUEUE_NR_ENTRIES)) 412 its->cmd_write = its->cmd_base; 413 414 /* Clear command */ 415 cmd->raw_cmd[0] = 0; 416 cmd->raw_cmd[1] = 0; 417 cmd->raw_cmd[2] = 0; 418 cmd->raw_cmd[3] = 0; 419 420 return cmd; 421 } 422 423 static struct its_cmd_block *its_post_commands(struct its_node *its) 424 { 425 u64 wr = its_cmd_ptr_to_offset(its, its->cmd_write); 426 427 writel_relaxed(wr, its->base + GITS_CWRITER); 428 429 return its->cmd_write; 430 } 431 432 static void its_flush_cmd(struct its_node *its, struct its_cmd_block *cmd) 433 { 434 /* 435 * Make sure the commands written to memory are observable by 436 * the ITS. 437 */ 438 if (its->flags & ITS_FLAGS_CMDQ_NEEDS_FLUSHING) 439 gic_flush_dcache_to_poc(cmd, sizeof(*cmd)); 440 else 441 dsb(ishst); 442 } 443 444 static void its_wait_for_range_completion(struct its_node *its, 445 struct its_cmd_block *from, 446 struct its_cmd_block *to) 447 { 448 u64 rd_idx, from_idx, to_idx; 449 u32 count = 1000000; /* 1s! */ 450 451 from_idx = its_cmd_ptr_to_offset(its, from); 452 to_idx = its_cmd_ptr_to_offset(its, to); 453 454 while (1) { 455 rd_idx = readl_relaxed(its->base + GITS_CREADR); 456 if (rd_idx >= to_idx || rd_idx < from_idx) 457 break; 458 459 count--; 460 if (!count) { 461 pr_err_ratelimited("ITS queue timeout\n"); 462 return; 463 } 464 cpu_relax(); 465 udelay(1); 466 } 467 } 468 469 static void its_send_single_command(struct its_node *its, 470 its_cmd_builder_t builder, 471 struct its_cmd_desc *desc) 472 { 473 struct its_cmd_block *cmd, *sync_cmd, *next_cmd; 474 struct its_collection *sync_col; 475 unsigned long flags; 476 477 raw_spin_lock_irqsave(&its->lock, flags); 478 479 cmd = its_allocate_entry(its); 480 if (!cmd) { /* We're soooooo screewed... */ 481 pr_err_ratelimited("ITS can't allocate, dropping command\n"); 482 raw_spin_unlock_irqrestore(&its->lock, flags); 483 return; 484 } 485 sync_col = builder(cmd, desc); 486 its_flush_cmd(its, cmd); 487 488 if (sync_col) { 489 sync_cmd = its_allocate_entry(its); 490 if (!sync_cmd) { 491 pr_err_ratelimited("ITS can't SYNC, skipping\n"); 492 goto post; 493 } 494 its_encode_cmd(sync_cmd, GITS_CMD_SYNC); 495 its_encode_target(sync_cmd, sync_col->target_address); 496 its_fixup_cmd(sync_cmd); 497 its_flush_cmd(its, sync_cmd); 498 } 499 500 post: 501 next_cmd = its_post_commands(its); 502 raw_spin_unlock_irqrestore(&its->lock, flags); 503 504 its_wait_for_range_completion(its, cmd, next_cmd); 505 } 506 507 static void its_send_inv(struct its_device *dev, u32 event_id) 508 { 509 struct its_cmd_desc desc; 510 511 desc.its_inv_cmd.dev = dev; 512 desc.its_inv_cmd.event_id = event_id; 513 514 its_send_single_command(dev->its, its_build_inv_cmd, &desc); 515 } 516 517 static void its_send_mapd(struct its_device *dev, int valid) 518 { 519 struct its_cmd_desc desc; 520 521 desc.its_mapd_cmd.dev = dev; 522 desc.its_mapd_cmd.valid = !!valid; 523 524 its_send_single_command(dev->its, its_build_mapd_cmd, &desc); 525 } 526 527 static void its_send_mapc(struct its_node *its, struct its_collection *col, 528 int valid) 529 { 530 struct its_cmd_desc desc; 531 532 desc.its_mapc_cmd.col = col; 533 desc.its_mapc_cmd.valid = !!valid; 534 535 its_send_single_command(its, its_build_mapc_cmd, &desc); 536 } 537 538 static void its_send_mapti(struct its_device *dev, u32 irq_id, u32 id) 539 { 540 struct its_cmd_desc desc; 541 542 desc.its_mapti_cmd.dev = dev; 543 desc.its_mapti_cmd.phys_id = irq_id; 544 desc.its_mapti_cmd.event_id = id; 545 546 its_send_single_command(dev->its, its_build_mapti_cmd, &desc); 547 } 548 549 static void its_send_movi(struct its_device *dev, 550 struct its_collection *col, u32 id) 551 { 552 struct its_cmd_desc desc; 553 554 desc.its_movi_cmd.dev = dev; 555 desc.its_movi_cmd.col = col; 556 desc.its_movi_cmd.event_id = id; 557 558 its_send_single_command(dev->its, its_build_movi_cmd, &desc); 559 } 560 561 static void its_send_discard(struct its_device *dev, u32 id) 562 { 563 struct its_cmd_desc desc; 564 565 desc.its_discard_cmd.dev = dev; 566 desc.its_discard_cmd.event_id = id; 567 568 its_send_single_command(dev->its, its_build_discard_cmd, &desc); 569 } 570 571 static void its_send_invall(struct its_node *its, struct its_collection *col) 572 { 573 struct its_cmd_desc desc; 574 575 desc.its_invall_cmd.col = col; 576 577 its_send_single_command(its, its_build_invall_cmd, &desc); 578 } 579 580 /* 581 * irqchip functions - assumes MSI, mostly. 582 */ 583 584 static inline u32 its_get_event_id(struct irq_data *d) 585 { 586 struct its_device *its_dev = irq_data_get_irq_chip_data(d); 587 return d->hwirq - its_dev->event_map.lpi_base; 588 } 589 590 static void lpi_set_config(struct irq_data *d, bool enable) 591 { 592 struct its_device *its_dev = irq_data_get_irq_chip_data(d); 593 irq_hw_number_t hwirq = d->hwirq; 594 u32 id = its_get_event_id(d); 595 u8 *cfg = page_address(gic_rdists->prop_page) + hwirq - 8192; 596 597 if (enable) 598 *cfg |= LPI_PROP_ENABLED; 599 else 600 *cfg &= ~LPI_PROP_ENABLED; 601 602 /* 603 * Make the above write visible to the redistributors. 604 * And yes, we're flushing exactly: One. Single. Byte. 605 * Humpf... 606 */ 607 if (gic_rdists->flags & RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING) 608 gic_flush_dcache_to_poc(cfg, sizeof(*cfg)); 609 else 610 dsb(ishst); 611 its_send_inv(its_dev, id); 612 } 613 614 static void its_mask_irq(struct irq_data *d) 615 { 616 lpi_set_config(d, false); 617 } 618 619 static void its_unmask_irq(struct irq_data *d) 620 { 621 lpi_set_config(d, true); 622 } 623 624 static int its_set_affinity(struct irq_data *d, const struct cpumask *mask_val, 625 bool force) 626 { 627 unsigned int cpu; 628 const struct cpumask *cpu_mask = cpu_online_mask; 629 struct its_device *its_dev = irq_data_get_irq_chip_data(d); 630 struct its_collection *target_col; 631 u32 id = its_get_event_id(d); 632 633 /* lpi cannot be routed to a redistributor that is on a foreign node */ 634 if (its_dev->its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) { 635 if (its_dev->its->numa_node >= 0) { 636 cpu_mask = cpumask_of_node(its_dev->its->numa_node); 637 if (!cpumask_intersects(mask_val, cpu_mask)) 638 return -EINVAL; 639 } 640 } 641 642 cpu = cpumask_any_and(mask_val, cpu_mask); 643 644 if (cpu >= nr_cpu_ids) 645 return -EINVAL; 646 647 target_col = &its_dev->its->collections[cpu]; 648 its_send_movi(its_dev, target_col, id); 649 its_dev->event_map.col_map[id] = cpu; 650 651 return IRQ_SET_MASK_OK_DONE; 652 } 653 654 static void its_irq_compose_msi_msg(struct irq_data *d, struct msi_msg *msg) 655 { 656 struct its_device *its_dev = irq_data_get_irq_chip_data(d); 657 struct its_node *its; 658 u64 addr; 659 660 its = its_dev->its; 661 addr = its->phys_base + GITS_TRANSLATER; 662 663 msg->address_lo = lower_32_bits(addr); 664 msg->address_hi = upper_32_bits(addr); 665 msg->data = its_get_event_id(d); 666 667 iommu_dma_map_msi_msg(d->irq, msg); 668 } 669 670 static struct irq_chip its_irq_chip = { 671 .name = "ITS", 672 .irq_mask = its_mask_irq, 673 .irq_unmask = its_unmask_irq, 674 .irq_eoi = irq_chip_eoi_parent, 675 .irq_set_affinity = its_set_affinity, 676 .irq_compose_msi_msg = its_irq_compose_msi_msg, 677 }; 678 679 /* 680 * How we allocate LPIs: 681 * 682 * The GIC has id_bits bits for interrupt identifiers. From there, we 683 * must subtract 8192 which are reserved for SGIs/PPIs/SPIs. Then, as 684 * we allocate LPIs by chunks of 32, we can shift the whole thing by 5 685 * bits to the right. 686 * 687 * This gives us (((1UL << id_bits) - 8192) >> 5) possible allocations. 688 */ 689 #define IRQS_PER_CHUNK_SHIFT 5 690 #define IRQS_PER_CHUNK (1 << IRQS_PER_CHUNK_SHIFT) 691 692 static unsigned long *lpi_bitmap; 693 static u32 lpi_chunks; 694 static DEFINE_SPINLOCK(lpi_lock); 695 696 static int its_lpi_to_chunk(int lpi) 697 { 698 return (lpi - 8192) >> IRQS_PER_CHUNK_SHIFT; 699 } 700 701 static int its_chunk_to_lpi(int chunk) 702 { 703 return (chunk << IRQS_PER_CHUNK_SHIFT) + 8192; 704 } 705 706 static int __init its_lpi_init(u32 id_bits) 707 { 708 lpi_chunks = its_lpi_to_chunk(1UL << id_bits); 709 710 lpi_bitmap = kzalloc(BITS_TO_LONGS(lpi_chunks) * sizeof(long), 711 GFP_KERNEL); 712 if (!lpi_bitmap) { 713 lpi_chunks = 0; 714 return -ENOMEM; 715 } 716 717 pr_info("ITS: Allocated %d chunks for LPIs\n", (int)lpi_chunks); 718 return 0; 719 } 720 721 static unsigned long *its_lpi_alloc_chunks(int nr_irqs, int *base, int *nr_ids) 722 { 723 unsigned long *bitmap = NULL; 724 int chunk_id; 725 int nr_chunks; 726 int i; 727 728 nr_chunks = DIV_ROUND_UP(nr_irqs, IRQS_PER_CHUNK); 729 730 spin_lock(&lpi_lock); 731 732 do { 733 chunk_id = bitmap_find_next_zero_area(lpi_bitmap, lpi_chunks, 734 0, nr_chunks, 0); 735 if (chunk_id < lpi_chunks) 736 break; 737 738 nr_chunks--; 739 } while (nr_chunks > 0); 740 741 if (!nr_chunks) 742 goto out; 743 744 bitmap = kzalloc(BITS_TO_LONGS(nr_chunks * IRQS_PER_CHUNK) * sizeof (long), 745 GFP_ATOMIC); 746 if (!bitmap) 747 goto out; 748 749 for (i = 0; i < nr_chunks; i++) 750 set_bit(chunk_id + i, lpi_bitmap); 751 752 *base = its_chunk_to_lpi(chunk_id); 753 *nr_ids = nr_chunks * IRQS_PER_CHUNK; 754 755 out: 756 spin_unlock(&lpi_lock); 757 758 if (!bitmap) 759 *base = *nr_ids = 0; 760 761 return bitmap; 762 } 763 764 static void its_lpi_free(struct event_lpi_map *map) 765 { 766 int base = map->lpi_base; 767 int nr_ids = map->nr_lpis; 768 int lpi; 769 770 spin_lock(&lpi_lock); 771 772 for (lpi = base; lpi < (base + nr_ids); lpi += IRQS_PER_CHUNK) { 773 int chunk = its_lpi_to_chunk(lpi); 774 BUG_ON(chunk > lpi_chunks); 775 if (test_bit(chunk, lpi_bitmap)) { 776 clear_bit(chunk, lpi_bitmap); 777 } else { 778 pr_err("Bad LPI chunk %d\n", chunk); 779 } 780 } 781 782 spin_unlock(&lpi_lock); 783 784 kfree(map->lpi_map); 785 kfree(map->col_map); 786 } 787 788 /* 789 * We allocate 64kB for PROPBASE. That gives us at most 64K LPIs to 790 * deal with (one configuration byte per interrupt). PENDBASE has to 791 * be 64kB aligned (one bit per LPI, plus 8192 bits for SPI/PPI/SGI). 792 */ 793 #define LPI_PROPBASE_SZ SZ_64K 794 #define LPI_PENDBASE_SZ (LPI_PROPBASE_SZ / 8 + SZ_1K) 795 796 /* 797 * This is how many bits of ID we need, including the useless ones. 798 */ 799 #define LPI_NRBITS ilog2(LPI_PROPBASE_SZ + SZ_8K) 800 801 #define LPI_PROP_DEFAULT_PRIO 0xa0 802 803 static int __init its_alloc_lpi_tables(void) 804 { 805 phys_addr_t paddr; 806 807 gic_rdists->prop_page = alloc_pages(GFP_NOWAIT, 808 get_order(LPI_PROPBASE_SZ)); 809 if (!gic_rdists->prop_page) { 810 pr_err("Failed to allocate PROPBASE\n"); 811 return -ENOMEM; 812 } 813 814 paddr = page_to_phys(gic_rdists->prop_page); 815 pr_info("GIC: using LPI property table @%pa\n", &paddr); 816 817 /* Priority 0xa0, Group-1, disabled */ 818 memset(page_address(gic_rdists->prop_page), 819 LPI_PROP_DEFAULT_PRIO | LPI_PROP_GROUP1, 820 LPI_PROPBASE_SZ); 821 822 /* Make sure the GIC will observe the written configuration */ 823 gic_flush_dcache_to_poc(page_address(gic_rdists->prop_page), LPI_PROPBASE_SZ); 824 825 return 0; 826 } 827 828 static const char *its_base_type_string[] = { 829 [GITS_BASER_TYPE_DEVICE] = "Devices", 830 [GITS_BASER_TYPE_VCPU] = "Virtual CPUs", 831 [GITS_BASER_TYPE_RESERVED3] = "Reserved (3)", 832 [GITS_BASER_TYPE_COLLECTION] = "Interrupt Collections", 833 [GITS_BASER_TYPE_RESERVED5] = "Reserved (5)", 834 [GITS_BASER_TYPE_RESERVED6] = "Reserved (6)", 835 [GITS_BASER_TYPE_RESERVED7] = "Reserved (7)", 836 }; 837 838 static u64 its_read_baser(struct its_node *its, struct its_baser *baser) 839 { 840 u32 idx = baser - its->tables; 841 842 return gits_read_baser(its->base + GITS_BASER + (idx << 3)); 843 } 844 845 static void its_write_baser(struct its_node *its, struct its_baser *baser, 846 u64 val) 847 { 848 u32 idx = baser - its->tables; 849 850 gits_write_baser(val, its->base + GITS_BASER + (idx << 3)); 851 baser->val = its_read_baser(its, baser); 852 } 853 854 static int its_setup_baser(struct its_node *its, struct its_baser *baser, 855 u64 cache, u64 shr, u32 psz, u32 order, 856 bool indirect) 857 { 858 u64 val = its_read_baser(its, baser); 859 u64 esz = GITS_BASER_ENTRY_SIZE(val); 860 u64 type = GITS_BASER_TYPE(val); 861 u32 alloc_pages; 862 void *base; 863 u64 tmp; 864 865 retry_alloc_baser: 866 alloc_pages = (PAGE_ORDER_TO_SIZE(order) / psz); 867 if (alloc_pages > GITS_BASER_PAGES_MAX) { 868 pr_warn("ITS@%pa: %s too large, reduce ITS pages %u->%u\n", 869 &its->phys_base, its_base_type_string[type], 870 alloc_pages, GITS_BASER_PAGES_MAX); 871 alloc_pages = GITS_BASER_PAGES_MAX; 872 order = get_order(GITS_BASER_PAGES_MAX * psz); 873 } 874 875 base = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, order); 876 if (!base) 877 return -ENOMEM; 878 879 retry_baser: 880 val = (virt_to_phys(base) | 881 (type << GITS_BASER_TYPE_SHIFT) | 882 ((esz - 1) << GITS_BASER_ENTRY_SIZE_SHIFT) | 883 ((alloc_pages - 1) << GITS_BASER_PAGES_SHIFT) | 884 cache | 885 shr | 886 GITS_BASER_VALID); 887 888 val |= indirect ? GITS_BASER_INDIRECT : 0x0; 889 890 switch (psz) { 891 case SZ_4K: 892 val |= GITS_BASER_PAGE_SIZE_4K; 893 break; 894 case SZ_16K: 895 val |= GITS_BASER_PAGE_SIZE_16K; 896 break; 897 case SZ_64K: 898 val |= GITS_BASER_PAGE_SIZE_64K; 899 break; 900 } 901 902 its_write_baser(its, baser, val); 903 tmp = baser->val; 904 905 if ((val ^ tmp) & GITS_BASER_SHAREABILITY_MASK) { 906 /* 907 * Shareability didn't stick. Just use 908 * whatever the read reported, which is likely 909 * to be the only thing this redistributor 910 * supports. If that's zero, make it 911 * non-cacheable as well. 912 */ 913 shr = tmp & GITS_BASER_SHAREABILITY_MASK; 914 if (!shr) { 915 cache = GITS_BASER_nC; 916 gic_flush_dcache_to_poc(base, PAGE_ORDER_TO_SIZE(order)); 917 } 918 goto retry_baser; 919 } 920 921 if ((val ^ tmp) & GITS_BASER_PAGE_SIZE_MASK) { 922 /* 923 * Page size didn't stick. Let's try a smaller 924 * size and retry. If we reach 4K, then 925 * something is horribly wrong... 926 */ 927 free_pages((unsigned long)base, order); 928 baser->base = NULL; 929 930 switch (psz) { 931 case SZ_16K: 932 psz = SZ_4K; 933 goto retry_alloc_baser; 934 case SZ_64K: 935 psz = SZ_16K; 936 goto retry_alloc_baser; 937 } 938 } 939 940 if (val != tmp) { 941 pr_err("ITS@%pa: %s doesn't stick: %llx %llx\n", 942 &its->phys_base, its_base_type_string[type], 943 val, tmp); 944 free_pages((unsigned long)base, order); 945 return -ENXIO; 946 } 947 948 baser->order = order; 949 baser->base = base; 950 baser->psz = psz; 951 tmp = indirect ? GITS_LVL1_ENTRY_SIZE : esz; 952 953 pr_info("ITS@%pa: allocated %d %s @%lx (%s, esz %d, psz %dK, shr %d)\n", 954 &its->phys_base, (int)(PAGE_ORDER_TO_SIZE(order) / (int)tmp), 955 its_base_type_string[type], 956 (unsigned long)virt_to_phys(base), 957 indirect ? "indirect" : "flat", (int)esz, 958 psz / SZ_1K, (int)shr >> GITS_BASER_SHAREABILITY_SHIFT); 959 960 return 0; 961 } 962 963 static bool its_parse_baser_device(struct its_node *its, struct its_baser *baser, 964 u32 psz, u32 *order) 965 { 966 u64 esz = GITS_BASER_ENTRY_SIZE(its_read_baser(its, baser)); 967 u64 val = GITS_BASER_InnerShareable | GITS_BASER_RaWaWb; 968 u32 ids = its->device_ids; 969 u32 new_order = *order; 970 bool indirect = false; 971 972 /* No need to enable Indirection if memory requirement < (psz*2)bytes */ 973 if ((esz << ids) > (psz * 2)) { 974 /* 975 * Find out whether hw supports a single or two-level table by 976 * table by reading bit at offset '62' after writing '1' to it. 977 */ 978 its_write_baser(its, baser, val | GITS_BASER_INDIRECT); 979 indirect = !!(baser->val & GITS_BASER_INDIRECT); 980 981 if (indirect) { 982 /* 983 * The size of the lvl2 table is equal to ITS page size 984 * which is 'psz'. For computing lvl1 table size, 985 * subtract ID bits that sparse lvl2 table from 'ids' 986 * which is reported by ITS hardware times lvl1 table 987 * entry size. 988 */ 989 ids -= ilog2(psz / (int)esz); 990 esz = GITS_LVL1_ENTRY_SIZE; 991 } 992 } 993 994 /* 995 * Allocate as many entries as required to fit the 996 * range of device IDs that the ITS can grok... The ID 997 * space being incredibly sparse, this results in a 998 * massive waste of memory if two-level device table 999 * feature is not supported by hardware. 1000 */ 1001 new_order = max_t(u32, get_order(esz << ids), new_order); 1002 if (new_order >= MAX_ORDER) { 1003 new_order = MAX_ORDER - 1; 1004 ids = ilog2(PAGE_ORDER_TO_SIZE(new_order) / (int)esz); 1005 pr_warn("ITS@%pa: Device Table too large, reduce ids %u->%u\n", 1006 &its->phys_base, its->device_ids, ids); 1007 } 1008 1009 *order = new_order; 1010 1011 return indirect; 1012 } 1013 1014 static void its_free_tables(struct its_node *its) 1015 { 1016 int i; 1017 1018 for (i = 0; i < GITS_BASER_NR_REGS; i++) { 1019 if (its->tables[i].base) { 1020 free_pages((unsigned long)its->tables[i].base, 1021 its->tables[i].order); 1022 its->tables[i].base = NULL; 1023 } 1024 } 1025 } 1026 1027 static int its_alloc_tables(struct its_node *its) 1028 { 1029 u64 typer = gic_read_typer(its->base + GITS_TYPER); 1030 u32 ids = GITS_TYPER_DEVBITS(typer); 1031 u64 shr = GITS_BASER_InnerShareable; 1032 u64 cache = GITS_BASER_RaWaWb; 1033 u32 psz = SZ_64K; 1034 int err, i; 1035 1036 if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_22375) { 1037 /* 1038 * erratum 22375: only alloc 8MB table size 1039 * erratum 24313: ignore memory access type 1040 */ 1041 cache = GITS_BASER_nCnB; 1042 ids = 0x14; /* 20 bits, 8MB */ 1043 } 1044 1045 its->device_ids = ids; 1046 1047 for (i = 0; i < GITS_BASER_NR_REGS; i++) { 1048 struct its_baser *baser = its->tables + i; 1049 u64 val = its_read_baser(its, baser); 1050 u64 type = GITS_BASER_TYPE(val); 1051 u32 order = get_order(psz); 1052 bool indirect = false; 1053 1054 if (type == GITS_BASER_TYPE_NONE) 1055 continue; 1056 1057 if (type == GITS_BASER_TYPE_DEVICE) 1058 indirect = its_parse_baser_device(its, baser, psz, &order); 1059 1060 err = its_setup_baser(its, baser, cache, shr, psz, order, indirect); 1061 if (err < 0) { 1062 its_free_tables(its); 1063 return err; 1064 } 1065 1066 /* Update settings which will be used for next BASERn */ 1067 psz = baser->psz; 1068 cache = baser->val & GITS_BASER_CACHEABILITY_MASK; 1069 shr = baser->val & GITS_BASER_SHAREABILITY_MASK; 1070 } 1071 1072 return 0; 1073 } 1074 1075 static int its_alloc_collections(struct its_node *its) 1076 { 1077 its->collections = kzalloc(nr_cpu_ids * sizeof(*its->collections), 1078 GFP_KERNEL); 1079 if (!its->collections) 1080 return -ENOMEM; 1081 1082 return 0; 1083 } 1084 1085 static void its_cpu_init_lpis(void) 1086 { 1087 void __iomem *rbase = gic_data_rdist_rd_base(); 1088 struct page *pend_page; 1089 u64 val, tmp; 1090 1091 /* If we didn't allocate the pending table yet, do it now */ 1092 pend_page = gic_data_rdist()->pend_page; 1093 if (!pend_page) { 1094 phys_addr_t paddr; 1095 /* 1096 * The pending pages have to be at least 64kB aligned, 1097 * hence the 'max(LPI_PENDBASE_SZ, SZ_64K)' below. 1098 */ 1099 pend_page = alloc_pages(GFP_NOWAIT | __GFP_ZERO, 1100 get_order(max(LPI_PENDBASE_SZ, SZ_64K))); 1101 if (!pend_page) { 1102 pr_err("Failed to allocate PENDBASE for CPU%d\n", 1103 smp_processor_id()); 1104 return; 1105 } 1106 1107 /* Make sure the GIC will observe the zero-ed page */ 1108 gic_flush_dcache_to_poc(page_address(pend_page), LPI_PENDBASE_SZ); 1109 1110 paddr = page_to_phys(pend_page); 1111 pr_info("CPU%d: using LPI pending table @%pa\n", 1112 smp_processor_id(), &paddr); 1113 gic_data_rdist()->pend_page = pend_page; 1114 } 1115 1116 /* Disable LPIs */ 1117 val = readl_relaxed(rbase + GICR_CTLR); 1118 val &= ~GICR_CTLR_ENABLE_LPIS; 1119 writel_relaxed(val, rbase + GICR_CTLR); 1120 1121 /* 1122 * Make sure any change to the table is observable by the GIC. 1123 */ 1124 dsb(sy); 1125 1126 /* set PROPBASE */ 1127 val = (page_to_phys(gic_rdists->prop_page) | 1128 GICR_PROPBASER_InnerShareable | 1129 GICR_PROPBASER_RaWaWb | 1130 ((LPI_NRBITS - 1) & GICR_PROPBASER_IDBITS_MASK)); 1131 1132 gicr_write_propbaser(val, rbase + GICR_PROPBASER); 1133 tmp = gicr_read_propbaser(rbase + GICR_PROPBASER); 1134 1135 if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) { 1136 if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) { 1137 /* 1138 * The HW reports non-shareable, we must 1139 * remove the cacheability attributes as 1140 * well. 1141 */ 1142 val &= ~(GICR_PROPBASER_SHAREABILITY_MASK | 1143 GICR_PROPBASER_CACHEABILITY_MASK); 1144 val |= GICR_PROPBASER_nC; 1145 gicr_write_propbaser(val, rbase + GICR_PROPBASER); 1146 } 1147 pr_info_once("GIC: using cache flushing for LPI property table\n"); 1148 gic_rdists->flags |= RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING; 1149 } 1150 1151 /* set PENDBASE */ 1152 val = (page_to_phys(pend_page) | 1153 GICR_PENDBASER_InnerShareable | 1154 GICR_PENDBASER_RaWaWb); 1155 1156 gicr_write_pendbaser(val, rbase + GICR_PENDBASER); 1157 tmp = gicr_read_pendbaser(rbase + GICR_PENDBASER); 1158 1159 if (!(tmp & GICR_PENDBASER_SHAREABILITY_MASK)) { 1160 /* 1161 * The HW reports non-shareable, we must remove the 1162 * cacheability attributes as well. 1163 */ 1164 val &= ~(GICR_PENDBASER_SHAREABILITY_MASK | 1165 GICR_PENDBASER_CACHEABILITY_MASK); 1166 val |= GICR_PENDBASER_nC; 1167 gicr_write_pendbaser(val, rbase + GICR_PENDBASER); 1168 } 1169 1170 /* Enable LPIs */ 1171 val = readl_relaxed(rbase + GICR_CTLR); 1172 val |= GICR_CTLR_ENABLE_LPIS; 1173 writel_relaxed(val, rbase + GICR_CTLR); 1174 1175 /* Make sure the GIC has seen the above */ 1176 dsb(sy); 1177 } 1178 1179 static void its_cpu_init_collection(void) 1180 { 1181 struct its_node *its; 1182 int cpu; 1183 1184 spin_lock(&its_lock); 1185 cpu = smp_processor_id(); 1186 1187 list_for_each_entry(its, &its_nodes, entry) { 1188 u64 target; 1189 1190 /* avoid cross node collections and its mapping */ 1191 if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) { 1192 struct device_node *cpu_node; 1193 1194 cpu_node = of_get_cpu_node(cpu, NULL); 1195 if (its->numa_node != NUMA_NO_NODE && 1196 its->numa_node != of_node_to_nid(cpu_node)) 1197 continue; 1198 } 1199 1200 /* 1201 * We now have to bind each collection to its target 1202 * redistributor. 1203 */ 1204 if (gic_read_typer(its->base + GITS_TYPER) & GITS_TYPER_PTA) { 1205 /* 1206 * This ITS wants the physical address of the 1207 * redistributor. 1208 */ 1209 target = gic_data_rdist()->phys_base; 1210 } else { 1211 /* 1212 * This ITS wants a linear CPU number. 1213 */ 1214 target = gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER); 1215 target = GICR_TYPER_CPU_NUMBER(target) << 16; 1216 } 1217 1218 /* Perform collection mapping */ 1219 its->collections[cpu].target_address = target; 1220 its->collections[cpu].col_id = cpu; 1221 1222 its_send_mapc(its, &its->collections[cpu], 1); 1223 its_send_invall(its, &its->collections[cpu]); 1224 } 1225 1226 spin_unlock(&its_lock); 1227 } 1228 1229 static struct its_device *its_find_device(struct its_node *its, u32 dev_id) 1230 { 1231 struct its_device *its_dev = NULL, *tmp; 1232 unsigned long flags; 1233 1234 raw_spin_lock_irqsave(&its->lock, flags); 1235 1236 list_for_each_entry(tmp, &its->its_device_list, entry) { 1237 if (tmp->device_id == dev_id) { 1238 its_dev = tmp; 1239 break; 1240 } 1241 } 1242 1243 raw_spin_unlock_irqrestore(&its->lock, flags); 1244 1245 return its_dev; 1246 } 1247 1248 static struct its_baser *its_get_baser(struct its_node *its, u32 type) 1249 { 1250 int i; 1251 1252 for (i = 0; i < GITS_BASER_NR_REGS; i++) { 1253 if (GITS_BASER_TYPE(its->tables[i].val) == type) 1254 return &its->tables[i]; 1255 } 1256 1257 return NULL; 1258 } 1259 1260 static bool its_alloc_device_table(struct its_node *its, u32 dev_id) 1261 { 1262 struct its_baser *baser; 1263 struct page *page; 1264 u32 esz, idx; 1265 __le64 *table; 1266 1267 baser = its_get_baser(its, GITS_BASER_TYPE_DEVICE); 1268 1269 /* Don't allow device id that exceeds ITS hardware limit */ 1270 if (!baser) 1271 return (ilog2(dev_id) < its->device_ids); 1272 1273 /* Don't allow device id that exceeds single, flat table limit */ 1274 esz = GITS_BASER_ENTRY_SIZE(baser->val); 1275 if (!(baser->val & GITS_BASER_INDIRECT)) 1276 return (dev_id < (PAGE_ORDER_TO_SIZE(baser->order) / esz)); 1277 1278 /* Compute 1st level table index & check if that exceeds table limit */ 1279 idx = dev_id >> ilog2(baser->psz / esz); 1280 if (idx >= (PAGE_ORDER_TO_SIZE(baser->order) / GITS_LVL1_ENTRY_SIZE)) 1281 return false; 1282 1283 table = baser->base; 1284 1285 /* Allocate memory for 2nd level table */ 1286 if (!table[idx]) { 1287 page = alloc_pages(GFP_KERNEL | __GFP_ZERO, get_order(baser->psz)); 1288 if (!page) 1289 return false; 1290 1291 /* Flush Lvl2 table to PoC if hw doesn't support coherency */ 1292 if (!(baser->val & GITS_BASER_SHAREABILITY_MASK)) 1293 gic_flush_dcache_to_poc(page_address(page), baser->psz); 1294 1295 table[idx] = cpu_to_le64(page_to_phys(page) | GITS_BASER_VALID); 1296 1297 /* Flush Lvl1 entry to PoC if hw doesn't support coherency */ 1298 if (!(baser->val & GITS_BASER_SHAREABILITY_MASK)) 1299 gic_flush_dcache_to_poc(table + idx, GITS_LVL1_ENTRY_SIZE); 1300 1301 /* Ensure updated table contents are visible to ITS hardware */ 1302 dsb(sy); 1303 } 1304 1305 return true; 1306 } 1307 1308 static struct its_device *its_create_device(struct its_node *its, u32 dev_id, 1309 int nvecs) 1310 { 1311 struct its_device *dev; 1312 unsigned long *lpi_map; 1313 unsigned long flags; 1314 u16 *col_map = NULL; 1315 void *itt; 1316 int lpi_base; 1317 int nr_lpis; 1318 int nr_ites; 1319 int sz; 1320 1321 if (!its_alloc_device_table(its, dev_id)) 1322 return NULL; 1323 1324 dev = kzalloc(sizeof(*dev), GFP_KERNEL); 1325 /* 1326 * At least one bit of EventID is being used, hence a minimum 1327 * of two entries. No, the architecture doesn't let you 1328 * express an ITT with a single entry. 1329 */ 1330 nr_ites = max(2UL, roundup_pow_of_two(nvecs)); 1331 sz = nr_ites * its->ite_size; 1332 sz = max(sz, ITS_ITT_ALIGN) + ITS_ITT_ALIGN - 1; 1333 itt = kzalloc(sz, GFP_KERNEL); 1334 lpi_map = its_lpi_alloc_chunks(nvecs, &lpi_base, &nr_lpis); 1335 if (lpi_map) 1336 col_map = kzalloc(sizeof(*col_map) * nr_lpis, GFP_KERNEL); 1337 1338 if (!dev || !itt || !lpi_map || !col_map) { 1339 kfree(dev); 1340 kfree(itt); 1341 kfree(lpi_map); 1342 kfree(col_map); 1343 return NULL; 1344 } 1345 1346 gic_flush_dcache_to_poc(itt, sz); 1347 1348 dev->its = its; 1349 dev->itt = itt; 1350 dev->nr_ites = nr_ites; 1351 dev->event_map.lpi_map = lpi_map; 1352 dev->event_map.col_map = col_map; 1353 dev->event_map.lpi_base = lpi_base; 1354 dev->event_map.nr_lpis = nr_lpis; 1355 dev->device_id = dev_id; 1356 INIT_LIST_HEAD(&dev->entry); 1357 1358 raw_spin_lock_irqsave(&its->lock, flags); 1359 list_add(&dev->entry, &its->its_device_list); 1360 raw_spin_unlock_irqrestore(&its->lock, flags); 1361 1362 /* Map device to its ITT */ 1363 its_send_mapd(dev, 1); 1364 1365 return dev; 1366 } 1367 1368 static void its_free_device(struct its_device *its_dev) 1369 { 1370 unsigned long flags; 1371 1372 raw_spin_lock_irqsave(&its_dev->its->lock, flags); 1373 list_del(&its_dev->entry); 1374 raw_spin_unlock_irqrestore(&its_dev->its->lock, flags); 1375 kfree(its_dev->itt); 1376 kfree(its_dev); 1377 } 1378 1379 static int its_alloc_device_irq(struct its_device *dev, irq_hw_number_t *hwirq) 1380 { 1381 int idx; 1382 1383 idx = find_first_zero_bit(dev->event_map.lpi_map, 1384 dev->event_map.nr_lpis); 1385 if (idx == dev->event_map.nr_lpis) 1386 return -ENOSPC; 1387 1388 *hwirq = dev->event_map.lpi_base + idx; 1389 set_bit(idx, dev->event_map.lpi_map); 1390 1391 return 0; 1392 } 1393 1394 static int its_msi_prepare(struct irq_domain *domain, struct device *dev, 1395 int nvec, msi_alloc_info_t *info) 1396 { 1397 struct its_node *its; 1398 struct its_device *its_dev; 1399 struct msi_domain_info *msi_info; 1400 u32 dev_id; 1401 1402 /* 1403 * We ignore "dev" entierely, and rely on the dev_id that has 1404 * been passed via the scratchpad. This limits this domain's 1405 * usefulness to upper layers that definitely know that they 1406 * are built on top of the ITS. 1407 */ 1408 dev_id = info->scratchpad[0].ul; 1409 1410 msi_info = msi_get_domain_info(domain); 1411 its = msi_info->data; 1412 1413 its_dev = its_find_device(its, dev_id); 1414 if (its_dev) { 1415 /* 1416 * We already have seen this ID, probably through 1417 * another alias (PCI bridge of some sort). No need to 1418 * create the device. 1419 */ 1420 pr_debug("Reusing ITT for devID %x\n", dev_id); 1421 goto out; 1422 } 1423 1424 its_dev = its_create_device(its, dev_id, nvec); 1425 if (!its_dev) 1426 return -ENOMEM; 1427 1428 pr_debug("ITT %d entries, %d bits\n", nvec, ilog2(nvec)); 1429 out: 1430 info->scratchpad[0].ptr = its_dev; 1431 return 0; 1432 } 1433 1434 static struct msi_domain_ops its_msi_domain_ops = { 1435 .msi_prepare = its_msi_prepare, 1436 }; 1437 1438 static int its_irq_gic_domain_alloc(struct irq_domain *domain, 1439 unsigned int virq, 1440 irq_hw_number_t hwirq) 1441 { 1442 struct irq_fwspec fwspec; 1443 1444 if (irq_domain_get_of_node(domain->parent)) { 1445 fwspec.fwnode = domain->parent->fwnode; 1446 fwspec.param_count = 3; 1447 fwspec.param[0] = GIC_IRQ_TYPE_LPI; 1448 fwspec.param[1] = hwirq; 1449 fwspec.param[2] = IRQ_TYPE_EDGE_RISING; 1450 } else if (is_fwnode_irqchip(domain->parent->fwnode)) { 1451 fwspec.fwnode = domain->parent->fwnode; 1452 fwspec.param_count = 2; 1453 fwspec.param[0] = hwirq; 1454 fwspec.param[1] = IRQ_TYPE_EDGE_RISING; 1455 } else { 1456 return -EINVAL; 1457 } 1458 1459 return irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec); 1460 } 1461 1462 static int its_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, 1463 unsigned int nr_irqs, void *args) 1464 { 1465 msi_alloc_info_t *info = args; 1466 struct its_device *its_dev = info->scratchpad[0].ptr; 1467 irq_hw_number_t hwirq; 1468 int err; 1469 int i; 1470 1471 for (i = 0; i < nr_irqs; i++) { 1472 err = its_alloc_device_irq(its_dev, &hwirq); 1473 if (err) 1474 return err; 1475 1476 err = its_irq_gic_domain_alloc(domain, virq + i, hwirq); 1477 if (err) 1478 return err; 1479 1480 irq_domain_set_hwirq_and_chip(domain, virq + i, 1481 hwirq, &its_irq_chip, its_dev); 1482 pr_debug("ID:%d pID:%d vID:%d\n", 1483 (int)(hwirq - its_dev->event_map.lpi_base), 1484 (int) hwirq, virq + i); 1485 } 1486 1487 return 0; 1488 } 1489 1490 static void its_irq_domain_activate(struct irq_domain *domain, 1491 struct irq_data *d) 1492 { 1493 struct its_device *its_dev = irq_data_get_irq_chip_data(d); 1494 u32 event = its_get_event_id(d); 1495 const struct cpumask *cpu_mask = cpu_online_mask; 1496 1497 /* get the cpu_mask of local node */ 1498 if (its_dev->its->numa_node >= 0) 1499 cpu_mask = cpumask_of_node(its_dev->its->numa_node); 1500 1501 /* Bind the LPI to the first possible CPU */ 1502 its_dev->event_map.col_map[event] = cpumask_first(cpu_mask); 1503 1504 /* Map the GIC IRQ and event to the device */ 1505 its_send_mapti(its_dev, d->hwirq, event); 1506 } 1507 1508 static void its_irq_domain_deactivate(struct irq_domain *domain, 1509 struct irq_data *d) 1510 { 1511 struct its_device *its_dev = irq_data_get_irq_chip_data(d); 1512 u32 event = its_get_event_id(d); 1513 1514 /* Stop the delivery of interrupts */ 1515 its_send_discard(its_dev, event); 1516 } 1517 1518 static void its_irq_domain_free(struct irq_domain *domain, unsigned int virq, 1519 unsigned int nr_irqs) 1520 { 1521 struct irq_data *d = irq_domain_get_irq_data(domain, virq); 1522 struct its_device *its_dev = irq_data_get_irq_chip_data(d); 1523 int i; 1524 1525 for (i = 0; i < nr_irqs; i++) { 1526 struct irq_data *data = irq_domain_get_irq_data(domain, 1527 virq + i); 1528 u32 event = its_get_event_id(data); 1529 1530 /* Mark interrupt index as unused */ 1531 clear_bit(event, its_dev->event_map.lpi_map); 1532 1533 /* Nuke the entry in the domain */ 1534 irq_domain_reset_irq_data(data); 1535 } 1536 1537 /* If all interrupts have been freed, start mopping the floor */ 1538 if (bitmap_empty(its_dev->event_map.lpi_map, 1539 its_dev->event_map.nr_lpis)) { 1540 its_lpi_free(&its_dev->event_map); 1541 1542 /* Unmap device/itt */ 1543 its_send_mapd(its_dev, 0); 1544 its_free_device(its_dev); 1545 } 1546 1547 irq_domain_free_irqs_parent(domain, virq, nr_irqs); 1548 } 1549 1550 static const struct irq_domain_ops its_domain_ops = { 1551 .alloc = its_irq_domain_alloc, 1552 .free = its_irq_domain_free, 1553 .activate = its_irq_domain_activate, 1554 .deactivate = its_irq_domain_deactivate, 1555 }; 1556 1557 static int its_force_quiescent(void __iomem *base) 1558 { 1559 u32 count = 1000000; /* 1s */ 1560 u32 val; 1561 1562 val = readl_relaxed(base + GITS_CTLR); 1563 /* 1564 * GIC architecture specification requires the ITS to be both 1565 * disabled and quiescent for writes to GITS_BASER<n> or 1566 * GITS_CBASER to not have UNPREDICTABLE results. 1567 */ 1568 if ((val & GITS_CTLR_QUIESCENT) && !(val & GITS_CTLR_ENABLE)) 1569 return 0; 1570 1571 /* Disable the generation of all interrupts to this ITS */ 1572 val &= ~GITS_CTLR_ENABLE; 1573 writel_relaxed(val, base + GITS_CTLR); 1574 1575 /* Poll GITS_CTLR and wait until ITS becomes quiescent */ 1576 while (1) { 1577 val = readl_relaxed(base + GITS_CTLR); 1578 if (val & GITS_CTLR_QUIESCENT) 1579 return 0; 1580 1581 count--; 1582 if (!count) 1583 return -EBUSY; 1584 1585 cpu_relax(); 1586 udelay(1); 1587 } 1588 } 1589 1590 static void __maybe_unused its_enable_quirk_cavium_22375(void *data) 1591 { 1592 struct its_node *its = data; 1593 1594 its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_22375; 1595 } 1596 1597 static void __maybe_unused its_enable_quirk_cavium_23144(void *data) 1598 { 1599 struct its_node *its = data; 1600 1601 its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_23144; 1602 } 1603 1604 static void __maybe_unused its_enable_quirk_qdf2400_e0065(void *data) 1605 { 1606 struct its_node *its = data; 1607 1608 /* On QDF2400, the size of the ITE is 16Bytes */ 1609 its->ite_size = 16; 1610 } 1611 1612 static const struct gic_quirk its_quirks[] = { 1613 #ifdef CONFIG_CAVIUM_ERRATUM_22375 1614 { 1615 .desc = "ITS: Cavium errata 22375, 24313", 1616 .iidr = 0xa100034c, /* ThunderX pass 1.x */ 1617 .mask = 0xffff0fff, 1618 .init = its_enable_quirk_cavium_22375, 1619 }, 1620 #endif 1621 #ifdef CONFIG_CAVIUM_ERRATUM_23144 1622 { 1623 .desc = "ITS: Cavium erratum 23144", 1624 .iidr = 0xa100034c, /* ThunderX pass 1.x */ 1625 .mask = 0xffff0fff, 1626 .init = its_enable_quirk_cavium_23144, 1627 }, 1628 #endif 1629 #ifdef CONFIG_QCOM_QDF2400_ERRATUM_0065 1630 { 1631 .desc = "ITS: QDF2400 erratum 0065", 1632 .iidr = 0x00001070, /* QDF2400 ITS rev 1.x */ 1633 .mask = 0xffffffff, 1634 .init = its_enable_quirk_qdf2400_e0065, 1635 }, 1636 #endif 1637 { 1638 } 1639 }; 1640 1641 static void its_enable_quirks(struct its_node *its) 1642 { 1643 u32 iidr = readl_relaxed(its->base + GITS_IIDR); 1644 1645 gic_enable_quirks(iidr, its_quirks, its); 1646 } 1647 1648 static int its_init_domain(struct fwnode_handle *handle, struct its_node *its) 1649 { 1650 struct irq_domain *inner_domain; 1651 struct msi_domain_info *info; 1652 1653 info = kzalloc(sizeof(*info), GFP_KERNEL); 1654 if (!info) 1655 return -ENOMEM; 1656 1657 inner_domain = irq_domain_create_tree(handle, &its_domain_ops, its); 1658 if (!inner_domain) { 1659 kfree(info); 1660 return -ENOMEM; 1661 } 1662 1663 inner_domain->parent = its_parent; 1664 inner_domain->bus_token = DOMAIN_BUS_NEXUS; 1665 inner_domain->flags |= IRQ_DOMAIN_FLAG_MSI_REMAP; 1666 info->ops = &its_msi_domain_ops; 1667 info->data = its; 1668 inner_domain->host_data = info; 1669 1670 return 0; 1671 } 1672 1673 static int __init its_probe_one(struct resource *res, 1674 struct fwnode_handle *handle, int numa_node) 1675 { 1676 struct its_node *its; 1677 void __iomem *its_base; 1678 u32 val; 1679 u64 baser, tmp; 1680 int err; 1681 1682 its_base = ioremap(res->start, resource_size(res)); 1683 if (!its_base) { 1684 pr_warn("ITS@%pa: Unable to map ITS registers\n", &res->start); 1685 return -ENOMEM; 1686 } 1687 1688 val = readl_relaxed(its_base + GITS_PIDR2) & GIC_PIDR2_ARCH_MASK; 1689 if (val != 0x30 && val != 0x40) { 1690 pr_warn("ITS@%pa: No ITS detected, giving up\n", &res->start); 1691 err = -ENODEV; 1692 goto out_unmap; 1693 } 1694 1695 err = its_force_quiescent(its_base); 1696 if (err) { 1697 pr_warn("ITS@%pa: Failed to quiesce, giving up\n", &res->start); 1698 goto out_unmap; 1699 } 1700 1701 pr_info("ITS %pR\n", res); 1702 1703 its = kzalloc(sizeof(*its), GFP_KERNEL); 1704 if (!its) { 1705 err = -ENOMEM; 1706 goto out_unmap; 1707 } 1708 1709 raw_spin_lock_init(&its->lock); 1710 INIT_LIST_HEAD(&its->entry); 1711 INIT_LIST_HEAD(&its->its_device_list); 1712 its->base = its_base; 1713 its->phys_base = res->start; 1714 its->ite_size = ((gic_read_typer(its_base + GITS_TYPER) >> 4) & 0xf) + 1; 1715 its->numa_node = numa_node; 1716 1717 its->cmd_base = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, 1718 get_order(ITS_CMD_QUEUE_SZ)); 1719 if (!its->cmd_base) { 1720 err = -ENOMEM; 1721 goto out_free_its; 1722 } 1723 its->cmd_write = its->cmd_base; 1724 1725 its_enable_quirks(its); 1726 1727 err = its_alloc_tables(its); 1728 if (err) 1729 goto out_free_cmd; 1730 1731 err = its_alloc_collections(its); 1732 if (err) 1733 goto out_free_tables; 1734 1735 baser = (virt_to_phys(its->cmd_base) | 1736 GITS_CBASER_RaWaWb | 1737 GITS_CBASER_InnerShareable | 1738 (ITS_CMD_QUEUE_SZ / SZ_4K - 1) | 1739 GITS_CBASER_VALID); 1740 1741 gits_write_cbaser(baser, its->base + GITS_CBASER); 1742 tmp = gits_read_cbaser(its->base + GITS_CBASER); 1743 1744 if ((tmp ^ baser) & GITS_CBASER_SHAREABILITY_MASK) { 1745 if (!(tmp & GITS_CBASER_SHAREABILITY_MASK)) { 1746 /* 1747 * The HW reports non-shareable, we must 1748 * remove the cacheability attributes as 1749 * well. 1750 */ 1751 baser &= ~(GITS_CBASER_SHAREABILITY_MASK | 1752 GITS_CBASER_CACHEABILITY_MASK); 1753 baser |= GITS_CBASER_nC; 1754 gits_write_cbaser(baser, its->base + GITS_CBASER); 1755 } 1756 pr_info("ITS: using cache flushing for cmd queue\n"); 1757 its->flags |= ITS_FLAGS_CMDQ_NEEDS_FLUSHING; 1758 } 1759 1760 gits_write_cwriter(0, its->base + GITS_CWRITER); 1761 writel_relaxed(GITS_CTLR_ENABLE, its->base + GITS_CTLR); 1762 1763 err = its_init_domain(handle, its); 1764 if (err) 1765 goto out_free_tables; 1766 1767 spin_lock(&its_lock); 1768 list_add(&its->entry, &its_nodes); 1769 spin_unlock(&its_lock); 1770 1771 return 0; 1772 1773 out_free_tables: 1774 its_free_tables(its); 1775 out_free_cmd: 1776 free_pages((unsigned long)its->cmd_base, get_order(ITS_CMD_QUEUE_SZ)); 1777 out_free_its: 1778 kfree(its); 1779 out_unmap: 1780 iounmap(its_base); 1781 pr_err("ITS@%pa: failed probing (%d)\n", &res->start, err); 1782 return err; 1783 } 1784 1785 static bool gic_rdists_supports_plpis(void) 1786 { 1787 return !!(gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER) & GICR_TYPER_PLPIS); 1788 } 1789 1790 int its_cpu_init(void) 1791 { 1792 if (!list_empty(&its_nodes)) { 1793 if (!gic_rdists_supports_plpis()) { 1794 pr_info("CPU%d: LPIs not supported\n", smp_processor_id()); 1795 return -ENXIO; 1796 } 1797 its_cpu_init_lpis(); 1798 its_cpu_init_collection(); 1799 } 1800 1801 return 0; 1802 } 1803 1804 static struct of_device_id its_device_id[] = { 1805 { .compatible = "arm,gic-v3-its", }, 1806 {}, 1807 }; 1808 1809 static int __init its_of_probe(struct device_node *node) 1810 { 1811 struct device_node *np; 1812 struct resource res; 1813 1814 for (np = of_find_matching_node(node, its_device_id); np; 1815 np = of_find_matching_node(np, its_device_id)) { 1816 if (!of_property_read_bool(np, "msi-controller")) { 1817 pr_warn("%s: no msi-controller property, ITS ignored\n", 1818 np->full_name); 1819 continue; 1820 } 1821 1822 if (of_address_to_resource(np, 0, &res)) { 1823 pr_warn("%s: no regs?\n", np->full_name); 1824 continue; 1825 } 1826 1827 its_probe_one(&res, &np->fwnode, of_node_to_nid(np)); 1828 } 1829 return 0; 1830 } 1831 1832 #ifdef CONFIG_ACPI 1833 1834 #define ACPI_GICV3_ITS_MEM_SIZE (SZ_128K) 1835 1836 static int __init gic_acpi_parse_madt_its(struct acpi_subtable_header *header, 1837 const unsigned long end) 1838 { 1839 struct acpi_madt_generic_translator *its_entry; 1840 struct fwnode_handle *dom_handle; 1841 struct resource res; 1842 int err; 1843 1844 its_entry = (struct acpi_madt_generic_translator *)header; 1845 memset(&res, 0, sizeof(res)); 1846 res.start = its_entry->base_address; 1847 res.end = its_entry->base_address + ACPI_GICV3_ITS_MEM_SIZE - 1; 1848 res.flags = IORESOURCE_MEM; 1849 1850 dom_handle = irq_domain_alloc_fwnode((void *)its_entry->base_address); 1851 if (!dom_handle) { 1852 pr_err("ITS@%pa: Unable to allocate GICv3 ITS domain token\n", 1853 &res.start); 1854 return -ENOMEM; 1855 } 1856 1857 err = iort_register_domain_token(its_entry->translation_id, dom_handle); 1858 if (err) { 1859 pr_err("ITS@%pa: Unable to register GICv3 ITS domain token (ITS ID %d) to IORT\n", 1860 &res.start, its_entry->translation_id); 1861 goto dom_err; 1862 } 1863 1864 err = its_probe_one(&res, dom_handle, NUMA_NO_NODE); 1865 if (!err) 1866 return 0; 1867 1868 iort_deregister_domain_token(its_entry->translation_id); 1869 dom_err: 1870 irq_domain_free_fwnode(dom_handle); 1871 return err; 1872 } 1873 1874 static void __init its_acpi_probe(void) 1875 { 1876 acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_TRANSLATOR, 1877 gic_acpi_parse_madt_its, 0); 1878 } 1879 #else 1880 static void __init its_acpi_probe(void) { } 1881 #endif 1882 1883 int __init its_init(struct fwnode_handle *handle, struct rdists *rdists, 1884 struct irq_domain *parent_domain) 1885 { 1886 struct device_node *of_node; 1887 1888 its_parent = parent_domain; 1889 of_node = to_of_node(handle); 1890 if (of_node) 1891 its_of_probe(of_node); 1892 else 1893 its_acpi_probe(); 1894 1895 if (list_empty(&its_nodes)) { 1896 pr_warn("ITS: No ITS available, not enabling LPIs\n"); 1897 return -ENXIO; 1898 } 1899 1900 gic_rdists = rdists; 1901 its_alloc_lpi_tables(); 1902 its_lpi_init(rdists->id_bits); 1903 1904 return 0; 1905 } 1906