1 /* 2 * Copyright (C) 2013, 2014 ARM Limited, All Rights Reserved. 3 * Author: Marc Zyngier <marc.zyngier@arm.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program. If not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #include <linux/bitmap.h> 19 #include <linux/cpu.h> 20 #include <linux/delay.h> 21 #include <linux/interrupt.h> 22 #include <linux/log2.h> 23 #include <linux/mm.h> 24 #include <linux/msi.h> 25 #include <linux/of.h> 26 #include <linux/of_address.h> 27 #include <linux/of_irq.h> 28 #include <linux/of_pci.h> 29 #include <linux/of_platform.h> 30 #include <linux/percpu.h> 31 #include <linux/slab.h> 32 33 #include <linux/irqchip.h> 34 #include <linux/irqchip/arm-gic-v3.h> 35 36 #include <asm/cacheflush.h> 37 #include <asm/cputype.h> 38 #include <asm/exception.h> 39 40 #define ITS_FLAGS_CMDQ_NEEDS_FLUSHING (1 << 0) 41 42 #define RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING (1 << 0) 43 44 /* 45 * Collection structure - just an ID, and a redistributor address to 46 * ping. We use one per CPU as a bag of interrupts assigned to this 47 * CPU. 48 */ 49 struct its_collection { 50 u64 target_address; 51 u16 col_id; 52 }; 53 54 /* 55 * The ITS structure - contains most of the infrastructure, with the 56 * top-level MSI domain, the command queue, the collections, and the 57 * list of devices writing to it. 58 */ 59 struct its_node { 60 raw_spinlock_t lock; 61 struct list_head entry; 62 void __iomem *base; 63 unsigned long phys_base; 64 struct its_cmd_block *cmd_base; 65 struct its_cmd_block *cmd_write; 66 void *tables[GITS_BASER_NR_REGS]; 67 struct its_collection *collections; 68 struct list_head its_device_list; 69 u64 flags; 70 u32 ite_size; 71 }; 72 73 #define ITS_ITT_ALIGN SZ_256 74 75 struct event_lpi_map { 76 unsigned long *lpi_map; 77 u16 *col_map; 78 irq_hw_number_t lpi_base; 79 int nr_lpis; 80 }; 81 82 /* 83 * The ITS view of a device - belongs to an ITS, a collection, owns an 84 * interrupt translation table, and a list of interrupts. 85 */ 86 struct its_device { 87 struct list_head entry; 88 struct its_node *its; 89 struct event_lpi_map event_map; 90 void *itt; 91 u32 nr_ites; 92 u32 device_id; 93 }; 94 95 static LIST_HEAD(its_nodes); 96 static DEFINE_SPINLOCK(its_lock); 97 static struct device_node *gic_root_node; 98 static struct rdists *gic_rdists; 99 100 #define gic_data_rdist() (raw_cpu_ptr(gic_rdists->rdist)) 101 #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base) 102 103 static struct its_collection *dev_event_to_col(struct its_device *its_dev, 104 u32 event) 105 { 106 struct its_node *its = its_dev->its; 107 108 return its->collections + its_dev->event_map.col_map[event]; 109 } 110 111 /* 112 * ITS command descriptors - parameters to be encoded in a command 113 * block. 114 */ 115 struct its_cmd_desc { 116 union { 117 struct { 118 struct its_device *dev; 119 u32 event_id; 120 } its_inv_cmd; 121 122 struct { 123 struct its_device *dev; 124 u32 event_id; 125 } its_int_cmd; 126 127 struct { 128 struct its_device *dev; 129 int valid; 130 } its_mapd_cmd; 131 132 struct { 133 struct its_collection *col; 134 int valid; 135 } its_mapc_cmd; 136 137 struct { 138 struct its_device *dev; 139 u32 phys_id; 140 u32 event_id; 141 } its_mapvi_cmd; 142 143 struct { 144 struct its_device *dev; 145 struct its_collection *col; 146 u32 event_id; 147 } its_movi_cmd; 148 149 struct { 150 struct its_device *dev; 151 u32 event_id; 152 } its_discard_cmd; 153 154 struct { 155 struct its_collection *col; 156 } its_invall_cmd; 157 }; 158 }; 159 160 /* 161 * The ITS command block, which is what the ITS actually parses. 162 */ 163 struct its_cmd_block { 164 u64 raw_cmd[4]; 165 }; 166 167 #define ITS_CMD_QUEUE_SZ SZ_64K 168 #define ITS_CMD_QUEUE_NR_ENTRIES (ITS_CMD_QUEUE_SZ / sizeof(struct its_cmd_block)) 169 170 typedef struct its_collection *(*its_cmd_builder_t)(struct its_cmd_block *, 171 struct its_cmd_desc *); 172 173 static void its_encode_cmd(struct its_cmd_block *cmd, u8 cmd_nr) 174 { 175 cmd->raw_cmd[0] &= ~0xffUL; 176 cmd->raw_cmd[0] |= cmd_nr; 177 } 178 179 static void its_encode_devid(struct its_cmd_block *cmd, u32 devid) 180 { 181 cmd->raw_cmd[0] &= BIT_ULL(32) - 1; 182 cmd->raw_cmd[0] |= ((u64)devid) << 32; 183 } 184 185 static void its_encode_event_id(struct its_cmd_block *cmd, u32 id) 186 { 187 cmd->raw_cmd[1] &= ~0xffffffffUL; 188 cmd->raw_cmd[1] |= id; 189 } 190 191 static void its_encode_phys_id(struct its_cmd_block *cmd, u32 phys_id) 192 { 193 cmd->raw_cmd[1] &= 0xffffffffUL; 194 cmd->raw_cmd[1] |= ((u64)phys_id) << 32; 195 } 196 197 static void its_encode_size(struct its_cmd_block *cmd, u8 size) 198 { 199 cmd->raw_cmd[1] &= ~0x1fUL; 200 cmd->raw_cmd[1] |= size & 0x1f; 201 } 202 203 static void its_encode_itt(struct its_cmd_block *cmd, u64 itt_addr) 204 { 205 cmd->raw_cmd[2] &= ~0xffffffffffffUL; 206 cmd->raw_cmd[2] |= itt_addr & 0xffffffffff00UL; 207 } 208 209 static void its_encode_valid(struct its_cmd_block *cmd, int valid) 210 { 211 cmd->raw_cmd[2] &= ~(1UL << 63); 212 cmd->raw_cmd[2] |= ((u64)!!valid) << 63; 213 } 214 215 static void its_encode_target(struct its_cmd_block *cmd, u64 target_addr) 216 { 217 cmd->raw_cmd[2] &= ~(0xffffffffUL << 16); 218 cmd->raw_cmd[2] |= (target_addr & (0xffffffffUL << 16)); 219 } 220 221 static void its_encode_collection(struct its_cmd_block *cmd, u16 col) 222 { 223 cmd->raw_cmd[2] &= ~0xffffUL; 224 cmd->raw_cmd[2] |= col; 225 } 226 227 static inline void its_fixup_cmd(struct its_cmd_block *cmd) 228 { 229 /* Let's fixup BE commands */ 230 cmd->raw_cmd[0] = cpu_to_le64(cmd->raw_cmd[0]); 231 cmd->raw_cmd[1] = cpu_to_le64(cmd->raw_cmd[1]); 232 cmd->raw_cmd[2] = cpu_to_le64(cmd->raw_cmd[2]); 233 cmd->raw_cmd[3] = cpu_to_le64(cmd->raw_cmd[3]); 234 } 235 236 static struct its_collection *its_build_mapd_cmd(struct its_cmd_block *cmd, 237 struct its_cmd_desc *desc) 238 { 239 unsigned long itt_addr; 240 u8 size = ilog2(desc->its_mapd_cmd.dev->nr_ites); 241 242 itt_addr = virt_to_phys(desc->its_mapd_cmd.dev->itt); 243 itt_addr = ALIGN(itt_addr, ITS_ITT_ALIGN); 244 245 its_encode_cmd(cmd, GITS_CMD_MAPD); 246 its_encode_devid(cmd, desc->its_mapd_cmd.dev->device_id); 247 its_encode_size(cmd, size - 1); 248 its_encode_itt(cmd, itt_addr); 249 its_encode_valid(cmd, desc->its_mapd_cmd.valid); 250 251 its_fixup_cmd(cmd); 252 253 return NULL; 254 } 255 256 static struct its_collection *its_build_mapc_cmd(struct its_cmd_block *cmd, 257 struct its_cmd_desc *desc) 258 { 259 its_encode_cmd(cmd, GITS_CMD_MAPC); 260 its_encode_collection(cmd, desc->its_mapc_cmd.col->col_id); 261 its_encode_target(cmd, desc->its_mapc_cmd.col->target_address); 262 its_encode_valid(cmd, desc->its_mapc_cmd.valid); 263 264 its_fixup_cmd(cmd); 265 266 return desc->its_mapc_cmd.col; 267 } 268 269 static struct its_collection *its_build_mapvi_cmd(struct its_cmd_block *cmd, 270 struct its_cmd_desc *desc) 271 { 272 struct its_collection *col; 273 274 col = dev_event_to_col(desc->its_mapvi_cmd.dev, 275 desc->its_mapvi_cmd.event_id); 276 277 its_encode_cmd(cmd, GITS_CMD_MAPVI); 278 its_encode_devid(cmd, desc->its_mapvi_cmd.dev->device_id); 279 its_encode_event_id(cmd, desc->its_mapvi_cmd.event_id); 280 its_encode_phys_id(cmd, desc->its_mapvi_cmd.phys_id); 281 its_encode_collection(cmd, col->col_id); 282 283 its_fixup_cmd(cmd); 284 285 return col; 286 } 287 288 static struct its_collection *its_build_movi_cmd(struct its_cmd_block *cmd, 289 struct its_cmd_desc *desc) 290 { 291 struct its_collection *col; 292 293 col = dev_event_to_col(desc->its_movi_cmd.dev, 294 desc->its_movi_cmd.event_id); 295 296 its_encode_cmd(cmd, GITS_CMD_MOVI); 297 its_encode_devid(cmd, desc->its_movi_cmd.dev->device_id); 298 its_encode_event_id(cmd, desc->its_movi_cmd.event_id); 299 its_encode_collection(cmd, desc->its_movi_cmd.col->col_id); 300 301 its_fixup_cmd(cmd); 302 303 return col; 304 } 305 306 static struct its_collection *its_build_discard_cmd(struct its_cmd_block *cmd, 307 struct its_cmd_desc *desc) 308 { 309 struct its_collection *col; 310 311 col = dev_event_to_col(desc->its_discard_cmd.dev, 312 desc->its_discard_cmd.event_id); 313 314 its_encode_cmd(cmd, GITS_CMD_DISCARD); 315 its_encode_devid(cmd, desc->its_discard_cmd.dev->device_id); 316 its_encode_event_id(cmd, desc->its_discard_cmd.event_id); 317 318 its_fixup_cmd(cmd); 319 320 return col; 321 } 322 323 static struct its_collection *its_build_inv_cmd(struct its_cmd_block *cmd, 324 struct its_cmd_desc *desc) 325 { 326 struct its_collection *col; 327 328 col = dev_event_to_col(desc->its_inv_cmd.dev, 329 desc->its_inv_cmd.event_id); 330 331 its_encode_cmd(cmd, GITS_CMD_INV); 332 its_encode_devid(cmd, desc->its_inv_cmd.dev->device_id); 333 its_encode_event_id(cmd, desc->its_inv_cmd.event_id); 334 335 its_fixup_cmd(cmd); 336 337 return col; 338 } 339 340 static struct its_collection *its_build_invall_cmd(struct its_cmd_block *cmd, 341 struct its_cmd_desc *desc) 342 { 343 its_encode_cmd(cmd, GITS_CMD_INVALL); 344 its_encode_collection(cmd, desc->its_mapc_cmd.col->col_id); 345 346 its_fixup_cmd(cmd); 347 348 return NULL; 349 } 350 351 static u64 its_cmd_ptr_to_offset(struct its_node *its, 352 struct its_cmd_block *ptr) 353 { 354 return (ptr - its->cmd_base) * sizeof(*ptr); 355 } 356 357 static int its_queue_full(struct its_node *its) 358 { 359 int widx; 360 int ridx; 361 362 widx = its->cmd_write - its->cmd_base; 363 ridx = readl_relaxed(its->base + GITS_CREADR) / sizeof(struct its_cmd_block); 364 365 /* This is incredibly unlikely to happen, unless the ITS locks up. */ 366 if (((widx + 1) % ITS_CMD_QUEUE_NR_ENTRIES) == ridx) 367 return 1; 368 369 return 0; 370 } 371 372 static struct its_cmd_block *its_allocate_entry(struct its_node *its) 373 { 374 struct its_cmd_block *cmd; 375 u32 count = 1000000; /* 1s! */ 376 377 while (its_queue_full(its)) { 378 count--; 379 if (!count) { 380 pr_err_ratelimited("ITS queue not draining\n"); 381 return NULL; 382 } 383 cpu_relax(); 384 udelay(1); 385 } 386 387 cmd = its->cmd_write++; 388 389 /* Handle queue wrapping */ 390 if (its->cmd_write == (its->cmd_base + ITS_CMD_QUEUE_NR_ENTRIES)) 391 its->cmd_write = its->cmd_base; 392 393 return cmd; 394 } 395 396 static struct its_cmd_block *its_post_commands(struct its_node *its) 397 { 398 u64 wr = its_cmd_ptr_to_offset(its, its->cmd_write); 399 400 writel_relaxed(wr, its->base + GITS_CWRITER); 401 402 return its->cmd_write; 403 } 404 405 static void its_flush_cmd(struct its_node *its, struct its_cmd_block *cmd) 406 { 407 /* 408 * Make sure the commands written to memory are observable by 409 * the ITS. 410 */ 411 if (its->flags & ITS_FLAGS_CMDQ_NEEDS_FLUSHING) 412 __flush_dcache_area(cmd, sizeof(*cmd)); 413 else 414 dsb(ishst); 415 } 416 417 static void its_wait_for_range_completion(struct its_node *its, 418 struct its_cmd_block *from, 419 struct its_cmd_block *to) 420 { 421 u64 rd_idx, from_idx, to_idx; 422 u32 count = 1000000; /* 1s! */ 423 424 from_idx = its_cmd_ptr_to_offset(its, from); 425 to_idx = its_cmd_ptr_to_offset(its, to); 426 427 while (1) { 428 rd_idx = readl_relaxed(its->base + GITS_CREADR); 429 if (rd_idx >= to_idx || rd_idx < from_idx) 430 break; 431 432 count--; 433 if (!count) { 434 pr_err_ratelimited("ITS queue timeout\n"); 435 return; 436 } 437 cpu_relax(); 438 udelay(1); 439 } 440 } 441 442 static void its_send_single_command(struct its_node *its, 443 its_cmd_builder_t builder, 444 struct its_cmd_desc *desc) 445 { 446 struct its_cmd_block *cmd, *sync_cmd, *next_cmd; 447 struct its_collection *sync_col; 448 unsigned long flags; 449 450 raw_spin_lock_irqsave(&its->lock, flags); 451 452 cmd = its_allocate_entry(its); 453 if (!cmd) { /* We're soooooo screewed... */ 454 pr_err_ratelimited("ITS can't allocate, dropping command\n"); 455 raw_spin_unlock_irqrestore(&its->lock, flags); 456 return; 457 } 458 sync_col = builder(cmd, desc); 459 its_flush_cmd(its, cmd); 460 461 if (sync_col) { 462 sync_cmd = its_allocate_entry(its); 463 if (!sync_cmd) { 464 pr_err_ratelimited("ITS can't SYNC, skipping\n"); 465 goto post; 466 } 467 its_encode_cmd(sync_cmd, GITS_CMD_SYNC); 468 its_encode_target(sync_cmd, sync_col->target_address); 469 its_fixup_cmd(sync_cmd); 470 its_flush_cmd(its, sync_cmd); 471 } 472 473 post: 474 next_cmd = its_post_commands(its); 475 raw_spin_unlock_irqrestore(&its->lock, flags); 476 477 its_wait_for_range_completion(its, cmd, next_cmd); 478 } 479 480 static void its_send_inv(struct its_device *dev, u32 event_id) 481 { 482 struct its_cmd_desc desc; 483 484 desc.its_inv_cmd.dev = dev; 485 desc.its_inv_cmd.event_id = event_id; 486 487 its_send_single_command(dev->its, its_build_inv_cmd, &desc); 488 } 489 490 static void its_send_mapd(struct its_device *dev, int valid) 491 { 492 struct its_cmd_desc desc; 493 494 desc.its_mapd_cmd.dev = dev; 495 desc.its_mapd_cmd.valid = !!valid; 496 497 its_send_single_command(dev->its, its_build_mapd_cmd, &desc); 498 } 499 500 static void its_send_mapc(struct its_node *its, struct its_collection *col, 501 int valid) 502 { 503 struct its_cmd_desc desc; 504 505 desc.its_mapc_cmd.col = col; 506 desc.its_mapc_cmd.valid = !!valid; 507 508 its_send_single_command(its, its_build_mapc_cmd, &desc); 509 } 510 511 static void its_send_mapvi(struct its_device *dev, u32 irq_id, u32 id) 512 { 513 struct its_cmd_desc desc; 514 515 desc.its_mapvi_cmd.dev = dev; 516 desc.its_mapvi_cmd.phys_id = irq_id; 517 desc.its_mapvi_cmd.event_id = id; 518 519 its_send_single_command(dev->its, its_build_mapvi_cmd, &desc); 520 } 521 522 static void its_send_movi(struct its_device *dev, 523 struct its_collection *col, u32 id) 524 { 525 struct its_cmd_desc desc; 526 527 desc.its_movi_cmd.dev = dev; 528 desc.its_movi_cmd.col = col; 529 desc.its_movi_cmd.event_id = id; 530 531 its_send_single_command(dev->its, its_build_movi_cmd, &desc); 532 } 533 534 static void its_send_discard(struct its_device *dev, u32 id) 535 { 536 struct its_cmd_desc desc; 537 538 desc.its_discard_cmd.dev = dev; 539 desc.its_discard_cmd.event_id = id; 540 541 its_send_single_command(dev->its, its_build_discard_cmd, &desc); 542 } 543 544 static void its_send_invall(struct its_node *its, struct its_collection *col) 545 { 546 struct its_cmd_desc desc; 547 548 desc.its_invall_cmd.col = col; 549 550 its_send_single_command(its, its_build_invall_cmd, &desc); 551 } 552 553 /* 554 * irqchip functions - assumes MSI, mostly. 555 */ 556 557 static inline u32 its_get_event_id(struct irq_data *d) 558 { 559 struct its_device *its_dev = irq_data_get_irq_chip_data(d); 560 return d->hwirq - its_dev->event_map.lpi_base; 561 } 562 563 static void lpi_set_config(struct irq_data *d, bool enable) 564 { 565 struct its_device *its_dev = irq_data_get_irq_chip_data(d); 566 irq_hw_number_t hwirq = d->hwirq; 567 u32 id = its_get_event_id(d); 568 u8 *cfg = page_address(gic_rdists->prop_page) + hwirq - 8192; 569 570 if (enable) 571 *cfg |= LPI_PROP_ENABLED; 572 else 573 *cfg &= ~LPI_PROP_ENABLED; 574 575 /* 576 * Make the above write visible to the redistributors. 577 * And yes, we're flushing exactly: One. Single. Byte. 578 * Humpf... 579 */ 580 if (gic_rdists->flags & RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING) 581 __flush_dcache_area(cfg, sizeof(*cfg)); 582 else 583 dsb(ishst); 584 its_send_inv(its_dev, id); 585 } 586 587 static void its_mask_irq(struct irq_data *d) 588 { 589 lpi_set_config(d, false); 590 } 591 592 static void its_unmask_irq(struct irq_data *d) 593 { 594 lpi_set_config(d, true); 595 } 596 597 static void its_eoi_irq(struct irq_data *d) 598 { 599 gic_write_eoir(d->hwirq); 600 } 601 602 static int its_set_affinity(struct irq_data *d, const struct cpumask *mask_val, 603 bool force) 604 { 605 unsigned int cpu = cpumask_any_and(mask_val, cpu_online_mask); 606 struct its_device *its_dev = irq_data_get_irq_chip_data(d); 607 struct its_collection *target_col; 608 u32 id = its_get_event_id(d); 609 610 if (cpu >= nr_cpu_ids) 611 return -EINVAL; 612 613 target_col = &its_dev->its->collections[cpu]; 614 its_send_movi(its_dev, target_col, id); 615 its_dev->event_map.col_map[id] = cpu; 616 617 return IRQ_SET_MASK_OK_DONE; 618 } 619 620 static void its_irq_compose_msi_msg(struct irq_data *d, struct msi_msg *msg) 621 { 622 struct its_device *its_dev = irq_data_get_irq_chip_data(d); 623 struct its_node *its; 624 u64 addr; 625 626 its = its_dev->its; 627 addr = its->phys_base + GITS_TRANSLATER; 628 629 msg->address_lo = addr & ((1UL << 32) - 1); 630 msg->address_hi = addr >> 32; 631 msg->data = its_get_event_id(d); 632 } 633 634 static struct irq_chip its_irq_chip = { 635 .name = "ITS", 636 .irq_mask = its_mask_irq, 637 .irq_unmask = its_unmask_irq, 638 .irq_eoi = its_eoi_irq, 639 .irq_set_affinity = its_set_affinity, 640 .irq_compose_msi_msg = its_irq_compose_msi_msg, 641 }; 642 643 /* 644 * How we allocate LPIs: 645 * 646 * The GIC has id_bits bits for interrupt identifiers. From there, we 647 * must subtract 8192 which are reserved for SGIs/PPIs/SPIs. Then, as 648 * we allocate LPIs by chunks of 32, we can shift the whole thing by 5 649 * bits to the right. 650 * 651 * This gives us (((1UL << id_bits) - 8192) >> 5) possible allocations. 652 */ 653 #define IRQS_PER_CHUNK_SHIFT 5 654 #define IRQS_PER_CHUNK (1 << IRQS_PER_CHUNK_SHIFT) 655 656 static unsigned long *lpi_bitmap; 657 static u32 lpi_chunks; 658 static DEFINE_SPINLOCK(lpi_lock); 659 660 static int its_lpi_to_chunk(int lpi) 661 { 662 return (lpi - 8192) >> IRQS_PER_CHUNK_SHIFT; 663 } 664 665 static int its_chunk_to_lpi(int chunk) 666 { 667 return (chunk << IRQS_PER_CHUNK_SHIFT) + 8192; 668 } 669 670 static int its_lpi_init(u32 id_bits) 671 { 672 lpi_chunks = its_lpi_to_chunk(1UL << id_bits); 673 674 lpi_bitmap = kzalloc(BITS_TO_LONGS(lpi_chunks) * sizeof(long), 675 GFP_KERNEL); 676 if (!lpi_bitmap) { 677 lpi_chunks = 0; 678 return -ENOMEM; 679 } 680 681 pr_info("ITS: Allocated %d chunks for LPIs\n", (int)lpi_chunks); 682 return 0; 683 } 684 685 static unsigned long *its_lpi_alloc_chunks(int nr_irqs, int *base, int *nr_ids) 686 { 687 unsigned long *bitmap = NULL; 688 int chunk_id; 689 int nr_chunks; 690 int i; 691 692 nr_chunks = DIV_ROUND_UP(nr_irqs, IRQS_PER_CHUNK); 693 694 spin_lock(&lpi_lock); 695 696 do { 697 chunk_id = bitmap_find_next_zero_area(lpi_bitmap, lpi_chunks, 698 0, nr_chunks, 0); 699 if (chunk_id < lpi_chunks) 700 break; 701 702 nr_chunks--; 703 } while (nr_chunks > 0); 704 705 if (!nr_chunks) 706 goto out; 707 708 bitmap = kzalloc(BITS_TO_LONGS(nr_chunks * IRQS_PER_CHUNK) * sizeof (long), 709 GFP_ATOMIC); 710 if (!bitmap) 711 goto out; 712 713 for (i = 0; i < nr_chunks; i++) 714 set_bit(chunk_id + i, lpi_bitmap); 715 716 *base = its_chunk_to_lpi(chunk_id); 717 *nr_ids = nr_chunks * IRQS_PER_CHUNK; 718 719 out: 720 spin_unlock(&lpi_lock); 721 722 return bitmap; 723 } 724 725 static void its_lpi_free(struct event_lpi_map *map) 726 { 727 int base = map->lpi_base; 728 int nr_ids = map->nr_lpis; 729 int lpi; 730 731 spin_lock(&lpi_lock); 732 733 for (lpi = base; lpi < (base + nr_ids); lpi += IRQS_PER_CHUNK) { 734 int chunk = its_lpi_to_chunk(lpi); 735 BUG_ON(chunk > lpi_chunks); 736 if (test_bit(chunk, lpi_bitmap)) { 737 clear_bit(chunk, lpi_bitmap); 738 } else { 739 pr_err("Bad LPI chunk %d\n", chunk); 740 } 741 } 742 743 spin_unlock(&lpi_lock); 744 745 kfree(map->lpi_map); 746 kfree(map->col_map); 747 } 748 749 /* 750 * We allocate 64kB for PROPBASE. That gives us at most 64K LPIs to 751 * deal with (one configuration byte per interrupt). PENDBASE has to 752 * be 64kB aligned (one bit per LPI, plus 8192 bits for SPI/PPI/SGI). 753 */ 754 #define LPI_PROPBASE_SZ SZ_64K 755 #define LPI_PENDBASE_SZ (LPI_PROPBASE_SZ / 8 + SZ_1K) 756 757 /* 758 * This is how many bits of ID we need, including the useless ones. 759 */ 760 #define LPI_NRBITS ilog2(LPI_PROPBASE_SZ + SZ_8K) 761 762 #define LPI_PROP_DEFAULT_PRIO 0xa0 763 764 static int __init its_alloc_lpi_tables(void) 765 { 766 phys_addr_t paddr; 767 768 gic_rdists->prop_page = alloc_pages(GFP_NOWAIT, 769 get_order(LPI_PROPBASE_SZ)); 770 if (!gic_rdists->prop_page) { 771 pr_err("Failed to allocate PROPBASE\n"); 772 return -ENOMEM; 773 } 774 775 paddr = page_to_phys(gic_rdists->prop_page); 776 pr_info("GIC: using LPI property table @%pa\n", &paddr); 777 778 /* Priority 0xa0, Group-1, disabled */ 779 memset(page_address(gic_rdists->prop_page), 780 LPI_PROP_DEFAULT_PRIO | LPI_PROP_GROUP1, 781 LPI_PROPBASE_SZ); 782 783 /* Make sure the GIC will observe the written configuration */ 784 __flush_dcache_area(page_address(gic_rdists->prop_page), LPI_PROPBASE_SZ); 785 786 return 0; 787 } 788 789 static const char *its_base_type_string[] = { 790 [GITS_BASER_TYPE_DEVICE] = "Devices", 791 [GITS_BASER_TYPE_VCPU] = "Virtual CPUs", 792 [GITS_BASER_TYPE_CPU] = "Physical CPUs", 793 [GITS_BASER_TYPE_COLLECTION] = "Interrupt Collections", 794 [GITS_BASER_TYPE_RESERVED5] = "Reserved (5)", 795 [GITS_BASER_TYPE_RESERVED6] = "Reserved (6)", 796 [GITS_BASER_TYPE_RESERVED7] = "Reserved (7)", 797 }; 798 799 static void its_free_tables(struct its_node *its) 800 { 801 int i; 802 803 for (i = 0; i < GITS_BASER_NR_REGS; i++) { 804 if (its->tables[i]) { 805 free_page((unsigned long)its->tables[i]); 806 its->tables[i] = NULL; 807 } 808 } 809 } 810 811 static int its_alloc_tables(const char *node_name, struct its_node *its) 812 { 813 int err; 814 int i; 815 int psz = SZ_64K; 816 u64 shr = GITS_BASER_InnerShareable; 817 u64 cache = GITS_BASER_WaWb; 818 819 for (i = 0; i < GITS_BASER_NR_REGS; i++) { 820 u64 val = readq_relaxed(its->base + GITS_BASER + i * 8); 821 u64 type = GITS_BASER_TYPE(val); 822 u64 entry_size = GITS_BASER_ENTRY_SIZE(val); 823 int order = get_order(psz); 824 int alloc_size; 825 u64 tmp; 826 void *base; 827 828 if (type == GITS_BASER_TYPE_NONE) 829 continue; 830 831 /* 832 * Allocate as many entries as required to fit the 833 * range of device IDs that the ITS can grok... The ID 834 * space being incredibly sparse, this results in a 835 * massive waste of memory. 836 * 837 * For other tables, only allocate a single page. 838 */ 839 if (type == GITS_BASER_TYPE_DEVICE) { 840 u64 typer = readq_relaxed(its->base + GITS_TYPER); 841 u32 ids = GITS_TYPER_DEVBITS(typer); 842 843 /* 844 * 'order' was initialized earlier to the default page 845 * granule of the the ITS. We can't have an allocation 846 * smaller than that. If the requested allocation 847 * is smaller, round up to the default page granule. 848 */ 849 order = max(get_order((1UL << ids) * entry_size), 850 order); 851 if (order >= MAX_ORDER) { 852 order = MAX_ORDER - 1; 853 pr_warn("%s: Device Table too large, reduce its page order to %u\n", 854 node_name, order); 855 } 856 } 857 858 alloc_size = (1 << order) * PAGE_SIZE; 859 base = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, order); 860 if (!base) { 861 err = -ENOMEM; 862 goto out_free; 863 } 864 865 its->tables[i] = base; 866 867 retry_baser: 868 val = (virt_to_phys(base) | 869 (type << GITS_BASER_TYPE_SHIFT) | 870 ((entry_size - 1) << GITS_BASER_ENTRY_SIZE_SHIFT) | 871 cache | 872 shr | 873 GITS_BASER_VALID); 874 875 switch (psz) { 876 case SZ_4K: 877 val |= GITS_BASER_PAGE_SIZE_4K; 878 break; 879 case SZ_16K: 880 val |= GITS_BASER_PAGE_SIZE_16K; 881 break; 882 case SZ_64K: 883 val |= GITS_BASER_PAGE_SIZE_64K; 884 break; 885 } 886 887 val |= (alloc_size / psz) - 1; 888 889 writeq_relaxed(val, its->base + GITS_BASER + i * 8); 890 tmp = readq_relaxed(its->base + GITS_BASER + i * 8); 891 892 if ((val ^ tmp) & GITS_BASER_SHAREABILITY_MASK) { 893 /* 894 * Shareability didn't stick. Just use 895 * whatever the read reported, which is likely 896 * to be the only thing this redistributor 897 * supports. If that's zero, make it 898 * non-cacheable as well. 899 */ 900 shr = tmp & GITS_BASER_SHAREABILITY_MASK; 901 if (!shr) 902 cache = GITS_BASER_nC; 903 goto retry_baser; 904 } 905 906 if ((val ^ tmp) & GITS_BASER_PAGE_SIZE_MASK) { 907 /* 908 * Page size didn't stick. Let's try a smaller 909 * size and retry. If we reach 4K, then 910 * something is horribly wrong... 911 */ 912 switch (psz) { 913 case SZ_16K: 914 psz = SZ_4K; 915 goto retry_baser; 916 case SZ_64K: 917 psz = SZ_16K; 918 goto retry_baser; 919 } 920 } 921 922 if (val != tmp) { 923 pr_err("ITS: %s: GITS_BASER%d doesn't stick: %lx %lx\n", 924 node_name, i, 925 (unsigned long) val, (unsigned long) tmp); 926 err = -ENXIO; 927 goto out_free; 928 } 929 930 pr_info("ITS: allocated %d %s @%lx (psz %dK, shr %d)\n", 931 (int)(alloc_size / entry_size), 932 its_base_type_string[type], 933 (unsigned long)virt_to_phys(base), 934 psz / SZ_1K, (int)shr >> GITS_BASER_SHAREABILITY_SHIFT); 935 } 936 937 return 0; 938 939 out_free: 940 its_free_tables(its); 941 942 return err; 943 } 944 945 static int its_alloc_collections(struct its_node *its) 946 { 947 its->collections = kzalloc(nr_cpu_ids * sizeof(*its->collections), 948 GFP_KERNEL); 949 if (!its->collections) 950 return -ENOMEM; 951 952 return 0; 953 } 954 955 static void its_cpu_init_lpis(void) 956 { 957 void __iomem *rbase = gic_data_rdist_rd_base(); 958 struct page *pend_page; 959 u64 val, tmp; 960 961 /* If we didn't allocate the pending table yet, do it now */ 962 pend_page = gic_data_rdist()->pend_page; 963 if (!pend_page) { 964 phys_addr_t paddr; 965 /* 966 * The pending pages have to be at least 64kB aligned, 967 * hence the 'max(LPI_PENDBASE_SZ, SZ_64K)' below. 968 */ 969 pend_page = alloc_pages(GFP_NOWAIT | __GFP_ZERO, 970 get_order(max(LPI_PENDBASE_SZ, SZ_64K))); 971 if (!pend_page) { 972 pr_err("Failed to allocate PENDBASE for CPU%d\n", 973 smp_processor_id()); 974 return; 975 } 976 977 /* Make sure the GIC will observe the zero-ed page */ 978 __flush_dcache_area(page_address(pend_page), LPI_PENDBASE_SZ); 979 980 paddr = page_to_phys(pend_page); 981 pr_info("CPU%d: using LPI pending table @%pa\n", 982 smp_processor_id(), &paddr); 983 gic_data_rdist()->pend_page = pend_page; 984 } 985 986 /* Disable LPIs */ 987 val = readl_relaxed(rbase + GICR_CTLR); 988 val &= ~GICR_CTLR_ENABLE_LPIS; 989 writel_relaxed(val, rbase + GICR_CTLR); 990 991 /* 992 * Make sure any change to the table is observable by the GIC. 993 */ 994 dsb(sy); 995 996 /* set PROPBASE */ 997 val = (page_to_phys(gic_rdists->prop_page) | 998 GICR_PROPBASER_InnerShareable | 999 GICR_PROPBASER_WaWb | 1000 ((LPI_NRBITS - 1) & GICR_PROPBASER_IDBITS_MASK)); 1001 1002 writeq_relaxed(val, rbase + GICR_PROPBASER); 1003 tmp = readq_relaxed(rbase + GICR_PROPBASER); 1004 1005 if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) { 1006 if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) { 1007 /* 1008 * The HW reports non-shareable, we must 1009 * remove the cacheability attributes as 1010 * well. 1011 */ 1012 val &= ~(GICR_PROPBASER_SHAREABILITY_MASK | 1013 GICR_PROPBASER_CACHEABILITY_MASK); 1014 val |= GICR_PROPBASER_nC; 1015 writeq_relaxed(val, rbase + GICR_PROPBASER); 1016 } 1017 pr_info_once("GIC: using cache flushing for LPI property table\n"); 1018 gic_rdists->flags |= RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING; 1019 } 1020 1021 /* set PENDBASE */ 1022 val = (page_to_phys(pend_page) | 1023 GICR_PENDBASER_InnerShareable | 1024 GICR_PENDBASER_WaWb); 1025 1026 writeq_relaxed(val, rbase + GICR_PENDBASER); 1027 tmp = readq_relaxed(rbase + GICR_PENDBASER); 1028 1029 if (!(tmp & GICR_PENDBASER_SHAREABILITY_MASK)) { 1030 /* 1031 * The HW reports non-shareable, we must remove the 1032 * cacheability attributes as well. 1033 */ 1034 val &= ~(GICR_PENDBASER_SHAREABILITY_MASK | 1035 GICR_PENDBASER_CACHEABILITY_MASK); 1036 val |= GICR_PENDBASER_nC; 1037 writeq_relaxed(val, rbase + GICR_PENDBASER); 1038 } 1039 1040 /* Enable LPIs */ 1041 val = readl_relaxed(rbase + GICR_CTLR); 1042 val |= GICR_CTLR_ENABLE_LPIS; 1043 writel_relaxed(val, rbase + GICR_CTLR); 1044 1045 /* Make sure the GIC has seen the above */ 1046 dsb(sy); 1047 } 1048 1049 static void its_cpu_init_collection(void) 1050 { 1051 struct its_node *its; 1052 int cpu; 1053 1054 spin_lock(&its_lock); 1055 cpu = smp_processor_id(); 1056 1057 list_for_each_entry(its, &its_nodes, entry) { 1058 u64 target; 1059 1060 /* 1061 * We now have to bind each collection to its target 1062 * redistributor. 1063 */ 1064 if (readq_relaxed(its->base + GITS_TYPER) & GITS_TYPER_PTA) { 1065 /* 1066 * This ITS wants the physical address of the 1067 * redistributor. 1068 */ 1069 target = gic_data_rdist()->phys_base; 1070 } else { 1071 /* 1072 * This ITS wants a linear CPU number. 1073 */ 1074 target = readq_relaxed(gic_data_rdist_rd_base() + GICR_TYPER); 1075 target = GICR_TYPER_CPU_NUMBER(target) << 16; 1076 } 1077 1078 /* Perform collection mapping */ 1079 its->collections[cpu].target_address = target; 1080 its->collections[cpu].col_id = cpu; 1081 1082 its_send_mapc(its, &its->collections[cpu], 1); 1083 its_send_invall(its, &its->collections[cpu]); 1084 } 1085 1086 spin_unlock(&its_lock); 1087 } 1088 1089 static struct its_device *its_find_device(struct its_node *its, u32 dev_id) 1090 { 1091 struct its_device *its_dev = NULL, *tmp; 1092 unsigned long flags; 1093 1094 raw_spin_lock_irqsave(&its->lock, flags); 1095 1096 list_for_each_entry(tmp, &its->its_device_list, entry) { 1097 if (tmp->device_id == dev_id) { 1098 its_dev = tmp; 1099 break; 1100 } 1101 } 1102 1103 raw_spin_unlock_irqrestore(&its->lock, flags); 1104 1105 return its_dev; 1106 } 1107 1108 static struct its_device *its_create_device(struct its_node *its, u32 dev_id, 1109 int nvecs) 1110 { 1111 struct its_device *dev; 1112 unsigned long *lpi_map; 1113 unsigned long flags; 1114 u16 *col_map = NULL; 1115 void *itt; 1116 int lpi_base; 1117 int nr_lpis; 1118 int nr_ites; 1119 int sz; 1120 1121 dev = kzalloc(sizeof(*dev), GFP_KERNEL); 1122 /* 1123 * At least one bit of EventID is being used, hence a minimum 1124 * of two entries. No, the architecture doesn't let you 1125 * express an ITT with a single entry. 1126 */ 1127 nr_ites = max(2UL, roundup_pow_of_two(nvecs)); 1128 sz = nr_ites * its->ite_size; 1129 sz = max(sz, ITS_ITT_ALIGN) + ITS_ITT_ALIGN - 1; 1130 itt = kzalloc(sz, GFP_KERNEL); 1131 lpi_map = its_lpi_alloc_chunks(nvecs, &lpi_base, &nr_lpis); 1132 if (lpi_map) 1133 col_map = kzalloc(sizeof(*col_map) * nr_lpis, GFP_KERNEL); 1134 1135 if (!dev || !itt || !lpi_map || !col_map) { 1136 kfree(dev); 1137 kfree(itt); 1138 kfree(lpi_map); 1139 kfree(col_map); 1140 return NULL; 1141 } 1142 1143 dev->its = its; 1144 dev->itt = itt; 1145 dev->nr_ites = nr_ites; 1146 dev->event_map.lpi_map = lpi_map; 1147 dev->event_map.col_map = col_map; 1148 dev->event_map.lpi_base = lpi_base; 1149 dev->event_map.nr_lpis = nr_lpis; 1150 dev->device_id = dev_id; 1151 INIT_LIST_HEAD(&dev->entry); 1152 1153 raw_spin_lock_irqsave(&its->lock, flags); 1154 list_add(&dev->entry, &its->its_device_list); 1155 raw_spin_unlock_irqrestore(&its->lock, flags); 1156 1157 /* Map device to its ITT */ 1158 its_send_mapd(dev, 1); 1159 1160 return dev; 1161 } 1162 1163 static void its_free_device(struct its_device *its_dev) 1164 { 1165 unsigned long flags; 1166 1167 raw_spin_lock_irqsave(&its_dev->its->lock, flags); 1168 list_del(&its_dev->entry); 1169 raw_spin_unlock_irqrestore(&its_dev->its->lock, flags); 1170 kfree(its_dev->itt); 1171 kfree(its_dev); 1172 } 1173 1174 static int its_alloc_device_irq(struct its_device *dev, irq_hw_number_t *hwirq) 1175 { 1176 int idx; 1177 1178 idx = find_first_zero_bit(dev->event_map.lpi_map, 1179 dev->event_map.nr_lpis); 1180 if (idx == dev->event_map.nr_lpis) 1181 return -ENOSPC; 1182 1183 *hwirq = dev->event_map.lpi_base + idx; 1184 set_bit(idx, dev->event_map.lpi_map); 1185 1186 return 0; 1187 } 1188 1189 static int its_msi_prepare(struct irq_domain *domain, struct device *dev, 1190 int nvec, msi_alloc_info_t *info) 1191 { 1192 struct its_node *its; 1193 struct its_device *its_dev; 1194 struct msi_domain_info *msi_info; 1195 u32 dev_id; 1196 1197 /* 1198 * We ignore "dev" entierely, and rely on the dev_id that has 1199 * been passed via the scratchpad. This limits this domain's 1200 * usefulness to upper layers that definitely know that they 1201 * are built on top of the ITS. 1202 */ 1203 dev_id = info->scratchpad[0].ul; 1204 1205 msi_info = msi_get_domain_info(domain); 1206 its = msi_info->data; 1207 1208 its_dev = its_find_device(its, dev_id); 1209 if (its_dev) { 1210 /* 1211 * We already have seen this ID, probably through 1212 * another alias (PCI bridge of some sort). No need to 1213 * create the device. 1214 */ 1215 pr_debug("Reusing ITT for devID %x\n", dev_id); 1216 goto out; 1217 } 1218 1219 its_dev = its_create_device(its, dev_id, nvec); 1220 if (!its_dev) 1221 return -ENOMEM; 1222 1223 pr_debug("ITT %d entries, %d bits\n", nvec, ilog2(nvec)); 1224 out: 1225 info->scratchpad[0].ptr = its_dev; 1226 return 0; 1227 } 1228 1229 static struct msi_domain_ops its_msi_domain_ops = { 1230 .msi_prepare = its_msi_prepare, 1231 }; 1232 1233 static int its_irq_gic_domain_alloc(struct irq_domain *domain, 1234 unsigned int virq, 1235 irq_hw_number_t hwirq) 1236 { 1237 struct of_phandle_args args; 1238 1239 args.np = domain->parent->of_node; 1240 args.args_count = 3; 1241 args.args[0] = GIC_IRQ_TYPE_LPI; 1242 args.args[1] = hwirq; 1243 args.args[2] = IRQ_TYPE_EDGE_RISING; 1244 1245 return irq_domain_alloc_irqs_parent(domain, virq, 1, &args); 1246 } 1247 1248 static int its_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, 1249 unsigned int nr_irqs, void *args) 1250 { 1251 msi_alloc_info_t *info = args; 1252 struct its_device *its_dev = info->scratchpad[0].ptr; 1253 irq_hw_number_t hwirq; 1254 int err; 1255 int i; 1256 1257 for (i = 0; i < nr_irqs; i++) { 1258 err = its_alloc_device_irq(its_dev, &hwirq); 1259 if (err) 1260 return err; 1261 1262 err = its_irq_gic_domain_alloc(domain, virq + i, hwirq); 1263 if (err) 1264 return err; 1265 1266 irq_domain_set_hwirq_and_chip(domain, virq + i, 1267 hwirq, &its_irq_chip, its_dev); 1268 pr_debug("ID:%d pID:%d vID:%d\n", 1269 (int)(hwirq - its_dev->event_map.lpi_base), 1270 (int) hwirq, virq + i); 1271 } 1272 1273 return 0; 1274 } 1275 1276 static void its_irq_domain_activate(struct irq_domain *domain, 1277 struct irq_data *d) 1278 { 1279 struct its_device *its_dev = irq_data_get_irq_chip_data(d); 1280 u32 event = its_get_event_id(d); 1281 1282 /* Bind the LPI to the first possible CPU */ 1283 its_dev->event_map.col_map[event] = cpumask_first(cpu_online_mask); 1284 1285 /* Map the GIC IRQ and event to the device */ 1286 its_send_mapvi(its_dev, d->hwirq, event); 1287 } 1288 1289 static void its_irq_domain_deactivate(struct irq_domain *domain, 1290 struct irq_data *d) 1291 { 1292 struct its_device *its_dev = irq_data_get_irq_chip_data(d); 1293 u32 event = its_get_event_id(d); 1294 1295 /* Stop the delivery of interrupts */ 1296 its_send_discard(its_dev, event); 1297 } 1298 1299 static void its_irq_domain_free(struct irq_domain *domain, unsigned int virq, 1300 unsigned int nr_irqs) 1301 { 1302 struct irq_data *d = irq_domain_get_irq_data(domain, virq); 1303 struct its_device *its_dev = irq_data_get_irq_chip_data(d); 1304 int i; 1305 1306 for (i = 0; i < nr_irqs; i++) { 1307 struct irq_data *data = irq_domain_get_irq_data(domain, 1308 virq + i); 1309 u32 event = its_get_event_id(data); 1310 1311 /* Mark interrupt index as unused */ 1312 clear_bit(event, its_dev->event_map.lpi_map); 1313 1314 /* Nuke the entry in the domain */ 1315 irq_domain_reset_irq_data(data); 1316 } 1317 1318 /* If all interrupts have been freed, start mopping the floor */ 1319 if (bitmap_empty(its_dev->event_map.lpi_map, 1320 its_dev->event_map.nr_lpis)) { 1321 its_lpi_free(&its_dev->event_map); 1322 1323 /* Unmap device/itt */ 1324 its_send_mapd(its_dev, 0); 1325 its_free_device(its_dev); 1326 } 1327 1328 irq_domain_free_irqs_parent(domain, virq, nr_irqs); 1329 } 1330 1331 static const struct irq_domain_ops its_domain_ops = { 1332 .alloc = its_irq_domain_alloc, 1333 .free = its_irq_domain_free, 1334 .activate = its_irq_domain_activate, 1335 .deactivate = its_irq_domain_deactivate, 1336 }; 1337 1338 static int its_force_quiescent(void __iomem *base) 1339 { 1340 u32 count = 1000000; /* 1s */ 1341 u32 val; 1342 1343 val = readl_relaxed(base + GITS_CTLR); 1344 if (val & GITS_CTLR_QUIESCENT) 1345 return 0; 1346 1347 /* Disable the generation of all interrupts to this ITS */ 1348 val &= ~GITS_CTLR_ENABLE; 1349 writel_relaxed(val, base + GITS_CTLR); 1350 1351 /* Poll GITS_CTLR and wait until ITS becomes quiescent */ 1352 while (1) { 1353 val = readl_relaxed(base + GITS_CTLR); 1354 if (val & GITS_CTLR_QUIESCENT) 1355 return 0; 1356 1357 count--; 1358 if (!count) 1359 return -EBUSY; 1360 1361 cpu_relax(); 1362 udelay(1); 1363 } 1364 } 1365 1366 static int its_probe(struct device_node *node, struct irq_domain *parent) 1367 { 1368 struct resource res; 1369 struct its_node *its; 1370 void __iomem *its_base; 1371 struct irq_domain *inner_domain; 1372 u32 val; 1373 u64 baser, tmp; 1374 int err; 1375 1376 err = of_address_to_resource(node, 0, &res); 1377 if (err) { 1378 pr_warn("%s: no regs?\n", node->full_name); 1379 return -ENXIO; 1380 } 1381 1382 its_base = ioremap(res.start, resource_size(&res)); 1383 if (!its_base) { 1384 pr_warn("%s: unable to map registers\n", node->full_name); 1385 return -ENOMEM; 1386 } 1387 1388 val = readl_relaxed(its_base + GITS_PIDR2) & GIC_PIDR2_ARCH_MASK; 1389 if (val != 0x30 && val != 0x40) { 1390 pr_warn("%s: no ITS detected, giving up\n", node->full_name); 1391 err = -ENODEV; 1392 goto out_unmap; 1393 } 1394 1395 err = its_force_quiescent(its_base); 1396 if (err) { 1397 pr_warn("%s: failed to quiesce, giving up\n", 1398 node->full_name); 1399 goto out_unmap; 1400 } 1401 1402 pr_info("ITS: %s\n", node->full_name); 1403 1404 its = kzalloc(sizeof(*its), GFP_KERNEL); 1405 if (!its) { 1406 err = -ENOMEM; 1407 goto out_unmap; 1408 } 1409 1410 raw_spin_lock_init(&its->lock); 1411 INIT_LIST_HEAD(&its->entry); 1412 INIT_LIST_HEAD(&its->its_device_list); 1413 its->base = its_base; 1414 its->phys_base = res.start; 1415 its->ite_size = ((readl_relaxed(its_base + GITS_TYPER) >> 4) & 0xf) + 1; 1416 1417 its->cmd_base = kzalloc(ITS_CMD_QUEUE_SZ, GFP_KERNEL); 1418 if (!its->cmd_base) { 1419 err = -ENOMEM; 1420 goto out_free_its; 1421 } 1422 its->cmd_write = its->cmd_base; 1423 1424 err = its_alloc_tables(node->full_name, its); 1425 if (err) 1426 goto out_free_cmd; 1427 1428 err = its_alloc_collections(its); 1429 if (err) 1430 goto out_free_tables; 1431 1432 baser = (virt_to_phys(its->cmd_base) | 1433 GITS_CBASER_WaWb | 1434 GITS_CBASER_InnerShareable | 1435 (ITS_CMD_QUEUE_SZ / SZ_4K - 1) | 1436 GITS_CBASER_VALID); 1437 1438 writeq_relaxed(baser, its->base + GITS_CBASER); 1439 tmp = readq_relaxed(its->base + GITS_CBASER); 1440 1441 if ((tmp ^ baser) & GITS_CBASER_SHAREABILITY_MASK) { 1442 if (!(tmp & GITS_CBASER_SHAREABILITY_MASK)) { 1443 /* 1444 * The HW reports non-shareable, we must 1445 * remove the cacheability attributes as 1446 * well. 1447 */ 1448 baser &= ~(GITS_CBASER_SHAREABILITY_MASK | 1449 GITS_CBASER_CACHEABILITY_MASK); 1450 baser |= GITS_CBASER_nC; 1451 writeq_relaxed(baser, its->base + GITS_CBASER); 1452 } 1453 pr_info("ITS: using cache flushing for cmd queue\n"); 1454 its->flags |= ITS_FLAGS_CMDQ_NEEDS_FLUSHING; 1455 } 1456 1457 writeq_relaxed(0, its->base + GITS_CWRITER); 1458 writel_relaxed(GITS_CTLR_ENABLE, its->base + GITS_CTLR); 1459 1460 if (of_property_read_bool(node, "msi-controller")) { 1461 struct msi_domain_info *info; 1462 1463 info = kzalloc(sizeof(*info), GFP_KERNEL); 1464 if (!info) { 1465 err = -ENOMEM; 1466 goto out_free_tables; 1467 } 1468 1469 inner_domain = irq_domain_add_tree(node, &its_domain_ops, its); 1470 if (!inner_domain) { 1471 err = -ENOMEM; 1472 kfree(info); 1473 goto out_free_tables; 1474 } 1475 1476 inner_domain->parent = parent; 1477 inner_domain->bus_token = DOMAIN_BUS_NEXUS; 1478 info->ops = &its_msi_domain_ops; 1479 info->data = its; 1480 inner_domain->host_data = info; 1481 } 1482 1483 spin_lock(&its_lock); 1484 list_add(&its->entry, &its_nodes); 1485 spin_unlock(&its_lock); 1486 1487 return 0; 1488 1489 out_free_tables: 1490 its_free_tables(its); 1491 out_free_cmd: 1492 kfree(its->cmd_base); 1493 out_free_its: 1494 kfree(its); 1495 out_unmap: 1496 iounmap(its_base); 1497 pr_err("ITS: failed probing %s (%d)\n", node->full_name, err); 1498 return err; 1499 } 1500 1501 static bool gic_rdists_supports_plpis(void) 1502 { 1503 return !!(readl_relaxed(gic_data_rdist_rd_base() + GICR_TYPER) & GICR_TYPER_PLPIS); 1504 } 1505 1506 int its_cpu_init(void) 1507 { 1508 if (!list_empty(&its_nodes)) { 1509 if (!gic_rdists_supports_plpis()) { 1510 pr_info("CPU%d: LPIs not supported\n", smp_processor_id()); 1511 return -ENXIO; 1512 } 1513 its_cpu_init_lpis(); 1514 its_cpu_init_collection(); 1515 } 1516 1517 return 0; 1518 } 1519 1520 static struct of_device_id its_device_id[] = { 1521 { .compatible = "arm,gic-v3-its", }, 1522 {}, 1523 }; 1524 1525 int its_init(struct device_node *node, struct rdists *rdists, 1526 struct irq_domain *parent_domain) 1527 { 1528 struct device_node *np; 1529 1530 for (np = of_find_matching_node(node, its_device_id); np; 1531 np = of_find_matching_node(np, its_device_id)) { 1532 its_probe(np, parent_domain); 1533 } 1534 1535 if (list_empty(&its_nodes)) { 1536 pr_warn("ITS: No ITS available, not enabling LPIs\n"); 1537 return -ENXIO; 1538 } 1539 1540 gic_rdists = rdists; 1541 gic_root_node = node; 1542 1543 its_alloc_lpi_tables(); 1544 its_lpi_init(rdists->id_bits); 1545 1546 return 0; 1547 } 1548