1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (C) 2013-2017 ARM Limited, All Rights Reserved.
4  * Author: Marc Zyngier <marc.zyngier@arm.com>
5  */
6 
7 #include <linux/acpi.h>
8 #include <linux/acpi_iort.h>
9 #include <linux/bitfield.h>
10 #include <linux/bitmap.h>
11 #include <linux/cpu.h>
12 #include <linux/crash_dump.h>
13 #include <linux/delay.h>
14 #include <linux/dma-iommu.h>
15 #include <linux/efi.h>
16 #include <linux/interrupt.h>
17 #include <linux/iopoll.h>
18 #include <linux/irqdomain.h>
19 #include <linux/list.h>
20 #include <linux/log2.h>
21 #include <linux/memblock.h>
22 #include <linux/mm.h>
23 #include <linux/msi.h>
24 #include <linux/of.h>
25 #include <linux/of_address.h>
26 #include <linux/of_irq.h>
27 #include <linux/of_pci.h>
28 #include <linux/of_platform.h>
29 #include <linux/percpu.h>
30 #include <linux/slab.h>
31 #include <linux/syscore_ops.h>
32 
33 #include <linux/irqchip.h>
34 #include <linux/irqchip/arm-gic-v3.h>
35 #include <linux/irqchip/arm-gic-v4.h>
36 
37 #include <asm/cputype.h>
38 #include <asm/exception.h>
39 
40 #include "irq-gic-common.h"
41 
42 #define ITS_FLAGS_CMDQ_NEEDS_FLUSHING		(1ULL << 0)
43 #define ITS_FLAGS_WORKAROUND_CAVIUM_22375	(1ULL << 1)
44 #define ITS_FLAGS_WORKAROUND_CAVIUM_23144	(1ULL << 2)
45 
46 #define RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING	(1 << 0)
47 #define RDIST_FLAGS_RD_TABLES_PREALLOCATED	(1 << 1)
48 
49 #define RD_LOCAL_LPI_ENABLED                    BIT(0)
50 #define RD_LOCAL_PENDTABLE_PREALLOCATED         BIT(1)
51 #define RD_LOCAL_MEMRESERVE_DONE                BIT(2)
52 
53 static u32 lpi_id_bits;
54 
55 /*
56  * We allocate memory for PROPBASE to cover 2 ^ lpi_id_bits LPIs to
57  * deal with (one configuration byte per interrupt). PENDBASE has to
58  * be 64kB aligned (one bit per LPI, plus 8192 bits for SPI/PPI/SGI).
59  */
60 #define LPI_NRBITS		lpi_id_bits
61 #define LPI_PROPBASE_SZ		ALIGN(BIT(LPI_NRBITS), SZ_64K)
62 #define LPI_PENDBASE_SZ		ALIGN(BIT(LPI_NRBITS) / 8, SZ_64K)
63 
64 #define LPI_PROP_DEFAULT_PRIO	GICD_INT_DEF_PRI
65 
66 /*
67  * Collection structure - just an ID, and a redistributor address to
68  * ping. We use one per CPU as a bag of interrupts assigned to this
69  * CPU.
70  */
71 struct its_collection {
72 	u64			target_address;
73 	u16			col_id;
74 };
75 
76 /*
77  * The ITS_BASER structure - contains memory information, cached
78  * value of BASER register configuration and ITS page size.
79  */
80 struct its_baser {
81 	void		*base;
82 	u64		val;
83 	u32		order;
84 	u32		psz;
85 };
86 
87 struct its_device;
88 
89 /*
90  * The ITS structure - contains most of the infrastructure, with the
91  * top-level MSI domain, the command queue, the collections, and the
92  * list of devices writing to it.
93  *
94  * dev_alloc_lock has to be taken for device allocations, while the
95  * spinlock must be taken to parse data structures such as the device
96  * list.
97  */
98 struct its_node {
99 	raw_spinlock_t		lock;
100 	struct mutex		dev_alloc_lock;
101 	struct list_head	entry;
102 	void __iomem		*base;
103 	void __iomem		*sgir_base;
104 	phys_addr_t		phys_base;
105 	struct its_cmd_block	*cmd_base;
106 	struct its_cmd_block	*cmd_write;
107 	struct its_baser	tables[GITS_BASER_NR_REGS];
108 	struct its_collection	*collections;
109 	struct fwnode_handle	*fwnode_handle;
110 	u64			(*get_msi_base)(struct its_device *its_dev);
111 	u64			typer;
112 	u64			cbaser_save;
113 	u32			ctlr_save;
114 	u32			mpidr;
115 	struct list_head	its_device_list;
116 	u64			flags;
117 	unsigned long		list_nr;
118 	int			numa_node;
119 	unsigned int		msi_domain_flags;
120 	u32			pre_its_base; /* for Socionext Synquacer */
121 	int			vlpi_redist_offset;
122 };
123 
124 #define is_v4(its)		(!!((its)->typer & GITS_TYPER_VLPIS))
125 #define is_v4_1(its)		(!!((its)->typer & GITS_TYPER_VMAPP))
126 #define device_ids(its)		(FIELD_GET(GITS_TYPER_DEVBITS, (its)->typer) + 1)
127 
128 #define ITS_ITT_ALIGN		SZ_256
129 
130 /* The maximum number of VPEID bits supported by VLPI commands */
131 #define ITS_MAX_VPEID_BITS						\
132 	({								\
133 		int nvpeid = 16;					\
134 		if (gic_rdists->has_rvpeid &&				\
135 		    gic_rdists->gicd_typer2 & GICD_TYPER2_VIL)		\
136 			nvpeid = 1 + (gic_rdists->gicd_typer2 &		\
137 				      GICD_TYPER2_VID);			\
138 									\
139 		nvpeid;							\
140 	})
141 #define ITS_MAX_VPEID		(1 << (ITS_MAX_VPEID_BITS))
142 
143 /* Convert page order to size in bytes */
144 #define PAGE_ORDER_TO_SIZE(o)	(PAGE_SIZE << (o))
145 
146 struct event_lpi_map {
147 	unsigned long		*lpi_map;
148 	u16			*col_map;
149 	irq_hw_number_t		lpi_base;
150 	int			nr_lpis;
151 	raw_spinlock_t		vlpi_lock;
152 	struct its_vm		*vm;
153 	struct its_vlpi_map	*vlpi_maps;
154 	int			nr_vlpis;
155 };
156 
157 /*
158  * The ITS view of a device - belongs to an ITS, owns an interrupt
159  * translation table, and a list of interrupts.  If it some of its
160  * LPIs are injected into a guest (GICv4), the event_map.vm field
161  * indicates which one.
162  */
163 struct its_device {
164 	struct list_head	entry;
165 	struct its_node		*its;
166 	struct event_lpi_map	event_map;
167 	void			*itt;
168 	u32			nr_ites;
169 	u32			device_id;
170 	bool			shared;
171 };
172 
173 static struct {
174 	raw_spinlock_t		lock;
175 	struct its_device	*dev;
176 	struct its_vpe		**vpes;
177 	int			next_victim;
178 } vpe_proxy;
179 
180 struct cpu_lpi_count {
181 	atomic_t	managed;
182 	atomic_t	unmanaged;
183 };
184 
185 static DEFINE_PER_CPU(struct cpu_lpi_count, cpu_lpi_count);
186 
187 static LIST_HEAD(its_nodes);
188 static DEFINE_RAW_SPINLOCK(its_lock);
189 static struct rdists *gic_rdists;
190 static struct irq_domain *its_parent;
191 
192 static unsigned long its_list_map;
193 static u16 vmovp_seq_num;
194 static DEFINE_RAW_SPINLOCK(vmovp_lock);
195 
196 static DEFINE_IDA(its_vpeid_ida);
197 
198 #define gic_data_rdist()		(raw_cpu_ptr(gic_rdists->rdist))
199 #define gic_data_rdist_cpu(cpu)		(per_cpu_ptr(gic_rdists->rdist, cpu))
200 #define gic_data_rdist_rd_base()	(gic_data_rdist()->rd_base)
201 #define gic_data_rdist_vlpi_base()	(gic_data_rdist_rd_base() + SZ_128K)
202 
203 /*
204  * Skip ITSs that have no vLPIs mapped, unless we're on GICv4.1, as we
205  * always have vSGIs mapped.
206  */
207 static bool require_its_list_vmovp(struct its_vm *vm, struct its_node *its)
208 {
209 	return (gic_rdists->has_rvpeid || vm->vlpi_count[its->list_nr]);
210 }
211 
212 static u16 get_its_list(struct its_vm *vm)
213 {
214 	struct its_node *its;
215 	unsigned long its_list = 0;
216 
217 	list_for_each_entry(its, &its_nodes, entry) {
218 		if (!is_v4(its))
219 			continue;
220 
221 		if (require_its_list_vmovp(vm, its))
222 			__set_bit(its->list_nr, &its_list);
223 	}
224 
225 	return (u16)its_list;
226 }
227 
228 static inline u32 its_get_event_id(struct irq_data *d)
229 {
230 	struct its_device *its_dev = irq_data_get_irq_chip_data(d);
231 	return d->hwirq - its_dev->event_map.lpi_base;
232 }
233 
234 static struct its_collection *dev_event_to_col(struct its_device *its_dev,
235 					       u32 event)
236 {
237 	struct its_node *its = its_dev->its;
238 
239 	return its->collections + its_dev->event_map.col_map[event];
240 }
241 
242 static struct its_vlpi_map *dev_event_to_vlpi_map(struct its_device *its_dev,
243 					       u32 event)
244 {
245 	if (WARN_ON_ONCE(event >= its_dev->event_map.nr_lpis))
246 		return NULL;
247 
248 	return &its_dev->event_map.vlpi_maps[event];
249 }
250 
251 static struct its_vlpi_map *get_vlpi_map(struct irq_data *d)
252 {
253 	if (irqd_is_forwarded_to_vcpu(d)) {
254 		struct its_device *its_dev = irq_data_get_irq_chip_data(d);
255 		u32 event = its_get_event_id(d);
256 
257 		return dev_event_to_vlpi_map(its_dev, event);
258 	}
259 
260 	return NULL;
261 }
262 
263 static int vpe_to_cpuid_lock(struct its_vpe *vpe, unsigned long *flags)
264 {
265 	raw_spin_lock_irqsave(&vpe->vpe_lock, *flags);
266 	return vpe->col_idx;
267 }
268 
269 static void vpe_to_cpuid_unlock(struct its_vpe *vpe, unsigned long flags)
270 {
271 	raw_spin_unlock_irqrestore(&vpe->vpe_lock, flags);
272 }
273 
274 static int irq_to_cpuid_lock(struct irq_data *d, unsigned long *flags)
275 {
276 	struct its_vlpi_map *map = get_vlpi_map(d);
277 	int cpu;
278 
279 	if (map) {
280 		cpu = vpe_to_cpuid_lock(map->vpe, flags);
281 	} else {
282 		/* Physical LPIs are already locked via the irq_desc lock */
283 		struct its_device *its_dev = irq_data_get_irq_chip_data(d);
284 		cpu = its_dev->event_map.col_map[its_get_event_id(d)];
285 		/* Keep GCC quiet... */
286 		*flags = 0;
287 	}
288 
289 	return cpu;
290 }
291 
292 static void irq_to_cpuid_unlock(struct irq_data *d, unsigned long flags)
293 {
294 	struct its_vlpi_map *map = get_vlpi_map(d);
295 
296 	if (map)
297 		vpe_to_cpuid_unlock(map->vpe, flags);
298 }
299 
300 static struct its_collection *valid_col(struct its_collection *col)
301 {
302 	if (WARN_ON_ONCE(col->target_address & GENMASK_ULL(15, 0)))
303 		return NULL;
304 
305 	return col;
306 }
307 
308 static struct its_vpe *valid_vpe(struct its_node *its, struct its_vpe *vpe)
309 {
310 	if (valid_col(its->collections + vpe->col_idx))
311 		return vpe;
312 
313 	return NULL;
314 }
315 
316 /*
317  * ITS command descriptors - parameters to be encoded in a command
318  * block.
319  */
320 struct its_cmd_desc {
321 	union {
322 		struct {
323 			struct its_device *dev;
324 			u32 event_id;
325 		} its_inv_cmd;
326 
327 		struct {
328 			struct its_device *dev;
329 			u32 event_id;
330 		} its_clear_cmd;
331 
332 		struct {
333 			struct its_device *dev;
334 			u32 event_id;
335 		} its_int_cmd;
336 
337 		struct {
338 			struct its_device *dev;
339 			int valid;
340 		} its_mapd_cmd;
341 
342 		struct {
343 			struct its_collection *col;
344 			int valid;
345 		} its_mapc_cmd;
346 
347 		struct {
348 			struct its_device *dev;
349 			u32 phys_id;
350 			u32 event_id;
351 		} its_mapti_cmd;
352 
353 		struct {
354 			struct its_device *dev;
355 			struct its_collection *col;
356 			u32 event_id;
357 		} its_movi_cmd;
358 
359 		struct {
360 			struct its_device *dev;
361 			u32 event_id;
362 		} its_discard_cmd;
363 
364 		struct {
365 			struct its_collection *col;
366 		} its_invall_cmd;
367 
368 		struct {
369 			struct its_vpe *vpe;
370 		} its_vinvall_cmd;
371 
372 		struct {
373 			struct its_vpe *vpe;
374 			struct its_collection *col;
375 			bool valid;
376 		} its_vmapp_cmd;
377 
378 		struct {
379 			struct its_vpe *vpe;
380 			struct its_device *dev;
381 			u32 virt_id;
382 			u32 event_id;
383 			bool db_enabled;
384 		} its_vmapti_cmd;
385 
386 		struct {
387 			struct its_vpe *vpe;
388 			struct its_device *dev;
389 			u32 event_id;
390 			bool db_enabled;
391 		} its_vmovi_cmd;
392 
393 		struct {
394 			struct its_vpe *vpe;
395 			struct its_collection *col;
396 			u16 seq_num;
397 			u16 its_list;
398 		} its_vmovp_cmd;
399 
400 		struct {
401 			struct its_vpe *vpe;
402 		} its_invdb_cmd;
403 
404 		struct {
405 			struct its_vpe *vpe;
406 			u8 sgi;
407 			u8 priority;
408 			bool enable;
409 			bool group;
410 			bool clear;
411 		} its_vsgi_cmd;
412 	};
413 };
414 
415 /*
416  * The ITS command block, which is what the ITS actually parses.
417  */
418 struct its_cmd_block {
419 	union {
420 		u64	raw_cmd[4];
421 		__le64	raw_cmd_le[4];
422 	};
423 };
424 
425 #define ITS_CMD_QUEUE_SZ		SZ_64K
426 #define ITS_CMD_QUEUE_NR_ENTRIES	(ITS_CMD_QUEUE_SZ / sizeof(struct its_cmd_block))
427 
428 typedef struct its_collection *(*its_cmd_builder_t)(struct its_node *,
429 						    struct its_cmd_block *,
430 						    struct its_cmd_desc *);
431 
432 typedef struct its_vpe *(*its_cmd_vbuilder_t)(struct its_node *,
433 					      struct its_cmd_block *,
434 					      struct its_cmd_desc *);
435 
436 static void its_mask_encode(u64 *raw_cmd, u64 val, int h, int l)
437 {
438 	u64 mask = GENMASK_ULL(h, l);
439 	*raw_cmd &= ~mask;
440 	*raw_cmd |= (val << l) & mask;
441 }
442 
443 static void its_encode_cmd(struct its_cmd_block *cmd, u8 cmd_nr)
444 {
445 	its_mask_encode(&cmd->raw_cmd[0], cmd_nr, 7, 0);
446 }
447 
448 static void its_encode_devid(struct its_cmd_block *cmd, u32 devid)
449 {
450 	its_mask_encode(&cmd->raw_cmd[0], devid, 63, 32);
451 }
452 
453 static void its_encode_event_id(struct its_cmd_block *cmd, u32 id)
454 {
455 	its_mask_encode(&cmd->raw_cmd[1], id, 31, 0);
456 }
457 
458 static void its_encode_phys_id(struct its_cmd_block *cmd, u32 phys_id)
459 {
460 	its_mask_encode(&cmd->raw_cmd[1], phys_id, 63, 32);
461 }
462 
463 static void its_encode_size(struct its_cmd_block *cmd, u8 size)
464 {
465 	its_mask_encode(&cmd->raw_cmd[1], size, 4, 0);
466 }
467 
468 static void its_encode_itt(struct its_cmd_block *cmd, u64 itt_addr)
469 {
470 	its_mask_encode(&cmd->raw_cmd[2], itt_addr >> 8, 51, 8);
471 }
472 
473 static void its_encode_valid(struct its_cmd_block *cmd, int valid)
474 {
475 	its_mask_encode(&cmd->raw_cmd[2], !!valid, 63, 63);
476 }
477 
478 static void its_encode_target(struct its_cmd_block *cmd, u64 target_addr)
479 {
480 	its_mask_encode(&cmd->raw_cmd[2], target_addr >> 16, 51, 16);
481 }
482 
483 static void its_encode_collection(struct its_cmd_block *cmd, u16 col)
484 {
485 	its_mask_encode(&cmd->raw_cmd[2], col, 15, 0);
486 }
487 
488 static void its_encode_vpeid(struct its_cmd_block *cmd, u16 vpeid)
489 {
490 	its_mask_encode(&cmd->raw_cmd[1], vpeid, 47, 32);
491 }
492 
493 static void its_encode_virt_id(struct its_cmd_block *cmd, u32 virt_id)
494 {
495 	its_mask_encode(&cmd->raw_cmd[2], virt_id, 31, 0);
496 }
497 
498 static void its_encode_db_phys_id(struct its_cmd_block *cmd, u32 db_phys_id)
499 {
500 	its_mask_encode(&cmd->raw_cmd[2], db_phys_id, 63, 32);
501 }
502 
503 static void its_encode_db_valid(struct its_cmd_block *cmd, bool db_valid)
504 {
505 	its_mask_encode(&cmd->raw_cmd[2], db_valid, 0, 0);
506 }
507 
508 static void its_encode_seq_num(struct its_cmd_block *cmd, u16 seq_num)
509 {
510 	its_mask_encode(&cmd->raw_cmd[0], seq_num, 47, 32);
511 }
512 
513 static void its_encode_its_list(struct its_cmd_block *cmd, u16 its_list)
514 {
515 	its_mask_encode(&cmd->raw_cmd[1], its_list, 15, 0);
516 }
517 
518 static void its_encode_vpt_addr(struct its_cmd_block *cmd, u64 vpt_pa)
519 {
520 	its_mask_encode(&cmd->raw_cmd[3], vpt_pa >> 16, 51, 16);
521 }
522 
523 static void its_encode_vpt_size(struct its_cmd_block *cmd, u8 vpt_size)
524 {
525 	its_mask_encode(&cmd->raw_cmd[3], vpt_size, 4, 0);
526 }
527 
528 static void its_encode_vconf_addr(struct its_cmd_block *cmd, u64 vconf_pa)
529 {
530 	its_mask_encode(&cmd->raw_cmd[0], vconf_pa >> 16, 51, 16);
531 }
532 
533 static void its_encode_alloc(struct its_cmd_block *cmd, bool alloc)
534 {
535 	its_mask_encode(&cmd->raw_cmd[0], alloc, 8, 8);
536 }
537 
538 static void its_encode_ptz(struct its_cmd_block *cmd, bool ptz)
539 {
540 	its_mask_encode(&cmd->raw_cmd[0], ptz, 9, 9);
541 }
542 
543 static void its_encode_vmapp_default_db(struct its_cmd_block *cmd,
544 					u32 vpe_db_lpi)
545 {
546 	its_mask_encode(&cmd->raw_cmd[1], vpe_db_lpi, 31, 0);
547 }
548 
549 static void its_encode_vmovp_default_db(struct its_cmd_block *cmd,
550 					u32 vpe_db_lpi)
551 {
552 	its_mask_encode(&cmd->raw_cmd[3], vpe_db_lpi, 31, 0);
553 }
554 
555 static void its_encode_db(struct its_cmd_block *cmd, bool db)
556 {
557 	its_mask_encode(&cmd->raw_cmd[2], db, 63, 63);
558 }
559 
560 static void its_encode_sgi_intid(struct its_cmd_block *cmd, u8 sgi)
561 {
562 	its_mask_encode(&cmd->raw_cmd[0], sgi, 35, 32);
563 }
564 
565 static void its_encode_sgi_priority(struct its_cmd_block *cmd, u8 prio)
566 {
567 	its_mask_encode(&cmd->raw_cmd[0], prio >> 4, 23, 20);
568 }
569 
570 static void its_encode_sgi_group(struct its_cmd_block *cmd, bool grp)
571 {
572 	its_mask_encode(&cmd->raw_cmd[0], grp, 10, 10);
573 }
574 
575 static void its_encode_sgi_clear(struct its_cmd_block *cmd, bool clr)
576 {
577 	its_mask_encode(&cmd->raw_cmd[0], clr, 9, 9);
578 }
579 
580 static void its_encode_sgi_enable(struct its_cmd_block *cmd, bool en)
581 {
582 	its_mask_encode(&cmd->raw_cmd[0], en, 8, 8);
583 }
584 
585 static inline void its_fixup_cmd(struct its_cmd_block *cmd)
586 {
587 	/* Let's fixup BE commands */
588 	cmd->raw_cmd_le[0] = cpu_to_le64(cmd->raw_cmd[0]);
589 	cmd->raw_cmd_le[1] = cpu_to_le64(cmd->raw_cmd[1]);
590 	cmd->raw_cmd_le[2] = cpu_to_le64(cmd->raw_cmd[2]);
591 	cmd->raw_cmd_le[3] = cpu_to_le64(cmd->raw_cmd[3]);
592 }
593 
594 static struct its_collection *its_build_mapd_cmd(struct its_node *its,
595 						 struct its_cmd_block *cmd,
596 						 struct its_cmd_desc *desc)
597 {
598 	unsigned long itt_addr;
599 	u8 size = ilog2(desc->its_mapd_cmd.dev->nr_ites);
600 
601 	itt_addr = virt_to_phys(desc->its_mapd_cmd.dev->itt);
602 	itt_addr = ALIGN(itt_addr, ITS_ITT_ALIGN);
603 
604 	its_encode_cmd(cmd, GITS_CMD_MAPD);
605 	its_encode_devid(cmd, desc->its_mapd_cmd.dev->device_id);
606 	its_encode_size(cmd, size - 1);
607 	its_encode_itt(cmd, itt_addr);
608 	its_encode_valid(cmd, desc->its_mapd_cmd.valid);
609 
610 	its_fixup_cmd(cmd);
611 
612 	return NULL;
613 }
614 
615 static struct its_collection *its_build_mapc_cmd(struct its_node *its,
616 						 struct its_cmd_block *cmd,
617 						 struct its_cmd_desc *desc)
618 {
619 	its_encode_cmd(cmd, GITS_CMD_MAPC);
620 	its_encode_collection(cmd, desc->its_mapc_cmd.col->col_id);
621 	its_encode_target(cmd, desc->its_mapc_cmd.col->target_address);
622 	its_encode_valid(cmd, desc->its_mapc_cmd.valid);
623 
624 	its_fixup_cmd(cmd);
625 
626 	return desc->its_mapc_cmd.col;
627 }
628 
629 static struct its_collection *its_build_mapti_cmd(struct its_node *its,
630 						  struct its_cmd_block *cmd,
631 						  struct its_cmd_desc *desc)
632 {
633 	struct its_collection *col;
634 
635 	col = dev_event_to_col(desc->its_mapti_cmd.dev,
636 			       desc->its_mapti_cmd.event_id);
637 
638 	its_encode_cmd(cmd, GITS_CMD_MAPTI);
639 	its_encode_devid(cmd, desc->its_mapti_cmd.dev->device_id);
640 	its_encode_event_id(cmd, desc->its_mapti_cmd.event_id);
641 	its_encode_phys_id(cmd, desc->its_mapti_cmd.phys_id);
642 	its_encode_collection(cmd, col->col_id);
643 
644 	its_fixup_cmd(cmd);
645 
646 	return valid_col(col);
647 }
648 
649 static struct its_collection *its_build_movi_cmd(struct its_node *its,
650 						 struct its_cmd_block *cmd,
651 						 struct its_cmd_desc *desc)
652 {
653 	struct its_collection *col;
654 
655 	col = dev_event_to_col(desc->its_movi_cmd.dev,
656 			       desc->its_movi_cmd.event_id);
657 
658 	its_encode_cmd(cmd, GITS_CMD_MOVI);
659 	its_encode_devid(cmd, desc->its_movi_cmd.dev->device_id);
660 	its_encode_event_id(cmd, desc->its_movi_cmd.event_id);
661 	its_encode_collection(cmd, desc->its_movi_cmd.col->col_id);
662 
663 	its_fixup_cmd(cmd);
664 
665 	return valid_col(col);
666 }
667 
668 static struct its_collection *its_build_discard_cmd(struct its_node *its,
669 						    struct its_cmd_block *cmd,
670 						    struct its_cmd_desc *desc)
671 {
672 	struct its_collection *col;
673 
674 	col = dev_event_to_col(desc->its_discard_cmd.dev,
675 			       desc->its_discard_cmd.event_id);
676 
677 	its_encode_cmd(cmd, GITS_CMD_DISCARD);
678 	its_encode_devid(cmd, desc->its_discard_cmd.dev->device_id);
679 	its_encode_event_id(cmd, desc->its_discard_cmd.event_id);
680 
681 	its_fixup_cmd(cmd);
682 
683 	return valid_col(col);
684 }
685 
686 static struct its_collection *its_build_inv_cmd(struct its_node *its,
687 						struct its_cmd_block *cmd,
688 						struct its_cmd_desc *desc)
689 {
690 	struct its_collection *col;
691 
692 	col = dev_event_to_col(desc->its_inv_cmd.dev,
693 			       desc->its_inv_cmd.event_id);
694 
695 	its_encode_cmd(cmd, GITS_CMD_INV);
696 	its_encode_devid(cmd, desc->its_inv_cmd.dev->device_id);
697 	its_encode_event_id(cmd, desc->its_inv_cmd.event_id);
698 
699 	its_fixup_cmd(cmd);
700 
701 	return valid_col(col);
702 }
703 
704 static struct its_collection *its_build_int_cmd(struct its_node *its,
705 						struct its_cmd_block *cmd,
706 						struct its_cmd_desc *desc)
707 {
708 	struct its_collection *col;
709 
710 	col = dev_event_to_col(desc->its_int_cmd.dev,
711 			       desc->its_int_cmd.event_id);
712 
713 	its_encode_cmd(cmd, GITS_CMD_INT);
714 	its_encode_devid(cmd, desc->its_int_cmd.dev->device_id);
715 	its_encode_event_id(cmd, desc->its_int_cmd.event_id);
716 
717 	its_fixup_cmd(cmd);
718 
719 	return valid_col(col);
720 }
721 
722 static struct its_collection *its_build_clear_cmd(struct its_node *its,
723 						  struct its_cmd_block *cmd,
724 						  struct its_cmd_desc *desc)
725 {
726 	struct its_collection *col;
727 
728 	col = dev_event_to_col(desc->its_clear_cmd.dev,
729 			       desc->its_clear_cmd.event_id);
730 
731 	its_encode_cmd(cmd, GITS_CMD_CLEAR);
732 	its_encode_devid(cmd, desc->its_clear_cmd.dev->device_id);
733 	its_encode_event_id(cmd, desc->its_clear_cmd.event_id);
734 
735 	its_fixup_cmd(cmd);
736 
737 	return valid_col(col);
738 }
739 
740 static struct its_collection *its_build_invall_cmd(struct its_node *its,
741 						   struct its_cmd_block *cmd,
742 						   struct its_cmd_desc *desc)
743 {
744 	its_encode_cmd(cmd, GITS_CMD_INVALL);
745 	its_encode_collection(cmd, desc->its_invall_cmd.col->col_id);
746 
747 	its_fixup_cmd(cmd);
748 
749 	return desc->its_invall_cmd.col;
750 }
751 
752 static struct its_vpe *its_build_vinvall_cmd(struct its_node *its,
753 					     struct its_cmd_block *cmd,
754 					     struct its_cmd_desc *desc)
755 {
756 	its_encode_cmd(cmd, GITS_CMD_VINVALL);
757 	its_encode_vpeid(cmd, desc->its_vinvall_cmd.vpe->vpe_id);
758 
759 	its_fixup_cmd(cmd);
760 
761 	return valid_vpe(its, desc->its_vinvall_cmd.vpe);
762 }
763 
764 static struct its_vpe *its_build_vmapp_cmd(struct its_node *its,
765 					   struct its_cmd_block *cmd,
766 					   struct its_cmd_desc *desc)
767 {
768 	unsigned long vpt_addr, vconf_addr;
769 	u64 target;
770 	bool alloc;
771 
772 	its_encode_cmd(cmd, GITS_CMD_VMAPP);
773 	its_encode_vpeid(cmd, desc->its_vmapp_cmd.vpe->vpe_id);
774 	its_encode_valid(cmd, desc->its_vmapp_cmd.valid);
775 
776 	if (!desc->its_vmapp_cmd.valid) {
777 		if (is_v4_1(its)) {
778 			alloc = !atomic_dec_return(&desc->its_vmapp_cmd.vpe->vmapp_count);
779 			its_encode_alloc(cmd, alloc);
780 		}
781 
782 		goto out;
783 	}
784 
785 	vpt_addr = virt_to_phys(page_address(desc->its_vmapp_cmd.vpe->vpt_page));
786 	target = desc->its_vmapp_cmd.col->target_address + its->vlpi_redist_offset;
787 
788 	its_encode_target(cmd, target);
789 	its_encode_vpt_addr(cmd, vpt_addr);
790 	its_encode_vpt_size(cmd, LPI_NRBITS - 1);
791 
792 	if (!is_v4_1(its))
793 		goto out;
794 
795 	vconf_addr = virt_to_phys(page_address(desc->its_vmapp_cmd.vpe->its_vm->vprop_page));
796 
797 	alloc = !atomic_fetch_inc(&desc->its_vmapp_cmd.vpe->vmapp_count);
798 
799 	its_encode_alloc(cmd, alloc);
800 
801 	/*
802 	 * GICv4.1 provides a way to get the VLPI state, which needs the vPE
803 	 * to be unmapped first, and in this case, we may remap the vPE
804 	 * back while the VPT is not empty. So we can't assume that the
805 	 * VPT is empty on map. This is why we never advertise PTZ.
806 	 */
807 	its_encode_ptz(cmd, false);
808 	its_encode_vconf_addr(cmd, vconf_addr);
809 	its_encode_vmapp_default_db(cmd, desc->its_vmapp_cmd.vpe->vpe_db_lpi);
810 
811 out:
812 	its_fixup_cmd(cmd);
813 
814 	return valid_vpe(its, desc->its_vmapp_cmd.vpe);
815 }
816 
817 static struct its_vpe *its_build_vmapti_cmd(struct its_node *its,
818 					    struct its_cmd_block *cmd,
819 					    struct its_cmd_desc *desc)
820 {
821 	u32 db;
822 
823 	if (!is_v4_1(its) && desc->its_vmapti_cmd.db_enabled)
824 		db = desc->its_vmapti_cmd.vpe->vpe_db_lpi;
825 	else
826 		db = 1023;
827 
828 	its_encode_cmd(cmd, GITS_CMD_VMAPTI);
829 	its_encode_devid(cmd, desc->its_vmapti_cmd.dev->device_id);
830 	its_encode_vpeid(cmd, desc->its_vmapti_cmd.vpe->vpe_id);
831 	its_encode_event_id(cmd, desc->its_vmapti_cmd.event_id);
832 	its_encode_db_phys_id(cmd, db);
833 	its_encode_virt_id(cmd, desc->its_vmapti_cmd.virt_id);
834 
835 	its_fixup_cmd(cmd);
836 
837 	return valid_vpe(its, desc->its_vmapti_cmd.vpe);
838 }
839 
840 static struct its_vpe *its_build_vmovi_cmd(struct its_node *its,
841 					   struct its_cmd_block *cmd,
842 					   struct its_cmd_desc *desc)
843 {
844 	u32 db;
845 
846 	if (!is_v4_1(its) && desc->its_vmovi_cmd.db_enabled)
847 		db = desc->its_vmovi_cmd.vpe->vpe_db_lpi;
848 	else
849 		db = 1023;
850 
851 	its_encode_cmd(cmd, GITS_CMD_VMOVI);
852 	its_encode_devid(cmd, desc->its_vmovi_cmd.dev->device_id);
853 	its_encode_vpeid(cmd, desc->its_vmovi_cmd.vpe->vpe_id);
854 	its_encode_event_id(cmd, desc->its_vmovi_cmd.event_id);
855 	its_encode_db_phys_id(cmd, db);
856 	its_encode_db_valid(cmd, true);
857 
858 	its_fixup_cmd(cmd);
859 
860 	return valid_vpe(its, desc->its_vmovi_cmd.vpe);
861 }
862 
863 static struct its_vpe *its_build_vmovp_cmd(struct its_node *its,
864 					   struct its_cmd_block *cmd,
865 					   struct its_cmd_desc *desc)
866 {
867 	u64 target;
868 
869 	target = desc->its_vmovp_cmd.col->target_address + its->vlpi_redist_offset;
870 	its_encode_cmd(cmd, GITS_CMD_VMOVP);
871 	its_encode_seq_num(cmd, desc->its_vmovp_cmd.seq_num);
872 	its_encode_its_list(cmd, desc->its_vmovp_cmd.its_list);
873 	its_encode_vpeid(cmd, desc->its_vmovp_cmd.vpe->vpe_id);
874 	its_encode_target(cmd, target);
875 
876 	if (is_v4_1(its)) {
877 		its_encode_db(cmd, true);
878 		its_encode_vmovp_default_db(cmd, desc->its_vmovp_cmd.vpe->vpe_db_lpi);
879 	}
880 
881 	its_fixup_cmd(cmd);
882 
883 	return valid_vpe(its, desc->its_vmovp_cmd.vpe);
884 }
885 
886 static struct its_vpe *its_build_vinv_cmd(struct its_node *its,
887 					  struct its_cmd_block *cmd,
888 					  struct its_cmd_desc *desc)
889 {
890 	struct its_vlpi_map *map;
891 
892 	map = dev_event_to_vlpi_map(desc->its_inv_cmd.dev,
893 				    desc->its_inv_cmd.event_id);
894 
895 	its_encode_cmd(cmd, GITS_CMD_INV);
896 	its_encode_devid(cmd, desc->its_inv_cmd.dev->device_id);
897 	its_encode_event_id(cmd, desc->its_inv_cmd.event_id);
898 
899 	its_fixup_cmd(cmd);
900 
901 	return valid_vpe(its, map->vpe);
902 }
903 
904 static struct its_vpe *its_build_vint_cmd(struct its_node *its,
905 					  struct its_cmd_block *cmd,
906 					  struct its_cmd_desc *desc)
907 {
908 	struct its_vlpi_map *map;
909 
910 	map = dev_event_to_vlpi_map(desc->its_int_cmd.dev,
911 				    desc->its_int_cmd.event_id);
912 
913 	its_encode_cmd(cmd, GITS_CMD_INT);
914 	its_encode_devid(cmd, desc->its_int_cmd.dev->device_id);
915 	its_encode_event_id(cmd, desc->its_int_cmd.event_id);
916 
917 	its_fixup_cmd(cmd);
918 
919 	return valid_vpe(its, map->vpe);
920 }
921 
922 static struct its_vpe *its_build_vclear_cmd(struct its_node *its,
923 					    struct its_cmd_block *cmd,
924 					    struct its_cmd_desc *desc)
925 {
926 	struct its_vlpi_map *map;
927 
928 	map = dev_event_to_vlpi_map(desc->its_clear_cmd.dev,
929 				    desc->its_clear_cmd.event_id);
930 
931 	its_encode_cmd(cmd, GITS_CMD_CLEAR);
932 	its_encode_devid(cmd, desc->its_clear_cmd.dev->device_id);
933 	its_encode_event_id(cmd, desc->its_clear_cmd.event_id);
934 
935 	its_fixup_cmd(cmd);
936 
937 	return valid_vpe(its, map->vpe);
938 }
939 
940 static struct its_vpe *its_build_invdb_cmd(struct its_node *its,
941 					   struct its_cmd_block *cmd,
942 					   struct its_cmd_desc *desc)
943 {
944 	if (WARN_ON(!is_v4_1(its)))
945 		return NULL;
946 
947 	its_encode_cmd(cmd, GITS_CMD_INVDB);
948 	its_encode_vpeid(cmd, desc->its_invdb_cmd.vpe->vpe_id);
949 
950 	its_fixup_cmd(cmd);
951 
952 	return valid_vpe(its, desc->its_invdb_cmd.vpe);
953 }
954 
955 static struct its_vpe *its_build_vsgi_cmd(struct its_node *its,
956 					  struct its_cmd_block *cmd,
957 					  struct its_cmd_desc *desc)
958 {
959 	if (WARN_ON(!is_v4_1(its)))
960 		return NULL;
961 
962 	its_encode_cmd(cmd, GITS_CMD_VSGI);
963 	its_encode_vpeid(cmd, desc->its_vsgi_cmd.vpe->vpe_id);
964 	its_encode_sgi_intid(cmd, desc->its_vsgi_cmd.sgi);
965 	its_encode_sgi_priority(cmd, desc->its_vsgi_cmd.priority);
966 	its_encode_sgi_group(cmd, desc->its_vsgi_cmd.group);
967 	its_encode_sgi_clear(cmd, desc->its_vsgi_cmd.clear);
968 	its_encode_sgi_enable(cmd, desc->its_vsgi_cmd.enable);
969 
970 	its_fixup_cmd(cmd);
971 
972 	return valid_vpe(its, desc->its_vsgi_cmd.vpe);
973 }
974 
975 static u64 its_cmd_ptr_to_offset(struct its_node *its,
976 				 struct its_cmd_block *ptr)
977 {
978 	return (ptr - its->cmd_base) * sizeof(*ptr);
979 }
980 
981 static int its_queue_full(struct its_node *its)
982 {
983 	int widx;
984 	int ridx;
985 
986 	widx = its->cmd_write - its->cmd_base;
987 	ridx = readl_relaxed(its->base + GITS_CREADR) / sizeof(struct its_cmd_block);
988 
989 	/* This is incredibly unlikely to happen, unless the ITS locks up. */
990 	if (((widx + 1) % ITS_CMD_QUEUE_NR_ENTRIES) == ridx)
991 		return 1;
992 
993 	return 0;
994 }
995 
996 static struct its_cmd_block *its_allocate_entry(struct its_node *its)
997 {
998 	struct its_cmd_block *cmd;
999 	u32 count = 1000000;	/* 1s! */
1000 
1001 	while (its_queue_full(its)) {
1002 		count--;
1003 		if (!count) {
1004 			pr_err_ratelimited("ITS queue not draining\n");
1005 			return NULL;
1006 		}
1007 		cpu_relax();
1008 		udelay(1);
1009 	}
1010 
1011 	cmd = its->cmd_write++;
1012 
1013 	/* Handle queue wrapping */
1014 	if (its->cmd_write == (its->cmd_base + ITS_CMD_QUEUE_NR_ENTRIES))
1015 		its->cmd_write = its->cmd_base;
1016 
1017 	/* Clear command  */
1018 	cmd->raw_cmd[0] = 0;
1019 	cmd->raw_cmd[1] = 0;
1020 	cmd->raw_cmd[2] = 0;
1021 	cmd->raw_cmd[3] = 0;
1022 
1023 	return cmd;
1024 }
1025 
1026 static struct its_cmd_block *its_post_commands(struct its_node *its)
1027 {
1028 	u64 wr = its_cmd_ptr_to_offset(its, its->cmd_write);
1029 
1030 	writel_relaxed(wr, its->base + GITS_CWRITER);
1031 
1032 	return its->cmd_write;
1033 }
1034 
1035 static void its_flush_cmd(struct its_node *its, struct its_cmd_block *cmd)
1036 {
1037 	/*
1038 	 * Make sure the commands written to memory are observable by
1039 	 * the ITS.
1040 	 */
1041 	if (its->flags & ITS_FLAGS_CMDQ_NEEDS_FLUSHING)
1042 		gic_flush_dcache_to_poc(cmd, sizeof(*cmd));
1043 	else
1044 		dsb(ishst);
1045 }
1046 
1047 static int its_wait_for_range_completion(struct its_node *its,
1048 					 u64	prev_idx,
1049 					 struct its_cmd_block *to)
1050 {
1051 	u64 rd_idx, to_idx, linear_idx;
1052 	u32 count = 1000000;	/* 1s! */
1053 
1054 	/* Linearize to_idx if the command set has wrapped around */
1055 	to_idx = its_cmd_ptr_to_offset(its, to);
1056 	if (to_idx < prev_idx)
1057 		to_idx += ITS_CMD_QUEUE_SZ;
1058 
1059 	linear_idx = prev_idx;
1060 
1061 	while (1) {
1062 		s64 delta;
1063 
1064 		rd_idx = readl_relaxed(its->base + GITS_CREADR);
1065 
1066 		/*
1067 		 * Compute the read pointer progress, taking the
1068 		 * potential wrap-around into account.
1069 		 */
1070 		delta = rd_idx - prev_idx;
1071 		if (rd_idx < prev_idx)
1072 			delta += ITS_CMD_QUEUE_SZ;
1073 
1074 		linear_idx += delta;
1075 		if (linear_idx >= to_idx)
1076 			break;
1077 
1078 		count--;
1079 		if (!count) {
1080 			pr_err_ratelimited("ITS queue timeout (%llu %llu)\n",
1081 					   to_idx, linear_idx);
1082 			return -1;
1083 		}
1084 		prev_idx = rd_idx;
1085 		cpu_relax();
1086 		udelay(1);
1087 	}
1088 
1089 	return 0;
1090 }
1091 
1092 /* Warning, macro hell follows */
1093 #define BUILD_SINGLE_CMD_FUNC(name, buildtype, synctype, buildfn)	\
1094 void name(struct its_node *its,						\
1095 	  buildtype builder,						\
1096 	  struct its_cmd_desc *desc)					\
1097 {									\
1098 	struct its_cmd_block *cmd, *sync_cmd, *next_cmd;		\
1099 	synctype *sync_obj;						\
1100 	unsigned long flags;						\
1101 	u64 rd_idx;							\
1102 									\
1103 	raw_spin_lock_irqsave(&its->lock, flags);			\
1104 									\
1105 	cmd = its_allocate_entry(its);					\
1106 	if (!cmd) {		/* We're soooooo screewed... */		\
1107 		raw_spin_unlock_irqrestore(&its->lock, flags);		\
1108 		return;							\
1109 	}								\
1110 	sync_obj = builder(its, cmd, desc);				\
1111 	its_flush_cmd(its, cmd);					\
1112 									\
1113 	if (sync_obj) {							\
1114 		sync_cmd = its_allocate_entry(its);			\
1115 		if (!sync_cmd)						\
1116 			goto post;					\
1117 									\
1118 		buildfn(its, sync_cmd, sync_obj);			\
1119 		its_flush_cmd(its, sync_cmd);				\
1120 	}								\
1121 									\
1122 post:									\
1123 	rd_idx = readl_relaxed(its->base + GITS_CREADR);		\
1124 	next_cmd = its_post_commands(its);				\
1125 	raw_spin_unlock_irqrestore(&its->lock, flags);			\
1126 									\
1127 	if (its_wait_for_range_completion(its, rd_idx, next_cmd))	\
1128 		pr_err_ratelimited("ITS cmd %ps failed\n", builder);	\
1129 }
1130 
1131 static void its_build_sync_cmd(struct its_node *its,
1132 			       struct its_cmd_block *sync_cmd,
1133 			       struct its_collection *sync_col)
1134 {
1135 	its_encode_cmd(sync_cmd, GITS_CMD_SYNC);
1136 	its_encode_target(sync_cmd, sync_col->target_address);
1137 
1138 	its_fixup_cmd(sync_cmd);
1139 }
1140 
1141 static BUILD_SINGLE_CMD_FUNC(its_send_single_command, its_cmd_builder_t,
1142 			     struct its_collection, its_build_sync_cmd)
1143 
1144 static void its_build_vsync_cmd(struct its_node *its,
1145 				struct its_cmd_block *sync_cmd,
1146 				struct its_vpe *sync_vpe)
1147 {
1148 	its_encode_cmd(sync_cmd, GITS_CMD_VSYNC);
1149 	its_encode_vpeid(sync_cmd, sync_vpe->vpe_id);
1150 
1151 	its_fixup_cmd(sync_cmd);
1152 }
1153 
1154 static BUILD_SINGLE_CMD_FUNC(its_send_single_vcommand, its_cmd_vbuilder_t,
1155 			     struct its_vpe, its_build_vsync_cmd)
1156 
1157 static void its_send_int(struct its_device *dev, u32 event_id)
1158 {
1159 	struct its_cmd_desc desc;
1160 
1161 	desc.its_int_cmd.dev = dev;
1162 	desc.its_int_cmd.event_id = event_id;
1163 
1164 	its_send_single_command(dev->its, its_build_int_cmd, &desc);
1165 }
1166 
1167 static void its_send_clear(struct its_device *dev, u32 event_id)
1168 {
1169 	struct its_cmd_desc desc;
1170 
1171 	desc.its_clear_cmd.dev = dev;
1172 	desc.its_clear_cmd.event_id = event_id;
1173 
1174 	its_send_single_command(dev->its, its_build_clear_cmd, &desc);
1175 }
1176 
1177 static void its_send_inv(struct its_device *dev, u32 event_id)
1178 {
1179 	struct its_cmd_desc desc;
1180 
1181 	desc.its_inv_cmd.dev = dev;
1182 	desc.its_inv_cmd.event_id = event_id;
1183 
1184 	its_send_single_command(dev->its, its_build_inv_cmd, &desc);
1185 }
1186 
1187 static void its_send_mapd(struct its_device *dev, int valid)
1188 {
1189 	struct its_cmd_desc desc;
1190 
1191 	desc.its_mapd_cmd.dev = dev;
1192 	desc.its_mapd_cmd.valid = !!valid;
1193 
1194 	its_send_single_command(dev->its, its_build_mapd_cmd, &desc);
1195 }
1196 
1197 static void its_send_mapc(struct its_node *its, struct its_collection *col,
1198 			  int valid)
1199 {
1200 	struct its_cmd_desc desc;
1201 
1202 	desc.its_mapc_cmd.col = col;
1203 	desc.its_mapc_cmd.valid = !!valid;
1204 
1205 	its_send_single_command(its, its_build_mapc_cmd, &desc);
1206 }
1207 
1208 static void its_send_mapti(struct its_device *dev, u32 irq_id, u32 id)
1209 {
1210 	struct its_cmd_desc desc;
1211 
1212 	desc.its_mapti_cmd.dev = dev;
1213 	desc.its_mapti_cmd.phys_id = irq_id;
1214 	desc.its_mapti_cmd.event_id = id;
1215 
1216 	its_send_single_command(dev->its, its_build_mapti_cmd, &desc);
1217 }
1218 
1219 static void its_send_movi(struct its_device *dev,
1220 			  struct its_collection *col, u32 id)
1221 {
1222 	struct its_cmd_desc desc;
1223 
1224 	desc.its_movi_cmd.dev = dev;
1225 	desc.its_movi_cmd.col = col;
1226 	desc.its_movi_cmd.event_id = id;
1227 
1228 	its_send_single_command(dev->its, its_build_movi_cmd, &desc);
1229 }
1230 
1231 static void its_send_discard(struct its_device *dev, u32 id)
1232 {
1233 	struct its_cmd_desc desc;
1234 
1235 	desc.its_discard_cmd.dev = dev;
1236 	desc.its_discard_cmd.event_id = id;
1237 
1238 	its_send_single_command(dev->its, its_build_discard_cmd, &desc);
1239 }
1240 
1241 static void its_send_invall(struct its_node *its, struct its_collection *col)
1242 {
1243 	struct its_cmd_desc desc;
1244 
1245 	desc.its_invall_cmd.col = col;
1246 
1247 	its_send_single_command(its, its_build_invall_cmd, &desc);
1248 }
1249 
1250 static void its_send_vmapti(struct its_device *dev, u32 id)
1251 {
1252 	struct its_vlpi_map *map = dev_event_to_vlpi_map(dev, id);
1253 	struct its_cmd_desc desc;
1254 
1255 	desc.its_vmapti_cmd.vpe = map->vpe;
1256 	desc.its_vmapti_cmd.dev = dev;
1257 	desc.its_vmapti_cmd.virt_id = map->vintid;
1258 	desc.its_vmapti_cmd.event_id = id;
1259 	desc.its_vmapti_cmd.db_enabled = map->db_enabled;
1260 
1261 	its_send_single_vcommand(dev->its, its_build_vmapti_cmd, &desc);
1262 }
1263 
1264 static void its_send_vmovi(struct its_device *dev, u32 id)
1265 {
1266 	struct its_vlpi_map *map = dev_event_to_vlpi_map(dev, id);
1267 	struct its_cmd_desc desc;
1268 
1269 	desc.its_vmovi_cmd.vpe = map->vpe;
1270 	desc.its_vmovi_cmd.dev = dev;
1271 	desc.its_vmovi_cmd.event_id = id;
1272 	desc.its_vmovi_cmd.db_enabled = map->db_enabled;
1273 
1274 	its_send_single_vcommand(dev->its, its_build_vmovi_cmd, &desc);
1275 }
1276 
1277 static void its_send_vmapp(struct its_node *its,
1278 			   struct its_vpe *vpe, bool valid)
1279 {
1280 	struct its_cmd_desc desc;
1281 
1282 	desc.its_vmapp_cmd.vpe = vpe;
1283 	desc.its_vmapp_cmd.valid = valid;
1284 	desc.its_vmapp_cmd.col = &its->collections[vpe->col_idx];
1285 
1286 	its_send_single_vcommand(its, its_build_vmapp_cmd, &desc);
1287 }
1288 
1289 static void its_send_vmovp(struct its_vpe *vpe)
1290 {
1291 	struct its_cmd_desc desc = {};
1292 	struct its_node *its;
1293 	unsigned long flags;
1294 	int col_id = vpe->col_idx;
1295 
1296 	desc.its_vmovp_cmd.vpe = vpe;
1297 
1298 	if (!its_list_map) {
1299 		its = list_first_entry(&its_nodes, struct its_node, entry);
1300 		desc.its_vmovp_cmd.col = &its->collections[col_id];
1301 		its_send_single_vcommand(its, its_build_vmovp_cmd, &desc);
1302 		return;
1303 	}
1304 
1305 	/*
1306 	 * Yet another marvel of the architecture. If using the
1307 	 * its_list "feature", we need to make sure that all ITSs
1308 	 * receive all VMOVP commands in the same order. The only way
1309 	 * to guarantee this is to make vmovp a serialization point.
1310 	 *
1311 	 * Wall <-- Head.
1312 	 */
1313 	raw_spin_lock_irqsave(&vmovp_lock, flags);
1314 
1315 	desc.its_vmovp_cmd.seq_num = vmovp_seq_num++;
1316 	desc.its_vmovp_cmd.its_list = get_its_list(vpe->its_vm);
1317 
1318 	/* Emit VMOVPs */
1319 	list_for_each_entry(its, &its_nodes, entry) {
1320 		if (!is_v4(its))
1321 			continue;
1322 
1323 		if (!require_its_list_vmovp(vpe->its_vm, its))
1324 			continue;
1325 
1326 		desc.its_vmovp_cmd.col = &its->collections[col_id];
1327 		its_send_single_vcommand(its, its_build_vmovp_cmd, &desc);
1328 	}
1329 
1330 	raw_spin_unlock_irqrestore(&vmovp_lock, flags);
1331 }
1332 
1333 static void its_send_vinvall(struct its_node *its, struct its_vpe *vpe)
1334 {
1335 	struct its_cmd_desc desc;
1336 
1337 	desc.its_vinvall_cmd.vpe = vpe;
1338 	its_send_single_vcommand(its, its_build_vinvall_cmd, &desc);
1339 }
1340 
1341 static void its_send_vinv(struct its_device *dev, u32 event_id)
1342 {
1343 	struct its_cmd_desc desc;
1344 
1345 	/*
1346 	 * There is no real VINV command. This is just a normal INV,
1347 	 * with a VSYNC instead of a SYNC.
1348 	 */
1349 	desc.its_inv_cmd.dev = dev;
1350 	desc.its_inv_cmd.event_id = event_id;
1351 
1352 	its_send_single_vcommand(dev->its, its_build_vinv_cmd, &desc);
1353 }
1354 
1355 static void its_send_vint(struct its_device *dev, u32 event_id)
1356 {
1357 	struct its_cmd_desc desc;
1358 
1359 	/*
1360 	 * There is no real VINT command. This is just a normal INT,
1361 	 * with a VSYNC instead of a SYNC.
1362 	 */
1363 	desc.its_int_cmd.dev = dev;
1364 	desc.its_int_cmd.event_id = event_id;
1365 
1366 	its_send_single_vcommand(dev->its, its_build_vint_cmd, &desc);
1367 }
1368 
1369 static void its_send_vclear(struct its_device *dev, u32 event_id)
1370 {
1371 	struct its_cmd_desc desc;
1372 
1373 	/*
1374 	 * There is no real VCLEAR command. This is just a normal CLEAR,
1375 	 * with a VSYNC instead of a SYNC.
1376 	 */
1377 	desc.its_clear_cmd.dev = dev;
1378 	desc.its_clear_cmd.event_id = event_id;
1379 
1380 	its_send_single_vcommand(dev->its, its_build_vclear_cmd, &desc);
1381 }
1382 
1383 static void its_send_invdb(struct its_node *its, struct its_vpe *vpe)
1384 {
1385 	struct its_cmd_desc desc;
1386 
1387 	desc.its_invdb_cmd.vpe = vpe;
1388 	its_send_single_vcommand(its, its_build_invdb_cmd, &desc);
1389 }
1390 
1391 /*
1392  * irqchip functions - assumes MSI, mostly.
1393  */
1394 static void lpi_write_config(struct irq_data *d, u8 clr, u8 set)
1395 {
1396 	struct its_vlpi_map *map = get_vlpi_map(d);
1397 	irq_hw_number_t hwirq;
1398 	void *va;
1399 	u8 *cfg;
1400 
1401 	if (map) {
1402 		va = page_address(map->vm->vprop_page);
1403 		hwirq = map->vintid;
1404 
1405 		/* Remember the updated property */
1406 		map->properties &= ~clr;
1407 		map->properties |= set | LPI_PROP_GROUP1;
1408 	} else {
1409 		va = gic_rdists->prop_table_va;
1410 		hwirq = d->hwirq;
1411 	}
1412 
1413 	cfg = va + hwirq - 8192;
1414 	*cfg &= ~clr;
1415 	*cfg |= set | LPI_PROP_GROUP1;
1416 
1417 	/*
1418 	 * Make the above write visible to the redistributors.
1419 	 * And yes, we're flushing exactly: One. Single. Byte.
1420 	 * Humpf...
1421 	 */
1422 	if (gic_rdists->flags & RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING)
1423 		gic_flush_dcache_to_poc(cfg, sizeof(*cfg));
1424 	else
1425 		dsb(ishst);
1426 }
1427 
1428 static void wait_for_syncr(void __iomem *rdbase)
1429 {
1430 	while (readl_relaxed(rdbase + GICR_SYNCR) & 1)
1431 		cpu_relax();
1432 }
1433 
1434 static void direct_lpi_inv(struct irq_data *d)
1435 {
1436 	struct its_vlpi_map *map = get_vlpi_map(d);
1437 	void __iomem *rdbase;
1438 	unsigned long flags;
1439 	u64 val;
1440 	int cpu;
1441 
1442 	if (map) {
1443 		struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1444 
1445 		WARN_ON(!is_v4_1(its_dev->its));
1446 
1447 		val  = GICR_INVLPIR_V;
1448 		val |= FIELD_PREP(GICR_INVLPIR_VPEID, map->vpe->vpe_id);
1449 		val |= FIELD_PREP(GICR_INVLPIR_INTID, map->vintid);
1450 	} else {
1451 		val = d->hwirq;
1452 	}
1453 
1454 	/* Target the redistributor this LPI is currently routed to */
1455 	cpu = irq_to_cpuid_lock(d, &flags);
1456 	raw_spin_lock(&gic_data_rdist_cpu(cpu)->rd_lock);
1457 	rdbase = per_cpu_ptr(gic_rdists->rdist, cpu)->rd_base;
1458 	gic_write_lpir(val, rdbase + GICR_INVLPIR);
1459 
1460 	wait_for_syncr(rdbase);
1461 	raw_spin_unlock(&gic_data_rdist_cpu(cpu)->rd_lock);
1462 	irq_to_cpuid_unlock(d, flags);
1463 }
1464 
1465 static void lpi_update_config(struct irq_data *d, u8 clr, u8 set)
1466 {
1467 	struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1468 
1469 	lpi_write_config(d, clr, set);
1470 	if (gic_rdists->has_direct_lpi &&
1471 	    (is_v4_1(its_dev->its) || !irqd_is_forwarded_to_vcpu(d)))
1472 		direct_lpi_inv(d);
1473 	else if (!irqd_is_forwarded_to_vcpu(d))
1474 		its_send_inv(its_dev, its_get_event_id(d));
1475 	else
1476 		its_send_vinv(its_dev, its_get_event_id(d));
1477 }
1478 
1479 static void its_vlpi_set_doorbell(struct irq_data *d, bool enable)
1480 {
1481 	struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1482 	u32 event = its_get_event_id(d);
1483 	struct its_vlpi_map *map;
1484 
1485 	/*
1486 	 * GICv4.1 does away with the per-LPI nonsense, nothing to do
1487 	 * here.
1488 	 */
1489 	if (is_v4_1(its_dev->its))
1490 		return;
1491 
1492 	map = dev_event_to_vlpi_map(its_dev, event);
1493 
1494 	if (map->db_enabled == enable)
1495 		return;
1496 
1497 	map->db_enabled = enable;
1498 
1499 	/*
1500 	 * More fun with the architecture:
1501 	 *
1502 	 * Ideally, we'd issue a VMAPTI to set the doorbell to its LPI
1503 	 * value or to 1023, depending on the enable bit. But that
1504 	 * would be issuing a mapping for an /existing/ DevID+EventID
1505 	 * pair, which is UNPREDICTABLE. Instead, let's issue a VMOVI
1506 	 * to the /same/ vPE, using this opportunity to adjust the
1507 	 * doorbell. Mouahahahaha. We loves it, Precious.
1508 	 */
1509 	its_send_vmovi(its_dev, event);
1510 }
1511 
1512 static void its_mask_irq(struct irq_data *d)
1513 {
1514 	if (irqd_is_forwarded_to_vcpu(d))
1515 		its_vlpi_set_doorbell(d, false);
1516 
1517 	lpi_update_config(d, LPI_PROP_ENABLED, 0);
1518 }
1519 
1520 static void its_unmask_irq(struct irq_data *d)
1521 {
1522 	if (irqd_is_forwarded_to_vcpu(d))
1523 		its_vlpi_set_doorbell(d, true);
1524 
1525 	lpi_update_config(d, 0, LPI_PROP_ENABLED);
1526 }
1527 
1528 static __maybe_unused u32 its_read_lpi_count(struct irq_data *d, int cpu)
1529 {
1530 	if (irqd_affinity_is_managed(d))
1531 		return atomic_read(&per_cpu_ptr(&cpu_lpi_count, cpu)->managed);
1532 
1533 	return atomic_read(&per_cpu_ptr(&cpu_lpi_count, cpu)->unmanaged);
1534 }
1535 
1536 static void its_inc_lpi_count(struct irq_data *d, int cpu)
1537 {
1538 	if (irqd_affinity_is_managed(d))
1539 		atomic_inc(&per_cpu_ptr(&cpu_lpi_count, cpu)->managed);
1540 	else
1541 		atomic_inc(&per_cpu_ptr(&cpu_lpi_count, cpu)->unmanaged);
1542 }
1543 
1544 static void its_dec_lpi_count(struct irq_data *d, int cpu)
1545 {
1546 	if (irqd_affinity_is_managed(d))
1547 		atomic_dec(&per_cpu_ptr(&cpu_lpi_count, cpu)->managed);
1548 	else
1549 		atomic_dec(&per_cpu_ptr(&cpu_lpi_count, cpu)->unmanaged);
1550 }
1551 
1552 static unsigned int cpumask_pick_least_loaded(struct irq_data *d,
1553 					      const struct cpumask *cpu_mask)
1554 {
1555 	unsigned int cpu = nr_cpu_ids, tmp;
1556 	int count = S32_MAX;
1557 
1558 	for_each_cpu(tmp, cpu_mask) {
1559 		int this_count = its_read_lpi_count(d, tmp);
1560 		if (this_count < count) {
1561 			cpu = tmp;
1562 		        count = this_count;
1563 		}
1564 	}
1565 
1566 	return cpu;
1567 }
1568 
1569 /*
1570  * As suggested by Thomas Gleixner in:
1571  * https://lore.kernel.org/r/87h80q2aoc.fsf@nanos.tec.linutronix.de
1572  */
1573 static int its_select_cpu(struct irq_data *d,
1574 			  const struct cpumask *aff_mask)
1575 {
1576 	struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1577 	cpumask_var_t tmpmask;
1578 	int cpu, node;
1579 
1580 	if (!alloc_cpumask_var(&tmpmask, GFP_ATOMIC))
1581 		return -ENOMEM;
1582 
1583 	node = its_dev->its->numa_node;
1584 
1585 	if (!irqd_affinity_is_managed(d)) {
1586 		/* First try the NUMA node */
1587 		if (node != NUMA_NO_NODE) {
1588 			/*
1589 			 * Try the intersection of the affinity mask and the
1590 			 * node mask (and the online mask, just to be safe).
1591 			 */
1592 			cpumask_and(tmpmask, cpumask_of_node(node), aff_mask);
1593 			cpumask_and(tmpmask, tmpmask, cpu_online_mask);
1594 
1595 			/*
1596 			 * Ideally, we would check if the mask is empty, and
1597 			 * try again on the full node here.
1598 			 *
1599 			 * But it turns out that the way ACPI describes the
1600 			 * affinity for ITSs only deals about memory, and
1601 			 * not target CPUs, so it cannot describe a single
1602 			 * ITS placed next to two NUMA nodes.
1603 			 *
1604 			 * Instead, just fallback on the online mask. This
1605 			 * diverges from Thomas' suggestion above.
1606 			 */
1607 			cpu = cpumask_pick_least_loaded(d, tmpmask);
1608 			if (cpu < nr_cpu_ids)
1609 				goto out;
1610 
1611 			/* If we can't cross sockets, give up */
1612 			if ((its_dev->its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144))
1613 				goto out;
1614 
1615 			/* If the above failed, expand the search */
1616 		}
1617 
1618 		/* Try the intersection of the affinity and online masks */
1619 		cpumask_and(tmpmask, aff_mask, cpu_online_mask);
1620 
1621 		/* If that doesn't fly, the online mask is the last resort */
1622 		if (cpumask_empty(tmpmask))
1623 			cpumask_copy(tmpmask, cpu_online_mask);
1624 
1625 		cpu = cpumask_pick_least_loaded(d, tmpmask);
1626 	} else {
1627 		cpumask_copy(tmpmask, aff_mask);
1628 
1629 		/* If we cannot cross sockets, limit the search to that node */
1630 		if ((its_dev->its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) &&
1631 		    node != NUMA_NO_NODE)
1632 			cpumask_and(tmpmask, tmpmask, cpumask_of_node(node));
1633 
1634 		cpu = cpumask_pick_least_loaded(d, tmpmask);
1635 	}
1636 out:
1637 	free_cpumask_var(tmpmask);
1638 
1639 	pr_debug("IRQ%d -> %*pbl CPU%d\n", d->irq, cpumask_pr_args(aff_mask), cpu);
1640 	return cpu;
1641 }
1642 
1643 static int its_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
1644 			    bool force)
1645 {
1646 	struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1647 	struct its_collection *target_col;
1648 	u32 id = its_get_event_id(d);
1649 	int cpu, prev_cpu;
1650 
1651 	/* A forwarded interrupt should use irq_set_vcpu_affinity */
1652 	if (irqd_is_forwarded_to_vcpu(d))
1653 		return -EINVAL;
1654 
1655 	prev_cpu = its_dev->event_map.col_map[id];
1656 	its_dec_lpi_count(d, prev_cpu);
1657 
1658 	if (!force)
1659 		cpu = its_select_cpu(d, mask_val);
1660 	else
1661 		cpu = cpumask_pick_least_loaded(d, mask_val);
1662 
1663 	if (cpu < 0 || cpu >= nr_cpu_ids)
1664 		goto err;
1665 
1666 	/* don't set the affinity when the target cpu is same as current one */
1667 	if (cpu != prev_cpu) {
1668 		target_col = &its_dev->its->collections[cpu];
1669 		its_send_movi(its_dev, target_col, id);
1670 		its_dev->event_map.col_map[id] = cpu;
1671 		irq_data_update_effective_affinity(d, cpumask_of(cpu));
1672 	}
1673 
1674 	its_inc_lpi_count(d, cpu);
1675 
1676 	return IRQ_SET_MASK_OK_DONE;
1677 
1678 err:
1679 	its_inc_lpi_count(d, prev_cpu);
1680 	return -EINVAL;
1681 }
1682 
1683 static u64 its_irq_get_msi_base(struct its_device *its_dev)
1684 {
1685 	struct its_node *its = its_dev->its;
1686 
1687 	return its->phys_base + GITS_TRANSLATER;
1688 }
1689 
1690 static void its_irq_compose_msi_msg(struct irq_data *d, struct msi_msg *msg)
1691 {
1692 	struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1693 	struct its_node *its;
1694 	u64 addr;
1695 
1696 	its = its_dev->its;
1697 	addr = its->get_msi_base(its_dev);
1698 
1699 	msg->address_lo		= lower_32_bits(addr);
1700 	msg->address_hi		= upper_32_bits(addr);
1701 	msg->data		= its_get_event_id(d);
1702 
1703 	iommu_dma_compose_msi_msg(irq_data_get_msi_desc(d), msg);
1704 }
1705 
1706 static int its_irq_set_irqchip_state(struct irq_data *d,
1707 				     enum irqchip_irq_state which,
1708 				     bool state)
1709 {
1710 	struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1711 	u32 event = its_get_event_id(d);
1712 
1713 	if (which != IRQCHIP_STATE_PENDING)
1714 		return -EINVAL;
1715 
1716 	if (irqd_is_forwarded_to_vcpu(d)) {
1717 		if (state)
1718 			its_send_vint(its_dev, event);
1719 		else
1720 			its_send_vclear(its_dev, event);
1721 	} else {
1722 		if (state)
1723 			its_send_int(its_dev, event);
1724 		else
1725 			its_send_clear(its_dev, event);
1726 	}
1727 
1728 	return 0;
1729 }
1730 
1731 static int its_irq_retrigger(struct irq_data *d)
1732 {
1733 	return !its_irq_set_irqchip_state(d, IRQCHIP_STATE_PENDING, true);
1734 }
1735 
1736 /*
1737  * Two favourable cases:
1738  *
1739  * (a) Either we have a GICv4.1, and all vPEs have to be mapped at all times
1740  *     for vSGI delivery
1741  *
1742  * (b) Or the ITSs do not use a list map, meaning that VMOVP is cheap enough
1743  *     and we're better off mapping all VPEs always
1744  *
1745  * If neither (a) nor (b) is true, then we map vPEs on demand.
1746  *
1747  */
1748 static bool gic_requires_eager_mapping(void)
1749 {
1750 	if (!its_list_map || gic_rdists->has_rvpeid)
1751 		return true;
1752 
1753 	return false;
1754 }
1755 
1756 static void its_map_vm(struct its_node *its, struct its_vm *vm)
1757 {
1758 	unsigned long flags;
1759 
1760 	if (gic_requires_eager_mapping())
1761 		return;
1762 
1763 	raw_spin_lock_irqsave(&vmovp_lock, flags);
1764 
1765 	/*
1766 	 * If the VM wasn't mapped yet, iterate over the vpes and get
1767 	 * them mapped now.
1768 	 */
1769 	vm->vlpi_count[its->list_nr]++;
1770 
1771 	if (vm->vlpi_count[its->list_nr] == 1) {
1772 		int i;
1773 
1774 		for (i = 0; i < vm->nr_vpes; i++) {
1775 			struct its_vpe *vpe = vm->vpes[i];
1776 			struct irq_data *d = irq_get_irq_data(vpe->irq);
1777 
1778 			/* Map the VPE to the first possible CPU */
1779 			vpe->col_idx = cpumask_first(cpu_online_mask);
1780 			its_send_vmapp(its, vpe, true);
1781 			its_send_vinvall(its, vpe);
1782 			irq_data_update_effective_affinity(d, cpumask_of(vpe->col_idx));
1783 		}
1784 	}
1785 
1786 	raw_spin_unlock_irqrestore(&vmovp_lock, flags);
1787 }
1788 
1789 static void its_unmap_vm(struct its_node *its, struct its_vm *vm)
1790 {
1791 	unsigned long flags;
1792 
1793 	/* Not using the ITS list? Everything is always mapped. */
1794 	if (gic_requires_eager_mapping())
1795 		return;
1796 
1797 	raw_spin_lock_irqsave(&vmovp_lock, flags);
1798 
1799 	if (!--vm->vlpi_count[its->list_nr]) {
1800 		int i;
1801 
1802 		for (i = 0; i < vm->nr_vpes; i++)
1803 			its_send_vmapp(its, vm->vpes[i], false);
1804 	}
1805 
1806 	raw_spin_unlock_irqrestore(&vmovp_lock, flags);
1807 }
1808 
1809 static int its_vlpi_map(struct irq_data *d, struct its_cmd_info *info)
1810 {
1811 	struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1812 	u32 event = its_get_event_id(d);
1813 	int ret = 0;
1814 
1815 	if (!info->map)
1816 		return -EINVAL;
1817 
1818 	raw_spin_lock(&its_dev->event_map.vlpi_lock);
1819 
1820 	if (!its_dev->event_map.vm) {
1821 		struct its_vlpi_map *maps;
1822 
1823 		maps = kcalloc(its_dev->event_map.nr_lpis, sizeof(*maps),
1824 			       GFP_ATOMIC);
1825 		if (!maps) {
1826 			ret = -ENOMEM;
1827 			goto out;
1828 		}
1829 
1830 		its_dev->event_map.vm = info->map->vm;
1831 		its_dev->event_map.vlpi_maps = maps;
1832 	} else if (its_dev->event_map.vm != info->map->vm) {
1833 		ret = -EINVAL;
1834 		goto out;
1835 	}
1836 
1837 	/* Get our private copy of the mapping information */
1838 	its_dev->event_map.vlpi_maps[event] = *info->map;
1839 
1840 	if (irqd_is_forwarded_to_vcpu(d)) {
1841 		/* Already mapped, move it around */
1842 		its_send_vmovi(its_dev, event);
1843 	} else {
1844 		/* Ensure all the VPEs are mapped on this ITS */
1845 		its_map_vm(its_dev->its, info->map->vm);
1846 
1847 		/*
1848 		 * Flag the interrupt as forwarded so that we can
1849 		 * start poking the virtual property table.
1850 		 */
1851 		irqd_set_forwarded_to_vcpu(d);
1852 
1853 		/* Write out the property to the prop table */
1854 		lpi_write_config(d, 0xff, info->map->properties);
1855 
1856 		/* Drop the physical mapping */
1857 		its_send_discard(its_dev, event);
1858 
1859 		/* and install the virtual one */
1860 		its_send_vmapti(its_dev, event);
1861 
1862 		/* Increment the number of VLPIs */
1863 		its_dev->event_map.nr_vlpis++;
1864 	}
1865 
1866 out:
1867 	raw_spin_unlock(&its_dev->event_map.vlpi_lock);
1868 	return ret;
1869 }
1870 
1871 static int its_vlpi_get(struct irq_data *d, struct its_cmd_info *info)
1872 {
1873 	struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1874 	struct its_vlpi_map *map;
1875 	int ret = 0;
1876 
1877 	raw_spin_lock(&its_dev->event_map.vlpi_lock);
1878 
1879 	map = get_vlpi_map(d);
1880 
1881 	if (!its_dev->event_map.vm || !map) {
1882 		ret = -EINVAL;
1883 		goto out;
1884 	}
1885 
1886 	/* Copy our mapping information to the incoming request */
1887 	*info->map = *map;
1888 
1889 out:
1890 	raw_spin_unlock(&its_dev->event_map.vlpi_lock);
1891 	return ret;
1892 }
1893 
1894 static int its_vlpi_unmap(struct irq_data *d)
1895 {
1896 	struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1897 	u32 event = its_get_event_id(d);
1898 	int ret = 0;
1899 
1900 	raw_spin_lock(&its_dev->event_map.vlpi_lock);
1901 
1902 	if (!its_dev->event_map.vm || !irqd_is_forwarded_to_vcpu(d)) {
1903 		ret = -EINVAL;
1904 		goto out;
1905 	}
1906 
1907 	/* Drop the virtual mapping */
1908 	its_send_discard(its_dev, event);
1909 
1910 	/* and restore the physical one */
1911 	irqd_clr_forwarded_to_vcpu(d);
1912 	its_send_mapti(its_dev, d->hwirq, event);
1913 	lpi_update_config(d, 0xff, (LPI_PROP_DEFAULT_PRIO |
1914 				    LPI_PROP_ENABLED |
1915 				    LPI_PROP_GROUP1));
1916 
1917 	/* Potentially unmap the VM from this ITS */
1918 	its_unmap_vm(its_dev->its, its_dev->event_map.vm);
1919 
1920 	/*
1921 	 * Drop the refcount and make the device available again if
1922 	 * this was the last VLPI.
1923 	 */
1924 	if (!--its_dev->event_map.nr_vlpis) {
1925 		its_dev->event_map.vm = NULL;
1926 		kfree(its_dev->event_map.vlpi_maps);
1927 	}
1928 
1929 out:
1930 	raw_spin_unlock(&its_dev->event_map.vlpi_lock);
1931 	return ret;
1932 }
1933 
1934 static int its_vlpi_prop_update(struct irq_data *d, struct its_cmd_info *info)
1935 {
1936 	struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1937 
1938 	if (!its_dev->event_map.vm || !irqd_is_forwarded_to_vcpu(d))
1939 		return -EINVAL;
1940 
1941 	if (info->cmd_type == PROP_UPDATE_AND_INV_VLPI)
1942 		lpi_update_config(d, 0xff, info->config);
1943 	else
1944 		lpi_write_config(d, 0xff, info->config);
1945 	its_vlpi_set_doorbell(d, !!(info->config & LPI_PROP_ENABLED));
1946 
1947 	return 0;
1948 }
1949 
1950 static int its_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
1951 {
1952 	struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1953 	struct its_cmd_info *info = vcpu_info;
1954 
1955 	/* Need a v4 ITS */
1956 	if (!is_v4(its_dev->its))
1957 		return -EINVAL;
1958 
1959 	/* Unmap request? */
1960 	if (!info)
1961 		return its_vlpi_unmap(d);
1962 
1963 	switch (info->cmd_type) {
1964 	case MAP_VLPI:
1965 		return its_vlpi_map(d, info);
1966 
1967 	case GET_VLPI:
1968 		return its_vlpi_get(d, info);
1969 
1970 	case PROP_UPDATE_VLPI:
1971 	case PROP_UPDATE_AND_INV_VLPI:
1972 		return its_vlpi_prop_update(d, info);
1973 
1974 	default:
1975 		return -EINVAL;
1976 	}
1977 }
1978 
1979 static struct irq_chip its_irq_chip = {
1980 	.name			= "ITS",
1981 	.irq_mask		= its_mask_irq,
1982 	.irq_unmask		= its_unmask_irq,
1983 	.irq_eoi		= irq_chip_eoi_parent,
1984 	.irq_set_affinity	= its_set_affinity,
1985 	.irq_compose_msi_msg	= its_irq_compose_msi_msg,
1986 	.irq_set_irqchip_state	= its_irq_set_irqchip_state,
1987 	.irq_retrigger		= its_irq_retrigger,
1988 	.irq_set_vcpu_affinity	= its_irq_set_vcpu_affinity,
1989 };
1990 
1991 
1992 /*
1993  * How we allocate LPIs:
1994  *
1995  * lpi_range_list contains ranges of LPIs that are to available to
1996  * allocate from. To allocate LPIs, just pick the first range that
1997  * fits the required allocation, and reduce it by the required
1998  * amount. Once empty, remove the range from the list.
1999  *
2000  * To free a range of LPIs, add a free range to the list, sort it and
2001  * merge the result if the new range happens to be adjacent to an
2002  * already free block.
2003  *
2004  * The consequence of the above is that allocation is cost is low, but
2005  * freeing is expensive. We assumes that freeing rarely occurs.
2006  */
2007 #define ITS_MAX_LPI_NRBITS	16 /* 64K LPIs */
2008 
2009 static DEFINE_MUTEX(lpi_range_lock);
2010 static LIST_HEAD(lpi_range_list);
2011 
2012 struct lpi_range {
2013 	struct list_head	entry;
2014 	u32			base_id;
2015 	u32			span;
2016 };
2017 
2018 static struct lpi_range *mk_lpi_range(u32 base, u32 span)
2019 {
2020 	struct lpi_range *range;
2021 
2022 	range = kmalloc(sizeof(*range), GFP_KERNEL);
2023 	if (range) {
2024 		range->base_id = base;
2025 		range->span = span;
2026 	}
2027 
2028 	return range;
2029 }
2030 
2031 static int alloc_lpi_range(u32 nr_lpis, u32 *base)
2032 {
2033 	struct lpi_range *range, *tmp;
2034 	int err = -ENOSPC;
2035 
2036 	mutex_lock(&lpi_range_lock);
2037 
2038 	list_for_each_entry_safe(range, tmp, &lpi_range_list, entry) {
2039 		if (range->span >= nr_lpis) {
2040 			*base = range->base_id;
2041 			range->base_id += nr_lpis;
2042 			range->span -= nr_lpis;
2043 
2044 			if (range->span == 0) {
2045 				list_del(&range->entry);
2046 				kfree(range);
2047 			}
2048 
2049 			err = 0;
2050 			break;
2051 		}
2052 	}
2053 
2054 	mutex_unlock(&lpi_range_lock);
2055 
2056 	pr_debug("ITS: alloc %u:%u\n", *base, nr_lpis);
2057 	return err;
2058 }
2059 
2060 static void merge_lpi_ranges(struct lpi_range *a, struct lpi_range *b)
2061 {
2062 	if (&a->entry == &lpi_range_list || &b->entry == &lpi_range_list)
2063 		return;
2064 	if (a->base_id + a->span != b->base_id)
2065 		return;
2066 	b->base_id = a->base_id;
2067 	b->span += a->span;
2068 	list_del(&a->entry);
2069 	kfree(a);
2070 }
2071 
2072 static int free_lpi_range(u32 base, u32 nr_lpis)
2073 {
2074 	struct lpi_range *new, *old;
2075 
2076 	new = mk_lpi_range(base, nr_lpis);
2077 	if (!new)
2078 		return -ENOMEM;
2079 
2080 	mutex_lock(&lpi_range_lock);
2081 
2082 	list_for_each_entry_reverse(old, &lpi_range_list, entry) {
2083 		if (old->base_id < base)
2084 			break;
2085 	}
2086 	/*
2087 	 * old is the last element with ->base_id smaller than base,
2088 	 * so new goes right after it. If there are no elements with
2089 	 * ->base_id smaller than base, &old->entry ends up pointing
2090 	 * at the head of the list, and inserting new it the start of
2091 	 * the list is the right thing to do in that case as well.
2092 	 */
2093 	list_add(&new->entry, &old->entry);
2094 	/*
2095 	 * Now check if we can merge with the preceding and/or
2096 	 * following ranges.
2097 	 */
2098 	merge_lpi_ranges(old, new);
2099 	merge_lpi_ranges(new, list_next_entry(new, entry));
2100 
2101 	mutex_unlock(&lpi_range_lock);
2102 	return 0;
2103 }
2104 
2105 static int __init its_lpi_init(u32 id_bits)
2106 {
2107 	u32 lpis = (1UL << id_bits) - 8192;
2108 	u32 numlpis;
2109 	int err;
2110 
2111 	numlpis = 1UL << GICD_TYPER_NUM_LPIS(gic_rdists->gicd_typer);
2112 
2113 	if (numlpis > 2 && !WARN_ON(numlpis > lpis)) {
2114 		lpis = numlpis;
2115 		pr_info("ITS: Using hypervisor restricted LPI range [%u]\n",
2116 			lpis);
2117 	}
2118 
2119 	/*
2120 	 * Initializing the allocator is just the same as freeing the
2121 	 * full range of LPIs.
2122 	 */
2123 	err = free_lpi_range(8192, lpis);
2124 	pr_debug("ITS: Allocator initialized for %u LPIs\n", lpis);
2125 	return err;
2126 }
2127 
2128 static unsigned long *its_lpi_alloc(int nr_irqs, u32 *base, int *nr_ids)
2129 {
2130 	unsigned long *bitmap = NULL;
2131 	int err = 0;
2132 
2133 	do {
2134 		err = alloc_lpi_range(nr_irqs, base);
2135 		if (!err)
2136 			break;
2137 
2138 		nr_irqs /= 2;
2139 	} while (nr_irqs > 0);
2140 
2141 	if (!nr_irqs)
2142 		err = -ENOSPC;
2143 
2144 	if (err)
2145 		goto out;
2146 
2147 	bitmap = bitmap_zalloc(nr_irqs, GFP_ATOMIC);
2148 	if (!bitmap)
2149 		goto out;
2150 
2151 	*nr_ids = nr_irqs;
2152 
2153 out:
2154 	if (!bitmap)
2155 		*base = *nr_ids = 0;
2156 
2157 	return bitmap;
2158 }
2159 
2160 static void its_lpi_free(unsigned long *bitmap, u32 base, u32 nr_ids)
2161 {
2162 	WARN_ON(free_lpi_range(base, nr_ids));
2163 	bitmap_free(bitmap);
2164 }
2165 
2166 static void gic_reset_prop_table(void *va)
2167 {
2168 	/* Priority 0xa0, Group-1, disabled */
2169 	memset(va, LPI_PROP_DEFAULT_PRIO | LPI_PROP_GROUP1, LPI_PROPBASE_SZ);
2170 
2171 	/* Make sure the GIC will observe the written configuration */
2172 	gic_flush_dcache_to_poc(va, LPI_PROPBASE_SZ);
2173 }
2174 
2175 static struct page *its_allocate_prop_table(gfp_t gfp_flags)
2176 {
2177 	struct page *prop_page;
2178 
2179 	prop_page = alloc_pages(gfp_flags, get_order(LPI_PROPBASE_SZ));
2180 	if (!prop_page)
2181 		return NULL;
2182 
2183 	gic_reset_prop_table(page_address(prop_page));
2184 
2185 	return prop_page;
2186 }
2187 
2188 static void its_free_prop_table(struct page *prop_page)
2189 {
2190 	free_pages((unsigned long)page_address(prop_page),
2191 		   get_order(LPI_PROPBASE_SZ));
2192 }
2193 
2194 static bool gic_check_reserved_range(phys_addr_t addr, unsigned long size)
2195 {
2196 	phys_addr_t start, end, addr_end;
2197 	u64 i;
2198 
2199 	/*
2200 	 * We don't bother checking for a kdump kernel as by
2201 	 * construction, the LPI tables are out of this kernel's
2202 	 * memory map.
2203 	 */
2204 	if (is_kdump_kernel())
2205 		return true;
2206 
2207 	addr_end = addr + size - 1;
2208 
2209 	for_each_reserved_mem_range(i, &start, &end) {
2210 		if (addr >= start && addr_end <= end)
2211 			return true;
2212 	}
2213 
2214 	/* Not found, not a good sign... */
2215 	pr_warn("GICv3: Expected reserved range [%pa:%pa], not found\n",
2216 		&addr, &addr_end);
2217 	add_taint(TAINT_CRAP, LOCKDEP_STILL_OK);
2218 	return false;
2219 }
2220 
2221 static int gic_reserve_range(phys_addr_t addr, unsigned long size)
2222 {
2223 	if (efi_enabled(EFI_CONFIG_TABLES))
2224 		return efi_mem_reserve_persistent(addr, size);
2225 
2226 	return 0;
2227 }
2228 
2229 static int __init its_setup_lpi_prop_table(void)
2230 {
2231 	if (gic_rdists->flags & RDIST_FLAGS_RD_TABLES_PREALLOCATED) {
2232 		u64 val;
2233 
2234 		val = gicr_read_propbaser(gic_data_rdist_rd_base() + GICR_PROPBASER);
2235 		lpi_id_bits = (val & GICR_PROPBASER_IDBITS_MASK) + 1;
2236 
2237 		gic_rdists->prop_table_pa = val & GENMASK_ULL(51, 12);
2238 		gic_rdists->prop_table_va = memremap(gic_rdists->prop_table_pa,
2239 						     LPI_PROPBASE_SZ,
2240 						     MEMREMAP_WB);
2241 		gic_reset_prop_table(gic_rdists->prop_table_va);
2242 	} else {
2243 		struct page *page;
2244 
2245 		lpi_id_bits = min_t(u32,
2246 				    GICD_TYPER_ID_BITS(gic_rdists->gicd_typer),
2247 				    ITS_MAX_LPI_NRBITS);
2248 		page = its_allocate_prop_table(GFP_NOWAIT);
2249 		if (!page) {
2250 			pr_err("Failed to allocate PROPBASE\n");
2251 			return -ENOMEM;
2252 		}
2253 
2254 		gic_rdists->prop_table_pa = page_to_phys(page);
2255 		gic_rdists->prop_table_va = page_address(page);
2256 		WARN_ON(gic_reserve_range(gic_rdists->prop_table_pa,
2257 					  LPI_PROPBASE_SZ));
2258 	}
2259 
2260 	pr_info("GICv3: using LPI property table @%pa\n",
2261 		&gic_rdists->prop_table_pa);
2262 
2263 	return its_lpi_init(lpi_id_bits);
2264 }
2265 
2266 static const char *its_base_type_string[] = {
2267 	[GITS_BASER_TYPE_DEVICE]	= "Devices",
2268 	[GITS_BASER_TYPE_VCPU]		= "Virtual CPUs",
2269 	[GITS_BASER_TYPE_RESERVED3]	= "Reserved (3)",
2270 	[GITS_BASER_TYPE_COLLECTION]	= "Interrupt Collections",
2271 	[GITS_BASER_TYPE_RESERVED5] 	= "Reserved (5)",
2272 	[GITS_BASER_TYPE_RESERVED6] 	= "Reserved (6)",
2273 	[GITS_BASER_TYPE_RESERVED7] 	= "Reserved (7)",
2274 };
2275 
2276 static u64 its_read_baser(struct its_node *its, struct its_baser *baser)
2277 {
2278 	u32 idx = baser - its->tables;
2279 
2280 	return gits_read_baser(its->base + GITS_BASER + (idx << 3));
2281 }
2282 
2283 static void its_write_baser(struct its_node *its, struct its_baser *baser,
2284 			    u64 val)
2285 {
2286 	u32 idx = baser - its->tables;
2287 
2288 	gits_write_baser(val, its->base + GITS_BASER + (idx << 3));
2289 	baser->val = its_read_baser(its, baser);
2290 }
2291 
2292 static int its_setup_baser(struct its_node *its, struct its_baser *baser,
2293 			   u64 cache, u64 shr, u32 order, bool indirect)
2294 {
2295 	u64 val = its_read_baser(its, baser);
2296 	u64 esz = GITS_BASER_ENTRY_SIZE(val);
2297 	u64 type = GITS_BASER_TYPE(val);
2298 	u64 baser_phys, tmp;
2299 	u32 alloc_pages, psz;
2300 	struct page *page;
2301 	void *base;
2302 
2303 	psz = baser->psz;
2304 	alloc_pages = (PAGE_ORDER_TO_SIZE(order) / psz);
2305 	if (alloc_pages > GITS_BASER_PAGES_MAX) {
2306 		pr_warn("ITS@%pa: %s too large, reduce ITS pages %u->%u\n",
2307 			&its->phys_base, its_base_type_string[type],
2308 			alloc_pages, GITS_BASER_PAGES_MAX);
2309 		alloc_pages = GITS_BASER_PAGES_MAX;
2310 		order = get_order(GITS_BASER_PAGES_MAX * psz);
2311 	}
2312 
2313 	page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO, order);
2314 	if (!page)
2315 		return -ENOMEM;
2316 
2317 	base = (void *)page_address(page);
2318 	baser_phys = virt_to_phys(base);
2319 
2320 	/* Check if the physical address of the memory is above 48bits */
2321 	if (IS_ENABLED(CONFIG_ARM64_64K_PAGES) && (baser_phys >> 48)) {
2322 
2323 		/* 52bit PA is supported only when PageSize=64K */
2324 		if (psz != SZ_64K) {
2325 			pr_err("ITS: no 52bit PA support when psz=%d\n", psz);
2326 			free_pages((unsigned long)base, order);
2327 			return -ENXIO;
2328 		}
2329 
2330 		/* Convert 52bit PA to 48bit field */
2331 		baser_phys = GITS_BASER_PHYS_52_to_48(baser_phys);
2332 	}
2333 
2334 retry_baser:
2335 	val = (baser_phys					 |
2336 		(type << GITS_BASER_TYPE_SHIFT)			 |
2337 		((esz - 1) << GITS_BASER_ENTRY_SIZE_SHIFT)	 |
2338 		((alloc_pages - 1) << GITS_BASER_PAGES_SHIFT)	 |
2339 		cache						 |
2340 		shr						 |
2341 		GITS_BASER_VALID);
2342 
2343 	val |=	indirect ? GITS_BASER_INDIRECT : 0x0;
2344 
2345 	switch (psz) {
2346 	case SZ_4K:
2347 		val |= GITS_BASER_PAGE_SIZE_4K;
2348 		break;
2349 	case SZ_16K:
2350 		val |= GITS_BASER_PAGE_SIZE_16K;
2351 		break;
2352 	case SZ_64K:
2353 		val |= GITS_BASER_PAGE_SIZE_64K;
2354 		break;
2355 	}
2356 
2357 	its_write_baser(its, baser, val);
2358 	tmp = baser->val;
2359 
2360 	if ((val ^ tmp) & GITS_BASER_SHAREABILITY_MASK) {
2361 		/*
2362 		 * Shareability didn't stick. Just use
2363 		 * whatever the read reported, which is likely
2364 		 * to be the only thing this redistributor
2365 		 * supports. If that's zero, make it
2366 		 * non-cacheable as well.
2367 		 */
2368 		shr = tmp & GITS_BASER_SHAREABILITY_MASK;
2369 		if (!shr) {
2370 			cache = GITS_BASER_nC;
2371 			gic_flush_dcache_to_poc(base, PAGE_ORDER_TO_SIZE(order));
2372 		}
2373 		goto retry_baser;
2374 	}
2375 
2376 	if (val != tmp) {
2377 		pr_err("ITS@%pa: %s doesn't stick: %llx %llx\n",
2378 		       &its->phys_base, its_base_type_string[type],
2379 		       val, tmp);
2380 		free_pages((unsigned long)base, order);
2381 		return -ENXIO;
2382 	}
2383 
2384 	baser->order = order;
2385 	baser->base = base;
2386 	baser->psz = psz;
2387 	tmp = indirect ? GITS_LVL1_ENTRY_SIZE : esz;
2388 
2389 	pr_info("ITS@%pa: allocated %d %s @%lx (%s, esz %d, psz %dK, shr %d)\n",
2390 		&its->phys_base, (int)(PAGE_ORDER_TO_SIZE(order) / (int)tmp),
2391 		its_base_type_string[type],
2392 		(unsigned long)virt_to_phys(base),
2393 		indirect ? "indirect" : "flat", (int)esz,
2394 		psz / SZ_1K, (int)shr >> GITS_BASER_SHAREABILITY_SHIFT);
2395 
2396 	return 0;
2397 }
2398 
2399 static bool its_parse_indirect_baser(struct its_node *its,
2400 				     struct its_baser *baser,
2401 				     u32 *order, u32 ids)
2402 {
2403 	u64 tmp = its_read_baser(its, baser);
2404 	u64 type = GITS_BASER_TYPE(tmp);
2405 	u64 esz = GITS_BASER_ENTRY_SIZE(tmp);
2406 	u64 val = GITS_BASER_InnerShareable | GITS_BASER_RaWaWb;
2407 	u32 new_order = *order;
2408 	u32 psz = baser->psz;
2409 	bool indirect = false;
2410 
2411 	/* No need to enable Indirection if memory requirement < (psz*2)bytes */
2412 	if ((esz << ids) > (psz * 2)) {
2413 		/*
2414 		 * Find out whether hw supports a single or two-level table by
2415 		 * table by reading bit at offset '62' after writing '1' to it.
2416 		 */
2417 		its_write_baser(its, baser, val | GITS_BASER_INDIRECT);
2418 		indirect = !!(baser->val & GITS_BASER_INDIRECT);
2419 
2420 		if (indirect) {
2421 			/*
2422 			 * The size of the lvl2 table is equal to ITS page size
2423 			 * which is 'psz'. For computing lvl1 table size,
2424 			 * subtract ID bits that sparse lvl2 table from 'ids'
2425 			 * which is reported by ITS hardware times lvl1 table
2426 			 * entry size.
2427 			 */
2428 			ids -= ilog2(psz / (int)esz);
2429 			esz = GITS_LVL1_ENTRY_SIZE;
2430 		}
2431 	}
2432 
2433 	/*
2434 	 * Allocate as many entries as required to fit the
2435 	 * range of device IDs that the ITS can grok... The ID
2436 	 * space being incredibly sparse, this results in a
2437 	 * massive waste of memory if two-level device table
2438 	 * feature is not supported by hardware.
2439 	 */
2440 	new_order = max_t(u32, get_order(esz << ids), new_order);
2441 	if (new_order >= MAX_ORDER) {
2442 		new_order = MAX_ORDER - 1;
2443 		ids = ilog2(PAGE_ORDER_TO_SIZE(new_order) / (int)esz);
2444 		pr_warn("ITS@%pa: %s Table too large, reduce ids %llu->%u\n",
2445 			&its->phys_base, its_base_type_string[type],
2446 			device_ids(its), ids);
2447 	}
2448 
2449 	*order = new_order;
2450 
2451 	return indirect;
2452 }
2453 
2454 static u32 compute_common_aff(u64 val)
2455 {
2456 	u32 aff, clpiaff;
2457 
2458 	aff = FIELD_GET(GICR_TYPER_AFFINITY, val);
2459 	clpiaff = FIELD_GET(GICR_TYPER_COMMON_LPI_AFF, val);
2460 
2461 	return aff & ~(GENMASK(31, 0) >> (clpiaff * 8));
2462 }
2463 
2464 static u32 compute_its_aff(struct its_node *its)
2465 {
2466 	u64 val;
2467 	u32 svpet;
2468 
2469 	/*
2470 	 * Reencode the ITS SVPET and MPIDR as a GICR_TYPER, and compute
2471 	 * the resulting affinity. We then use that to see if this match
2472 	 * our own affinity.
2473 	 */
2474 	svpet = FIELD_GET(GITS_TYPER_SVPET, its->typer);
2475 	val  = FIELD_PREP(GICR_TYPER_COMMON_LPI_AFF, svpet);
2476 	val |= FIELD_PREP(GICR_TYPER_AFFINITY, its->mpidr);
2477 	return compute_common_aff(val);
2478 }
2479 
2480 static struct its_node *find_sibling_its(struct its_node *cur_its)
2481 {
2482 	struct its_node *its;
2483 	u32 aff;
2484 
2485 	if (!FIELD_GET(GITS_TYPER_SVPET, cur_its->typer))
2486 		return NULL;
2487 
2488 	aff = compute_its_aff(cur_its);
2489 
2490 	list_for_each_entry(its, &its_nodes, entry) {
2491 		u64 baser;
2492 
2493 		if (!is_v4_1(its) || its == cur_its)
2494 			continue;
2495 
2496 		if (!FIELD_GET(GITS_TYPER_SVPET, its->typer))
2497 			continue;
2498 
2499 		if (aff != compute_its_aff(its))
2500 			continue;
2501 
2502 		/* GICv4.1 guarantees that the vPE table is GITS_BASER2 */
2503 		baser = its->tables[2].val;
2504 		if (!(baser & GITS_BASER_VALID))
2505 			continue;
2506 
2507 		return its;
2508 	}
2509 
2510 	return NULL;
2511 }
2512 
2513 static void its_free_tables(struct its_node *its)
2514 {
2515 	int i;
2516 
2517 	for (i = 0; i < GITS_BASER_NR_REGS; i++) {
2518 		if (its->tables[i].base) {
2519 			free_pages((unsigned long)its->tables[i].base,
2520 				   its->tables[i].order);
2521 			its->tables[i].base = NULL;
2522 		}
2523 	}
2524 }
2525 
2526 static int its_probe_baser_psz(struct its_node *its, struct its_baser *baser)
2527 {
2528 	u64 psz = SZ_64K;
2529 
2530 	while (psz) {
2531 		u64 val, gpsz;
2532 
2533 		val = its_read_baser(its, baser);
2534 		val &= ~GITS_BASER_PAGE_SIZE_MASK;
2535 
2536 		switch (psz) {
2537 		case SZ_64K:
2538 			gpsz = GITS_BASER_PAGE_SIZE_64K;
2539 			break;
2540 		case SZ_16K:
2541 			gpsz = GITS_BASER_PAGE_SIZE_16K;
2542 			break;
2543 		case SZ_4K:
2544 		default:
2545 			gpsz = GITS_BASER_PAGE_SIZE_4K;
2546 			break;
2547 		}
2548 
2549 		gpsz >>= GITS_BASER_PAGE_SIZE_SHIFT;
2550 
2551 		val |= FIELD_PREP(GITS_BASER_PAGE_SIZE_MASK, gpsz);
2552 		its_write_baser(its, baser, val);
2553 
2554 		if (FIELD_GET(GITS_BASER_PAGE_SIZE_MASK, baser->val) == gpsz)
2555 			break;
2556 
2557 		switch (psz) {
2558 		case SZ_64K:
2559 			psz = SZ_16K;
2560 			break;
2561 		case SZ_16K:
2562 			psz = SZ_4K;
2563 			break;
2564 		case SZ_4K:
2565 		default:
2566 			return -1;
2567 		}
2568 	}
2569 
2570 	baser->psz = psz;
2571 	return 0;
2572 }
2573 
2574 static int its_alloc_tables(struct its_node *its)
2575 {
2576 	u64 shr = GITS_BASER_InnerShareable;
2577 	u64 cache = GITS_BASER_RaWaWb;
2578 	int err, i;
2579 
2580 	if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_22375)
2581 		/* erratum 24313: ignore memory access type */
2582 		cache = GITS_BASER_nCnB;
2583 
2584 	for (i = 0; i < GITS_BASER_NR_REGS; i++) {
2585 		struct its_baser *baser = its->tables + i;
2586 		u64 val = its_read_baser(its, baser);
2587 		u64 type = GITS_BASER_TYPE(val);
2588 		bool indirect = false;
2589 		u32 order;
2590 
2591 		if (type == GITS_BASER_TYPE_NONE)
2592 			continue;
2593 
2594 		if (its_probe_baser_psz(its, baser)) {
2595 			its_free_tables(its);
2596 			return -ENXIO;
2597 		}
2598 
2599 		order = get_order(baser->psz);
2600 
2601 		switch (type) {
2602 		case GITS_BASER_TYPE_DEVICE:
2603 			indirect = its_parse_indirect_baser(its, baser, &order,
2604 							    device_ids(its));
2605 			break;
2606 
2607 		case GITS_BASER_TYPE_VCPU:
2608 			if (is_v4_1(its)) {
2609 				struct its_node *sibling;
2610 
2611 				WARN_ON(i != 2);
2612 				if ((sibling = find_sibling_its(its))) {
2613 					*baser = sibling->tables[2];
2614 					its_write_baser(its, baser, baser->val);
2615 					continue;
2616 				}
2617 			}
2618 
2619 			indirect = its_parse_indirect_baser(its, baser, &order,
2620 							    ITS_MAX_VPEID_BITS);
2621 			break;
2622 		}
2623 
2624 		err = its_setup_baser(its, baser, cache, shr, order, indirect);
2625 		if (err < 0) {
2626 			its_free_tables(its);
2627 			return err;
2628 		}
2629 
2630 		/* Update settings which will be used for next BASERn */
2631 		cache = baser->val & GITS_BASER_CACHEABILITY_MASK;
2632 		shr = baser->val & GITS_BASER_SHAREABILITY_MASK;
2633 	}
2634 
2635 	return 0;
2636 }
2637 
2638 static u64 inherit_vpe_l1_table_from_its(void)
2639 {
2640 	struct its_node *its;
2641 	u64 val;
2642 	u32 aff;
2643 
2644 	val = gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER);
2645 	aff = compute_common_aff(val);
2646 
2647 	list_for_each_entry(its, &its_nodes, entry) {
2648 		u64 baser, addr;
2649 
2650 		if (!is_v4_1(its))
2651 			continue;
2652 
2653 		if (!FIELD_GET(GITS_TYPER_SVPET, its->typer))
2654 			continue;
2655 
2656 		if (aff != compute_its_aff(its))
2657 			continue;
2658 
2659 		/* GICv4.1 guarantees that the vPE table is GITS_BASER2 */
2660 		baser = its->tables[2].val;
2661 		if (!(baser & GITS_BASER_VALID))
2662 			continue;
2663 
2664 		/* We have a winner! */
2665 		gic_data_rdist()->vpe_l1_base = its->tables[2].base;
2666 
2667 		val  = GICR_VPROPBASER_4_1_VALID;
2668 		if (baser & GITS_BASER_INDIRECT)
2669 			val |= GICR_VPROPBASER_4_1_INDIRECT;
2670 		val |= FIELD_PREP(GICR_VPROPBASER_4_1_PAGE_SIZE,
2671 				  FIELD_GET(GITS_BASER_PAGE_SIZE_MASK, baser));
2672 		switch (FIELD_GET(GITS_BASER_PAGE_SIZE_MASK, baser)) {
2673 		case GIC_PAGE_SIZE_64K:
2674 			addr = GITS_BASER_ADDR_48_to_52(baser);
2675 			break;
2676 		default:
2677 			addr = baser & GENMASK_ULL(47, 12);
2678 			break;
2679 		}
2680 		val |= FIELD_PREP(GICR_VPROPBASER_4_1_ADDR, addr >> 12);
2681 		val |= FIELD_PREP(GICR_VPROPBASER_SHAREABILITY_MASK,
2682 				  FIELD_GET(GITS_BASER_SHAREABILITY_MASK, baser));
2683 		val |= FIELD_PREP(GICR_VPROPBASER_INNER_CACHEABILITY_MASK,
2684 				  FIELD_GET(GITS_BASER_INNER_CACHEABILITY_MASK, baser));
2685 		val |= FIELD_PREP(GICR_VPROPBASER_4_1_SIZE, GITS_BASER_NR_PAGES(baser) - 1);
2686 
2687 		return val;
2688 	}
2689 
2690 	return 0;
2691 }
2692 
2693 static u64 inherit_vpe_l1_table_from_rd(cpumask_t **mask)
2694 {
2695 	u32 aff;
2696 	u64 val;
2697 	int cpu;
2698 
2699 	val = gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER);
2700 	aff = compute_common_aff(val);
2701 
2702 	for_each_possible_cpu(cpu) {
2703 		void __iomem *base = gic_data_rdist_cpu(cpu)->rd_base;
2704 
2705 		if (!base || cpu == smp_processor_id())
2706 			continue;
2707 
2708 		val = gic_read_typer(base + GICR_TYPER);
2709 		if (aff != compute_common_aff(val))
2710 			continue;
2711 
2712 		/*
2713 		 * At this point, we have a victim. This particular CPU
2714 		 * has already booted, and has an affinity that matches
2715 		 * ours wrt CommonLPIAff. Let's use its own VPROPBASER.
2716 		 * Make sure we don't write the Z bit in that case.
2717 		 */
2718 		val = gicr_read_vpropbaser(base + SZ_128K + GICR_VPROPBASER);
2719 		val &= ~GICR_VPROPBASER_4_1_Z;
2720 
2721 		gic_data_rdist()->vpe_l1_base = gic_data_rdist_cpu(cpu)->vpe_l1_base;
2722 		*mask = gic_data_rdist_cpu(cpu)->vpe_table_mask;
2723 
2724 		return val;
2725 	}
2726 
2727 	return 0;
2728 }
2729 
2730 static bool allocate_vpe_l2_table(int cpu, u32 id)
2731 {
2732 	void __iomem *base = gic_data_rdist_cpu(cpu)->rd_base;
2733 	unsigned int psz, esz, idx, npg, gpsz;
2734 	u64 val;
2735 	struct page *page;
2736 	__le64 *table;
2737 
2738 	if (!gic_rdists->has_rvpeid)
2739 		return true;
2740 
2741 	/* Skip non-present CPUs */
2742 	if (!base)
2743 		return true;
2744 
2745 	val  = gicr_read_vpropbaser(base + SZ_128K + GICR_VPROPBASER);
2746 
2747 	esz  = FIELD_GET(GICR_VPROPBASER_4_1_ENTRY_SIZE, val) + 1;
2748 	gpsz = FIELD_GET(GICR_VPROPBASER_4_1_PAGE_SIZE, val);
2749 	npg  = FIELD_GET(GICR_VPROPBASER_4_1_SIZE, val) + 1;
2750 
2751 	switch (gpsz) {
2752 	default:
2753 		WARN_ON(1);
2754 		fallthrough;
2755 	case GIC_PAGE_SIZE_4K:
2756 		psz = SZ_4K;
2757 		break;
2758 	case GIC_PAGE_SIZE_16K:
2759 		psz = SZ_16K;
2760 		break;
2761 	case GIC_PAGE_SIZE_64K:
2762 		psz = SZ_64K;
2763 		break;
2764 	}
2765 
2766 	/* Don't allow vpe_id that exceeds single, flat table limit */
2767 	if (!(val & GICR_VPROPBASER_4_1_INDIRECT))
2768 		return (id < (npg * psz / (esz * SZ_8)));
2769 
2770 	/* Compute 1st level table index & check if that exceeds table limit */
2771 	idx = id >> ilog2(psz / (esz * SZ_8));
2772 	if (idx >= (npg * psz / GITS_LVL1_ENTRY_SIZE))
2773 		return false;
2774 
2775 	table = gic_data_rdist_cpu(cpu)->vpe_l1_base;
2776 
2777 	/* Allocate memory for 2nd level table */
2778 	if (!table[idx]) {
2779 		page = alloc_pages(GFP_KERNEL | __GFP_ZERO, get_order(psz));
2780 		if (!page)
2781 			return false;
2782 
2783 		/* Flush Lvl2 table to PoC if hw doesn't support coherency */
2784 		if (!(val & GICR_VPROPBASER_SHAREABILITY_MASK))
2785 			gic_flush_dcache_to_poc(page_address(page), psz);
2786 
2787 		table[idx] = cpu_to_le64(page_to_phys(page) | GITS_BASER_VALID);
2788 
2789 		/* Flush Lvl1 entry to PoC if hw doesn't support coherency */
2790 		if (!(val & GICR_VPROPBASER_SHAREABILITY_MASK))
2791 			gic_flush_dcache_to_poc(table + idx, GITS_LVL1_ENTRY_SIZE);
2792 
2793 		/* Ensure updated table contents are visible to RD hardware */
2794 		dsb(sy);
2795 	}
2796 
2797 	return true;
2798 }
2799 
2800 static int allocate_vpe_l1_table(void)
2801 {
2802 	void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
2803 	u64 val, gpsz, npg, pa;
2804 	unsigned int psz = SZ_64K;
2805 	unsigned int np, epp, esz;
2806 	struct page *page;
2807 
2808 	if (!gic_rdists->has_rvpeid)
2809 		return 0;
2810 
2811 	/*
2812 	 * if VPENDBASER.Valid is set, disable any previously programmed
2813 	 * VPE by setting PendingLast while clearing Valid. This has the
2814 	 * effect of making sure no doorbell will be generated and we can
2815 	 * then safely clear VPROPBASER.Valid.
2816 	 */
2817 	if (gicr_read_vpendbaser(vlpi_base + GICR_VPENDBASER) & GICR_VPENDBASER_Valid)
2818 		gicr_write_vpendbaser(GICR_VPENDBASER_PendingLast,
2819 				      vlpi_base + GICR_VPENDBASER);
2820 
2821 	/*
2822 	 * If we can inherit the configuration from another RD, let's do
2823 	 * so. Otherwise, we have to go through the allocation process. We
2824 	 * assume that all RDs have the exact same requirements, as
2825 	 * nothing will work otherwise.
2826 	 */
2827 	val = inherit_vpe_l1_table_from_rd(&gic_data_rdist()->vpe_table_mask);
2828 	if (val & GICR_VPROPBASER_4_1_VALID)
2829 		goto out;
2830 
2831 	gic_data_rdist()->vpe_table_mask = kzalloc(sizeof(cpumask_t), GFP_ATOMIC);
2832 	if (!gic_data_rdist()->vpe_table_mask)
2833 		return -ENOMEM;
2834 
2835 	val = inherit_vpe_l1_table_from_its();
2836 	if (val & GICR_VPROPBASER_4_1_VALID)
2837 		goto out;
2838 
2839 	/* First probe the page size */
2840 	val = FIELD_PREP(GICR_VPROPBASER_4_1_PAGE_SIZE, GIC_PAGE_SIZE_64K);
2841 	gicr_write_vpropbaser(val, vlpi_base + GICR_VPROPBASER);
2842 	val = gicr_read_vpropbaser(vlpi_base + GICR_VPROPBASER);
2843 	gpsz = FIELD_GET(GICR_VPROPBASER_4_1_PAGE_SIZE, val);
2844 	esz = FIELD_GET(GICR_VPROPBASER_4_1_ENTRY_SIZE, val);
2845 
2846 	switch (gpsz) {
2847 	default:
2848 		gpsz = GIC_PAGE_SIZE_4K;
2849 		fallthrough;
2850 	case GIC_PAGE_SIZE_4K:
2851 		psz = SZ_4K;
2852 		break;
2853 	case GIC_PAGE_SIZE_16K:
2854 		psz = SZ_16K;
2855 		break;
2856 	case GIC_PAGE_SIZE_64K:
2857 		psz = SZ_64K;
2858 		break;
2859 	}
2860 
2861 	/*
2862 	 * Start populating the register from scratch, including RO fields
2863 	 * (which we want to print in debug cases...)
2864 	 */
2865 	val = 0;
2866 	val |= FIELD_PREP(GICR_VPROPBASER_4_1_PAGE_SIZE, gpsz);
2867 	val |= FIELD_PREP(GICR_VPROPBASER_4_1_ENTRY_SIZE, esz);
2868 
2869 	/* How many entries per GIC page? */
2870 	esz++;
2871 	epp = psz / (esz * SZ_8);
2872 
2873 	/*
2874 	 * If we need more than just a single L1 page, flag the table
2875 	 * as indirect and compute the number of required L1 pages.
2876 	 */
2877 	if (epp < ITS_MAX_VPEID) {
2878 		int nl2;
2879 
2880 		val |= GICR_VPROPBASER_4_1_INDIRECT;
2881 
2882 		/* Number of L2 pages required to cover the VPEID space */
2883 		nl2 = DIV_ROUND_UP(ITS_MAX_VPEID, epp);
2884 
2885 		/* Number of L1 pages to point to the L2 pages */
2886 		npg = DIV_ROUND_UP(nl2 * SZ_8, psz);
2887 	} else {
2888 		npg = 1;
2889 	}
2890 
2891 	val |= FIELD_PREP(GICR_VPROPBASER_4_1_SIZE, npg - 1);
2892 
2893 	/* Right, that's the number of CPU pages we need for L1 */
2894 	np = DIV_ROUND_UP(npg * psz, PAGE_SIZE);
2895 
2896 	pr_debug("np = %d, npg = %lld, psz = %d, epp = %d, esz = %d\n",
2897 		 np, npg, psz, epp, esz);
2898 	page = alloc_pages(GFP_ATOMIC | __GFP_ZERO, get_order(np * PAGE_SIZE));
2899 	if (!page)
2900 		return -ENOMEM;
2901 
2902 	gic_data_rdist()->vpe_l1_base = page_address(page);
2903 	pa = virt_to_phys(page_address(page));
2904 	WARN_ON(!IS_ALIGNED(pa, psz));
2905 
2906 	val |= FIELD_PREP(GICR_VPROPBASER_4_1_ADDR, pa >> 12);
2907 	val |= GICR_VPROPBASER_RaWb;
2908 	val |= GICR_VPROPBASER_InnerShareable;
2909 	val |= GICR_VPROPBASER_4_1_Z;
2910 	val |= GICR_VPROPBASER_4_1_VALID;
2911 
2912 out:
2913 	gicr_write_vpropbaser(val, vlpi_base + GICR_VPROPBASER);
2914 	cpumask_set_cpu(smp_processor_id(), gic_data_rdist()->vpe_table_mask);
2915 
2916 	pr_debug("CPU%d: VPROPBASER = %llx %*pbl\n",
2917 		 smp_processor_id(), val,
2918 		 cpumask_pr_args(gic_data_rdist()->vpe_table_mask));
2919 
2920 	return 0;
2921 }
2922 
2923 static int its_alloc_collections(struct its_node *its)
2924 {
2925 	int i;
2926 
2927 	its->collections = kcalloc(nr_cpu_ids, sizeof(*its->collections),
2928 				   GFP_KERNEL);
2929 	if (!its->collections)
2930 		return -ENOMEM;
2931 
2932 	for (i = 0; i < nr_cpu_ids; i++)
2933 		its->collections[i].target_address = ~0ULL;
2934 
2935 	return 0;
2936 }
2937 
2938 static struct page *its_allocate_pending_table(gfp_t gfp_flags)
2939 {
2940 	struct page *pend_page;
2941 
2942 	pend_page = alloc_pages(gfp_flags | __GFP_ZERO,
2943 				get_order(LPI_PENDBASE_SZ));
2944 	if (!pend_page)
2945 		return NULL;
2946 
2947 	/* Make sure the GIC will observe the zero-ed page */
2948 	gic_flush_dcache_to_poc(page_address(pend_page), LPI_PENDBASE_SZ);
2949 
2950 	return pend_page;
2951 }
2952 
2953 static void its_free_pending_table(struct page *pt)
2954 {
2955 	free_pages((unsigned long)page_address(pt), get_order(LPI_PENDBASE_SZ));
2956 }
2957 
2958 /*
2959  * Booting with kdump and LPIs enabled is generally fine. Any other
2960  * case is wrong in the absence of firmware/EFI support.
2961  */
2962 static bool enabled_lpis_allowed(void)
2963 {
2964 	phys_addr_t addr;
2965 	u64 val;
2966 
2967 	/* Check whether the property table is in a reserved region */
2968 	val = gicr_read_propbaser(gic_data_rdist_rd_base() + GICR_PROPBASER);
2969 	addr = val & GENMASK_ULL(51, 12);
2970 
2971 	return gic_check_reserved_range(addr, LPI_PROPBASE_SZ);
2972 }
2973 
2974 static int __init allocate_lpi_tables(void)
2975 {
2976 	u64 val;
2977 	int err, cpu;
2978 
2979 	/*
2980 	 * If LPIs are enabled while we run this from the boot CPU,
2981 	 * flag the RD tables as pre-allocated if the stars do align.
2982 	 */
2983 	val = readl_relaxed(gic_data_rdist_rd_base() + GICR_CTLR);
2984 	if ((val & GICR_CTLR_ENABLE_LPIS) && enabled_lpis_allowed()) {
2985 		gic_rdists->flags |= (RDIST_FLAGS_RD_TABLES_PREALLOCATED |
2986 				      RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING);
2987 		pr_info("GICv3: Using preallocated redistributor tables\n");
2988 	}
2989 
2990 	err = its_setup_lpi_prop_table();
2991 	if (err)
2992 		return err;
2993 
2994 	/*
2995 	 * We allocate all the pending tables anyway, as we may have a
2996 	 * mix of RDs that have had LPIs enabled, and some that
2997 	 * don't. We'll free the unused ones as each CPU comes online.
2998 	 */
2999 	for_each_possible_cpu(cpu) {
3000 		struct page *pend_page;
3001 
3002 		pend_page = its_allocate_pending_table(GFP_NOWAIT);
3003 		if (!pend_page) {
3004 			pr_err("Failed to allocate PENDBASE for CPU%d\n", cpu);
3005 			return -ENOMEM;
3006 		}
3007 
3008 		gic_data_rdist_cpu(cpu)->pend_page = pend_page;
3009 	}
3010 
3011 	return 0;
3012 }
3013 
3014 static u64 read_vpend_dirty_clear(void __iomem *vlpi_base)
3015 {
3016 	u32 count = 1000000;	/* 1s! */
3017 	bool clean;
3018 	u64 val;
3019 
3020 	do {
3021 		val = gicr_read_vpendbaser(vlpi_base + GICR_VPENDBASER);
3022 		clean = !(val & GICR_VPENDBASER_Dirty);
3023 		if (!clean) {
3024 			count--;
3025 			cpu_relax();
3026 			udelay(1);
3027 		}
3028 	} while (!clean && count);
3029 
3030 	if (unlikely(!clean))
3031 		pr_err_ratelimited("ITS virtual pending table not cleaning\n");
3032 
3033 	return val;
3034 }
3035 
3036 static u64 its_clear_vpend_valid(void __iomem *vlpi_base, u64 clr, u64 set)
3037 {
3038 	u64 val;
3039 
3040 	/* Make sure we wait until the RD is done with the initial scan */
3041 	val = read_vpend_dirty_clear(vlpi_base);
3042 	val &= ~GICR_VPENDBASER_Valid;
3043 	val &= ~clr;
3044 	val |= set;
3045 	gicr_write_vpendbaser(val, vlpi_base + GICR_VPENDBASER);
3046 
3047 	val = read_vpend_dirty_clear(vlpi_base);
3048 	if (unlikely(val & GICR_VPENDBASER_Dirty))
3049 		val |= GICR_VPENDBASER_PendingLast;
3050 
3051 	return val;
3052 }
3053 
3054 static void its_cpu_init_lpis(void)
3055 {
3056 	void __iomem *rbase = gic_data_rdist_rd_base();
3057 	struct page *pend_page;
3058 	phys_addr_t paddr;
3059 	u64 val, tmp;
3060 
3061 	if (gic_data_rdist()->flags & RD_LOCAL_LPI_ENABLED)
3062 		return;
3063 
3064 	val = readl_relaxed(rbase + GICR_CTLR);
3065 	if ((gic_rdists->flags & RDIST_FLAGS_RD_TABLES_PREALLOCATED) &&
3066 	    (val & GICR_CTLR_ENABLE_LPIS)) {
3067 		/*
3068 		 * Check that we get the same property table on all
3069 		 * RDs. If we don't, this is hopeless.
3070 		 */
3071 		paddr = gicr_read_propbaser(rbase + GICR_PROPBASER);
3072 		paddr &= GENMASK_ULL(51, 12);
3073 		if (WARN_ON(gic_rdists->prop_table_pa != paddr))
3074 			add_taint(TAINT_CRAP, LOCKDEP_STILL_OK);
3075 
3076 		paddr = gicr_read_pendbaser(rbase + GICR_PENDBASER);
3077 		paddr &= GENMASK_ULL(51, 16);
3078 
3079 		WARN_ON(!gic_check_reserved_range(paddr, LPI_PENDBASE_SZ));
3080 		gic_data_rdist()->flags |= RD_LOCAL_PENDTABLE_PREALLOCATED;
3081 
3082 		goto out;
3083 	}
3084 
3085 	pend_page = gic_data_rdist()->pend_page;
3086 	paddr = page_to_phys(pend_page);
3087 
3088 	/* set PROPBASE */
3089 	val = (gic_rdists->prop_table_pa |
3090 	       GICR_PROPBASER_InnerShareable |
3091 	       GICR_PROPBASER_RaWaWb |
3092 	       ((LPI_NRBITS - 1) & GICR_PROPBASER_IDBITS_MASK));
3093 
3094 	gicr_write_propbaser(val, rbase + GICR_PROPBASER);
3095 	tmp = gicr_read_propbaser(rbase + GICR_PROPBASER);
3096 
3097 	if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) {
3098 		if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) {
3099 			/*
3100 			 * The HW reports non-shareable, we must
3101 			 * remove the cacheability attributes as
3102 			 * well.
3103 			 */
3104 			val &= ~(GICR_PROPBASER_SHAREABILITY_MASK |
3105 				 GICR_PROPBASER_CACHEABILITY_MASK);
3106 			val |= GICR_PROPBASER_nC;
3107 			gicr_write_propbaser(val, rbase + GICR_PROPBASER);
3108 		}
3109 		pr_info_once("GIC: using cache flushing for LPI property table\n");
3110 		gic_rdists->flags |= RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING;
3111 	}
3112 
3113 	/* set PENDBASE */
3114 	val = (page_to_phys(pend_page) |
3115 	       GICR_PENDBASER_InnerShareable |
3116 	       GICR_PENDBASER_RaWaWb);
3117 
3118 	gicr_write_pendbaser(val, rbase + GICR_PENDBASER);
3119 	tmp = gicr_read_pendbaser(rbase + GICR_PENDBASER);
3120 
3121 	if (!(tmp & GICR_PENDBASER_SHAREABILITY_MASK)) {
3122 		/*
3123 		 * The HW reports non-shareable, we must remove the
3124 		 * cacheability attributes as well.
3125 		 */
3126 		val &= ~(GICR_PENDBASER_SHAREABILITY_MASK |
3127 			 GICR_PENDBASER_CACHEABILITY_MASK);
3128 		val |= GICR_PENDBASER_nC;
3129 		gicr_write_pendbaser(val, rbase + GICR_PENDBASER);
3130 	}
3131 
3132 	/* Enable LPIs */
3133 	val = readl_relaxed(rbase + GICR_CTLR);
3134 	val |= GICR_CTLR_ENABLE_LPIS;
3135 	writel_relaxed(val, rbase + GICR_CTLR);
3136 
3137 	if (gic_rdists->has_vlpis && !gic_rdists->has_rvpeid) {
3138 		void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
3139 
3140 		/*
3141 		 * It's possible for CPU to receive VLPIs before it is
3142 		 * scheduled as a vPE, especially for the first CPU, and the
3143 		 * VLPI with INTID larger than 2^(IDbits+1) will be considered
3144 		 * as out of range and dropped by GIC.
3145 		 * So we initialize IDbits to known value to avoid VLPI drop.
3146 		 */
3147 		val = (LPI_NRBITS - 1) & GICR_VPROPBASER_IDBITS_MASK;
3148 		pr_debug("GICv4: CPU%d: Init IDbits to 0x%llx for GICR_VPROPBASER\n",
3149 			smp_processor_id(), val);
3150 		gicr_write_vpropbaser(val, vlpi_base + GICR_VPROPBASER);
3151 
3152 		/*
3153 		 * Also clear Valid bit of GICR_VPENDBASER, in case some
3154 		 * ancient programming gets left in and has possibility of
3155 		 * corrupting memory.
3156 		 */
3157 		val = its_clear_vpend_valid(vlpi_base, 0, 0);
3158 	}
3159 
3160 	if (allocate_vpe_l1_table()) {
3161 		/*
3162 		 * If the allocation has failed, we're in massive trouble.
3163 		 * Disable direct injection, and pray that no VM was
3164 		 * already running...
3165 		 */
3166 		gic_rdists->has_rvpeid = false;
3167 		gic_rdists->has_vlpis = false;
3168 	}
3169 
3170 	/* Make sure the GIC has seen the above */
3171 	dsb(sy);
3172 out:
3173 	gic_data_rdist()->flags |= RD_LOCAL_LPI_ENABLED;
3174 	pr_info("GICv3: CPU%d: using %s LPI pending table @%pa\n",
3175 		smp_processor_id(),
3176 		gic_data_rdist()->flags & RD_LOCAL_PENDTABLE_PREALLOCATED ?
3177 		"reserved" : "allocated",
3178 		&paddr);
3179 }
3180 
3181 static void its_cpu_init_collection(struct its_node *its)
3182 {
3183 	int cpu = smp_processor_id();
3184 	u64 target;
3185 
3186 	/* avoid cross node collections and its mapping */
3187 	if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) {
3188 		struct device_node *cpu_node;
3189 
3190 		cpu_node = of_get_cpu_node(cpu, NULL);
3191 		if (its->numa_node != NUMA_NO_NODE &&
3192 			its->numa_node != of_node_to_nid(cpu_node))
3193 			return;
3194 	}
3195 
3196 	/*
3197 	 * We now have to bind each collection to its target
3198 	 * redistributor.
3199 	 */
3200 	if (gic_read_typer(its->base + GITS_TYPER) & GITS_TYPER_PTA) {
3201 		/*
3202 		 * This ITS wants the physical address of the
3203 		 * redistributor.
3204 		 */
3205 		target = gic_data_rdist()->phys_base;
3206 	} else {
3207 		/* This ITS wants a linear CPU number. */
3208 		target = gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER);
3209 		target = GICR_TYPER_CPU_NUMBER(target) << 16;
3210 	}
3211 
3212 	/* Perform collection mapping */
3213 	its->collections[cpu].target_address = target;
3214 	its->collections[cpu].col_id = cpu;
3215 
3216 	its_send_mapc(its, &its->collections[cpu], 1);
3217 	its_send_invall(its, &its->collections[cpu]);
3218 }
3219 
3220 static void its_cpu_init_collections(void)
3221 {
3222 	struct its_node *its;
3223 
3224 	raw_spin_lock(&its_lock);
3225 
3226 	list_for_each_entry(its, &its_nodes, entry)
3227 		its_cpu_init_collection(its);
3228 
3229 	raw_spin_unlock(&its_lock);
3230 }
3231 
3232 static struct its_device *its_find_device(struct its_node *its, u32 dev_id)
3233 {
3234 	struct its_device *its_dev = NULL, *tmp;
3235 	unsigned long flags;
3236 
3237 	raw_spin_lock_irqsave(&its->lock, flags);
3238 
3239 	list_for_each_entry(tmp, &its->its_device_list, entry) {
3240 		if (tmp->device_id == dev_id) {
3241 			its_dev = tmp;
3242 			break;
3243 		}
3244 	}
3245 
3246 	raw_spin_unlock_irqrestore(&its->lock, flags);
3247 
3248 	return its_dev;
3249 }
3250 
3251 static struct its_baser *its_get_baser(struct its_node *its, u32 type)
3252 {
3253 	int i;
3254 
3255 	for (i = 0; i < GITS_BASER_NR_REGS; i++) {
3256 		if (GITS_BASER_TYPE(its->tables[i].val) == type)
3257 			return &its->tables[i];
3258 	}
3259 
3260 	return NULL;
3261 }
3262 
3263 static bool its_alloc_table_entry(struct its_node *its,
3264 				  struct its_baser *baser, u32 id)
3265 {
3266 	struct page *page;
3267 	u32 esz, idx;
3268 	__le64 *table;
3269 
3270 	/* Don't allow device id that exceeds single, flat table limit */
3271 	esz = GITS_BASER_ENTRY_SIZE(baser->val);
3272 	if (!(baser->val & GITS_BASER_INDIRECT))
3273 		return (id < (PAGE_ORDER_TO_SIZE(baser->order) / esz));
3274 
3275 	/* Compute 1st level table index & check if that exceeds table limit */
3276 	idx = id >> ilog2(baser->psz / esz);
3277 	if (idx >= (PAGE_ORDER_TO_SIZE(baser->order) / GITS_LVL1_ENTRY_SIZE))
3278 		return false;
3279 
3280 	table = baser->base;
3281 
3282 	/* Allocate memory for 2nd level table */
3283 	if (!table[idx]) {
3284 		page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO,
3285 					get_order(baser->psz));
3286 		if (!page)
3287 			return false;
3288 
3289 		/* Flush Lvl2 table to PoC if hw doesn't support coherency */
3290 		if (!(baser->val & GITS_BASER_SHAREABILITY_MASK))
3291 			gic_flush_dcache_to_poc(page_address(page), baser->psz);
3292 
3293 		table[idx] = cpu_to_le64(page_to_phys(page) | GITS_BASER_VALID);
3294 
3295 		/* Flush Lvl1 entry to PoC if hw doesn't support coherency */
3296 		if (!(baser->val & GITS_BASER_SHAREABILITY_MASK))
3297 			gic_flush_dcache_to_poc(table + idx, GITS_LVL1_ENTRY_SIZE);
3298 
3299 		/* Ensure updated table contents are visible to ITS hardware */
3300 		dsb(sy);
3301 	}
3302 
3303 	return true;
3304 }
3305 
3306 static bool its_alloc_device_table(struct its_node *its, u32 dev_id)
3307 {
3308 	struct its_baser *baser;
3309 
3310 	baser = its_get_baser(its, GITS_BASER_TYPE_DEVICE);
3311 
3312 	/* Don't allow device id that exceeds ITS hardware limit */
3313 	if (!baser)
3314 		return (ilog2(dev_id) < device_ids(its));
3315 
3316 	return its_alloc_table_entry(its, baser, dev_id);
3317 }
3318 
3319 static bool its_alloc_vpe_table(u32 vpe_id)
3320 {
3321 	struct its_node *its;
3322 	int cpu;
3323 
3324 	/*
3325 	 * Make sure the L2 tables are allocated on *all* v4 ITSs. We
3326 	 * could try and only do it on ITSs corresponding to devices
3327 	 * that have interrupts targeted at this VPE, but the
3328 	 * complexity becomes crazy (and you have tons of memory
3329 	 * anyway, right?).
3330 	 */
3331 	list_for_each_entry(its, &its_nodes, entry) {
3332 		struct its_baser *baser;
3333 
3334 		if (!is_v4(its))
3335 			continue;
3336 
3337 		baser = its_get_baser(its, GITS_BASER_TYPE_VCPU);
3338 		if (!baser)
3339 			return false;
3340 
3341 		if (!its_alloc_table_entry(its, baser, vpe_id))
3342 			return false;
3343 	}
3344 
3345 	/* Non v4.1? No need to iterate RDs and go back early. */
3346 	if (!gic_rdists->has_rvpeid)
3347 		return true;
3348 
3349 	/*
3350 	 * Make sure the L2 tables are allocated for all copies of
3351 	 * the L1 table on *all* v4.1 RDs.
3352 	 */
3353 	for_each_possible_cpu(cpu) {
3354 		if (!allocate_vpe_l2_table(cpu, vpe_id))
3355 			return false;
3356 	}
3357 
3358 	return true;
3359 }
3360 
3361 static struct its_device *its_create_device(struct its_node *its, u32 dev_id,
3362 					    int nvecs, bool alloc_lpis)
3363 {
3364 	struct its_device *dev;
3365 	unsigned long *lpi_map = NULL;
3366 	unsigned long flags;
3367 	u16 *col_map = NULL;
3368 	void *itt;
3369 	int lpi_base;
3370 	int nr_lpis;
3371 	int nr_ites;
3372 	int sz;
3373 
3374 	if (!its_alloc_device_table(its, dev_id))
3375 		return NULL;
3376 
3377 	if (WARN_ON(!is_power_of_2(nvecs)))
3378 		nvecs = roundup_pow_of_two(nvecs);
3379 
3380 	dev = kzalloc(sizeof(*dev), GFP_KERNEL);
3381 	/*
3382 	 * Even if the device wants a single LPI, the ITT must be
3383 	 * sized as a power of two (and you need at least one bit...).
3384 	 */
3385 	nr_ites = max(2, nvecs);
3386 	sz = nr_ites * (FIELD_GET(GITS_TYPER_ITT_ENTRY_SIZE, its->typer) + 1);
3387 	sz = max(sz, ITS_ITT_ALIGN) + ITS_ITT_ALIGN - 1;
3388 	itt = kzalloc_node(sz, GFP_KERNEL, its->numa_node);
3389 	if (alloc_lpis) {
3390 		lpi_map = its_lpi_alloc(nvecs, &lpi_base, &nr_lpis);
3391 		if (lpi_map)
3392 			col_map = kcalloc(nr_lpis, sizeof(*col_map),
3393 					  GFP_KERNEL);
3394 	} else {
3395 		col_map = kcalloc(nr_ites, sizeof(*col_map), GFP_KERNEL);
3396 		nr_lpis = 0;
3397 		lpi_base = 0;
3398 	}
3399 
3400 	if (!dev || !itt ||  !col_map || (!lpi_map && alloc_lpis)) {
3401 		kfree(dev);
3402 		kfree(itt);
3403 		bitmap_free(lpi_map);
3404 		kfree(col_map);
3405 		return NULL;
3406 	}
3407 
3408 	gic_flush_dcache_to_poc(itt, sz);
3409 
3410 	dev->its = its;
3411 	dev->itt = itt;
3412 	dev->nr_ites = nr_ites;
3413 	dev->event_map.lpi_map = lpi_map;
3414 	dev->event_map.col_map = col_map;
3415 	dev->event_map.lpi_base = lpi_base;
3416 	dev->event_map.nr_lpis = nr_lpis;
3417 	raw_spin_lock_init(&dev->event_map.vlpi_lock);
3418 	dev->device_id = dev_id;
3419 	INIT_LIST_HEAD(&dev->entry);
3420 
3421 	raw_spin_lock_irqsave(&its->lock, flags);
3422 	list_add(&dev->entry, &its->its_device_list);
3423 	raw_spin_unlock_irqrestore(&its->lock, flags);
3424 
3425 	/* Map device to its ITT */
3426 	its_send_mapd(dev, 1);
3427 
3428 	return dev;
3429 }
3430 
3431 static void its_free_device(struct its_device *its_dev)
3432 {
3433 	unsigned long flags;
3434 
3435 	raw_spin_lock_irqsave(&its_dev->its->lock, flags);
3436 	list_del(&its_dev->entry);
3437 	raw_spin_unlock_irqrestore(&its_dev->its->lock, flags);
3438 	kfree(its_dev->event_map.col_map);
3439 	kfree(its_dev->itt);
3440 	kfree(its_dev);
3441 }
3442 
3443 static int its_alloc_device_irq(struct its_device *dev, int nvecs, irq_hw_number_t *hwirq)
3444 {
3445 	int idx;
3446 
3447 	/* Find a free LPI region in lpi_map and allocate them. */
3448 	idx = bitmap_find_free_region(dev->event_map.lpi_map,
3449 				      dev->event_map.nr_lpis,
3450 				      get_count_order(nvecs));
3451 	if (idx < 0)
3452 		return -ENOSPC;
3453 
3454 	*hwirq = dev->event_map.lpi_base + idx;
3455 
3456 	return 0;
3457 }
3458 
3459 static int its_msi_prepare(struct irq_domain *domain, struct device *dev,
3460 			   int nvec, msi_alloc_info_t *info)
3461 {
3462 	struct its_node *its;
3463 	struct its_device *its_dev;
3464 	struct msi_domain_info *msi_info;
3465 	u32 dev_id;
3466 	int err = 0;
3467 
3468 	/*
3469 	 * We ignore "dev" entirely, and rely on the dev_id that has
3470 	 * been passed via the scratchpad. This limits this domain's
3471 	 * usefulness to upper layers that definitely know that they
3472 	 * are built on top of the ITS.
3473 	 */
3474 	dev_id = info->scratchpad[0].ul;
3475 
3476 	msi_info = msi_get_domain_info(domain);
3477 	its = msi_info->data;
3478 
3479 	if (!gic_rdists->has_direct_lpi &&
3480 	    vpe_proxy.dev &&
3481 	    vpe_proxy.dev->its == its &&
3482 	    dev_id == vpe_proxy.dev->device_id) {
3483 		/* Bad luck. Get yourself a better implementation */
3484 		WARN_ONCE(1, "DevId %x clashes with GICv4 VPE proxy device\n",
3485 			  dev_id);
3486 		return -EINVAL;
3487 	}
3488 
3489 	mutex_lock(&its->dev_alloc_lock);
3490 	its_dev = its_find_device(its, dev_id);
3491 	if (its_dev) {
3492 		/*
3493 		 * We already have seen this ID, probably through
3494 		 * another alias (PCI bridge of some sort). No need to
3495 		 * create the device.
3496 		 */
3497 		its_dev->shared = true;
3498 		pr_debug("Reusing ITT for devID %x\n", dev_id);
3499 		goto out;
3500 	}
3501 
3502 	its_dev = its_create_device(its, dev_id, nvec, true);
3503 	if (!its_dev) {
3504 		err = -ENOMEM;
3505 		goto out;
3506 	}
3507 
3508 	if (info->flags & MSI_ALLOC_FLAGS_PROXY_DEVICE)
3509 		its_dev->shared = true;
3510 
3511 	pr_debug("ITT %d entries, %d bits\n", nvec, ilog2(nvec));
3512 out:
3513 	mutex_unlock(&its->dev_alloc_lock);
3514 	info->scratchpad[0].ptr = its_dev;
3515 	return err;
3516 }
3517 
3518 static struct msi_domain_ops its_msi_domain_ops = {
3519 	.msi_prepare	= its_msi_prepare,
3520 };
3521 
3522 static int its_irq_gic_domain_alloc(struct irq_domain *domain,
3523 				    unsigned int virq,
3524 				    irq_hw_number_t hwirq)
3525 {
3526 	struct irq_fwspec fwspec;
3527 
3528 	if (irq_domain_get_of_node(domain->parent)) {
3529 		fwspec.fwnode = domain->parent->fwnode;
3530 		fwspec.param_count = 3;
3531 		fwspec.param[0] = GIC_IRQ_TYPE_LPI;
3532 		fwspec.param[1] = hwirq;
3533 		fwspec.param[2] = IRQ_TYPE_EDGE_RISING;
3534 	} else if (is_fwnode_irqchip(domain->parent->fwnode)) {
3535 		fwspec.fwnode = domain->parent->fwnode;
3536 		fwspec.param_count = 2;
3537 		fwspec.param[0] = hwirq;
3538 		fwspec.param[1] = IRQ_TYPE_EDGE_RISING;
3539 	} else {
3540 		return -EINVAL;
3541 	}
3542 
3543 	return irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
3544 }
3545 
3546 static int its_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
3547 				unsigned int nr_irqs, void *args)
3548 {
3549 	msi_alloc_info_t *info = args;
3550 	struct its_device *its_dev = info->scratchpad[0].ptr;
3551 	struct its_node *its = its_dev->its;
3552 	struct irq_data *irqd;
3553 	irq_hw_number_t hwirq;
3554 	int err;
3555 	int i;
3556 
3557 	err = its_alloc_device_irq(its_dev, nr_irqs, &hwirq);
3558 	if (err)
3559 		return err;
3560 
3561 	err = iommu_dma_prepare_msi(info->desc, its->get_msi_base(its_dev));
3562 	if (err)
3563 		return err;
3564 
3565 	for (i = 0; i < nr_irqs; i++) {
3566 		err = its_irq_gic_domain_alloc(domain, virq + i, hwirq + i);
3567 		if (err)
3568 			return err;
3569 
3570 		irq_domain_set_hwirq_and_chip(domain, virq + i,
3571 					      hwirq + i, &its_irq_chip, its_dev);
3572 		irqd = irq_get_irq_data(virq + i);
3573 		irqd_set_single_target(irqd);
3574 		irqd_set_affinity_on_activate(irqd);
3575 		pr_debug("ID:%d pID:%d vID:%d\n",
3576 			 (int)(hwirq + i - its_dev->event_map.lpi_base),
3577 			 (int)(hwirq + i), virq + i);
3578 	}
3579 
3580 	return 0;
3581 }
3582 
3583 static int its_irq_domain_activate(struct irq_domain *domain,
3584 				   struct irq_data *d, bool reserve)
3585 {
3586 	struct its_device *its_dev = irq_data_get_irq_chip_data(d);
3587 	u32 event = its_get_event_id(d);
3588 	int cpu;
3589 
3590 	cpu = its_select_cpu(d, cpu_online_mask);
3591 	if (cpu < 0 || cpu >= nr_cpu_ids)
3592 		return -EINVAL;
3593 
3594 	its_inc_lpi_count(d, cpu);
3595 	its_dev->event_map.col_map[event] = cpu;
3596 	irq_data_update_effective_affinity(d, cpumask_of(cpu));
3597 
3598 	/* Map the GIC IRQ and event to the device */
3599 	its_send_mapti(its_dev, d->hwirq, event);
3600 	return 0;
3601 }
3602 
3603 static void its_irq_domain_deactivate(struct irq_domain *domain,
3604 				      struct irq_data *d)
3605 {
3606 	struct its_device *its_dev = irq_data_get_irq_chip_data(d);
3607 	u32 event = its_get_event_id(d);
3608 
3609 	its_dec_lpi_count(d, its_dev->event_map.col_map[event]);
3610 	/* Stop the delivery of interrupts */
3611 	its_send_discard(its_dev, event);
3612 }
3613 
3614 static void its_irq_domain_free(struct irq_domain *domain, unsigned int virq,
3615 				unsigned int nr_irqs)
3616 {
3617 	struct irq_data *d = irq_domain_get_irq_data(domain, virq);
3618 	struct its_device *its_dev = irq_data_get_irq_chip_data(d);
3619 	struct its_node *its = its_dev->its;
3620 	int i;
3621 
3622 	bitmap_release_region(its_dev->event_map.lpi_map,
3623 			      its_get_event_id(irq_domain_get_irq_data(domain, virq)),
3624 			      get_count_order(nr_irqs));
3625 
3626 	for (i = 0; i < nr_irqs; i++) {
3627 		struct irq_data *data = irq_domain_get_irq_data(domain,
3628 								virq + i);
3629 		/* Nuke the entry in the domain */
3630 		irq_domain_reset_irq_data(data);
3631 	}
3632 
3633 	mutex_lock(&its->dev_alloc_lock);
3634 
3635 	/*
3636 	 * If all interrupts have been freed, start mopping the
3637 	 * floor. This is conditioned on the device not being shared.
3638 	 */
3639 	if (!its_dev->shared &&
3640 	    bitmap_empty(its_dev->event_map.lpi_map,
3641 			 its_dev->event_map.nr_lpis)) {
3642 		its_lpi_free(its_dev->event_map.lpi_map,
3643 			     its_dev->event_map.lpi_base,
3644 			     its_dev->event_map.nr_lpis);
3645 
3646 		/* Unmap device/itt */
3647 		its_send_mapd(its_dev, 0);
3648 		its_free_device(its_dev);
3649 	}
3650 
3651 	mutex_unlock(&its->dev_alloc_lock);
3652 
3653 	irq_domain_free_irqs_parent(domain, virq, nr_irqs);
3654 }
3655 
3656 static const struct irq_domain_ops its_domain_ops = {
3657 	.alloc			= its_irq_domain_alloc,
3658 	.free			= its_irq_domain_free,
3659 	.activate		= its_irq_domain_activate,
3660 	.deactivate		= its_irq_domain_deactivate,
3661 };
3662 
3663 /*
3664  * This is insane.
3665  *
3666  * If a GICv4.0 doesn't implement Direct LPIs (which is extremely
3667  * likely), the only way to perform an invalidate is to use a fake
3668  * device to issue an INV command, implying that the LPI has first
3669  * been mapped to some event on that device. Since this is not exactly
3670  * cheap, we try to keep that mapping around as long as possible, and
3671  * only issue an UNMAP if we're short on available slots.
3672  *
3673  * Broken by design(tm).
3674  *
3675  * GICv4.1, on the other hand, mandates that we're able to invalidate
3676  * by writing to a MMIO register. It doesn't implement the whole of
3677  * DirectLPI, but that's good enough. And most of the time, we don't
3678  * even have to invalidate anything, as the redistributor can be told
3679  * whether to generate a doorbell or not (we thus leave it enabled,
3680  * always).
3681  */
3682 static void its_vpe_db_proxy_unmap_locked(struct its_vpe *vpe)
3683 {
3684 	/* GICv4.1 doesn't use a proxy, so nothing to do here */
3685 	if (gic_rdists->has_rvpeid)
3686 		return;
3687 
3688 	/* Already unmapped? */
3689 	if (vpe->vpe_proxy_event == -1)
3690 		return;
3691 
3692 	its_send_discard(vpe_proxy.dev, vpe->vpe_proxy_event);
3693 	vpe_proxy.vpes[vpe->vpe_proxy_event] = NULL;
3694 
3695 	/*
3696 	 * We don't track empty slots at all, so let's move the
3697 	 * next_victim pointer if we can quickly reuse that slot
3698 	 * instead of nuking an existing entry. Not clear that this is
3699 	 * always a win though, and this might just generate a ripple
3700 	 * effect... Let's just hope VPEs don't migrate too often.
3701 	 */
3702 	if (vpe_proxy.vpes[vpe_proxy.next_victim])
3703 		vpe_proxy.next_victim = vpe->vpe_proxy_event;
3704 
3705 	vpe->vpe_proxy_event = -1;
3706 }
3707 
3708 static void its_vpe_db_proxy_unmap(struct its_vpe *vpe)
3709 {
3710 	/* GICv4.1 doesn't use a proxy, so nothing to do here */
3711 	if (gic_rdists->has_rvpeid)
3712 		return;
3713 
3714 	if (!gic_rdists->has_direct_lpi) {
3715 		unsigned long flags;
3716 
3717 		raw_spin_lock_irqsave(&vpe_proxy.lock, flags);
3718 		its_vpe_db_proxy_unmap_locked(vpe);
3719 		raw_spin_unlock_irqrestore(&vpe_proxy.lock, flags);
3720 	}
3721 }
3722 
3723 static void its_vpe_db_proxy_map_locked(struct its_vpe *vpe)
3724 {
3725 	/* GICv4.1 doesn't use a proxy, so nothing to do here */
3726 	if (gic_rdists->has_rvpeid)
3727 		return;
3728 
3729 	/* Already mapped? */
3730 	if (vpe->vpe_proxy_event != -1)
3731 		return;
3732 
3733 	/* This slot was already allocated. Kick the other VPE out. */
3734 	if (vpe_proxy.vpes[vpe_proxy.next_victim])
3735 		its_vpe_db_proxy_unmap_locked(vpe_proxy.vpes[vpe_proxy.next_victim]);
3736 
3737 	/* Map the new VPE instead */
3738 	vpe_proxy.vpes[vpe_proxy.next_victim] = vpe;
3739 	vpe->vpe_proxy_event = vpe_proxy.next_victim;
3740 	vpe_proxy.next_victim = (vpe_proxy.next_victim + 1) % vpe_proxy.dev->nr_ites;
3741 
3742 	vpe_proxy.dev->event_map.col_map[vpe->vpe_proxy_event] = vpe->col_idx;
3743 	its_send_mapti(vpe_proxy.dev, vpe->vpe_db_lpi, vpe->vpe_proxy_event);
3744 }
3745 
3746 static void its_vpe_db_proxy_move(struct its_vpe *vpe, int from, int to)
3747 {
3748 	unsigned long flags;
3749 	struct its_collection *target_col;
3750 
3751 	/* GICv4.1 doesn't use a proxy, so nothing to do here */
3752 	if (gic_rdists->has_rvpeid)
3753 		return;
3754 
3755 	if (gic_rdists->has_direct_lpi) {
3756 		void __iomem *rdbase;
3757 
3758 		rdbase = per_cpu_ptr(gic_rdists->rdist, from)->rd_base;
3759 		gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_CLRLPIR);
3760 		wait_for_syncr(rdbase);
3761 
3762 		return;
3763 	}
3764 
3765 	raw_spin_lock_irqsave(&vpe_proxy.lock, flags);
3766 
3767 	its_vpe_db_proxy_map_locked(vpe);
3768 
3769 	target_col = &vpe_proxy.dev->its->collections[to];
3770 	its_send_movi(vpe_proxy.dev, target_col, vpe->vpe_proxy_event);
3771 	vpe_proxy.dev->event_map.col_map[vpe->vpe_proxy_event] = to;
3772 
3773 	raw_spin_unlock_irqrestore(&vpe_proxy.lock, flags);
3774 }
3775 
3776 static int its_vpe_set_affinity(struct irq_data *d,
3777 				const struct cpumask *mask_val,
3778 				bool force)
3779 {
3780 	struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
3781 	int from, cpu = cpumask_first(mask_val);
3782 	unsigned long flags;
3783 
3784 	/*
3785 	 * Changing affinity is mega expensive, so let's be as lazy as
3786 	 * we can and only do it if we really have to. Also, if mapped
3787 	 * into the proxy device, we need to move the doorbell
3788 	 * interrupt to its new location.
3789 	 *
3790 	 * Another thing is that changing the affinity of a vPE affects
3791 	 * *other interrupts* such as all the vLPIs that are routed to
3792 	 * this vPE. This means that the irq_desc lock is not enough to
3793 	 * protect us, and that we must ensure nobody samples vpe->col_idx
3794 	 * during the update, hence the lock below which must also be
3795 	 * taken on any vLPI handling path that evaluates vpe->col_idx.
3796 	 */
3797 	from = vpe_to_cpuid_lock(vpe, &flags);
3798 	if (from == cpu)
3799 		goto out;
3800 
3801 	vpe->col_idx = cpu;
3802 
3803 	/*
3804 	 * GICv4.1 allows us to skip VMOVP if moving to a cpu whose RD
3805 	 * is sharing its VPE table with the current one.
3806 	 */
3807 	if (gic_data_rdist_cpu(cpu)->vpe_table_mask &&
3808 	    cpumask_test_cpu(from, gic_data_rdist_cpu(cpu)->vpe_table_mask))
3809 		goto out;
3810 
3811 	its_send_vmovp(vpe);
3812 	its_vpe_db_proxy_move(vpe, from, cpu);
3813 
3814 out:
3815 	irq_data_update_effective_affinity(d, cpumask_of(cpu));
3816 	vpe_to_cpuid_unlock(vpe, flags);
3817 
3818 	return IRQ_SET_MASK_OK_DONE;
3819 }
3820 
3821 static void its_wait_vpt_parse_complete(void)
3822 {
3823 	void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
3824 	u64 val;
3825 
3826 	if (!gic_rdists->has_vpend_valid_dirty)
3827 		return;
3828 
3829 	WARN_ON_ONCE(readq_relaxed_poll_timeout_atomic(vlpi_base + GICR_VPENDBASER,
3830 						       val,
3831 						       !(val & GICR_VPENDBASER_Dirty),
3832 						       1, 500));
3833 }
3834 
3835 static void its_vpe_schedule(struct its_vpe *vpe)
3836 {
3837 	void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
3838 	u64 val;
3839 
3840 	/* Schedule the VPE */
3841 	val  = virt_to_phys(page_address(vpe->its_vm->vprop_page)) &
3842 		GENMASK_ULL(51, 12);
3843 	val |= (LPI_NRBITS - 1) & GICR_VPROPBASER_IDBITS_MASK;
3844 	val |= GICR_VPROPBASER_RaWb;
3845 	val |= GICR_VPROPBASER_InnerShareable;
3846 	gicr_write_vpropbaser(val, vlpi_base + GICR_VPROPBASER);
3847 
3848 	val  = virt_to_phys(page_address(vpe->vpt_page)) &
3849 		GENMASK_ULL(51, 16);
3850 	val |= GICR_VPENDBASER_RaWaWb;
3851 	val |= GICR_VPENDBASER_InnerShareable;
3852 	/*
3853 	 * There is no good way of finding out if the pending table is
3854 	 * empty as we can race against the doorbell interrupt very
3855 	 * easily. So in the end, vpe->pending_last is only an
3856 	 * indication that the vcpu has something pending, not one
3857 	 * that the pending table is empty. A good implementation
3858 	 * would be able to read its coarse map pretty quickly anyway,
3859 	 * making this a tolerable issue.
3860 	 */
3861 	val |= GICR_VPENDBASER_PendingLast;
3862 	val |= vpe->idai ? GICR_VPENDBASER_IDAI : 0;
3863 	val |= GICR_VPENDBASER_Valid;
3864 	gicr_write_vpendbaser(val, vlpi_base + GICR_VPENDBASER);
3865 }
3866 
3867 static void its_vpe_deschedule(struct its_vpe *vpe)
3868 {
3869 	void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
3870 	u64 val;
3871 
3872 	val = its_clear_vpend_valid(vlpi_base, 0, 0);
3873 
3874 	vpe->idai = !!(val & GICR_VPENDBASER_IDAI);
3875 	vpe->pending_last = !!(val & GICR_VPENDBASER_PendingLast);
3876 }
3877 
3878 static void its_vpe_invall(struct its_vpe *vpe)
3879 {
3880 	struct its_node *its;
3881 
3882 	list_for_each_entry(its, &its_nodes, entry) {
3883 		if (!is_v4(its))
3884 			continue;
3885 
3886 		if (its_list_map && !vpe->its_vm->vlpi_count[its->list_nr])
3887 			continue;
3888 
3889 		/*
3890 		 * Sending a VINVALL to a single ITS is enough, as all
3891 		 * we need is to reach the redistributors.
3892 		 */
3893 		its_send_vinvall(its, vpe);
3894 		return;
3895 	}
3896 }
3897 
3898 static int its_vpe_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
3899 {
3900 	struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
3901 	struct its_cmd_info *info = vcpu_info;
3902 
3903 	switch (info->cmd_type) {
3904 	case SCHEDULE_VPE:
3905 		its_vpe_schedule(vpe);
3906 		return 0;
3907 
3908 	case DESCHEDULE_VPE:
3909 		its_vpe_deschedule(vpe);
3910 		return 0;
3911 
3912 	case COMMIT_VPE:
3913 		its_wait_vpt_parse_complete();
3914 		return 0;
3915 
3916 	case INVALL_VPE:
3917 		its_vpe_invall(vpe);
3918 		return 0;
3919 
3920 	default:
3921 		return -EINVAL;
3922 	}
3923 }
3924 
3925 static void its_vpe_send_cmd(struct its_vpe *vpe,
3926 			     void (*cmd)(struct its_device *, u32))
3927 {
3928 	unsigned long flags;
3929 
3930 	raw_spin_lock_irqsave(&vpe_proxy.lock, flags);
3931 
3932 	its_vpe_db_proxy_map_locked(vpe);
3933 	cmd(vpe_proxy.dev, vpe->vpe_proxy_event);
3934 
3935 	raw_spin_unlock_irqrestore(&vpe_proxy.lock, flags);
3936 }
3937 
3938 static void its_vpe_send_inv(struct irq_data *d)
3939 {
3940 	struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
3941 
3942 	if (gic_rdists->has_direct_lpi) {
3943 		void __iomem *rdbase;
3944 
3945 		/* Target the redistributor this VPE is currently known on */
3946 		raw_spin_lock(&gic_data_rdist_cpu(vpe->col_idx)->rd_lock);
3947 		rdbase = per_cpu_ptr(gic_rdists->rdist, vpe->col_idx)->rd_base;
3948 		gic_write_lpir(d->parent_data->hwirq, rdbase + GICR_INVLPIR);
3949 		wait_for_syncr(rdbase);
3950 		raw_spin_unlock(&gic_data_rdist_cpu(vpe->col_idx)->rd_lock);
3951 	} else {
3952 		its_vpe_send_cmd(vpe, its_send_inv);
3953 	}
3954 }
3955 
3956 static void its_vpe_mask_irq(struct irq_data *d)
3957 {
3958 	/*
3959 	 * We need to unmask the LPI, which is described by the parent
3960 	 * irq_data. Instead of calling into the parent (which won't
3961 	 * exactly do the right thing, let's simply use the
3962 	 * parent_data pointer. Yes, I'm naughty.
3963 	 */
3964 	lpi_write_config(d->parent_data, LPI_PROP_ENABLED, 0);
3965 	its_vpe_send_inv(d);
3966 }
3967 
3968 static void its_vpe_unmask_irq(struct irq_data *d)
3969 {
3970 	/* Same hack as above... */
3971 	lpi_write_config(d->parent_data, 0, LPI_PROP_ENABLED);
3972 	its_vpe_send_inv(d);
3973 }
3974 
3975 static int its_vpe_set_irqchip_state(struct irq_data *d,
3976 				     enum irqchip_irq_state which,
3977 				     bool state)
3978 {
3979 	struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
3980 
3981 	if (which != IRQCHIP_STATE_PENDING)
3982 		return -EINVAL;
3983 
3984 	if (gic_rdists->has_direct_lpi) {
3985 		void __iomem *rdbase;
3986 
3987 		rdbase = per_cpu_ptr(gic_rdists->rdist, vpe->col_idx)->rd_base;
3988 		if (state) {
3989 			gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_SETLPIR);
3990 		} else {
3991 			gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_CLRLPIR);
3992 			wait_for_syncr(rdbase);
3993 		}
3994 	} else {
3995 		if (state)
3996 			its_vpe_send_cmd(vpe, its_send_int);
3997 		else
3998 			its_vpe_send_cmd(vpe, its_send_clear);
3999 	}
4000 
4001 	return 0;
4002 }
4003 
4004 static int its_vpe_retrigger(struct irq_data *d)
4005 {
4006 	return !its_vpe_set_irqchip_state(d, IRQCHIP_STATE_PENDING, true);
4007 }
4008 
4009 static struct irq_chip its_vpe_irq_chip = {
4010 	.name			= "GICv4-vpe",
4011 	.irq_mask		= its_vpe_mask_irq,
4012 	.irq_unmask		= its_vpe_unmask_irq,
4013 	.irq_eoi		= irq_chip_eoi_parent,
4014 	.irq_set_affinity	= its_vpe_set_affinity,
4015 	.irq_retrigger		= its_vpe_retrigger,
4016 	.irq_set_irqchip_state	= its_vpe_set_irqchip_state,
4017 	.irq_set_vcpu_affinity	= its_vpe_set_vcpu_affinity,
4018 };
4019 
4020 static struct its_node *find_4_1_its(void)
4021 {
4022 	static struct its_node *its = NULL;
4023 
4024 	if (!its) {
4025 		list_for_each_entry(its, &its_nodes, entry) {
4026 			if (is_v4_1(its))
4027 				return its;
4028 		}
4029 
4030 		/* Oops? */
4031 		its = NULL;
4032 	}
4033 
4034 	return its;
4035 }
4036 
4037 static void its_vpe_4_1_send_inv(struct irq_data *d)
4038 {
4039 	struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4040 	struct its_node *its;
4041 
4042 	/*
4043 	 * GICv4.1 wants doorbells to be invalidated using the
4044 	 * INVDB command in order to be broadcast to all RDs. Send
4045 	 * it to the first valid ITS, and let the HW do its magic.
4046 	 */
4047 	its = find_4_1_its();
4048 	if (its)
4049 		its_send_invdb(its, vpe);
4050 }
4051 
4052 static void its_vpe_4_1_mask_irq(struct irq_data *d)
4053 {
4054 	lpi_write_config(d->parent_data, LPI_PROP_ENABLED, 0);
4055 	its_vpe_4_1_send_inv(d);
4056 }
4057 
4058 static void its_vpe_4_1_unmask_irq(struct irq_data *d)
4059 {
4060 	lpi_write_config(d->parent_data, 0, LPI_PROP_ENABLED);
4061 	its_vpe_4_1_send_inv(d);
4062 }
4063 
4064 static void its_vpe_4_1_schedule(struct its_vpe *vpe,
4065 				 struct its_cmd_info *info)
4066 {
4067 	void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
4068 	u64 val = 0;
4069 
4070 	/* Schedule the VPE */
4071 	val |= GICR_VPENDBASER_Valid;
4072 	val |= info->g0en ? GICR_VPENDBASER_4_1_VGRP0EN : 0;
4073 	val |= info->g1en ? GICR_VPENDBASER_4_1_VGRP1EN : 0;
4074 	val |= FIELD_PREP(GICR_VPENDBASER_4_1_VPEID, vpe->vpe_id);
4075 
4076 	gicr_write_vpendbaser(val, vlpi_base + GICR_VPENDBASER);
4077 }
4078 
4079 static void its_vpe_4_1_deschedule(struct its_vpe *vpe,
4080 				   struct its_cmd_info *info)
4081 {
4082 	void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
4083 	u64 val;
4084 
4085 	if (info->req_db) {
4086 		unsigned long flags;
4087 
4088 		/*
4089 		 * vPE is going to block: make the vPE non-resident with
4090 		 * PendingLast clear and DB set. The GIC guarantees that if
4091 		 * we read-back PendingLast clear, then a doorbell will be
4092 		 * delivered when an interrupt comes.
4093 		 *
4094 		 * Note the locking to deal with the concurrent update of
4095 		 * pending_last from the doorbell interrupt handler that can
4096 		 * run concurrently.
4097 		 */
4098 		raw_spin_lock_irqsave(&vpe->vpe_lock, flags);
4099 		val = its_clear_vpend_valid(vlpi_base,
4100 					    GICR_VPENDBASER_PendingLast,
4101 					    GICR_VPENDBASER_4_1_DB);
4102 		vpe->pending_last = !!(val & GICR_VPENDBASER_PendingLast);
4103 		raw_spin_unlock_irqrestore(&vpe->vpe_lock, flags);
4104 	} else {
4105 		/*
4106 		 * We're not blocking, so just make the vPE non-resident
4107 		 * with PendingLast set, indicating that we'll be back.
4108 		 */
4109 		val = its_clear_vpend_valid(vlpi_base,
4110 					    0,
4111 					    GICR_VPENDBASER_PendingLast);
4112 		vpe->pending_last = true;
4113 	}
4114 }
4115 
4116 static void its_vpe_4_1_invall(struct its_vpe *vpe)
4117 {
4118 	void __iomem *rdbase;
4119 	unsigned long flags;
4120 	u64 val;
4121 	int cpu;
4122 
4123 	val  = GICR_INVALLR_V;
4124 	val |= FIELD_PREP(GICR_INVALLR_VPEID, vpe->vpe_id);
4125 
4126 	/* Target the redistributor this vPE is currently known on */
4127 	cpu = vpe_to_cpuid_lock(vpe, &flags);
4128 	raw_spin_lock(&gic_data_rdist_cpu(cpu)->rd_lock);
4129 	rdbase = per_cpu_ptr(gic_rdists->rdist, cpu)->rd_base;
4130 	gic_write_lpir(val, rdbase + GICR_INVALLR);
4131 
4132 	wait_for_syncr(rdbase);
4133 	raw_spin_unlock(&gic_data_rdist_cpu(cpu)->rd_lock);
4134 	vpe_to_cpuid_unlock(vpe, flags);
4135 }
4136 
4137 static int its_vpe_4_1_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
4138 {
4139 	struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4140 	struct its_cmd_info *info = vcpu_info;
4141 
4142 	switch (info->cmd_type) {
4143 	case SCHEDULE_VPE:
4144 		its_vpe_4_1_schedule(vpe, info);
4145 		return 0;
4146 
4147 	case DESCHEDULE_VPE:
4148 		its_vpe_4_1_deschedule(vpe, info);
4149 		return 0;
4150 
4151 	case COMMIT_VPE:
4152 		its_wait_vpt_parse_complete();
4153 		return 0;
4154 
4155 	case INVALL_VPE:
4156 		its_vpe_4_1_invall(vpe);
4157 		return 0;
4158 
4159 	default:
4160 		return -EINVAL;
4161 	}
4162 }
4163 
4164 static struct irq_chip its_vpe_4_1_irq_chip = {
4165 	.name			= "GICv4.1-vpe",
4166 	.irq_mask		= its_vpe_4_1_mask_irq,
4167 	.irq_unmask		= its_vpe_4_1_unmask_irq,
4168 	.irq_eoi		= irq_chip_eoi_parent,
4169 	.irq_set_affinity	= its_vpe_set_affinity,
4170 	.irq_set_vcpu_affinity	= its_vpe_4_1_set_vcpu_affinity,
4171 };
4172 
4173 static void its_configure_sgi(struct irq_data *d, bool clear)
4174 {
4175 	struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4176 	struct its_cmd_desc desc;
4177 
4178 	desc.its_vsgi_cmd.vpe = vpe;
4179 	desc.its_vsgi_cmd.sgi = d->hwirq;
4180 	desc.its_vsgi_cmd.priority = vpe->sgi_config[d->hwirq].priority;
4181 	desc.its_vsgi_cmd.enable = vpe->sgi_config[d->hwirq].enabled;
4182 	desc.its_vsgi_cmd.group = vpe->sgi_config[d->hwirq].group;
4183 	desc.its_vsgi_cmd.clear = clear;
4184 
4185 	/*
4186 	 * GICv4.1 allows us to send VSGI commands to any ITS as long as the
4187 	 * destination VPE is mapped there. Since we map them eagerly at
4188 	 * activation time, we're pretty sure the first GICv4.1 ITS will do.
4189 	 */
4190 	its_send_single_vcommand(find_4_1_its(), its_build_vsgi_cmd, &desc);
4191 }
4192 
4193 static void its_sgi_mask_irq(struct irq_data *d)
4194 {
4195 	struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4196 
4197 	vpe->sgi_config[d->hwirq].enabled = false;
4198 	its_configure_sgi(d, false);
4199 }
4200 
4201 static void its_sgi_unmask_irq(struct irq_data *d)
4202 {
4203 	struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4204 
4205 	vpe->sgi_config[d->hwirq].enabled = true;
4206 	its_configure_sgi(d, false);
4207 }
4208 
4209 static int its_sgi_set_affinity(struct irq_data *d,
4210 				const struct cpumask *mask_val,
4211 				bool force)
4212 {
4213 	/*
4214 	 * There is no notion of affinity for virtual SGIs, at least
4215 	 * not on the host (since they can only be targeting a vPE).
4216 	 * Tell the kernel we've done whatever it asked for.
4217 	 */
4218 	irq_data_update_effective_affinity(d, mask_val);
4219 	return IRQ_SET_MASK_OK;
4220 }
4221 
4222 static int its_sgi_set_irqchip_state(struct irq_data *d,
4223 				     enum irqchip_irq_state which,
4224 				     bool state)
4225 {
4226 	if (which != IRQCHIP_STATE_PENDING)
4227 		return -EINVAL;
4228 
4229 	if (state) {
4230 		struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4231 		struct its_node *its = find_4_1_its();
4232 		u64 val;
4233 
4234 		val  = FIELD_PREP(GITS_SGIR_VPEID, vpe->vpe_id);
4235 		val |= FIELD_PREP(GITS_SGIR_VINTID, d->hwirq);
4236 		writeq_relaxed(val, its->sgir_base + GITS_SGIR - SZ_128K);
4237 	} else {
4238 		its_configure_sgi(d, true);
4239 	}
4240 
4241 	return 0;
4242 }
4243 
4244 static int its_sgi_get_irqchip_state(struct irq_data *d,
4245 				     enum irqchip_irq_state which, bool *val)
4246 {
4247 	struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4248 	void __iomem *base;
4249 	unsigned long flags;
4250 	u32 count = 1000000;	/* 1s! */
4251 	u32 status;
4252 	int cpu;
4253 
4254 	if (which != IRQCHIP_STATE_PENDING)
4255 		return -EINVAL;
4256 
4257 	/*
4258 	 * Locking galore! We can race against two different events:
4259 	 *
4260 	 * - Concurrent vPE affinity change: we must make sure it cannot
4261 	 *   happen, or we'll talk to the wrong redistributor. This is
4262 	 *   identical to what happens with vLPIs.
4263 	 *
4264 	 * - Concurrent VSGIPENDR access: As it involves accessing two
4265 	 *   MMIO registers, this must be made atomic one way or another.
4266 	 */
4267 	cpu = vpe_to_cpuid_lock(vpe, &flags);
4268 	raw_spin_lock(&gic_data_rdist_cpu(cpu)->rd_lock);
4269 	base = gic_data_rdist_cpu(cpu)->rd_base + SZ_128K;
4270 	writel_relaxed(vpe->vpe_id, base + GICR_VSGIR);
4271 	do {
4272 		status = readl_relaxed(base + GICR_VSGIPENDR);
4273 		if (!(status & GICR_VSGIPENDR_BUSY))
4274 			goto out;
4275 
4276 		count--;
4277 		if (!count) {
4278 			pr_err_ratelimited("Unable to get SGI status\n");
4279 			goto out;
4280 		}
4281 		cpu_relax();
4282 		udelay(1);
4283 	} while (count);
4284 
4285 out:
4286 	raw_spin_unlock(&gic_data_rdist_cpu(cpu)->rd_lock);
4287 	vpe_to_cpuid_unlock(vpe, flags);
4288 
4289 	if (!count)
4290 		return -ENXIO;
4291 
4292 	*val = !!(status & (1 << d->hwirq));
4293 
4294 	return 0;
4295 }
4296 
4297 static int its_sgi_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
4298 {
4299 	struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4300 	struct its_cmd_info *info = vcpu_info;
4301 
4302 	switch (info->cmd_type) {
4303 	case PROP_UPDATE_VSGI:
4304 		vpe->sgi_config[d->hwirq].priority = info->priority;
4305 		vpe->sgi_config[d->hwirq].group = info->group;
4306 		its_configure_sgi(d, false);
4307 		return 0;
4308 
4309 	default:
4310 		return -EINVAL;
4311 	}
4312 }
4313 
4314 static struct irq_chip its_sgi_irq_chip = {
4315 	.name			= "GICv4.1-sgi",
4316 	.irq_mask		= its_sgi_mask_irq,
4317 	.irq_unmask		= its_sgi_unmask_irq,
4318 	.irq_set_affinity	= its_sgi_set_affinity,
4319 	.irq_set_irqchip_state	= its_sgi_set_irqchip_state,
4320 	.irq_get_irqchip_state	= its_sgi_get_irqchip_state,
4321 	.irq_set_vcpu_affinity	= its_sgi_set_vcpu_affinity,
4322 };
4323 
4324 static int its_sgi_irq_domain_alloc(struct irq_domain *domain,
4325 				    unsigned int virq, unsigned int nr_irqs,
4326 				    void *args)
4327 {
4328 	struct its_vpe *vpe = args;
4329 	int i;
4330 
4331 	/* Yes, we do want 16 SGIs */
4332 	WARN_ON(nr_irqs != 16);
4333 
4334 	for (i = 0; i < 16; i++) {
4335 		vpe->sgi_config[i].priority = 0;
4336 		vpe->sgi_config[i].enabled = false;
4337 		vpe->sgi_config[i].group = false;
4338 
4339 		irq_domain_set_hwirq_and_chip(domain, virq + i, i,
4340 					      &its_sgi_irq_chip, vpe);
4341 		irq_set_status_flags(virq + i, IRQ_DISABLE_UNLAZY);
4342 	}
4343 
4344 	return 0;
4345 }
4346 
4347 static void its_sgi_irq_domain_free(struct irq_domain *domain,
4348 				    unsigned int virq,
4349 				    unsigned int nr_irqs)
4350 {
4351 	/* Nothing to do */
4352 }
4353 
4354 static int its_sgi_irq_domain_activate(struct irq_domain *domain,
4355 				       struct irq_data *d, bool reserve)
4356 {
4357 	/* Write out the initial SGI configuration */
4358 	its_configure_sgi(d, false);
4359 	return 0;
4360 }
4361 
4362 static void its_sgi_irq_domain_deactivate(struct irq_domain *domain,
4363 					  struct irq_data *d)
4364 {
4365 	struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4366 
4367 	/*
4368 	 * The VSGI command is awkward:
4369 	 *
4370 	 * - To change the configuration, CLEAR must be set to false,
4371 	 *   leaving the pending bit unchanged.
4372 	 * - To clear the pending bit, CLEAR must be set to true, leaving
4373 	 *   the configuration unchanged.
4374 	 *
4375 	 * You just can't do both at once, hence the two commands below.
4376 	 */
4377 	vpe->sgi_config[d->hwirq].enabled = false;
4378 	its_configure_sgi(d, false);
4379 	its_configure_sgi(d, true);
4380 }
4381 
4382 static const struct irq_domain_ops its_sgi_domain_ops = {
4383 	.alloc		= its_sgi_irq_domain_alloc,
4384 	.free		= its_sgi_irq_domain_free,
4385 	.activate	= its_sgi_irq_domain_activate,
4386 	.deactivate	= its_sgi_irq_domain_deactivate,
4387 };
4388 
4389 static int its_vpe_id_alloc(void)
4390 {
4391 	return ida_simple_get(&its_vpeid_ida, 0, ITS_MAX_VPEID, GFP_KERNEL);
4392 }
4393 
4394 static void its_vpe_id_free(u16 id)
4395 {
4396 	ida_simple_remove(&its_vpeid_ida, id);
4397 }
4398 
4399 static int its_vpe_init(struct its_vpe *vpe)
4400 {
4401 	struct page *vpt_page;
4402 	int vpe_id;
4403 
4404 	/* Allocate vpe_id */
4405 	vpe_id = its_vpe_id_alloc();
4406 	if (vpe_id < 0)
4407 		return vpe_id;
4408 
4409 	/* Allocate VPT */
4410 	vpt_page = its_allocate_pending_table(GFP_KERNEL);
4411 	if (!vpt_page) {
4412 		its_vpe_id_free(vpe_id);
4413 		return -ENOMEM;
4414 	}
4415 
4416 	if (!its_alloc_vpe_table(vpe_id)) {
4417 		its_vpe_id_free(vpe_id);
4418 		its_free_pending_table(vpt_page);
4419 		return -ENOMEM;
4420 	}
4421 
4422 	raw_spin_lock_init(&vpe->vpe_lock);
4423 	vpe->vpe_id = vpe_id;
4424 	vpe->vpt_page = vpt_page;
4425 	if (gic_rdists->has_rvpeid)
4426 		atomic_set(&vpe->vmapp_count, 0);
4427 	else
4428 		vpe->vpe_proxy_event = -1;
4429 
4430 	return 0;
4431 }
4432 
4433 static void its_vpe_teardown(struct its_vpe *vpe)
4434 {
4435 	its_vpe_db_proxy_unmap(vpe);
4436 	its_vpe_id_free(vpe->vpe_id);
4437 	its_free_pending_table(vpe->vpt_page);
4438 }
4439 
4440 static void its_vpe_irq_domain_free(struct irq_domain *domain,
4441 				    unsigned int virq,
4442 				    unsigned int nr_irqs)
4443 {
4444 	struct its_vm *vm = domain->host_data;
4445 	int i;
4446 
4447 	irq_domain_free_irqs_parent(domain, virq, nr_irqs);
4448 
4449 	for (i = 0; i < nr_irqs; i++) {
4450 		struct irq_data *data = irq_domain_get_irq_data(domain,
4451 								virq + i);
4452 		struct its_vpe *vpe = irq_data_get_irq_chip_data(data);
4453 
4454 		BUG_ON(vm != vpe->its_vm);
4455 
4456 		clear_bit(data->hwirq, vm->db_bitmap);
4457 		its_vpe_teardown(vpe);
4458 		irq_domain_reset_irq_data(data);
4459 	}
4460 
4461 	if (bitmap_empty(vm->db_bitmap, vm->nr_db_lpis)) {
4462 		its_lpi_free(vm->db_bitmap, vm->db_lpi_base, vm->nr_db_lpis);
4463 		its_free_prop_table(vm->vprop_page);
4464 	}
4465 }
4466 
4467 static int its_vpe_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
4468 				    unsigned int nr_irqs, void *args)
4469 {
4470 	struct irq_chip *irqchip = &its_vpe_irq_chip;
4471 	struct its_vm *vm = args;
4472 	unsigned long *bitmap;
4473 	struct page *vprop_page;
4474 	int base, nr_ids, i, err = 0;
4475 
4476 	BUG_ON(!vm);
4477 
4478 	bitmap = its_lpi_alloc(roundup_pow_of_two(nr_irqs), &base, &nr_ids);
4479 	if (!bitmap)
4480 		return -ENOMEM;
4481 
4482 	if (nr_ids < nr_irqs) {
4483 		its_lpi_free(bitmap, base, nr_ids);
4484 		return -ENOMEM;
4485 	}
4486 
4487 	vprop_page = its_allocate_prop_table(GFP_KERNEL);
4488 	if (!vprop_page) {
4489 		its_lpi_free(bitmap, base, nr_ids);
4490 		return -ENOMEM;
4491 	}
4492 
4493 	vm->db_bitmap = bitmap;
4494 	vm->db_lpi_base = base;
4495 	vm->nr_db_lpis = nr_ids;
4496 	vm->vprop_page = vprop_page;
4497 
4498 	if (gic_rdists->has_rvpeid)
4499 		irqchip = &its_vpe_4_1_irq_chip;
4500 
4501 	for (i = 0; i < nr_irqs; i++) {
4502 		vm->vpes[i]->vpe_db_lpi = base + i;
4503 		err = its_vpe_init(vm->vpes[i]);
4504 		if (err)
4505 			break;
4506 		err = its_irq_gic_domain_alloc(domain, virq + i,
4507 					       vm->vpes[i]->vpe_db_lpi);
4508 		if (err)
4509 			break;
4510 		irq_domain_set_hwirq_and_chip(domain, virq + i, i,
4511 					      irqchip, vm->vpes[i]);
4512 		set_bit(i, bitmap);
4513 	}
4514 
4515 	if (err) {
4516 		if (i > 0)
4517 			its_vpe_irq_domain_free(domain, virq, i);
4518 
4519 		its_lpi_free(bitmap, base, nr_ids);
4520 		its_free_prop_table(vprop_page);
4521 	}
4522 
4523 	return err;
4524 }
4525 
4526 static int its_vpe_irq_domain_activate(struct irq_domain *domain,
4527 				       struct irq_data *d, bool reserve)
4528 {
4529 	struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4530 	struct its_node *its;
4531 
4532 	/*
4533 	 * If we use the list map, we issue VMAPP on demand... Unless
4534 	 * we're on a GICv4.1 and we eagerly map the VPE on all ITSs
4535 	 * so that VSGIs can work.
4536 	 */
4537 	if (!gic_requires_eager_mapping())
4538 		return 0;
4539 
4540 	/* Map the VPE to the first possible CPU */
4541 	vpe->col_idx = cpumask_first(cpu_online_mask);
4542 
4543 	list_for_each_entry(its, &its_nodes, entry) {
4544 		if (!is_v4(its))
4545 			continue;
4546 
4547 		its_send_vmapp(its, vpe, true);
4548 		its_send_vinvall(its, vpe);
4549 	}
4550 
4551 	irq_data_update_effective_affinity(d, cpumask_of(vpe->col_idx));
4552 
4553 	return 0;
4554 }
4555 
4556 static void its_vpe_irq_domain_deactivate(struct irq_domain *domain,
4557 					  struct irq_data *d)
4558 {
4559 	struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4560 	struct its_node *its;
4561 
4562 	/*
4563 	 * If we use the list map on GICv4.0, we unmap the VPE once no
4564 	 * VLPIs are associated with the VM.
4565 	 */
4566 	if (!gic_requires_eager_mapping())
4567 		return;
4568 
4569 	list_for_each_entry(its, &its_nodes, entry) {
4570 		if (!is_v4(its))
4571 			continue;
4572 
4573 		its_send_vmapp(its, vpe, false);
4574 	}
4575 
4576 	/*
4577 	 * There may be a direct read to the VPT after unmapping the
4578 	 * vPE, to guarantee the validity of this, we make the VPT
4579 	 * memory coherent with the CPU caches here.
4580 	 */
4581 	if (find_4_1_its() && !atomic_read(&vpe->vmapp_count))
4582 		gic_flush_dcache_to_poc(page_address(vpe->vpt_page),
4583 					LPI_PENDBASE_SZ);
4584 }
4585 
4586 static const struct irq_domain_ops its_vpe_domain_ops = {
4587 	.alloc			= its_vpe_irq_domain_alloc,
4588 	.free			= its_vpe_irq_domain_free,
4589 	.activate		= its_vpe_irq_domain_activate,
4590 	.deactivate		= its_vpe_irq_domain_deactivate,
4591 };
4592 
4593 static int its_force_quiescent(void __iomem *base)
4594 {
4595 	u32 count = 1000000;	/* 1s */
4596 	u32 val;
4597 
4598 	val = readl_relaxed(base + GITS_CTLR);
4599 	/*
4600 	 * GIC architecture specification requires the ITS to be both
4601 	 * disabled and quiescent for writes to GITS_BASER<n> or
4602 	 * GITS_CBASER to not have UNPREDICTABLE results.
4603 	 */
4604 	if ((val & GITS_CTLR_QUIESCENT) && !(val & GITS_CTLR_ENABLE))
4605 		return 0;
4606 
4607 	/* Disable the generation of all interrupts to this ITS */
4608 	val &= ~(GITS_CTLR_ENABLE | GITS_CTLR_ImDe);
4609 	writel_relaxed(val, base + GITS_CTLR);
4610 
4611 	/* Poll GITS_CTLR and wait until ITS becomes quiescent */
4612 	while (1) {
4613 		val = readl_relaxed(base + GITS_CTLR);
4614 		if (val & GITS_CTLR_QUIESCENT)
4615 			return 0;
4616 
4617 		count--;
4618 		if (!count)
4619 			return -EBUSY;
4620 
4621 		cpu_relax();
4622 		udelay(1);
4623 	}
4624 }
4625 
4626 static bool __maybe_unused its_enable_quirk_cavium_22375(void *data)
4627 {
4628 	struct its_node *its = data;
4629 
4630 	/* erratum 22375: only alloc 8MB table size (20 bits) */
4631 	its->typer &= ~GITS_TYPER_DEVBITS;
4632 	its->typer |= FIELD_PREP(GITS_TYPER_DEVBITS, 20 - 1);
4633 	its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_22375;
4634 
4635 	return true;
4636 }
4637 
4638 static bool __maybe_unused its_enable_quirk_cavium_23144(void *data)
4639 {
4640 	struct its_node *its = data;
4641 
4642 	its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_23144;
4643 
4644 	return true;
4645 }
4646 
4647 static bool __maybe_unused its_enable_quirk_qdf2400_e0065(void *data)
4648 {
4649 	struct its_node *its = data;
4650 
4651 	/* On QDF2400, the size of the ITE is 16Bytes */
4652 	its->typer &= ~GITS_TYPER_ITT_ENTRY_SIZE;
4653 	its->typer |= FIELD_PREP(GITS_TYPER_ITT_ENTRY_SIZE, 16 - 1);
4654 
4655 	return true;
4656 }
4657 
4658 static u64 its_irq_get_msi_base_pre_its(struct its_device *its_dev)
4659 {
4660 	struct its_node *its = its_dev->its;
4661 
4662 	/*
4663 	 * The Socionext Synquacer SoC has a so-called 'pre-ITS',
4664 	 * which maps 32-bit writes targeted at a separate window of
4665 	 * size '4 << device_id_bits' onto writes to GITS_TRANSLATER
4666 	 * with device ID taken from bits [device_id_bits + 1:2] of
4667 	 * the window offset.
4668 	 */
4669 	return its->pre_its_base + (its_dev->device_id << 2);
4670 }
4671 
4672 static bool __maybe_unused its_enable_quirk_socionext_synquacer(void *data)
4673 {
4674 	struct its_node *its = data;
4675 	u32 pre_its_window[2];
4676 	u32 ids;
4677 
4678 	if (!fwnode_property_read_u32_array(its->fwnode_handle,
4679 					   "socionext,synquacer-pre-its",
4680 					   pre_its_window,
4681 					   ARRAY_SIZE(pre_its_window))) {
4682 
4683 		its->pre_its_base = pre_its_window[0];
4684 		its->get_msi_base = its_irq_get_msi_base_pre_its;
4685 
4686 		ids = ilog2(pre_its_window[1]) - 2;
4687 		if (device_ids(its) > ids) {
4688 			its->typer &= ~GITS_TYPER_DEVBITS;
4689 			its->typer |= FIELD_PREP(GITS_TYPER_DEVBITS, ids - 1);
4690 		}
4691 
4692 		/* the pre-ITS breaks isolation, so disable MSI remapping */
4693 		its->msi_domain_flags &= ~IRQ_DOMAIN_FLAG_MSI_REMAP;
4694 		return true;
4695 	}
4696 	return false;
4697 }
4698 
4699 static bool __maybe_unused its_enable_quirk_hip07_161600802(void *data)
4700 {
4701 	struct its_node *its = data;
4702 
4703 	/*
4704 	 * Hip07 insists on using the wrong address for the VLPI
4705 	 * page. Trick it into doing the right thing...
4706 	 */
4707 	its->vlpi_redist_offset = SZ_128K;
4708 	return true;
4709 }
4710 
4711 static const struct gic_quirk its_quirks[] = {
4712 #ifdef CONFIG_CAVIUM_ERRATUM_22375
4713 	{
4714 		.desc	= "ITS: Cavium errata 22375, 24313",
4715 		.iidr	= 0xa100034c,	/* ThunderX pass 1.x */
4716 		.mask	= 0xffff0fff,
4717 		.init	= its_enable_quirk_cavium_22375,
4718 	},
4719 #endif
4720 #ifdef CONFIG_CAVIUM_ERRATUM_23144
4721 	{
4722 		.desc	= "ITS: Cavium erratum 23144",
4723 		.iidr	= 0xa100034c,	/* ThunderX pass 1.x */
4724 		.mask	= 0xffff0fff,
4725 		.init	= its_enable_quirk_cavium_23144,
4726 	},
4727 #endif
4728 #ifdef CONFIG_QCOM_QDF2400_ERRATUM_0065
4729 	{
4730 		.desc	= "ITS: QDF2400 erratum 0065",
4731 		.iidr	= 0x00001070, /* QDF2400 ITS rev 1.x */
4732 		.mask	= 0xffffffff,
4733 		.init	= its_enable_quirk_qdf2400_e0065,
4734 	},
4735 #endif
4736 #ifdef CONFIG_SOCIONEXT_SYNQUACER_PREITS
4737 	{
4738 		/*
4739 		 * The Socionext Synquacer SoC incorporates ARM's own GIC-500
4740 		 * implementation, but with a 'pre-ITS' added that requires
4741 		 * special handling in software.
4742 		 */
4743 		.desc	= "ITS: Socionext Synquacer pre-ITS",
4744 		.iidr	= 0x0001143b,
4745 		.mask	= 0xffffffff,
4746 		.init	= its_enable_quirk_socionext_synquacer,
4747 	},
4748 #endif
4749 #ifdef CONFIG_HISILICON_ERRATUM_161600802
4750 	{
4751 		.desc	= "ITS: Hip07 erratum 161600802",
4752 		.iidr	= 0x00000004,
4753 		.mask	= 0xffffffff,
4754 		.init	= its_enable_quirk_hip07_161600802,
4755 	},
4756 #endif
4757 	{
4758 	}
4759 };
4760 
4761 static void its_enable_quirks(struct its_node *its)
4762 {
4763 	u32 iidr = readl_relaxed(its->base + GITS_IIDR);
4764 
4765 	gic_enable_quirks(iidr, its_quirks, its);
4766 }
4767 
4768 static int its_save_disable(void)
4769 {
4770 	struct its_node *its;
4771 	int err = 0;
4772 
4773 	raw_spin_lock(&its_lock);
4774 	list_for_each_entry(its, &its_nodes, entry) {
4775 		void __iomem *base;
4776 
4777 		base = its->base;
4778 		its->ctlr_save = readl_relaxed(base + GITS_CTLR);
4779 		err = its_force_quiescent(base);
4780 		if (err) {
4781 			pr_err("ITS@%pa: failed to quiesce: %d\n",
4782 			       &its->phys_base, err);
4783 			writel_relaxed(its->ctlr_save, base + GITS_CTLR);
4784 			goto err;
4785 		}
4786 
4787 		its->cbaser_save = gits_read_cbaser(base + GITS_CBASER);
4788 	}
4789 
4790 err:
4791 	if (err) {
4792 		list_for_each_entry_continue_reverse(its, &its_nodes, entry) {
4793 			void __iomem *base;
4794 
4795 			base = its->base;
4796 			writel_relaxed(its->ctlr_save, base + GITS_CTLR);
4797 		}
4798 	}
4799 	raw_spin_unlock(&its_lock);
4800 
4801 	return err;
4802 }
4803 
4804 static void its_restore_enable(void)
4805 {
4806 	struct its_node *its;
4807 	int ret;
4808 
4809 	raw_spin_lock(&its_lock);
4810 	list_for_each_entry(its, &its_nodes, entry) {
4811 		void __iomem *base;
4812 		int i;
4813 
4814 		base = its->base;
4815 
4816 		/*
4817 		 * Make sure that the ITS is disabled. If it fails to quiesce,
4818 		 * don't restore it since writing to CBASER or BASER<n>
4819 		 * registers is undefined according to the GIC v3 ITS
4820 		 * Specification.
4821 		 *
4822 		 * Firmware resuming with the ITS enabled is terminally broken.
4823 		 */
4824 		WARN_ON(readl_relaxed(base + GITS_CTLR) & GITS_CTLR_ENABLE);
4825 		ret = its_force_quiescent(base);
4826 		if (ret) {
4827 			pr_err("ITS@%pa: failed to quiesce on resume: %d\n",
4828 			       &its->phys_base, ret);
4829 			continue;
4830 		}
4831 
4832 		gits_write_cbaser(its->cbaser_save, base + GITS_CBASER);
4833 
4834 		/*
4835 		 * Writing CBASER resets CREADR to 0, so make CWRITER and
4836 		 * cmd_write line up with it.
4837 		 */
4838 		its->cmd_write = its->cmd_base;
4839 		gits_write_cwriter(0, base + GITS_CWRITER);
4840 
4841 		/* Restore GITS_BASER from the value cache. */
4842 		for (i = 0; i < GITS_BASER_NR_REGS; i++) {
4843 			struct its_baser *baser = &its->tables[i];
4844 
4845 			if (!(baser->val & GITS_BASER_VALID))
4846 				continue;
4847 
4848 			its_write_baser(its, baser, baser->val);
4849 		}
4850 		writel_relaxed(its->ctlr_save, base + GITS_CTLR);
4851 
4852 		/*
4853 		 * Reinit the collection if it's stored in the ITS. This is
4854 		 * indicated by the col_id being less than the HCC field.
4855 		 * CID < HCC as specified in the GIC v3 Documentation.
4856 		 */
4857 		if (its->collections[smp_processor_id()].col_id <
4858 		    GITS_TYPER_HCC(gic_read_typer(base + GITS_TYPER)))
4859 			its_cpu_init_collection(its);
4860 	}
4861 	raw_spin_unlock(&its_lock);
4862 }
4863 
4864 static struct syscore_ops its_syscore_ops = {
4865 	.suspend = its_save_disable,
4866 	.resume = its_restore_enable,
4867 };
4868 
4869 static void __init __iomem *its_map_one(struct resource *res, int *err)
4870 {
4871 	void __iomem *its_base;
4872 	u32 val;
4873 
4874 	its_base = ioremap(res->start, SZ_64K);
4875 	if (!its_base) {
4876 		pr_warn("ITS@%pa: Unable to map ITS registers\n", &res->start);
4877 		*err = -ENOMEM;
4878 		return NULL;
4879 	}
4880 
4881 	val = readl_relaxed(its_base + GITS_PIDR2) & GIC_PIDR2_ARCH_MASK;
4882 	if (val != 0x30 && val != 0x40) {
4883 		pr_warn("ITS@%pa: No ITS detected, giving up\n", &res->start);
4884 		*err = -ENODEV;
4885 		goto out_unmap;
4886 	}
4887 
4888 	*err = its_force_quiescent(its_base);
4889 	if (*err) {
4890 		pr_warn("ITS@%pa: Failed to quiesce, giving up\n", &res->start);
4891 		goto out_unmap;
4892 	}
4893 
4894 	return its_base;
4895 
4896 out_unmap:
4897 	iounmap(its_base);
4898 	return NULL;
4899 }
4900 
4901 static int its_init_domain(struct fwnode_handle *handle, struct its_node *its)
4902 {
4903 	struct irq_domain *inner_domain;
4904 	struct msi_domain_info *info;
4905 
4906 	info = kzalloc(sizeof(*info), GFP_KERNEL);
4907 	if (!info)
4908 		return -ENOMEM;
4909 
4910 	inner_domain = irq_domain_create_tree(handle, &its_domain_ops, its);
4911 	if (!inner_domain) {
4912 		kfree(info);
4913 		return -ENOMEM;
4914 	}
4915 
4916 	inner_domain->parent = its_parent;
4917 	irq_domain_update_bus_token(inner_domain, DOMAIN_BUS_NEXUS);
4918 	inner_domain->flags |= its->msi_domain_flags;
4919 	info->ops = &its_msi_domain_ops;
4920 	info->data = its;
4921 	inner_domain->host_data = info;
4922 
4923 	return 0;
4924 }
4925 
4926 static int its_init_vpe_domain(void)
4927 {
4928 	struct its_node *its;
4929 	u32 devid;
4930 	int entries;
4931 
4932 	if (gic_rdists->has_direct_lpi) {
4933 		pr_info("ITS: Using DirectLPI for VPE invalidation\n");
4934 		return 0;
4935 	}
4936 
4937 	/* Any ITS will do, even if not v4 */
4938 	its = list_first_entry(&its_nodes, struct its_node, entry);
4939 
4940 	entries = roundup_pow_of_two(nr_cpu_ids);
4941 	vpe_proxy.vpes = kcalloc(entries, sizeof(*vpe_proxy.vpes),
4942 				 GFP_KERNEL);
4943 	if (!vpe_proxy.vpes)
4944 		return -ENOMEM;
4945 
4946 	/* Use the last possible DevID */
4947 	devid = GENMASK(device_ids(its) - 1, 0);
4948 	vpe_proxy.dev = its_create_device(its, devid, entries, false);
4949 	if (!vpe_proxy.dev) {
4950 		kfree(vpe_proxy.vpes);
4951 		pr_err("ITS: Can't allocate GICv4 proxy device\n");
4952 		return -ENOMEM;
4953 	}
4954 
4955 	BUG_ON(entries > vpe_proxy.dev->nr_ites);
4956 
4957 	raw_spin_lock_init(&vpe_proxy.lock);
4958 	vpe_proxy.next_victim = 0;
4959 	pr_info("ITS: Allocated DevID %x as GICv4 proxy device (%d slots)\n",
4960 		devid, vpe_proxy.dev->nr_ites);
4961 
4962 	return 0;
4963 }
4964 
4965 static int __init its_compute_its_list_map(struct resource *res,
4966 					   void __iomem *its_base)
4967 {
4968 	int its_number;
4969 	u32 ctlr;
4970 
4971 	/*
4972 	 * This is assumed to be done early enough that we're
4973 	 * guaranteed to be single-threaded, hence no
4974 	 * locking. Should this change, we should address
4975 	 * this.
4976 	 */
4977 	its_number = find_first_zero_bit(&its_list_map, GICv4_ITS_LIST_MAX);
4978 	if (its_number >= GICv4_ITS_LIST_MAX) {
4979 		pr_err("ITS@%pa: No ITSList entry available!\n",
4980 		       &res->start);
4981 		return -EINVAL;
4982 	}
4983 
4984 	ctlr = readl_relaxed(its_base + GITS_CTLR);
4985 	ctlr &= ~GITS_CTLR_ITS_NUMBER;
4986 	ctlr |= its_number << GITS_CTLR_ITS_NUMBER_SHIFT;
4987 	writel_relaxed(ctlr, its_base + GITS_CTLR);
4988 	ctlr = readl_relaxed(its_base + GITS_CTLR);
4989 	if ((ctlr & GITS_CTLR_ITS_NUMBER) != (its_number << GITS_CTLR_ITS_NUMBER_SHIFT)) {
4990 		its_number = ctlr & GITS_CTLR_ITS_NUMBER;
4991 		its_number >>= GITS_CTLR_ITS_NUMBER_SHIFT;
4992 	}
4993 
4994 	if (test_and_set_bit(its_number, &its_list_map)) {
4995 		pr_err("ITS@%pa: Duplicate ITSList entry %d\n",
4996 		       &res->start, its_number);
4997 		return -EINVAL;
4998 	}
4999 
5000 	return its_number;
5001 }
5002 
5003 static int __init its_probe_one(struct resource *res,
5004 				struct fwnode_handle *handle, int numa_node)
5005 {
5006 	struct its_node *its;
5007 	void __iomem *its_base;
5008 	u64 baser, tmp, typer;
5009 	struct page *page;
5010 	u32 ctlr;
5011 	int err;
5012 
5013 	its_base = its_map_one(res, &err);
5014 	if (!its_base)
5015 		return err;
5016 
5017 	pr_info("ITS %pR\n", res);
5018 
5019 	its = kzalloc(sizeof(*its), GFP_KERNEL);
5020 	if (!its) {
5021 		err = -ENOMEM;
5022 		goto out_unmap;
5023 	}
5024 
5025 	raw_spin_lock_init(&its->lock);
5026 	mutex_init(&its->dev_alloc_lock);
5027 	INIT_LIST_HEAD(&its->entry);
5028 	INIT_LIST_HEAD(&its->its_device_list);
5029 	typer = gic_read_typer(its_base + GITS_TYPER);
5030 	its->typer = typer;
5031 	its->base = its_base;
5032 	its->phys_base = res->start;
5033 	if (is_v4(its)) {
5034 		if (!(typer & GITS_TYPER_VMOVP)) {
5035 			err = its_compute_its_list_map(res, its_base);
5036 			if (err < 0)
5037 				goto out_free_its;
5038 
5039 			its->list_nr = err;
5040 
5041 			pr_info("ITS@%pa: Using ITS number %d\n",
5042 				&res->start, err);
5043 		} else {
5044 			pr_info("ITS@%pa: Single VMOVP capable\n", &res->start);
5045 		}
5046 
5047 		if (is_v4_1(its)) {
5048 			u32 svpet = FIELD_GET(GITS_TYPER_SVPET, typer);
5049 
5050 			its->sgir_base = ioremap(res->start + SZ_128K, SZ_64K);
5051 			if (!its->sgir_base) {
5052 				err = -ENOMEM;
5053 				goto out_free_its;
5054 			}
5055 
5056 			its->mpidr = readl_relaxed(its_base + GITS_MPIDR);
5057 
5058 			pr_info("ITS@%pa: Using GICv4.1 mode %08x %08x\n",
5059 				&res->start, its->mpidr, svpet);
5060 		}
5061 	}
5062 
5063 	its->numa_node = numa_node;
5064 
5065 	page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO,
5066 				get_order(ITS_CMD_QUEUE_SZ));
5067 	if (!page) {
5068 		err = -ENOMEM;
5069 		goto out_unmap_sgir;
5070 	}
5071 	its->cmd_base = (void *)page_address(page);
5072 	its->cmd_write = its->cmd_base;
5073 	its->fwnode_handle = handle;
5074 	its->get_msi_base = its_irq_get_msi_base;
5075 	its->msi_domain_flags = IRQ_DOMAIN_FLAG_MSI_REMAP;
5076 
5077 	its_enable_quirks(its);
5078 
5079 	err = its_alloc_tables(its);
5080 	if (err)
5081 		goto out_free_cmd;
5082 
5083 	err = its_alloc_collections(its);
5084 	if (err)
5085 		goto out_free_tables;
5086 
5087 	baser = (virt_to_phys(its->cmd_base)	|
5088 		 GITS_CBASER_RaWaWb		|
5089 		 GITS_CBASER_InnerShareable	|
5090 		 (ITS_CMD_QUEUE_SZ / SZ_4K - 1)	|
5091 		 GITS_CBASER_VALID);
5092 
5093 	gits_write_cbaser(baser, its->base + GITS_CBASER);
5094 	tmp = gits_read_cbaser(its->base + GITS_CBASER);
5095 
5096 	if ((tmp ^ baser) & GITS_CBASER_SHAREABILITY_MASK) {
5097 		if (!(tmp & GITS_CBASER_SHAREABILITY_MASK)) {
5098 			/*
5099 			 * The HW reports non-shareable, we must
5100 			 * remove the cacheability attributes as
5101 			 * well.
5102 			 */
5103 			baser &= ~(GITS_CBASER_SHAREABILITY_MASK |
5104 				   GITS_CBASER_CACHEABILITY_MASK);
5105 			baser |= GITS_CBASER_nC;
5106 			gits_write_cbaser(baser, its->base + GITS_CBASER);
5107 		}
5108 		pr_info("ITS: using cache flushing for cmd queue\n");
5109 		its->flags |= ITS_FLAGS_CMDQ_NEEDS_FLUSHING;
5110 	}
5111 
5112 	gits_write_cwriter(0, its->base + GITS_CWRITER);
5113 	ctlr = readl_relaxed(its->base + GITS_CTLR);
5114 	ctlr |= GITS_CTLR_ENABLE;
5115 	if (is_v4(its))
5116 		ctlr |= GITS_CTLR_ImDe;
5117 	writel_relaxed(ctlr, its->base + GITS_CTLR);
5118 
5119 	err = its_init_domain(handle, its);
5120 	if (err)
5121 		goto out_free_tables;
5122 
5123 	raw_spin_lock(&its_lock);
5124 	list_add(&its->entry, &its_nodes);
5125 	raw_spin_unlock(&its_lock);
5126 
5127 	return 0;
5128 
5129 out_free_tables:
5130 	its_free_tables(its);
5131 out_free_cmd:
5132 	free_pages((unsigned long)its->cmd_base, get_order(ITS_CMD_QUEUE_SZ));
5133 out_unmap_sgir:
5134 	if (its->sgir_base)
5135 		iounmap(its->sgir_base);
5136 out_free_its:
5137 	kfree(its);
5138 out_unmap:
5139 	iounmap(its_base);
5140 	pr_err("ITS@%pa: failed probing (%d)\n", &res->start, err);
5141 	return err;
5142 }
5143 
5144 static bool gic_rdists_supports_plpis(void)
5145 {
5146 	return !!(gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER) & GICR_TYPER_PLPIS);
5147 }
5148 
5149 static int redist_disable_lpis(void)
5150 {
5151 	void __iomem *rbase = gic_data_rdist_rd_base();
5152 	u64 timeout = USEC_PER_SEC;
5153 	u64 val;
5154 
5155 	if (!gic_rdists_supports_plpis()) {
5156 		pr_info("CPU%d: LPIs not supported\n", smp_processor_id());
5157 		return -ENXIO;
5158 	}
5159 
5160 	val = readl_relaxed(rbase + GICR_CTLR);
5161 	if (!(val & GICR_CTLR_ENABLE_LPIS))
5162 		return 0;
5163 
5164 	/*
5165 	 * If coming via a CPU hotplug event, we don't need to disable
5166 	 * LPIs before trying to re-enable them. They are already
5167 	 * configured and all is well in the world.
5168 	 *
5169 	 * If running with preallocated tables, there is nothing to do.
5170 	 */
5171 	if ((gic_data_rdist()->flags & RD_LOCAL_LPI_ENABLED) ||
5172 	    (gic_rdists->flags & RDIST_FLAGS_RD_TABLES_PREALLOCATED))
5173 		return 0;
5174 
5175 	/*
5176 	 * From that point on, we only try to do some damage control.
5177 	 */
5178 	pr_warn("GICv3: CPU%d: Booted with LPIs enabled, memory probably corrupted\n",
5179 		smp_processor_id());
5180 	add_taint(TAINT_CRAP, LOCKDEP_STILL_OK);
5181 
5182 	/* Disable LPIs */
5183 	val &= ~GICR_CTLR_ENABLE_LPIS;
5184 	writel_relaxed(val, rbase + GICR_CTLR);
5185 
5186 	/* Make sure any change to GICR_CTLR is observable by the GIC */
5187 	dsb(sy);
5188 
5189 	/*
5190 	 * Software must observe RWP==0 after clearing GICR_CTLR.EnableLPIs
5191 	 * from 1 to 0 before programming GICR_PEND{PROP}BASER registers.
5192 	 * Error out if we time out waiting for RWP to clear.
5193 	 */
5194 	while (readl_relaxed(rbase + GICR_CTLR) & GICR_CTLR_RWP) {
5195 		if (!timeout) {
5196 			pr_err("CPU%d: Timeout while disabling LPIs\n",
5197 			       smp_processor_id());
5198 			return -ETIMEDOUT;
5199 		}
5200 		udelay(1);
5201 		timeout--;
5202 	}
5203 
5204 	/*
5205 	 * After it has been written to 1, it is IMPLEMENTATION
5206 	 * DEFINED whether GICR_CTLR.EnableLPI becomes RES1 or can be
5207 	 * cleared to 0. Error out if clearing the bit failed.
5208 	 */
5209 	if (readl_relaxed(rbase + GICR_CTLR) & GICR_CTLR_ENABLE_LPIS) {
5210 		pr_err("CPU%d: Failed to disable LPIs\n", smp_processor_id());
5211 		return -EBUSY;
5212 	}
5213 
5214 	return 0;
5215 }
5216 
5217 int its_cpu_init(void)
5218 {
5219 	if (!list_empty(&its_nodes)) {
5220 		int ret;
5221 
5222 		ret = redist_disable_lpis();
5223 		if (ret)
5224 			return ret;
5225 
5226 		its_cpu_init_lpis();
5227 		its_cpu_init_collections();
5228 	}
5229 
5230 	return 0;
5231 }
5232 
5233 static void rdist_memreserve_cpuhp_cleanup_workfn(struct work_struct *work)
5234 {
5235 	cpuhp_remove_state_nocalls(gic_rdists->cpuhp_memreserve_state);
5236 	gic_rdists->cpuhp_memreserve_state = CPUHP_INVALID;
5237 }
5238 
5239 static DECLARE_WORK(rdist_memreserve_cpuhp_cleanup_work,
5240 		    rdist_memreserve_cpuhp_cleanup_workfn);
5241 
5242 static int its_cpu_memreserve_lpi(unsigned int cpu)
5243 {
5244 	struct page *pend_page;
5245 	int ret = 0;
5246 
5247 	/* This gets to run exactly once per CPU */
5248 	if (gic_data_rdist()->flags & RD_LOCAL_MEMRESERVE_DONE)
5249 		return 0;
5250 
5251 	pend_page = gic_data_rdist()->pend_page;
5252 	if (WARN_ON(!pend_page)) {
5253 		ret = -ENOMEM;
5254 		goto out;
5255 	}
5256 	/*
5257 	 * If the pending table was pre-programmed, free the memory we
5258 	 * preemptively allocated. Otherwise, reserve that memory for
5259 	 * later kexecs.
5260 	 */
5261 	if (gic_data_rdist()->flags & RD_LOCAL_PENDTABLE_PREALLOCATED) {
5262 		its_free_pending_table(pend_page);
5263 		gic_data_rdist()->pend_page = NULL;
5264 	} else {
5265 		phys_addr_t paddr = page_to_phys(pend_page);
5266 		WARN_ON(gic_reserve_range(paddr, LPI_PENDBASE_SZ));
5267 	}
5268 
5269 out:
5270 	/* Last CPU being brought up gets to issue the cleanup */
5271 	if (!IS_ENABLED(CONFIG_SMP) ||
5272 	    cpumask_equal(&cpus_booted_once_mask, cpu_possible_mask))
5273 		schedule_work(&rdist_memreserve_cpuhp_cleanup_work);
5274 
5275 	gic_data_rdist()->flags |= RD_LOCAL_MEMRESERVE_DONE;
5276 	return ret;
5277 }
5278 
5279 /* Mark all the BASER registers as invalid before they get reprogrammed */
5280 static int __init its_reset_one(struct resource *res)
5281 {
5282 	void __iomem *its_base;
5283 	int err, i;
5284 
5285 	its_base = its_map_one(res, &err);
5286 	if (!its_base)
5287 		return err;
5288 
5289 	for (i = 0; i < GITS_BASER_NR_REGS; i++)
5290 		gits_write_baser(0, its_base + GITS_BASER + (i << 3));
5291 
5292 	iounmap(its_base);
5293 	return 0;
5294 }
5295 
5296 static const struct of_device_id its_device_id[] = {
5297 	{	.compatible	= "arm,gic-v3-its",	},
5298 	{},
5299 };
5300 
5301 static int __init its_of_probe(struct device_node *node)
5302 {
5303 	struct device_node *np;
5304 	struct resource res;
5305 
5306 	/*
5307 	 * Make sure *all* the ITS are reset before we probe any, as
5308 	 * they may be sharing memory. If any of the ITS fails to
5309 	 * reset, don't even try to go any further, as this could
5310 	 * result in something even worse.
5311 	 */
5312 	for (np = of_find_matching_node(node, its_device_id); np;
5313 	     np = of_find_matching_node(np, its_device_id)) {
5314 		int err;
5315 
5316 		if (!of_device_is_available(np) ||
5317 		    !of_property_read_bool(np, "msi-controller") ||
5318 		    of_address_to_resource(np, 0, &res))
5319 			continue;
5320 
5321 		err = its_reset_one(&res);
5322 		if (err)
5323 			return err;
5324 	}
5325 
5326 	for (np = of_find_matching_node(node, its_device_id); np;
5327 	     np = of_find_matching_node(np, its_device_id)) {
5328 		if (!of_device_is_available(np))
5329 			continue;
5330 		if (!of_property_read_bool(np, "msi-controller")) {
5331 			pr_warn("%pOF: no msi-controller property, ITS ignored\n",
5332 				np);
5333 			continue;
5334 		}
5335 
5336 		if (of_address_to_resource(np, 0, &res)) {
5337 			pr_warn("%pOF: no regs?\n", np);
5338 			continue;
5339 		}
5340 
5341 		its_probe_one(&res, &np->fwnode, of_node_to_nid(np));
5342 	}
5343 	return 0;
5344 }
5345 
5346 #ifdef CONFIG_ACPI
5347 
5348 #define ACPI_GICV3_ITS_MEM_SIZE (SZ_128K)
5349 
5350 #ifdef CONFIG_ACPI_NUMA
5351 struct its_srat_map {
5352 	/* numa node id */
5353 	u32	numa_node;
5354 	/* GIC ITS ID */
5355 	u32	its_id;
5356 };
5357 
5358 static struct its_srat_map *its_srat_maps __initdata;
5359 static int its_in_srat __initdata;
5360 
5361 static int __init acpi_get_its_numa_node(u32 its_id)
5362 {
5363 	int i;
5364 
5365 	for (i = 0; i < its_in_srat; i++) {
5366 		if (its_id == its_srat_maps[i].its_id)
5367 			return its_srat_maps[i].numa_node;
5368 	}
5369 	return NUMA_NO_NODE;
5370 }
5371 
5372 static int __init gic_acpi_match_srat_its(union acpi_subtable_headers *header,
5373 					  const unsigned long end)
5374 {
5375 	return 0;
5376 }
5377 
5378 static int __init gic_acpi_parse_srat_its(union acpi_subtable_headers *header,
5379 			 const unsigned long end)
5380 {
5381 	int node;
5382 	struct acpi_srat_gic_its_affinity *its_affinity;
5383 
5384 	its_affinity = (struct acpi_srat_gic_its_affinity *)header;
5385 	if (!its_affinity)
5386 		return -EINVAL;
5387 
5388 	if (its_affinity->header.length < sizeof(*its_affinity)) {
5389 		pr_err("SRAT: Invalid header length %d in ITS affinity\n",
5390 			its_affinity->header.length);
5391 		return -EINVAL;
5392 	}
5393 
5394 	/*
5395 	 * Note that in theory a new proximity node could be created by this
5396 	 * entry as it is an SRAT resource allocation structure.
5397 	 * We do not currently support doing so.
5398 	 */
5399 	node = pxm_to_node(its_affinity->proximity_domain);
5400 
5401 	if (node == NUMA_NO_NODE || node >= MAX_NUMNODES) {
5402 		pr_err("SRAT: Invalid NUMA node %d in ITS affinity\n", node);
5403 		return 0;
5404 	}
5405 
5406 	its_srat_maps[its_in_srat].numa_node = node;
5407 	its_srat_maps[its_in_srat].its_id = its_affinity->its_id;
5408 	its_in_srat++;
5409 	pr_info("SRAT: PXM %d -> ITS %d -> Node %d\n",
5410 		its_affinity->proximity_domain, its_affinity->its_id, node);
5411 
5412 	return 0;
5413 }
5414 
5415 static void __init acpi_table_parse_srat_its(void)
5416 {
5417 	int count;
5418 
5419 	count = acpi_table_parse_entries(ACPI_SIG_SRAT,
5420 			sizeof(struct acpi_table_srat),
5421 			ACPI_SRAT_TYPE_GIC_ITS_AFFINITY,
5422 			gic_acpi_match_srat_its, 0);
5423 	if (count <= 0)
5424 		return;
5425 
5426 	its_srat_maps = kmalloc_array(count, sizeof(struct its_srat_map),
5427 				      GFP_KERNEL);
5428 	if (!its_srat_maps)
5429 		return;
5430 
5431 	acpi_table_parse_entries(ACPI_SIG_SRAT,
5432 			sizeof(struct acpi_table_srat),
5433 			ACPI_SRAT_TYPE_GIC_ITS_AFFINITY,
5434 			gic_acpi_parse_srat_its, 0);
5435 }
5436 
5437 /* free the its_srat_maps after ITS probing */
5438 static void __init acpi_its_srat_maps_free(void)
5439 {
5440 	kfree(its_srat_maps);
5441 }
5442 #else
5443 static void __init acpi_table_parse_srat_its(void)	{ }
5444 static int __init acpi_get_its_numa_node(u32 its_id) { return NUMA_NO_NODE; }
5445 static void __init acpi_its_srat_maps_free(void) { }
5446 #endif
5447 
5448 static int __init gic_acpi_parse_madt_its(union acpi_subtable_headers *header,
5449 					  const unsigned long end)
5450 {
5451 	struct acpi_madt_generic_translator *its_entry;
5452 	struct fwnode_handle *dom_handle;
5453 	struct resource res;
5454 	int err;
5455 
5456 	its_entry = (struct acpi_madt_generic_translator *)header;
5457 	memset(&res, 0, sizeof(res));
5458 	res.start = its_entry->base_address;
5459 	res.end = its_entry->base_address + ACPI_GICV3_ITS_MEM_SIZE - 1;
5460 	res.flags = IORESOURCE_MEM;
5461 
5462 	dom_handle = irq_domain_alloc_fwnode(&res.start);
5463 	if (!dom_handle) {
5464 		pr_err("ITS@%pa: Unable to allocate GICv3 ITS domain token\n",
5465 		       &res.start);
5466 		return -ENOMEM;
5467 	}
5468 
5469 	err = iort_register_domain_token(its_entry->translation_id, res.start,
5470 					 dom_handle);
5471 	if (err) {
5472 		pr_err("ITS@%pa: Unable to register GICv3 ITS domain token (ITS ID %d) to IORT\n",
5473 		       &res.start, its_entry->translation_id);
5474 		goto dom_err;
5475 	}
5476 
5477 	err = its_probe_one(&res, dom_handle,
5478 			acpi_get_its_numa_node(its_entry->translation_id));
5479 	if (!err)
5480 		return 0;
5481 
5482 	iort_deregister_domain_token(its_entry->translation_id);
5483 dom_err:
5484 	irq_domain_free_fwnode(dom_handle);
5485 	return err;
5486 }
5487 
5488 static int __init its_acpi_reset(union acpi_subtable_headers *header,
5489 				 const unsigned long end)
5490 {
5491 	struct acpi_madt_generic_translator *its_entry;
5492 	struct resource res;
5493 
5494 	its_entry = (struct acpi_madt_generic_translator *)header;
5495 	res = (struct resource) {
5496 		.start	= its_entry->base_address,
5497 		.end	= its_entry->base_address + ACPI_GICV3_ITS_MEM_SIZE - 1,
5498 		.flags	= IORESOURCE_MEM,
5499 	};
5500 
5501 	return its_reset_one(&res);
5502 }
5503 
5504 static void __init its_acpi_probe(void)
5505 {
5506 	acpi_table_parse_srat_its();
5507 	/*
5508 	 * Make sure *all* the ITS are reset before we probe any, as
5509 	 * they may be sharing memory. If any of the ITS fails to
5510 	 * reset, don't even try to go any further, as this could
5511 	 * result in something even worse.
5512 	 */
5513 	if (acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_TRANSLATOR,
5514 				  its_acpi_reset, 0) > 0)
5515 		acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_TRANSLATOR,
5516 				      gic_acpi_parse_madt_its, 0);
5517 	acpi_its_srat_maps_free();
5518 }
5519 #else
5520 static void __init its_acpi_probe(void) { }
5521 #endif
5522 
5523 int __init its_lpi_memreserve_init(void)
5524 {
5525 	int state;
5526 
5527 	if (!efi_enabled(EFI_CONFIG_TABLES))
5528 		return 0;
5529 
5530 	if (list_empty(&its_nodes))
5531 		return 0;
5532 
5533 	gic_rdists->cpuhp_memreserve_state = CPUHP_INVALID;
5534 	state = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN,
5535 				  "irqchip/arm/gicv3/memreserve:online",
5536 				  its_cpu_memreserve_lpi,
5537 				  NULL);
5538 	if (state < 0)
5539 		return state;
5540 
5541 	gic_rdists->cpuhp_memreserve_state = state;
5542 
5543 	return 0;
5544 }
5545 
5546 int __init its_init(struct fwnode_handle *handle, struct rdists *rdists,
5547 		    struct irq_domain *parent_domain)
5548 {
5549 	struct device_node *of_node;
5550 	struct its_node *its;
5551 	bool has_v4 = false;
5552 	bool has_v4_1 = false;
5553 	int err;
5554 
5555 	gic_rdists = rdists;
5556 
5557 	its_parent = parent_domain;
5558 	of_node = to_of_node(handle);
5559 	if (of_node)
5560 		its_of_probe(of_node);
5561 	else
5562 		its_acpi_probe();
5563 
5564 	if (list_empty(&its_nodes)) {
5565 		pr_warn("ITS: No ITS available, not enabling LPIs\n");
5566 		return -ENXIO;
5567 	}
5568 
5569 	err = allocate_lpi_tables();
5570 	if (err)
5571 		return err;
5572 
5573 	list_for_each_entry(its, &its_nodes, entry) {
5574 		has_v4 |= is_v4(its);
5575 		has_v4_1 |= is_v4_1(its);
5576 	}
5577 
5578 	/* Don't bother with inconsistent systems */
5579 	if (WARN_ON(!has_v4_1 && rdists->has_rvpeid))
5580 		rdists->has_rvpeid = false;
5581 
5582 	if (has_v4 & rdists->has_vlpis) {
5583 		const struct irq_domain_ops *sgi_ops;
5584 
5585 		if (has_v4_1)
5586 			sgi_ops = &its_sgi_domain_ops;
5587 		else
5588 			sgi_ops = NULL;
5589 
5590 		if (its_init_vpe_domain() ||
5591 		    its_init_v4(parent_domain, &its_vpe_domain_ops, sgi_ops)) {
5592 			rdists->has_vlpis = false;
5593 			pr_err("ITS: Disabling GICv4 support\n");
5594 		}
5595 	}
5596 
5597 	register_syscore_ops(&its_syscore_ops);
5598 
5599 	return 0;
5600 }
5601