1cc2d3216SMarc Zyngier /* 2cc2d3216SMarc Zyngier * Copyright (C) 2013, 2014 ARM Limited, All Rights Reserved. 3cc2d3216SMarc Zyngier * Author: Marc Zyngier <marc.zyngier@arm.com> 4cc2d3216SMarc Zyngier * 5cc2d3216SMarc Zyngier * This program is free software; you can redistribute it and/or modify 6cc2d3216SMarc Zyngier * it under the terms of the GNU General Public License version 2 as 7cc2d3216SMarc Zyngier * published by the Free Software Foundation. 8cc2d3216SMarc Zyngier * 9cc2d3216SMarc Zyngier * This program is distributed in the hope that it will be useful, 10cc2d3216SMarc Zyngier * but WITHOUT ANY WARRANTY; without even the implied warranty of 11cc2d3216SMarc Zyngier * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12cc2d3216SMarc Zyngier * GNU General Public License for more details. 13cc2d3216SMarc Zyngier * 14cc2d3216SMarc Zyngier * You should have received a copy of the GNU General Public License 15cc2d3216SMarc Zyngier * along with this program. If not, see <http://www.gnu.org/licenses/>. 16cc2d3216SMarc Zyngier */ 17cc2d3216SMarc Zyngier 183f010cf1STomasz Nowicki #include <linux/acpi.h> 19cc2d3216SMarc Zyngier #include <linux/bitmap.h> 20cc2d3216SMarc Zyngier #include <linux/cpu.h> 21cc2d3216SMarc Zyngier #include <linux/delay.h> 2244bb7e24SRobin Murphy #include <linux/dma-iommu.h> 23cc2d3216SMarc Zyngier #include <linux/interrupt.h> 243f010cf1STomasz Nowicki #include <linux/irqdomain.h> 253f010cf1STomasz Nowicki #include <linux/acpi_iort.h> 26cc2d3216SMarc Zyngier #include <linux/log2.h> 27cc2d3216SMarc Zyngier #include <linux/mm.h> 28cc2d3216SMarc Zyngier #include <linux/msi.h> 29cc2d3216SMarc Zyngier #include <linux/of.h> 30cc2d3216SMarc Zyngier #include <linux/of_address.h> 31cc2d3216SMarc Zyngier #include <linux/of_irq.h> 32cc2d3216SMarc Zyngier #include <linux/of_pci.h> 33cc2d3216SMarc Zyngier #include <linux/of_platform.h> 34cc2d3216SMarc Zyngier #include <linux/percpu.h> 35cc2d3216SMarc Zyngier #include <linux/slab.h> 36cc2d3216SMarc Zyngier 3741a83e06SJoel Porquet #include <linux/irqchip.h> 38cc2d3216SMarc Zyngier #include <linux/irqchip/arm-gic-v3.h> 39cc2d3216SMarc Zyngier 40cc2d3216SMarc Zyngier #include <asm/cacheflush.h> 41cc2d3216SMarc Zyngier #include <asm/cputype.h> 42cc2d3216SMarc Zyngier #include <asm/exception.h> 43cc2d3216SMarc Zyngier 4467510ccaSRobert Richter #include "irq-gic-common.h" 4567510ccaSRobert Richter 4694100970SRobert Richter #define ITS_FLAGS_CMDQ_NEEDS_FLUSHING (1ULL << 0) 4794100970SRobert Richter #define ITS_FLAGS_WORKAROUND_CAVIUM_22375 (1ULL << 1) 48fbf8f40eSGanapatrao Kulkarni #define ITS_FLAGS_WORKAROUND_CAVIUM_23144 (1ULL << 2) 49cc2d3216SMarc Zyngier 50c48ed51cSMarc Zyngier #define RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING (1 << 0) 51c48ed51cSMarc Zyngier 52cc2d3216SMarc Zyngier /* 53cc2d3216SMarc Zyngier * Collection structure - just an ID, and a redistributor address to 54cc2d3216SMarc Zyngier * ping. We use one per CPU as a bag of interrupts assigned to this 55cc2d3216SMarc Zyngier * CPU. 56cc2d3216SMarc Zyngier */ 57cc2d3216SMarc Zyngier struct its_collection { 58cc2d3216SMarc Zyngier u64 target_address; 59cc2d3216SMarc Zyngier u16 col_id; 60cc2d3216SMarc Zyngier }; 61cc2d3216SMarc Zyngier 62cc2d3216SMarc Zyngier /* 639347359aSShanker Donthineni * The ITS_BASER structure - contains memory information, cached 649347359aSShanker Donthineni * value of BASER register configuration and ITS page size. 65466b7d16SShanker Donthineni */ 66466b7d16SShanker Donthineni struct its_baser { 67466b7d16SShanker Donthineni void *base; 68466b7d16SShanker Donthineni u64 val; 69466b7d16SShanker Donthineni u32 order; 709347359aSShanker Donthineni u32 psz; 71466b7d16SShanker Donthineni }; 72466b7d16SShanker Donthineni 73466b7d16SShanker Donthineni /* 74cc2d3216SMarc Zyngier * The ITS structure - contains most of the infrastructure, with the 75841514abSMarc Zyngier * top-level MSI domain, the command queue, the collections, and the 76841514abSMarc Zyngier * list of devices writing to it. 77cc2d3216SMarc Zyngier */ 78cc2d3216SMarc Zyngier struct its_node { 79cc2d3216SMarc Zyngier raw_spinlock_t lock; 80cc2d3216SMarc Zyngier struct list_head entry; 81cc2d3216SMarc Zyngier void __iomem *base; 82db40f0a7STomasz Nowicki phys_addr_t phys_base; 83cc2d3216SMarc Zyngier struct its_cmd_block *cmd_base; 84cc2d3216SMarc Zyngier struct its_cmd_block *cmd_write; 85466b7d16SShanker Donthineni struct its_baser tables[GITS_BASER_NR_REGS]; 86cc2d3216SMarc Zyngier struct its_collection *collections; 87cc2d3216SMarc Zyngier struct list_head its_device_list; 88cc2d3216SMarc Zyngier u64 flags; 89cc2d3216SMarc Zyngier u32 ite_size; 90466b7d16SShanker Donthineni u32 device_ids; 91fbf8f40eSGanapatrao Kulkarni int numa_node; 92cc2d3216SMarc Zyngier }; 93cc2d3216SMarc Zyngier 94cc2d3216SMarc Zyngier #define ITS_ITT_ALIGN SZ_256 95cc2d3216SMarc Zyngier 962eca0d6cSShanker Donthineni /* Convert page order to size in bytes */ 972eca0d6cSShanker Donthineni #define PAGE_ORDER_TO_SIZE(o) (PAGE_SIZE << (o)) 982eca0d6cSShanker Donthineni 99591e5becSMarc Zyngier struct event_lpi_map { 100591e5becSMarc Zyngier unsigned long *lpi_map; 101591e5becSMarc Zyngier u16 *col_map; 102591e5becSMarc Zyngier irq_hw_number_t lpi_base; 103591e5becSMarc Zyngier int nr_lpis; 104591e5becSMarc Zyngier }; 105591e5becSMarc Zyngier 106cc2d3216SMarc Zyngier /* 107cc2d3216SMarc Zyngier * The ITS view of a device - belongs to an ITS, a collection, owns an 108cc2d3216SMarc Zyngier * interrupt translation table, and a list of interrupts. 109cc2d3216SMarc Zyngier */ 110cc2d3216SMarc Zyngier struct its_device { 111cc2d3216SMarc Zyngier struct list_head entry; 112cc2d3216SMarc Zyngier struct its_node *its; 113591e5becSMarc Zyngier struct event_lpi_map event_map; 114cc2d3216SMarc Zyngier void *itt; 115cc2d3216SMarc Zyngier u32 nr_ites; 116cc2d3216SMarc Zyngier u32 device_id; 117cc2d3216SMarc Zyngier }; 118cc2d3216SMarc Zyngier 1191ac19ca6SMarc Zyngier static LIST_HEAD(its_nodes); 1201ac19ca6SMarc Zyngier static DEFINE_SPINLOCK(its_lock); 1211ac19ca6SMarc Zyngier static struct rdists *gic_rdists; 122db40f0a7STomasz Nowicki static struct irq_domain *its_parent; 1231ac19ca6SMarc Zyngier 1241ac19ca6SMarc Zyngier #define gic_data_rdist() (raw_cpu_ptr(gic_rdists->rdist)) 1251ac19ca6SMarc Zyngier #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base) 1261ac19ca6SMarc Zyngier 127591e5becSMarc Zyngier static struct its_collection *dev_event_to_col(struct its_device *its_dev, 128591e5becSMarc Zyngier u32 event) 129591e5becSMarc Zyngier { 130591e5becSMarc Zyngier struct its_node *its = its_dev->its; 131591e5becSMarc Zyngier 132591e5becSMarc Zyngier return its->collections + its_dev->event_map.col_map[event]; 133591e5becSMarc Zyngier } 134591e5becSMarc Zyngier 135cc2d3216SMarc Zyngier /* 136cc2d3216SMarc Zyngier * ITS command descriptors - parameters to be encoded in a command 137cc2d3216SMarc Zyngier * block. 138cc2d3216SMarc Zyngier */ 139cc2d3216SMarc Zyngier struct its_cmd_desc { 140cc2d3216SMarc Zyngier union { 141cc2d3216SMarc Zyngier struct { 142cc2d3216SMarc Zyngier struct its_device *dev; 143cc2d3216SMarc Zyngier u32 event_id; 144cc2d3216SMarc Zyngier } its_inv_cmd; 145cc2d3216SMarc Zyngier 146cc2d3216SMarc Zyngier struct { 147cc2d3216SMarc Zyngier struct its_device *dev; 148cc2d3216SMarc Zyngier u32 event_id; 149cc2d3216SMarc Zyngier } its_int_cmd; 150cc2d3216SMarc Zyngier 151cc2d3216SMarc Zyngier struct { 152cc2d3216SMarc Zyngier struct its_device *dev; 153cc2d3216SMarc Zyngier int valid; 154cc2d3216SMarc Zyngier } its_mapd_cmd; 155cc2d3216SMarc Zyngier 156cc2d3216SMarc Zyngier struct { 157cc2d3216SMarc Zyngier struct its_collection *col; 158cc2d3216SMarc Zyngier int valid; 159cc2d3216SMarc Zyngier } its_mapc_cmd; 160cc2d3216SMarc Zyngier 161cc2d3216SMarc Zyngier struct { 162cc2d3216SMarc Zyngier struct its_device *dev; 163cc2d3216SMarc Zyngier u32 phys_id; 164cc2d3216SMarc Zyngier u32 event_id; 165cc2d3216SMarc Zyngier } its_mapvi_cmd; 166cc2d3216SMarc Zyngier 167cc2d3216SMarc Zyngier struct { 168cc2d3216SMarc Zyngier struct its_device *dev; 169cc2d3216SMarc Zyngier struct its_collection *col; 170591e5becSMarc Zyngier u32 event_id; 171cc2d3216SMarc Zyngier } its_movi_cmd; 172cc2d3216SMarc Zyngier 173cc2d3216SMarc Zyngier struct { 174cc2d3216SMarc Zyngier struct its_device *dev; 175cc2d3216SMarc Zyngier u32 event_id; 176cc2d3216SMarc Zyngier } its_discard_cmd; 177cc2d3216SMarc Zyngier 178cc2d3216SMarc Zyngier struct { 179cc2d3216SMarc Zyngier struct its_collection *col; 180cc2d3216SMarc Zyngier } its_invall_cmd; 181cc2d3216SMarc Zyngier }; 182cc2d3216SMarc Zyngier }; 183cc2d3216SMarc Zyngier 184cc2d3216SMarc Zyngier /* 185cc2d3216SMarc Zyngier * The ITS command block, which is what the ITS actually parses. 186cc2d3216SMarc Zyngier */ 187cc2d3216SMarc Zyngier struct its_cmd_block { 188cc2d3216SMarc Zyngier u64 raw_cmd[4]; 189cc2d3216SMarc Zyngier }; 190cc2d3216SMarc Zyngier 191cc2d3216SMarc Zyngier #define ITS_CMD_QUEUE_SZ SZ_64K 192cc2d3216SMarc Zyngier #define ITS_CMD_QUEUE_NR_ENTRIES (ITS_CMD_QUEUE_SZ / sizeof(struct its_cmd_block)) 193cc2d3216SMarc Zyngier 194cc2d3216SMarc Zyngier typedef struct its_collection *(*its_cmd_builder_t)(struct its_cmd_block *, 195cc2d3216SMarc Zyngier struct its_cmd_desc *); 196cc2d3216SMarc Zyngier 197cc2d3216SMarc Zyngier static void its_encode_cmd(struct its_cmd_block *cmd, u8 cmd_nr) 198cc2d3216SMarc Zyngier { 199*b11283ebSVladimir Murzin cmd->raw_cmd[0] &= ~0xffULL; 200cc2d3216SMarc Zyngier cmd->raw_cmd[0] |= cmd_nr; 201cc2d3216SMarc Zyngier } 202cc2d3216SMarc Zyngier 203cc2d3216SMarc Zyngier static void its_encode_devid(struct its_cmd_block *cmd, u32 devid) 204cc2d3216SMarc Zyngier { 2057e195ba0SAndre Przywara cmd->raw_cmd[0] &= BIT_ULL(32) - 1; 206cc2d3216SMarc Zyngier cmd->raw_cmd[0] |= ((u64)devid) << 32; 207cc2d3216SMarc Zyngier } 208cc2d3216SMarc Zyngier 209cc2d3216SMarc Zyngier static void its_encode_event_id(struct its_cmd_block *cmd, u32 id) 210cc2d3216SMarc Zyngier { 211*b11283ebSVladimir Murzin cmd->raw_cmd[1] &= ~0xffffffffULL; 212cc2d3216SMarc Zyngier cmd->raw_cmd[1] |= id; 213cc2d3216SMarc Zyngier } 214cc2d3216SMarc Zyngier 215cc2d3216SMarc Zyngier static void its_encode_phys_id(struct its_cmd_block *cmd, u32 phys_id) 216cc2d3216SMarc Zyngier { 217*b11283ebSVladimir Murzin cmd->raw_cmd[1] &= 0xffffffffULL; 218cc2d3216SMarc Zyngier cmd->raw_cmd[1] |= ((u64)phys_id) << 32; 219cc2d3216SMarc Zyngier } 220cc2d3216SMarc Zyngier 221cc2d3216SMarc Zyngier static void its_encode_size(struct its_cmd_block *cmd, u8 size) 222cc2d3216SMarc Zyngier { 223*b11283ebSVladimir Murzin cmd->raw_cmd[1] &= ~0x1fULL; 224cc2d3216SMarc Zyngier cmd->raw_cmd[1] |= size & 0x1f; 225cc2d3216SMarc Zyngier } 226cc2d3216SMarc Zyngier 227cc2d3216SMarc Zyngier static void its_encode_itt(struct its_cmd_block *cmd, u64 itt_addr) 228cc2d3216SMarc Zyngier { 229*b11283ebSVladimir Murzin cmd->raw_cmd[2] &= ~0xffffffffffffULL; 230*b11283ebSVladimir Murzin cmd->raw_cmd[2] |= itt_addr & 0xffffffffff00ULL; 231cc2d3216SMarc Zyngier } 232cc2d3216SMarc Zyngier 233cc2d3216SMarc Zyngier static void its_encode_valid(struct its_cmd_block *cmd, int valid) 234cc2d3216SMarc Zyngier { 235*b11283ebSVladimir Murzin cmd->raw_cmd[2] &= ~(1ULL << 63); 236cc2d3216SMarc Zyngier cmd->raw_cmd[2] |= ((u64)!!valid) << 63; 237cc2d3216SMarc Zyngier } 238cc2d3216SMarc Zyngier 239cc2d3216SMarc Zyngier static void its_encode_target(struct its_cmd_block *cmd, u64 target_addr) 240cc2d3216SMarc Zyngier { 241*b11283ebSVladimir Murzin cmd->raw_cmd[2] &= ~(0xffffffffULL << 16); 242*b11283ebSVladimir Murzin cmd->raw_cmd[2] |= (target_addr & (0xffffffffULL << 16)); 243cc2d3216SMarc Zyngier } 244cc2d3216SMarc Zyngier 245cc2d3216SMarc Zyngier static void its_encode_collection(struct its_cmd_block *cmd, u16 col) 246cc2d3216SMarc Zyngier { 247*b11283ebSVladimir Murzin cmd->raw_cmd[2] &= ~0xffffULL; 248cc2d3216SMarc Zyngier cmd->raw_cmd[2] |= col; 249cc2d3216SMarc Zyngier } 250cc2d3216SMarc Zyngier 251cc2d3216SMarc Zyngier static inline void its_fixup_cmd(struct its_cmd_block *cmd) 252cc2d3216SMarc Zyngier { 253cc2d3216SMarc Zyngier /* Let's fixup BE commands */ 254cc2d3216SMarc Zyngier cmd->raw_cmd[0] = cpu_to_le64(cmd->raw_cmd[0]); 255cc2d3216SMarc Zyngier cmd->raw_cmd[1] = cpu_to_le64(cmd->raw_cmd[1]); 256cc2d3216SMarc Zyngier cmd->raw_cmd[2] = cpu_to_le64(cmd->raw_cmd[2]); 257cc2d3216SMarc Zyngier cmd->raw_cmd[3] = cpu_to_le64(cmd->raw_cmd[3]); 258cc2d3216SMarc Zyngier } 259cc2d3216SMarc Zyngier 260cc2d3216SMarc Zyngier static struct its_collection *its_build_mapd_cmd(struct its_cmd_block *cmd, 261cc2d3216SMarc Zyngier struct its_cmd_desc *desc) 262cc2d3216SMarc Zyngier { 263cc2d3216SMarc Zyngier unsigned long itt_addr; 264c8481267SMarc Zyngier u8 size = ilog2(desc->its_mapd_cmd.dev->nr_ites); 265cc2d3216SMarc Zyngier 266cc2d3216SMarc Zyngier itt_addr = virt_to_phys(desc->its_mapd_cmd.dev->itt); 267cc2d3216SMarc Zyngier itt_addr = ALIGN(itt_addr, ITS_ITT_ALIGN); 268cc2d3216SMarc Zyngier 269cc2d3216SMarc Zyngier its_encode_cmd(cmd, GITS_CMD_MAPD); 270cc2d3216SMarc Zyngier its_encode_devid(cmd, desc->its_mapd_cmd.dev->device_id); 271cc2d3216SMarc Zyngier its_encode_size(cmd, size - 1); 272cc2d3216SMarc Zyngier its_encode_itt(cmd, itt_addr); 273cc2d3216SMarc Zyngier its_encode_valid(cmd, desc->its_mapd_cmd.valid); 274cc2d3216SMarc Zyngier 275cc2d3216SMarc Zyngier its_fixup_cmd(cmd); 276cc2d3216SMarc Zyngier 277591e5becSMarc Zyngier return NULL; 278cc2d3216SMarc Zyngier } 279cc2d3216SMarc Zyngier 280cc2d3216SMarc Zyngier static struct its_collection *its_build_mapc_cmd(struct its_cmd_block *cmd, 281cc2d3216SMarc Zyngier struct its_cmd_desc *desc) 282cc2d3216SMarc Zyngier { 283cc2d3216SMarc Zyngier its_encode_cmd(cmd, GITS_CMD_MAPC); 284cc2d3216SMarc Zyngier its_encode_collection(cmd, desc->its_mapc_cmd.col->col_id); 285cc2d3216SMarc Zyngier its_encode_target(cmd, desc->its_mapc_cmd.col->target_address); 286cc2d3216SMarc Zyngier its_encode_valid(cmd, desc->its_mapc_cmd.valid); 287cc2d3216SMarc Zyngier 288cc2d3216SMarc Zyngier its_fixup_cmd(cmd); 289cc2d3216SMarc Zyngier 290cc2d3216SMarc Zyngier return desc->its_mapc_cmd.col; 291cc2d3216SMarc Zyngier } 292cc2d3216SMarc Zyngier 293cc2d3216SMarc Zyngier static struct its_collection *its_build_mapvi_cmd(struct its_cmd_block *cmd, 294cc2d3216SMarc Zyngier struct its_cmd_desc *desc) 295cc2d3216SMarc Zyngier { 296591e5becSMarc Zyngier struct its_collection *col; 297591e5becSMarc Zyngier 298591e5becSMarc Zyngier col = dev_event_to_col(desc->its_mapvi_cmd.dev, 299591e5becSMarc Zyngier desc->its_mapvi_cmd.event_id); 300591e5becSMarc Zyngier 301cc2d3216SMarc Zyngier its_encode_cmd(cmd, GITS_CMD_MAPVI); 302cc2d3216SMarc Zyngier its_encode_devid(cmd, desc->its_mapvi_cmd.dev->device_id); 303cc2d3216SMarc Zyngier its_encode_event_id(cmd, desc->its_mapvi_cmd.event_id); 304cc2d3216SMarc Zyngier its_encode_phys_id(cmd, desc->its_mapvi_cmd.phys_id); 305591e5becSMarc Zyngier its_encode_collection(cmd, col->col_id); 306cc2d3216SMarc Zyngier 307cc2d3216SMarc Zyngier its_fixup_cmd(cmd); 308cc2d3216SMarc Zyngier 309591e5becSMarc Zyngier return col; 310cc2d3216SMarc Zyngier } 311cc2d3216SMarc Zyngier 312cc2d3216SMarc Zyngier static struct its_collection *its_build_movi_cmd(struct its_cmd_block *cmd, 313cc2d3216SMarc Zyngier struct its_cmd_desc *desc) 314cc2d3216SMarc Zyngier { 315591e5becSMarc Zyngier struct its_collection *col; 316591e5becSMarc Zyngier 317591e5becSMarc Zyngier col = dev_event_to_col(desc->its_movi_cmd.dev, 318591e5becSMarc Zyngier desc->its_movi_cmd.event_id); 319591e5becSMarc Zyngier 320cc2d3216SMarc Zyngier its_encode_cmd(cmd, GITS_CMD_MOVI); 321cc2d3216SMarc Zyngier its_encode_devid(cmd, desc->its_movi_cmd.dev->device_id); 322591e5becSMarc Zyngier its_encode_event_id(cmd, desc->its_movi_cmd.event_id); 323cc2d3216SMarc Zyngier its_encode_collection(cmd, desc->its_movi_cmd.col->col_id); 324cc2d3216SMarc Zyngier 325cc2d3216SMarc Zyngier its_fixup_cmd(cmd); 326cc2d3216SMarc Zyngier 327591e5becSMarc Zyngier return col; 328cc2d3216SMarc Zyngier } 329cc2d3216SMarc Zyngier 330cc2d3216SMarc Zyngier static struct its_collection *its_build_discard_cmd(struct its_cmd_block *cmd, 331cc2d3216SMarc Zyngier struct its_cmd_desc *desc) 332cc2d3216SMarc Zyngier { 333591e5becSMarc Zyngier struct its_collection *col; 334591e5becSMarc Zyngier 335591e5becSMarc Zyngier col = dev_event_to_col(desc->its_discard_cmd.dev, 336591e5becSMarc Zyngier desc->its_discard_cmd.event_id); 337591e5becSMarc Zyngier 338cc2d3216SMarc Zyngier its_encode_cmd(cmd, GITS_CMD_DISCARD); 339cc2d3216SMarc Zyngier its_encode_devid(cmd, desc->its_discard_cmd.dev->device_id); 340cc2d3216SMarc Zyngier its_encode_event_id(cmd, desc->its_discard_cmd.event_id); 341cc2d3216SMarc Zyngier 342cc2d3216SMarc Zyngier its_fixup_cmd(cmd); 343cc2d3216SMarc Zyngier 344591e5becSMarc Zyngier return col; 345cc2d3216SMarc Zyngier } 346cc2d3216SMarc Zyngier 347cc2d3216SMarc Zyngier static struct its_collection *its_build_inv_cmd(struct its_cmd_block *cmd, 348cc2d3216SMarc Zyngier struct its_cmd_desc *desc) 349cc2d3216SMarc Zyngier { 350591e5becSMarc Zyngier struct its_collection *col; 351591e5becSMarc Zyngier 352591e5becSMarc Zyngier col = dev_event_to_col(desc->its_inv_cmd.dev, 353591e5becSMarc Zyngier desc->its_inv_cmd.event_id); 354591e5becSMarc Zyngier 355cc2d3216SMarc Zyngier its_encode_cmd(cmd, GITS_CMD_INV); 356cc2d3216SMarc Zyngier its_encode_devid(cmd, desc->its_inv_cmd.dev->device_id); 357cc2d3216SMarc Zyngier its_encode_event_id(cmd, desc->its_inv_cmd.event_id); 358cc2d3216SMarc Zyngier 359cc2d3216SMarc Zyngier its_fixup_cmd(cmd); 360cc2d3216SMarc Zyngier 361591e5becSMarc Zyngier return col; 362cc2d3216SMarc Zyngier } 363cc2d3216SMarc Zyngier 364cc2d3216SMarc Zyngier static struct its_collection *its_build_invall_cmd(struct its_cmd_block *cmd, 365cc2d3216SMarc Zyngier struct its_cmd_desc *desc) 366cc2d3216SMarc Zyngier { 367cc2d3216SMarc Zyngier its_encode_cmd(cmd, GITS_CMD_INVALL); 368cc2d3216SMarc Zyngier its_encode_collection(cmd, desc->its_mapc_cmd.col->col_id); 369cc2d3216SMarc Zyngier 370cc2d3216SMarc Zyngier its_fixup_cmd(cmd); 371cc2d3216SMarc Zyngier 372cc2d3216SMarc Zyngier return NULL; 373cc2d3216SMarc Zyngier } 374cc2d3216SMarc Zyngier 375cc2d3216SMarc Zyngier static u64 its_cmd_ptr_to_offset(struct its_node *its, 376cc2d3216SMarc Zyngier struct its_cmd_block *ptr) 377cc2d3216SMarc Zyngier { 378cc2d3216SMarc Zyngier return (ptr - its->cmd_base) * sizeof(*ptr); 379cc2d3216SMarc Zyngier } 380cc2d3216SMarc Zyngier 381cc2d3216SMarc Zyngier static int its_queue_full(struct its_node *its) 382cc2d3216SMarc Zyngier { 383cc2d3216SMarc Zyngier int widx; 384cc2d3216SMarc Zyngier int ridx; 385cc2d3216SMarc Zyngier 386cc2d3216SMarc Zyngier widx = its->cmd_write - its->cmd_base; 387cc2d3216SMarc Zyngier ridx = readl_relaxed(its->base + GITS_CREADR) / sizeof(struct its_cmd_block); 388cc2d3216SMarc Zyngier 389cc2d3216SMarc Zyngier /* This is incredibly unlikely to happen, unless the ITS locks up. */ 390cc2d3216SMarc Zyngier if (((widx + 1) % ITS_CMD_QUEUE_NR_ENTRIES) == ridx) 391cc2d3216SMarc Zyngier return 1; 392cc2d3216SMarc Zyngier 393cc2d3216SMarc Zyngier return 0; 394cc2d3216SMarc Zyngier } 395cc2d3216SMarc Zyngier 396cc2d3216SMarc Zyngier static struct its_cmd_block *its_allocate_entry(struct its_node *its) 397cc2d3216SMarc Zyngier { 398cc2d3216SMarc Zyngier struct its_cmd_block *cmd; 399cc2d3216SMarc Zyngier u32 count = 1000000; /* 1s! */ 400cc2d3216SMarc Zyngier 401cc2d3216SMarc Zyngier while (its_queue_full(its)) { 402cc2d3216SMarc Zyngier count--; 403cc2d3216SMarc Zyngier if (!count) { 404cc2d3216SMarc Zyngier pr_err_ratelimited("ITS queue not draining\n"); 405cc2d3216SMarc Zyngier return NULL; 406cc2d3216SMarc Zyngier } 407cc2d3216SMarc Zyngier cpu_relax(); 408cc2d3216SMarc Zyngier udelay(1); 409cc2d3216SMarc Zyngier } 410cc2d3216SMarc Zyngier 411cc2d3216SMarc Zyngier cmd = its->cmd_write++; 412cc2d3216SMarc Zyngier 413cc2d3216SMarc Zyngier /* Handle queue wrapping */ 414cc2d3216SMarc Zyngier if (its->cmd_write == (its->cmd_base + ITS_CMD_QUEUE_NR_ENTRIES)) 415cc2d3216SMarc Zyngier its->cmd_write = its->cmd_base; 416cc2d3216SMarc Zyngier 417cc2d3216SMarc Zyngier return cmd; 418cc2d3216SMarc Zyngier } 419cc2d3216SMarc Zyngier 420cc2d3216SMarc Zyngier static struct its_cmd_block *its_post_commands(struct its_node *its) 421cc2d3216SMarc Zyngier { 422cc2d3216SMarc Zyngier u64 wr = its_cmd_ptr_to_offset(its, its->cmd_write); 423cc2d3216SMarc Zyngier 424cc2d3216SMarc Zyngier writel_relaxed(wr, its->base + GITS_CWRITER); 425cc2d3216SMarc Zyngier 426cc2d3216SMarc Zyngier return its->cmd_write; 427cc2d3216SMarc Zyngier } 428cc2d3216SMarc Zyngier 429cc2d3216SMarc Zyngier static void its_flush_cmd(struct its_node *its, struct its_cmd_block *cmd) 430cc2d3216SMarc Zyngier { 431cc2d3216SMarc Zyngier /* 432cc2d3216SMarc Zyngier * Make sure the commands written to memory are observable by 433cc2d3216SMarc Zyngier * the ITS. 434cc2d3216SMarc Zyngier */ 435cc2d3216SMarc Zyngier if (its->flags & ITS_FLAGS_CMDQ_NEEDS_FLUSHING) 436cc2d3216SMarc Zyngier __flush_dcache_area(cmd, sizeof(*cmd)); 437cc2d3216SMarc Zyngier else 438cc2d3216SMarc Zyngier dsb(ishst); 439cc2d3216SMarc Zyngier } 440cc2d3216SMarc Zyngier 441cc2d3216SMarc Zyngier static void its_wait_for_range_completion(struct its_node *its, 442cc2d3216SMarc Zyngier struct its_cmd_block *from, 443cc2d3216SMarc Zyngier struct its_cmd_block *to) 444cc2d3216SMarc Zyngier { 445cc2d3216SMarc Zyngier u64 rd_idx, from_idx, to_idx; 446cc2d3216SMarc Zyngier u32 count = 1000000; /* 1s! */ 447cc2d3216SMarc Zyngier 448cc2d3216SMarc Zyngier from_idx = its_cmd_ptr_to_offset(its, from); 449cc2d3216SMarc Zyngier to_idx = its_cmd_ptr_to_offset(its, to); 450cc2d3216SMarc Zyngier 451cc2d3216SMarc Zyngier while (1) { 452cc2d3216SMarc Zyngier rd_idx = readl_relaxed(its->base + GITS_CREADR); 453cc2d3216SMarc Zyngier if (rd_idx >= to_idx || rd_idx < from_idx) 454cc2d3216SMarc Zyngier break; 455cc2d3216SMarc Zyngier 456cc2d3216SMarc Zyngier count--; 457cc2d3216SMarc Zyngier if (!count) { 458cc2d3216SMarc Zyngier pr_err_ratelimited("ITS queue timeout\n"); 459cc2d3216SMarc Zyngier return; 460cc2d3216SMarc Zyngier } 461cc2d3216SMarc Zyngier cpu_relax(); 462cc2d3216SMarc Zyngier udelay(1); 463cc2d3216SMarc Zyngier } 464cc2d3216SMarc Zyngier } 465cc2d3216SMarc Zyngier 466cc2d3216SMarc Zyngier static void its_send_single_command(struct its_node *its, 467cc2d3216SMarc Zyngier its_cmd_builder_t builder, 468cc2d3216SMarc Zyngier struct its_cmd_desc *desc) 469cc2d3216SMarc Zyngier { 470cc2d3216SMarc Zyngier struct its_cmd_block *cmd, *sync_cmd, *next_cmd; 471cc2d3216SMarc Zyngier struct its_collection *sync_col; 4723e39e8f5SMarc Zyngier unsigned long flags; 473cc2d3216SMarc Zyngier 4743e39e8f5SMarc Zyngier raw_spin_lock_irqsave(&its->lock, flags); 475cc2d3216SMarc Zyngier 476cc2d3216SMarc Zyngier cmd = its_allocate_entry(its); 477cc2d3216SMarc Zyngier if (!cmd) { /* We're soooooo screewed... */ 478cc2d3216SMarc Zyngier pr_err_ratelimited("ITS can't allocate, dropping command\n"); 4793e39e8f5SMarc Zyngier raw_spin_unlock_irqrestore(&its->lock, flags); 480cc2d3216SMarc Zyngier return; 481cc2d3216SMarc Zyngier } 482cc2d3216SMarc Zyngier sync_col = builder(cmd, desc); 483cc2d3216SMarc Zyngier its_flush_cmd(its, cmd); 484cc2d3216SMarc Zyngier 485cc2d3216SMarc Zyngier if (sync_col) { 486cc2d3216SMarc Zyngier sync_cmd = its_allocate_entry(its); 487cc2d3216SMarc Zyngier if (!sync_cmd) { 488cc2d3216SMarc Zyngier pr_err_ratelimited("ITS can't SYNC, skipping\n"); 489cc2d3216SMarc Zyngier goto post; 490cc2d3216SMarc Zyngier } 491cc2d3216SMarc Zyngier its_encode_cmd(sync_cmd, GITS_CMD_SYNC); 492cc2d3216SMarc Zyngier its_encode_target(sync_cmd, sync_col->target_address); 493cc2d3216SMarc Zyngier its_fixup_cmd(sync_cmd); 494cc2d3216SMarc Zyngier its_flush_cmd(its, sync_cmd); 495cc2d3216SMarc Zyngier } 496cc2d3216SMarc Zyngier 497cc2d3216SMarc Zyngier post: 498cc2d3216SMarc Zyngier next_cmd = its_post_commands(its); 4993e39e8f5SMarc Zyngier raw_spin_unlock_irqrestore(&its->lock, flags); 500cc2d3216SMarc Zyngier 501cc2d3216SMarc Zyngier its_wait_for_range_completion(its, cmd, next_cmd); 502cc2d3216SMarc Zyngier } 503cc2d3216SMarc Zyngier 504cc2d3216SMarc Zyngier static void its_send_inv(struct its_device *dev, u32 event_id) 505cc2d3216SMarc Zyngier { 506cc2d3216SMarc Zyngier struct its_cmd_desc desc; 507cc2d3216SMarc Zyngier 508cc2d3216SMarc Zyngier desc.its_inv_cmd.dev = dev; 509cc2d3216SMarc Zyngier desc.its_inv_cmd.event_id = event_id; 510cc2d3216SMarc Zyngier 511cc2d3216SMarc Zyngier its_send_single_command(dev->its, its_build_inv_cmd, &desc); 512cc2d3216SMarc Zyngier } 513cc2d3216SMarc Zyngier 514cc2d3216SMarc Zyngier static void its_send_mapd(struct its_device *dev, int valid) 515cc2d3216SMarc Zyngier { 516cc2d3216SMarc Zyngier struct its_cmd_desc desc; 517cc2d3216SMarc Zyngier 518cc2d3216SMarc Zyngier desc.its_mapd_cmd.dev = dev; 519cc2d3216SMarc Zyngier desc.its_mapd_cmd.valid = !!valid; 520cc2d3216SMarc Zyngier 521cc2d3216SMarc Zyngier its_send_single_command(dev->its, its_build_mapd_cmd, &desc); 522cc2d3216SMarc Zyngier } 523cc2d3216SMarc Zyngier 524cc2d3216SMarc Zyngier static void its_send_mapc(struct its_node *its, struct its_collection *col, 525cc2d3216SMarc Zyngier int valid) 526cc2d3216SMarc Zyngier { 527cc2d3216SMarc Zyngier struct its_cmd_desc desc; 528cc2d3216SMarc Zyngier 529cc2d3216SMarc Zyngier desc.its_mapc_cmd.col = col; 530cc2d3216SMarc Zyngier desc.its_mapc_cmd.valid = !!valid; 531cc2d3216SMarc Zyngier 532cc2d3216SMarc Zyngier its_send_single_command(its, its_build_mapc_cmd, &desc); 533cc2d3216SMarc Zyngier } 534cc2d3216SMarc Zyngier 535cc2d3216SMarc Zyngier static void its_send_mapvi(struct its_device *dev, u32 irq_id, u32 id) 536cc2d3216SMarc Zyngier { 537cc2d3216SMarc Zyngier struct its_cmd_desc desc; 538cc2d3216SMarc Zyngier 539cc2d3216SMarc Zyngier desc.its_mapvi_cmd.dev = dev; 540cc2d3216SMarc Zyngier desc.its_mapvi_cmd.phys_id = irq_id; 541cc2d3216SMarc Zyngier desc.its_mapvi_cmd.event_id = id; 542cc2d3216SMarc Zyngier 543cc2d3216SMarc Zyngier its_send_single_command(dev->its, its_build_mapvi_cmd, &desc); 544cc2d3216SMarc Zyngier } 545cc2d3216SMarc Zyngier 546cc2d3216SMarc Zyngier static void its_send_movi(struct its_device *dev, 547cc2d3216SMarc Zyngier struct its_collection *col, u32 id) 548cc2d3216SMarc Zyngier { 549cc2d3216SMarc Zyngier struct its_cmd_desc desc; 550cc2d3216SMarc Zyngier 551cc2d3216SMarc Zyngier desc.its_movi_cmd.dev = dev; 552cc2d3216SMarc Zyngier desc.its_movi_cmd.col = col; 553591e5becSMarc Zyngier desc.its_movi_cmd.event_id = id; 554cc2d3216SMarc Zyngier 555cc2d3216SMarc Zyngier its_send_single_command(dev->its, its_build_movi_cmd, &desc); 556cc2d3216SMarc Zyngier } 557cc2d3216SMarc Zyngier 558cc2d3216SMarc Zyngier static void its_send_discard(struct its_device *dev, u32 id) 559cc2d3216SMarc Zyngier { 560cc2d3216SMarc Zyngier struct its_cmd_desc desc; 561cc2d3216SMarc Zyngier 562cc2d3216SMarc Zyngier desc.its_discard_cmd.dev = dev; 563cc2d3216SMarc Zyngier desc.its_discard_cmd.event_id = id; 564cc2d3216SMarc Zyngier 565cc2d3216SMarc Zyngier its_send_single_command(dev->its, its_build_discard_cmd, &desc); 566cc2d3216SMarc Zyngier } 567cc2d3216SMarc Zyngier 568cc2d3216SMarc Zyngier static void its_send_invall(struct its_node *its, struct its_collection *col) 569cc2d3216SMarc Zyngier { 570cc2d3216SMarc Zyngier struct its_cmd_desc desc; 571cc2d3216SMarc Zyngier 572cc2d3216SMarc Zyngier desc.its_invall_cmd.col = col; 573cc2d3216SMarc Zyngier 574cc2d3216SMarc Zyngier its_send_single_command(its, its_build_invall_cmd, &desc); 575cc2d3216SMarc Zyngier } 576c48ed51cSMarc Zyngier 577c48ed51cSMarc Zyngier /* 578c48ed51cSMarc Zyngier * irqchip functions - assumes MSI, mostly. 579c48ed51cSMarc Zyngier */ 580c48ed51cSMarc Zyngier 581c48ed51cSMarc Zyngier static inline u32 its_get_event_id(struct irq_data *d) 582c48ed51cSMarc Zyngier { 583c48ed51cSMarc Zyngier struct its_device *its_dev = irq_data_get_irq_chip_data(d); 584591e5becSMarc Zyngier return d->hwirq - its_dev->event_map.lpi_base; 585c48ed51cSMarc Zyngier } 586c48ed51cSMarc Zyngier 587c48ed51cSMarc Zyngier static void lpi_set_config(struct irq_data *d, bool enable) 588c48ed51cSMarc Zyngier { 589c48ed51cSMarc Zyngier struct its_device *its_dev = irq_data_get_irq_chip_data(d); 590c48ed51cSMarc Zyngier irq_hw_number_t hwirq = d->hwirq; 591c48ed51cSMarc Zyngier u32 id = its_get_event_id(d); 592c48ed51cSMarc Zyngier u8 *cfg = page_address(gic_rdists->prop_page) + hwirq - 8192; 593c48ed51cSMarc Zyngier 594c48ed51cSMarc Zyngier if (enable) 595c48ed51cSMarc Zyngier *cfg |= LPI_PROP_ENABLED; 596c48ed51cSMarc Zyngier else 597c48ed51cSMarc Zyngier *cfg &= ~LPI_PROP_ENABLED; 598c48ed51cSMarc Zyngier 599c48ed51cSMarc Zyngier /* 600c48ed51cSMarc Zyngier * Make the above write visible to the redistributors. 601c48ed51cSMarc Zyngier * And yes, we're flushing exactly: One. Single. Byte. 602c48ed51cSMarc Zyngier * Humpf... 603c48ed51cSMarc Zyngier */ 604c48ed51cSMarc Zyngier if (gic_rdists->flags & RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING) 605c48ed51cSMarc Zyngier __flush_dcache_area(cfg, sizeof(*cfg)); 606c48ed51cSMarc Zyngier else 607c48ed51cSMarc Zyngier dsb(ishst); 608c48ed51cSMarc Zyngier its_send_inv(its_dev, id); 609c48ed51cSMarc Zyngier } 610c48ed51cSMarc Zyngier 611c48ed51cSMarc Zyngier static void its_mask_irq(struct irq_data *d) 612c48ed51cSMarc Zyngier { 613c48ed51cSMarc Zyngier lpi_set_config(d, false); 614c48ed51cSMarc Zyngier } 615c48ed51cSMarc Zyngier 616c48ed51cSMarc Zyngier static void its_unmask_irq(struct irq_data *d) 617c48ed51cSMarc Zyngier { 618c48ed51cSMarc Zyngier lpi_set_config(d, true); 619c48ed51cSMarc Zyngier } 620c48ed51cSMarc Zyngier 621c48ed51cSMarc Zyngier static int its_set_affinity(struct irq_data *d, const struct cpumask *mask_val, 622c48ed51cSMarc Zyngier bool force) 623c48ed51cSMarc Zyngier { 624fbf8f40eSGanapatrao Kulkarni unsigned int cpu; 625fbf8f40eSGanapatrao Kulkarni const struct cpumask *cpu_mask = cpu_online_mask; 626c48ed51cSMarc Zyngier struct its_device *its_dev = irq_data_get_irq_chip_data(d); 627c48ed51cSMarc Zyngier struct its_collection *target_col; 628c48ed51cSMarc Zyngier u32 id = its_get_event_id(d); 629c48ed51cSMarc Zyngier 630fbf8f40eSGanapatrao Kulkarni /* lpi cannot be routed to a redistributor that is on a foreign node */ 631fbf8f40eSGanapatrao Kulkarni if (its_dev->its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) { 632fbf8f40eSGanapatrao Kulkarni if (its_dev->its->numa_node >= 0) { 633fbf8f40eSGanapatrao Kulkarni cpu_mask = cpumask_of_node(its_dev->its->numa_node); 634fbf8f40eSGanapatrao Kulkarni if (!cpumask_intersects(mask_val, cpu_mask)) 635fbf8f40eSGanapatrao Kulkarni return -EINVAL; 636fbf8f40eSGanapatrao Kulkarni } 637fbf8f40eSGanapatrao Kulkarni } 638fbf8f40eSGanapatrao Kulkarni 639fbf8f40eSGanapatrao Kulkarni cpu = cpumask_any_and(mask_val, cpu_mask); 640fbf8f40eSGanapatrao Kulkarni 641c48ed51cSMarc Zyngier if (cpu >= nr_cpu_ids) 642c48ed51cSMarc Zyngier return -EINVAL; 643c48ed51cSMarc Zyngier 644c48ed51cSMarc Zyngier target_col = &its_dev->its->collections[cpu]; 645c48ed51cSMarc Zyngier its_send_movi(its_dev, target_col, id); 646591e5becSMarc Zyngier its_dev->event_map.col_map[id] = cpu; 647c48ed51cSMarc Zyngier 648c48ed51cSMarc Zyngier return IRQ_SET_MASK_OK_DONE; 649c48ed51cSMarc Zyngier } 650c48ed51cSMarc Zyngier 651b48ac83dSMarc Zyngier static void its_irq_compose_msi_msg(struct irq_data *d, struct msi_msg *msg) 652b48ac83dSMarc Zyngier { 653b48ac83dSMarc Zyngier struct its_device *its_dev = irq_data_get_irq_chip_data(d); 654b48ac83dSMarc Zyngier struct its_node *its; 655b48ac83dSMarc Zyngier u64 addr; 656b48ac83dSMarc Zyngier 657b48ac83dSMarc Zyngier its = its_dev->its; 658b48ac83dSMarc Zyngier addr = its->phys_base + GITS_TRANSLATER; 659b48ac83dSMarc Zyngier 660*b11283ebSVladimir Murzin msg->address_lo = lower_32_bits(addr); 661*b11283ebSVladimir Murzin msg->address_hi = upper_32_bits(addr); 662b48ac83dSMarc Zyngier msg->data = its_get_event_id(d); 66344bb7e24SRobin Murphy 66444bb7e24SRobin Murphy iommu_dma_map_msi_msg(d->irq, msg); 665b48ac83dSMarc Zyngier } 666b48ac83dSMarc Zyngier 667c48ed51cSMarc Zyngier static struct irq_chip its_irq_chip = { 668c48ed51cSMarc Zyngier .name = "ITS", 669c48ed51cSMarc Zyngier .irq_mask = its_mask_irq, 670c48ed51cSMarc Zyngier .irq_unmask = its_unmask_irq, 671004fa08dSAshok Kumar .irq_eoi = irq_chip_eoi_parent, 672c48ed51cSMarc Zyngier .irq_set_affinity = its_set_affinity, 673b48ac83dSMarc Zyngier .irq_compose_msi_msg = its_irq_compose_msi_msg, 674b48ac83dSMarc Zyngier }; 675b48ac83dSMarc Zyngier 676bf9529f8SMarc Zyngier /* 677bf9529f8SMarc Zyngier * How we allocate LPIs: 678bf9529f8SMarc Zyngier * 679bf9529f8SMarc Zyngier * The GIC has id_bits bits for interrupt identifiers. From there, we 680bf9529f8SMarc Zyngier * must subtract 8192 which are reserved for SGIs/PPIs/SPIs. Then, as 681bf9529f8SMarc Zyngier * we allocate LPIs by chunks of 32, we can shift the whole thing by 5 682bf9529f8SMarc Zyngier * bits to the right. 683bf9529f8SMarc Zyngier * 684bf9529f8SMarc Zyngier * This gives us (((1UL << id_bits) - 8192) >> 5) possible allocations. 685bf9529f8SMarc Zyngier */ 686bf9529f8SMarc Zyngier #define IRQS_PER_CHUNK_SHIFT 5 687bf9529f8SMarc Zyngier #define IRQS_PER_CHUNK (1 << IRQS_PER_CHUNK_SHIFT) 688bf9529f8SMarc Zyngier 689bf9529f8SMarc Zyngier static unsigned long *lpi_bitmap; 690bf9529f8SMarc Zyngier static u32 lpi_chunks; 691bf9529f8SMarc Zyngier static DEFINE_SPINLOCK(lpi_lock); 692bf9529f8SMarc Zyngier 693bf9529f8SMarc Zyngier static int its_lpi_to_chunk(int lpi) 694bf9529f8SMarc Zyngier { 695bf9529f8SMarc Zyngier return (lpi - 8192) >> IRQS_PER_CHUNK_SHIFT; 696bf9529f8SMarc Zyngier } 697bf9529f8SMarc Zyngier 698bf9529f8SMarc Zyngier static int its_chunk_to_lpi(int chunk) 699bf9529f8SMarc Zyngier { 700bf9529f8SMarc Zyngier return (chunk << IRQS_PER_CHUNK_SHIFT) + 8192; 701bf9529f8SMarc Zyngier } 702bf9529f8SMarc Zyngier 70304a0e4deSTomasz Nowicki static int __init its_lpi_init(u32 id_bits) 704bf9529f8SMarc Zyngier { 705bf9529f8SMarc Zyngier lpi_chunks = its_lpi_to_chunk(1UL << id_bits); 706bf9529f8SMarc Zyngier 707bf9529f8SMarc Zyngier lpi_bitmap = kzalloc(BITS_TO_LONGS(lpi_chunks) * sizeof(long), 708bf9529f8SMarc Zyngier GFP_KERNEL); 709bf9529f8SMarc Zyngier if (!lpi_bitmap) { 710bf9529f8SMarc Zyngier lpi_chunks = 0; 711bf9529f8SMarc Zyngier return -ENOMEM; 712bf9529f8SMarc Zyngier } 713bf9529f8SMarc Zyngier 714bf9529f8SMarc Zyngier pr_info("ITS: Allocated %d chunks for LPIs\n", (int)lpi_chunks); 715bf9529f8SMarc Zyngier return 0; 716bf9529f8SMarc Zyngier } 717bf9529f8SMarc Zyngier 718bf9529f8SMarc Zyngier static unsigned long *its_lpi_alloc_chunks(int nr_irqs, int *base, int *nr_ids) 719bf9529f8SMarc Zyngier { 720bf9529f8SMarc Zyngier unsigned long *bitmap = NULL; 721bf9529f8SMarc Zyngier int chunk_id; 722bf9529f8SMarc Zyngier int nr_chunks; 723bf9529f8SMarc Zyngier int i; 724bf9529f8SMarc Zyngier 725bf9529f8SMarc Zyngier nr_chunks = DIV_ROUND_UP(nr_irqs, IRQS_PER_CHUNK); 726bf9529f8SMarc Zyngier 727bf9529f8SMarc Zyngier spin_lock(&lpi_lock); 728bf9529f8SMarc Zyngier 729bf9529f8SMarc Zyngier do { 730bf9529f8SMarc Zyngier chunk_id = bitmap_find_next_zero_area(lpi_bitmap, lpi_chunks, 731bf9529f8SMarc Zyngier 0, nr_chunks, 0); 732bf9529f8SMarc Zyngier if (chunk_id < lpi_chunks) 733bf9529f8SMarc Zyngier break; 734bf9529f8SMarc Zyngier 735bf9529f8SMarc Zyngier nr_chunks--; 736bf9529f8SMarc Zyngier } while (nr_chunks > 0); 737bf9529f8SMarc Zyngier 738bf9529f8SMarc Zyngier if (!nr_chunks) 739bf9529f8SMarc Zyngier goto out; 740bf9529f8SMarc Zyngier 741bf9529f8SMarc Zyngier bitmap = kzalloc(BITS_TO_LONGS(nr_chunks * IRQS_PER_CHUNK) * sizeof (long), 742bf9529f8SMarc Zyngier GFP_ATOMIC); 743bf9529f8SMarc Zyngier if (!bitmap) 744bf9529f8SMarc Zyngier goto out; 745bf9529f8SMarc Zyngier 746bf9529f8SMarc Zyngier for (i = 0; i < nr_chunks; i++) 747bf9529f8SMarc Zyngier set_bit(chunk_id + i, lpi_bitmap); 748bf9529f8SMarc Zyngier 749bf9529f8SMarc Zyngier *base = its_chunk_to_lpi(chunk_id); 750bf9529f8SMarc Zyngier *nr_ids = nr_chunks * IRQS_PER_CHUNK; 751bf9529f8SMarc Zyngier 752bf9529f8SMarc Zyngier out: 753bf9529f8SMarc Zyngier spin_unlock(&lpi_lock); 754bf9529f8SMarc Zyngier 755c8415b94SMarc Zyngier if (!bitmap) 756c8415b94SMarc Zyngier *base = *nr_ids = 0; 757c8415b94SMarc Zyngier 758bf9529f8SMarc Zyngier return bitmap; 759bf9529f8SMarc Zyngier } 760bf9529f8SMarc Zyngier 761591e5becSMarc Zyngier static void its_lpi_free(struct event_lpi_map *map) 762bf9529f8SMarc Zyngier { 763591e5becSMarc Zyngier int base = map->lpi_base; 764591e5becSMarc Zyngier int nr_ids = map->nr_lpis; 765bf9529f8SMarc Zyngier int lpi; 766bf9529f8SMarc Zyngier 767bf9529f8SMarc Zyngier spin_lock(&lpi_lock); 768bf9529f8SMarc Zyngier 769bf9529f8SMarc Zyngier for (lpi = base; lpi < (base + nr_ids); lpi += IRQS_PER_CHUNK) { 770bf9529f8SMarc Zyngier int chunk = its_lpi_to_chunk(lpi); 771bf9529f8SMarc Zyngier BUG_ON(chunk > lpi_chunks); 772bf9529f8SMarc Zyngier if (test_bit(chunk, lpi_bitmap)) { 773bf9529f8SMarc Zyngier clear_bit(chunk, lpi_bitmap); 774bf9529f8SMarc Zyngier } else { 775bf9529f8SMarc Zyngier pr_err("Bad LPI chunk %d\n", chunk); 776bf9529f8SMarc Zyngier } 777bf9529f8SMarc Zyngier } 778bf9529f8SMarc Zyngier 779bf9529f8SMarc Zyngier spin_unlock(&lpi_lock); 780bf9529f8SMarc Zyngier 781591e5becSMarc Zyngier kfree(map->lpi_map); 782591e5becSMarc Zyngier kfree(map->col_map); 783bf9529f8SMarc Zyngier } 7841ac19ca6SMarc Zyngier 7851ac19ca6SMarc Zyngier /* 7861ac19ca6SMarc Zyngier * We allocate 64kB for PROPBASE. That gives us at most 64K LPIs to 7871ac19ca6SMarc Zyngier * deal with (one configuration byte per interrupt). PENDBASE has to 7881ac19ca6SMarc Zyngier * be 64kB aligned (one bit per LPI, plus 8192 bits for SPI/PPI/SGI). 7891ac19ca6SMarc Zyngier */ 7901ac19ca6SMarc Zyngier #define LPI_PROPBASE_SZ SZ_64K 7911ac19ca6SMarc Zyngier #define LPI_PENDBASE_SZ (LPI_PROPBASE_SZ / 8 + SZ_1K) 7921ac19ca6SMarc Zyngier 7931ac19ca6SMarc Zyngier /* 7941ac19ca6SMarc Zyngier * This is how many bits of ID we need, including the useless ones. 7951ac19ca6SMarc Zyngier */ 7961ac19ca6SMarc Zyngier #define LPI_NRBITS ilog2(LPI_PROPBASE_SZ + SZ_8K) 7971ac19ca6SMarc Zyngier 7981ac19ca6SMarc Zyngier #define LPI_PROP_DEFAULT_PRIO 0xa0 7991ac19ca6SMarc Zyngier 8001ac19ca6SMarc Zyngier static int __init its_alloc_lpi_tables(void) 8011ac19ca6SMarc Zyngier { 8021ac19ca6SMarc Zyngier phys_addr_t paddr; 8031ac19ca6SMarc Zyngier 8041ac19ca6SMarc Zyngier gic_rdists->prop_page = alloc_pages(GFP_NOWAIT, 8051ac19ca6SMarc Zyngier get_order(LPI_PROPBASE_SZ)); 8061ac19ca6SMarc Zyngier if (!gic_rdists->prop_page) { 8071ac19ca6SMarc Zyngier pr_err("Failed to allocate PROPBASE\n"); 8081ac19ca6SMarc Zyngier return -ENOMEM; 8091ac19ca6SMarc Zyngier } 8101ac19ca6SMarc Zyngier 8111ac19ca6SMarc Zyngier paddr = page_to_phys(gic_rdists->prop_page); 8121ac19ca6SMarc Zyngier pr_info("GIC: using LPI property table @%pa\n", &paddr); 8131ac19ca6SMarc Zyngier 8141ac19ca6SMarc Zyngier /* Priority 0xa0, Group-1, disabled */ 8151ac19ca6SMarc Zyngier memset(page_address(gic_rdists->prop_page), 8161ac19ca6SMarc Zyngier LPI_PROP_DEFAULT_PRIO | LPI_PROP_GROUP1, 8171ac19ca6SMarc Zyngier LPI_PROPBASE_SZ); 8181ac19ca6SMarc Zyngier 8191ac19ca6SMarc Zyngier /* Make sure the GIC will observe the written configuration */ 8201ac19ca6SMarc Zyngier __flush_dcache_area(page_address(gic_rdists->prop_page), LPI_PROPBASE_SZ); 8211ac19ca6SMarc Zyngier 8221ac19ca6SMarc Zyngier return 0; 8231ac19ca6SMarc Zyngier } 8241ac19ca6SMarc Zyngier 8251ac19ca6SMarc Zyngier static const char *its_base_type_string[] = { 8261ac19ca6SMarc Zyngier [GITS_BASER_TYPE_DEVICE] = "Devices", 8271ac19ca6SMarc Zyngier [GITS_BASER_TYPE_VCPU] = "Virtual CPUs", 8281ac19ca6SMarc Zyngier [GITS_BASER_TYPE_CPU] = "Physical CPUs", 8291ac19ca6SMarc Zyngier [GITS_BASER_TYPE_COLLECTION] = "Interrupt Collections", 8301ac19ca6SMarc Zyngier [GITS_BASER_TYPE_RESERVED5] = "Reserved (5)", 8311ac19ca6SMarc Zyngier [GITS_BASER_TYPE_RESERVED6] = "Reserved (6)", 8321ac19ca6SMarc Zyngier [GITS_BASER_TYPE_RESERVED7] = "Reserved (7)", 8331ac19ca6SMarc Zyngier }; 8341ac19ca6SMarc Zyngier 8352d81d425SShanker Donthineni static u64 its_read_baser(struct its_node *its, struct its_baser *baser) 8362d81d425SShanker Donthineni { 8372d81d425SShanker Donthineni u32 idx = baser - its->tables; 8382d81d425SShanker Donthineni 8392d81d425SShanker Donthineni return readq_relaxed(its->base + GITS_BASER + (idx << 3)); 8402d81d425SShanker Donthineni } 8412d81d425SShanker Donthineni 8422d81d425SShanker Donthineni static void its_write_baser(struct its_node *its, struct its_baser *baser, 8432d81d425SShanker Donthineni u64 val) 8442d81d425SShanker Donthineni { 8452d81d425SShanker Donthineni u32 idx = baser - its->tables; 8462d81d425SShanker Donthineni 8472d81d425SShanker Donthineni writeq_relaxed(val, its->base + GITS_BASER + (idx << 3)); 8482d81d425SShanker Donthineni baser->val = its_read_baser(its, baser); 8492d81d425SShanker Donthineni } 8502d81d425SShanker Donthineni 8519347359aSShanker Donthineni static int its_setup_baser(struct its_node *its, struct its_baser *baser, 8523faf24eaSShanker Donthineni u64 cache, u64 shr, u32 psz, u32 order, 8533faf24eaSShanker Donthineni bool indirect) 8549347359aSShanker Donthineni { 8559347359aSShanker Donthineni u64 val = its_read_baser(its, baser); 8569347359aSShanker Donthineni u64 esz = GITS_BASER_ENTRY_SIZE(val); 8579347359aSShanker Donthineni u64 type = GITS_BASER_TYPE(val); 8589347359aSShanker Donthineni u32 alloc_pages; 8599347359aSShanker Donthineni void *base; 8609347359aSShanker Donthineni u64 tmp; 8619347359aSShanker Donthineni 8629347359aSShanker Donthineni retry_alloc_baser: 8639347359aSShanker Donthineni alloc_pages = (PAGE_ORDER_TO_SIZE(order) / psz); 8649347359aSShanker Donthineni if (alloc_pages > GITS_BASER_PAGES_MAX) { 8659347359aSShanker Donthineni pr_warn("ITS@%pa: %s too large, reduce ITS pages %u->%u\n", 8669347359aSShanker Donthineni &its->phys_base, its_base_type_string[type], 8679347359aSShanker Donthineni alloc_pages, GITS_BASER_PAGES_MAX); 8689347359aSShanker Donthineni alloc_pages = GITS_BASER_PAGES_MAX; 8699347359aSShanker Donthineni order = get_order(GITS_BASER_PAGES_MAX * psz); 8709347359aSShanker Donthineni } 8719347359aSShanker Donthineni 8729347359aSShanker Donthineni base = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, order); 8739347359aSShanker Donthineni if (!base) 8749347359aSShanker Donthineni return -ENOMEM; 8759347359aSShanker Donthineni 8769347359aSShanker Donthineni retry_baser: 8779347359aSShanker Donthineni val = (virt_to_phys(base) | 8789347359aSShanker Donthineni (type << GITS_BASER_TYPE_SHIFT) | 8799347359aSShanker Donthineni ((esz - 1) << GITS_BASER_ENTRY_SIZE_SHIFT) | 8809347359aSShanker Donthineni ((alloc_pages - 1) << GITS_BASER_PAGES_SHIFT) | 8819347359aSShanker Donthineni cache | 8829347359aSShanker Donthineni shr | 8839347359aSShanker Donthineni GITS_BASER_VALID); 8849347359aSShanker Donthineni 8853faf24eaSShanker Donthineni val |= indirect ? GITS_BASER_INDIRECT : 0x0; 8863faf24eaSShanker Donthineni 8879347359aSShanker Donthineni switch (psz) { 8889347359aSShanker Donthineni case SZ_4K: 8899347359aSShanker Donthineni val |= GITS_BASER_PAGE_SIZE_4K; 8909347359aSShanker Donthineni break; 8919347359aSShanker Donthineni case SZ_16K: 8929347359aSShanker Donthineni val |= GITS_BASER_PAGE_SIZE_16K; 8939347359aSShanker Donthineni break; 8949347359aSShanker Donthineni case SZ_64K: 8959347359aSShanker Donthineni val |= GITS_BASER_PAGE_SIZE_64K; 8969347359aSShanker Donthineni break; 8979347359aSShanker Donthineni } 8989347359aSShanker Donthineni 8999347359aSShanker Donthineni its_write_baser(its, baser, val); 9009347359aSShanker Donthineni tmp = baser->val; 9019347359aSShanker Donthineni 9029347359aSShanker Donthineni if ((val ^ tmp) & GITS_BASER_SHAREABILITY_MASK) { 9039347359aSShanker Donthineni /* 9049347359aSShanker Donthineni * Shareability didn't stick. Just use 9059347359aSShanker Donthineni * whatever the read reported, which is likely 9069347359aSShanker Donthineni * to be the only thing this redistributor 9079347359aSShanker Donthineni * supports. If that's zero, make it 9089347359aSShanker Donthineni * non-cacheable as well. 9099347359aSShanker Donthineni */ 9109347359aSShanker Donthineni shr = tmp & GITS_BASER_SHAREABILITY_MASK; 9119347359aSShanker Donthineni if (!shr) { 9129347359aSShanker Donthineni cache = GITS_BASER_nC; 9139347359aSShanker Donthineni __flush_dcache_area(base, PAGE_ORDER_TO_SIZE(order)); 9149347359aSShanker Donthineni } 9159347359aSShanker Donthineni goto retry_baser; 9169347359aSShanker Donthineni } 9179347359aSShanker Donthineni 9189347359aSShanker Donthineni if ((val ^ tmp) & GITS_BASER_PAGE_SIZE_MASK) { 9199347359aSShanker Donthineni /* 9209347359aSShanker Donthineni * Page size didn't stick. Let's try a smaller 9219347359aSShanker Donthineni * size and retry. If we reach 4K, then 9229347359aSShanker Donthineni * something is horribly wrong... 9239347359aSShanker Donthineni */ 9249347359aSShanker Donthineni free_pages((unsigned long)base, order); 9259347359aSShanker Donthineni baser->base = NULL; 9269347359aSShanker Donthineni 9279347359aSShanker Donthineni switch (psz) { 9289347359aSShanker Donthineni case SZ_16K: 9299347359aSShanker Donthineni psz = SZ_4K; 9309347359aSShanker Donthineni goto retry_alloc_baser; 9319347359aSShanker Donthineni case SZ_64K: 9329347359aSShanker Donthineni psz = SZ_16K; 9339347359aSShanker Donthineni goto retry_alloc_baser; 9349347359aSShanker Donthineni } 9359347359aSShanker Donthineni } 9369347359aSShanker Donthineni 9379347359aSShanker Donthineni if (val != tmp) { 938*b11283ebSVladimir Murzin pr_err("ITS@%pa: %s doesn't stick: %llx %llx\n", 9399347359aSShanker Donthineni &its->phys_base, its_base_type_string[type], 940*b11283ebSVladimir Murzin val, tmp); 9419347359aSShanker Donthineni free_pages((unsigned long)base, order); 9429347359aSShanker Donthineni return -ENXIO; 9439347359aSShanker Donthineni } 9449347359aSShanker Donthineni 9459347359aSShanker Donthineni baser->order = order; 9469347359aSShanker Donthineni baser->base = base; 9479347359aSShanker Donthineni baser->psz = psz; 9483faf24eaSShanker Donthineni tmp = indirect ? GITS_LVL1_ENTRY_SIZE : esz; 9499347359aSShanker Donthineni 9503faf24eaSShanker Donthineni pr_info("ITS@%pa: allocated %d %s @%lx (%s, esz %d, psz %dK, shr %d)\n", 9513faf24eaSShanker Donthineni &its->phys_base, (int)(PAGE_ORDER_TO_SIZE(order) / tmp), 9529347359aSShanker Donthineni its_base_type_string[type], 9539347359aSShanker Donthineni (unsigned long)virt_to_phys(base), 9543faf24eaSShanker Donthineni indirect ? "indirect" : "flat", (int)esz, 9559347359aSShanker Donthineni psz / SZ_1K, (int)shr >> GITS_BASER_SHAREABILITY_SHIFT); 9569347359aSShanker Donthineni 9579347359aSShanker Donthineni return 0; 9589347359aSShanker Donthineni } 9599347359aSShanker Donthineni 9603faf24eaSShanker Donthineni static bool its_parse_baser_device(struct its_node *its, struct its_baser *baser, 9613faf24eaSShanker Donthineni u32 psz, u32 *order) 9624b75c459SShanker Donthineni { 9634b75c459SShanker Donthineni u64 esz = GITS_BASER_ENTRY_SIZE(its_read_baser(its, baser)); 9643faf24eaSShanker Donthineni u64 val = GITS_BASER_InnerShareable | GITS_BASER_WaWb; 9654b75c459SShanker Donthineni u32 ids = its->device_ids; 9664b75c459SShanker Donthineni u32 new_order = *order; 9673faf24eaSShanker Donthineni bool indirect = false; 9683faf24eaSShanker Donthineni 9693faf24eaSShanker Donthineni /* No need to enable Indirection if memory requirement < (psz*2)bytes */ 9703faf24eaSShanker Donthineni if ((esz << ids) > (psz * 2)) { 9713faf24eaSShanker Donthineni /* 9723faf24eaSShanker Donthineni * Find out whether hw supports a single or two-level table by 9733faf24eaSShanker Donthineni * table by reading bit at offset '62' after writing '1' to it. 9743faf24eaSShanker Donthineni */ 9753faf24eaSShanker Donthineni its_write_baser(its, baser, val | GITS_BASER_INDIRECT); 9763faf24eaSShanker Donthineni indirect = !!(baser->val & GITS_BASER_INDIRECT); 9773faf24eaSShanker Donthineni 9783faf24eaSShanker Donthineni if (indirect) { 9793faf24eaSShanker Donthineni /* 9803faf24eaSShanker Donthineni * The size of the lvl2 table is equal to ITS page size 9813faf24eaSShanker Donthineni * which is 'psz'. For computing lvl1 table size, 9823faf24eaSShanker Donthineni * subtract ID bits that sparse lvl2 table from 'ids' 9833faf24eaSShanker Donthineni * which is reported by ITS hardware times lvl1 table 9843faf24eaSShanker Donthineni * entry size. 9853faf24eaSShanker Donthineni */ 9863faf24eaSShanker Donthineni ids -= ilog2(psz / esz); 9873faf24eaSShanker Donthineni esz = GITS_LVL1_ENTRY_SIZE; 9883faf24eaSShanker Donthineni } 9893faf24eaSShanker Donthineni } 9904b75c459SShanker Donthineni 9914b75c459SShanker Donthineni /* 9924b75c459SShanker Donthineni * Allocate as many entries as required to fit the 9934b75c459SShanker Donthineni * range of device IDs that the ITS can grok... The ID 9944b75c459SShanker Donthineni * space being incredibly sparse, this results in a 9953faf24eaSShanker Donthineni * massive waste of memory if two-level device table 9963faf24eaSShanker Donthineni * feature is not supported by hardware. 9974b75c459SShanker Donthineni */ 9984b75c459SShanker Donthineni new_order = max_t(u32, get_order(esz << ids), new_order); 9994b75c459SShanker Donthineni if (new_order >= MAX_ORDER) { 10004b75c459SShanker Donthineni new_order = MAX_ORDER - 1; 10014b75c459SShanker Donthineni ids = ilog2(PAGE_ORDER_TO_SIZE(new_order) / esz); 10024b75c459SShanker Donthineni pr_warn("ITS@%pa: Device Table too large, reduce ids %u->%u\n", 10034b75c459SShanker Donthineni &its->phys_base, its->device_ids, ids); 10044b75c459SShanker Donthineni } 10054b75c459SShanker Donthineni 10064b75c459SShanker Donthineni *order = new_order; 10073faf24eaSShanker Donthineni 10083faf24eaSShanker Donthineni return indirect; 10094b75c459SShanker Donthineni } 10104b75c459SShanker Donthineni 10111ac19ca6SMarc Zyngier static void its_free_tables(struct its_node *its) 10121ac19ca6SMarc Zyngier { 10131ac19ca6SMarc Zyngier int i; 10141ac19ca6SMarc Zyngier 10151ac19ca6SMarc Zyngier for (i = 0; i < GITS_BASER_NR_REGS; i++) { 10161a485f4dSShanker Donthineni if (its->tables[i].base) { 10171a485f4dSShanker Donthineni free_pages((unsigned long)its->tables[i].base, 10181a485f4dSShanker Donthineni its->tables[i].order); 10191a485f4dSShanker Donthineni its->tables[i].base = NULL; 10201ac19ca6SMarc Zyngier } 10211ac19ca6SMarc Zyngier } 10221ac19ca6SMarc Zyngier } 10231ac19ca6SMarc Zyngier 10240e0b0f69SShanker Donthineni static int its_alloc_tables(struct its_node *its) 10251ac19ca6SMarc Zyngier { 1026589ce5f4SMarc Zyngier u64 typer = gic_read_typer(its->base + GITS_TYPER); 10279347359aSShanker Donthineni u32 ids = GITS_TYPER_DEVBITS(typer); 10281ac19ca6SMarc Zyngier u64 shr = GITS_BASER_InnerShareable; 10299347359aSShanker Donthineni u64 cache = GITS_BASER_WaWb; 10309347359aSShanker Donthineni u32 psz = SZ_64K; 10319347359aSShanker Donthineni int err, i; 103294100970SRobert Richter 103394100970SRobert Richter if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_22375) { 103494100970SRobert Richter /* 103594100970SRobert Richter * erratum 22375: only alloc 8MB table size 103694100970SRobert Richter * erratum 24313: ignore memory access type 103794100970SRobert Richter */ 10389347359aSShanker Donthineni cache = GITS_BASER_nCnB; 103994100970SRobert Richter ids = 0x14; /* 20 bits, 8MB */ 104094100970SRobert Richter } 10411ac19ca6SMarc Zyngier 1042466b7d16SShanker Donthineni its->device_ids = ids; 1043466b7d16SShanker Donthineni 10441ac19ca6SMarc Zyngier for (i = 0; i < GITS_BASER_NR_REGS; i++) { 10452d81d425SShanker Donthineni struct its_baser *baser = its->tables + i; 10462d81d425SShanker Donthineni u64 val = its_read_baser(its, baser); 10471ac19ca6SMarc Zyngier u64 type = GITS_BASER_TYPE(val); 10489347359aSShanker Donthineni u32 order = get_order(psz); 10493faf24eaSShanker Donthineni bool indirect = false; 10501ac19ca6SMarc Zyngier 10511ac19ca6SMarc Zyngier if (type == GITS_BASER_TYPE_NONE) 10521ac19ca6SMarc Zyngier continue; 10531ac19ca6SMarc Zyngier 10544b75c459SShanker Donthineni if (type == GITS_BASER_TYPE_DEVICE) 10553faf24eaSShanker Donthineni indirect = its_parse_baser_device(its, baser, psz, &order); 1056f54b97edSMarc Zyngier 10573faf24eaSShanker Donthineni err = its_setup_baser(its, baser, cache, shr, psz, order, indirect); 10589347359aSShanker Donthineni if (err < 0) { 10599347359aSShanker Donthineni its_free_tables(its); 10609347359aSShanker Donthineni return err; 106130f21363SRobert Richter } 106230f21363SRobert Richter 10639347359aSShanker Donthineni /* Update settings which will be used for next BASERn */ 10649347359aSShanker Donthineni psz = baser->psz; 10659347359aSShanker Donthineni cache = baser->val & GITS_BASER_CACHEABILITY_MASK; 10669347359aSShanker Donthineni shr = baser->val & GITS_BASER_SHAREABILITY_MASK; 10671ac19ca6SMarc Zyngier } 10681ac19ca6SMarc Zyngier 10691ac19ca6SMarc Zyngier return 0; 10701ac19ca6SMarc Zyngier } 10711ac19ca6SMarc Zyngier 10721ac19ca6SMarc Zyngier static int its_alloc_collections(struct its_node *its) 10731ac19ca6SMarc Zyngier { 10741ac19ca6SMarc Zyngier its->collections = kzalloc(nr_cpu_ids * sizeof(*its->collections), 10751ac19ca6SMarc Zyngier GFP_KERNEL); 10761ac19ca6SMarc Zyngier if (!its->collections) 10771ac19ca6SMarc Zyngier return -ENOMEM; 10781ac19ca6SMarc Zyngier 10791ac19ca6SMarc Zyngier return 0; 10801ac19ca6SMarc Zyngier } 10811ac19ca6SMarc Zyngier 10821ac19ca6SMarc Zyngier static void its_cpu_init_lpis(void) 10831ac19ca6SMarc Zyngier { 10841ac19ca6SMarc Zyngier void __iomem *rbase = gic_data_rdist_rd_base(); 10851ac19ca6SMarc Zyngier struct page *pend_page; 10861ac19ca6SMarc Zyngier u64 val, tmp; 10871ac19ca6SMarc Zyngier 10881ac19ca6SMarc Zyngier /* If we didn't allocate the pending table yet, do it now */ 10891ac19ca6SMarc Zyngier pend_page = gic_data_rdist()->pend_page; 10901ac19ca6SMarc Zyngier if (!pend_page) { 10911ac19ca6SMarc Zyngier phys_addr_t paddr; 10921ac19ca6SMarc Zyngier /* 10931ac19ca6SMarc Zyngier * The pending pages have to be at least 64kB aligned, 10941ac19ca6SMarc Zyngier * hence the 'max(LPI_PENDBASE_SZ, SZ_64K)' below. 10951ac19ca6SMarc Zyngier */ 10961ac19ca6SMarc Zyngier pend_page = alloc_pages(GFP_NOWAIT | __GFP_ZERO, 10971ac19ca6SMarc Zyngier get_order(max(LPI_PENDBASE_SZ, SZ_64K))); 10981ac19ca6SMarc Zyngier if (!pend_page) { 10991ac19ca6SMarc Zyngier pr_err("Failed to allocate PENDBASE for CPU%d\n", 11001ac19ca6SMarc Zyngier smp_processor_id()); 11011ac19ca6SMarc Zyngier return; 11021ac19ca6SMarc Zyngier } 11031ac19ca6SMarc Zyngier 11041ac19ca6SMarc Zyngier /* Make sure the GIC will observe the zero-ed page */ 11051ac19ca6SMarc Zyngier __flush_dcache_area(page_address(pend_page), LPI_PENDBASE_SZ); 11061ac19ca6SMarc Zyngier 11071ac19ca6SMarc Zyngier paddr = page_to_phys(pend_page); 11081ac19ca6SMarc Zyngier pr_info("CPU%d: using LPI pending table @%pa\n", 11091ac19ca6SMarc Zyngier smp_processor_id(), &paddr); 11101ac19ca6SMarc Zyngier gic_data_rdist()->pend_page = pend_page; 11111ac19ca6SMarc Zyngier } 11121ac19ca6SMarc Zyngier 11131ac19ca6SMarc Zyngier /* Disable LPIs */ 11141ac19ca6SMarc Zyngier val = readl_relaxed(rbase + GICR_CTLR); 11151ac19ca6SMarc Zyngier val &= ~GICR_CTLR_ENABLE_LPIS; 11161ac19ca6SMarc Zyngier writel_relaxed(val, rbase + GICR_CTLR); 11171ac19ca6SMarc Zyngier 11181ac19ca6SMarc Zyngier /* 11191ac19ca6SMarc Zyngier * Make sure any change to the table is observable by the GIC. 11201ac19ca6SMarc Zyngier */ 11211ac19ca6SMarc Zyngier dsb(sy); 11221ac19ca6SMarc Zyngier 11231ac19ca6SMarc Zyngier /* set PROPBASE */ 11241ac19ca6SMarc Zyngier val = (page_to_phys(gic_rdists->prop_page) | 11251ac19ca6SMarc Zyngier GICR_PROPBASER_InnerShareable | 11261ac19ca6SMarc Zyngier GICR_PROPBASER_WaWb | 11271ac19ca6SMarc Zyngier ((LPI_NRBITS - 1) & GICR_PROPBASER_IDBITS_MASK)); 11281ac19ca6SMarc Zyngier 11291ac19ca6SMarc Zyngier writeq_relaxed(val, rbase + GICR_PROPBASER); 11301ac19ca6SMarc Zyngier tmp = readq_relaxed(rbase + GICR_PROPBASER); 11311ac19ca6SMarc Zyngier 11321ac19ca6SMarc Zyngier if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) { 1133241a386cSMarc Zyngier if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) { 1134241a386cSMarc Zyngier /* 1135241a386cSMarc Zyngier * The HW reports non-shareable, we must 1136241a386cSMarc Zyngier * remove the cacheability attributes as 1137241a386cSMarc Zyngier * well. 1138241a386cSMarc Zyngier */ 1139241a386cSMarc Zyngier val &= ~(GICR_PROPBASER_SHAREABILITY_MASK | 1140241a386cSMarc Zyngier GICR_PROPBASER_CACHEABILITY_MASK); 1141241a386cSMarc Zyngier val |= GICR_PROPBASER_nC; 1142241a386cSMarc Zyngier writeq_relaxed(val, rbase + GICR_PROPBASER); 1143241a386cSMarc Zyngier } 11441ac19ca6SMarc Zyngier pr_info_once("GIC: using cache flushing for LPI property table\n"); 11451ac19ca6SMarc Zyngier gic_rdists->flags |= RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING; 11461ac19ca6SMarc Zyngier } 11471ac19ca6SMarc Zyngier 11481ac19ca6SMarc Zyngier /* set PENDBASE */ 11491ac19ca6SMarc Zyngier val = (page_to_phys(pend_page) | 11504ad3e363SMarc Zyngier GICR_PENDBASER_InnerShareable | 11514ad3e363SMarc Zyngier GICR_PENDBASER_WaWb); 11521ac19ca6SMarc Zyngier 11531ac19ca6SMarc Zyngier writeq_relaxed(val, rbase + GICR_PENDBASER); 1154241a386cSMarc Zyngier tmp = readq_relaxed(rbase + GICR_PENDBASER); 1155241a386cSMarc Zyngier 1156241a386cSMarc Zyngier if (!(tmp & GICR_PENDBASER_SHAREABILITY_MASK)) { 1157241a386cSMarc Zyngier /* 1158241a386cSMarc Zyngier * The HW reports non-shareable, we must remove the 1159241a386cSMarc Zyngier * cacheability attributes as well. 1160241a386cSMarc Zyngier */ 1161241a386cSMarc Zyngier val &= ~(GICR_PENDBASER_SHAREABILITY_MASK | 1162241a386cSMarc Zyngier GICR_PENDBASER_CACHEABILITY_MASK); 1163241a386cSMarc Zyngier val |= GICR_PENDBASER_nC; 1164241a386cSMarc Zyngier writeq_relaxed(val, rbase + GICR_PENDBASER); 1165241a386cSMarc Zyngier } 11661ac19ca6SMarc Zyngier 11671ac19ca6SMarc Zyngier /* Enable LPIs */ 11681ac19ca6SMarc Zyngier val = readl_relaxed(rbase + GICR_CTLR); 11691ac19ca6SMarc Zyngier val |= GICR_CTLR_ENABLE_LPIS; 11701ac19ca6SMarc Zyngier writel_relaxed(val, rbase + GICR_CTLR); 11711ac19ca6SMarc Zyngier 11721ac19ca6SMarc Zyngier /* Make sure the GIC has seen the above */ 11731ac19ca6SMarc Zyngier dsb(sy); 11741ac19ca6SMarc Zyngier } 11751ac19ca6SMarc Zyngier 11761ac19ca6SMarc Zyngier static void its_cpu_init_collection(void) 11771ac19ca6SMarc Zyngier { 11781ac19ca6SMarc Zyngier struct its_node *its; 11791ac19ca6SMarc Zyngier int cpu; 11801ac19ca6SMarc Zyngier 11811ac19ca6SMarc Zyngier spin_lock(&its_lock); 11821ac19ca6SMarc Zyngier cpu = smp_processor_id(); 11831ac19ca6SMarc Zyngier 11841ac19ca6SMarc Zyngier list_for_each_entry(its, &its_nodes, entry) { 11851ac19ca6SMarc Zyngier u64 target; 11861ac19ca6SMarc Zyngier 1187fbf8f40eSGanapatrao Kulkarni /* avoid cross node collections and its mapping */ 1188fbf8f40eSGanapatrao Kulkarni if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) { 1189fbf8f40eSGanapatrao Kulkarni struct device_node *cpu_node; 1190fbf8f40eSGanapatrao Kulkarni 1191fbf8f40eSGanapatrao Kulkarni cpu_node = of_get_cpu_node(cpu, NULL); 1192fbf8f40eSGanapatrao Kulkarni if (its->numa_node != NUMA_NO_NODE && 1193fbf8f40eSGanapatrao Kulkarni its->numa_node != of_node_to_nid(cpu_node)) 1194fbf8f40eSGanapatrao Kulkarni continue; 1195fbf8f40eSGanapatrao Kulkarni } 1196fbf8f40eSGanapatrao Kulkarni 11971ac19ca6SMarc Zyngier /* 11981ac19ca6SMarc Zyngier * We now have to bind each collection to its target 11991ac19ca6SMarc Zyngier * redistributor. 12001ac19ca6SMarc Zyngier */ 1201589ce5f4SMarc Zyngier if (gic_read_typer(its->base + GITS_TYPER) & GITS_TYPER_PTA) { 12021ac19ca6SMarc Zyngier /* 12031ac19ca6SMarc Zyngier * This ITS wants the physical address of the 12041ac19ca6SMarc Zyngier * redistributor. 12051ac19ca6SMarc Zyngier */ 12061ac19ca6SMarc Zyngier target = gic_data_rdist()->phys_base; 12071ac19ca6SMarc Zyngier } else { 12081ac19ca6SMarc Zyngier /* 12091ac19ca6SMarc Zyngier * This ITS wants a linear CPU number. 12101ac19ca6SMarc Zyngier */ 1211589ce5f4SMarc Zyngier target = gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER); 1212263fcd31SMarc Zyngier target = GICR_TYPER_CPU_NUMBER(target) << 16; 12131ac19ca6SMarc Zyngier } 12141ac19ca6SMarc Zyngier 12151ac19ca6SMarc Zyngier /* Perform collection mapping */ 12161ac19ca6SMarc Zyngier its->collections[cpu].target_address = target; 12171ac19ca6SMarc Zyngier its->collections[cpu].col_id = cpu; 12181ac19ca6SMarc Zyngier 12191ac19ca6SMarc Zyngier its_send_mapc(its, &its->collections[cpu], 1); 12201ac19ca6SMarc Zyngier its_send_invall(its, &its->collections[cpu]); 12211ac19ca6SMarc Zyngier } 12221ac19ca6SMarc Zyngier 12231ac19ca6SMarc Zyngier spin_unlock(&its_lock); 12241ac19ca6SMarc Zyngier } 122584a6a2e7SMarc Zyngier 122684a6a2e7SMarc Zyngier static struct its_device *its_find_device(struct its_node *its, u32 dev_id) 122784a6a2e7SMarc Zyngier { 122884a6a2e7SMarc Zyngier struct its_device *its_dev = NULL, *tmp; 12293e39e8f5SMarc Zyngier unsigned long flags; 123084a6a2e7SMarc Zyngier 12313e39e8f5SMarc Zyngier raw_spin_lock_irqsave(&its->lock, flags); 123284a6a2e7SMarc Zyngier 123384a6a2e7SMarc Zyngier list_for_each_entry(tmp, &its->its_device_list, entry) { 123484a6a2e7SMarc Zyngier if (tmp->device_id == dev_id) { 123584a6a2e7SMarc Zyngier its_dev = tmp; 123684a6a2e7SMarc Zyngier break; 123784a6a2e7SMarc Zyngier } 123884a6a2e7SMarc Zyngier } 123984a6a2e7SMarc Zyngier 12403e39e8f5SMarc Zyngier raw_spin_unlock_irqrestore(&its->lock, flags); 124184a6a2e7SMarc Zyngier 124284a6a2e7SMarc Zyngier return its_dev; 124384a6a2e7SMarc Zyngier } 124484a6a2e7SMarc Zyngier 1245466b7d16SShanker Donthineni static struct its_baser *its_get_baser(struct its_node *its, u32 type) 1246466b7d16SShanker Donthineni { 1247466b7d16SShanker Donthineni int i; 1248466b7d16SShanker Donthineni 1249466b7d16SShanker Donthineni for (i = 0; i < GITS_BASER_NR_REGS; i++) { 1250466b7d16SShanker Donthineni if (GITS_BASER_TYPE(its->tables[i].val) == type) 1251466b7d16SShanker Donthineni return &its->tables[i]; 1252466b7d16SShanker Donthineni } 1253466b7d16SShanker Donthineni 1254466b7d16SShanker Donthineni return NULL; 1255466b7d16SShanker Donthineni } 1256466b7d16SShanker Donthineni 12573faf24eaSShanker Donthineni static bool its_alloc_device_table(struct its_node *its, u32 dev_id) 12583faf24eaSShanker Donthineni { 12593faf24eaSShanker Donthineni struct its_baser *baser; 12603faf24eaSShanker Donthineni struct page *page; 12613faf24eaSShanker Donthineni u32 esz, idx; 12623faf24eaSShanker Donthineni __le64 *table; 12633faf24eaSShanker Donthineni 12643faf24eaSShanker Donthineni baser = its_get_baser(its, GITS_BASER_TYPE_DEVICE); 12653faf24eaSShanker Donthineni 12663faf24eaSShanker Donthineni /* Don't allow device id that exceeds ITS hardware limit */ 12673faf24eaSShanker Donthineni if (!baser) 12683faf24eaSShanker Donthineni return (ilog2(dev_id) < its->device_ids); 12693faf24eaSShanker Donthineni 12703faf24eaSShanker Donthineni /* Don't allow device id that exceeds single, flat table limit */ 12713faf24eaSShanker Donthineni esz = GITS_BASER_ENTRY_SIZE(baser->val); 12723faf24eaSShanker Donthineni if (!(baser->val & GITS_BASER_INDIRECT)) 12733faf24eaSShanker Donthineni return (dev_id < (PAGE_ORDER_TO_SIZE(baser->order) / esz)); 12743faf24eaSShanker Donthineni 12753faf24eaSShanker Donthineni /* Compute 1st level table index & check if that exceeds table limit */ 12763faf24eaSShanker Donthineni idx = dev_id >> ilog2(baser->psz / esz); 12773faf24eaSShanker Donthineni if (idx >= (PAGE_ORDER_TO_SIZE(baser->order) / GITS_LVL1_ENTRY_SIZE)) 12783faf24eaSShanker Donthineni return false; 12793faf24eaSShanker Donthineni 12803faf24eaSShanker Donthineni table = baser->base; 12813faf24eaSShanker Donthineni 12823faf24eaSShanker Donthineni /* Allocate memory for 2nd level table */ 12833faf24eaSShanker Donthineni if (!table[idx]) { 12843faf24eaSShanker Donthineni page = alloc_pages(GFP_KERNEL | __GFP_ZERO, get_order(baser->psz)); 12853faf24eaSShanker Donthineni if (!page) 12863faf24eaSShanker Donthineni return false; 12873faf24eaSShanker Donthineni 12883faf24eaSShanker Donthineni /* Flush Lvl2 table to PoC if hw doesn't support coherency */ 12893faf24eaSShanker Donthineni if (!(baser->val & GITS_BASER_SHAREABILITY_MASK)) 12903faf24eaSShanker Donthineni __flush_dcache_area(page_address(page), baser->psz); 12913faf24eaSShanker Donthineni 12923faf24eaSShanker Donthineni table[idx] = cpu_to_le64(page_to_phys(page) | GITS_BASER_VALID); 12933faf24eaSShanker Donthineni 12943faf24eaSShanker Donthineni /* Flush Lvl1 entry to PoC if hw doesn't support coherency */ 12953faf24eaSShanker Donthineni if (!(baser->val & GITS_BASER_SHAREABILITY_MASK)) 12963faf24eaSShanker Donthineni __flush_dcache_area(table + idx, GITS_LVL1_ENTRY_SIZE); 12973faf24eaSShanker Donthineni 12983faf24eaSShanker Donthineni /* Ensure updated table contents are visible to ITS hardware */ 12993faf24eaSShanker Donthineni dsb(sy); 13003faf24eaSShanker Donthineni } 13013faf24eaSShanker Donthineni 13023faf24eaSShanker Donthineni return true; 13033faf24eaSShanker Donthineni } 13043faf24eaSShanker Donthineni 130584a6a2e7SMarc Zyngier static struct its_device *its_create_device(struct its_node *its, u32 dev_id, 130684a6a2e7SMarc Zyngier int nvecs) 130784a6a2e7SMarc Zyngier { 130884a6a2e7SMarc Zyngier struct its_device *dev; 130984a6a2e7SMarc Zyngier unsigned long *lpi_map; 13103e39e8f5SMarc Zyngier unsigned long flags; 1311591e5becSMarc Zyngier u16 *col_map = NULL; 131284a6a2e7SMarc Zyngier void *itt; 131384a6a2e7SMarc Zyngier int lpi_base; 131484a6a2e7SMarc Zyngier int nr_lpis; 1315c8481267SMarc Zyngier int nr_ites; 131684a6a2e7SMarc Zyngier int sz; 131784a6a2e7SMarc Zyngier 13183faf24eaSShanker Donthineni if (!its_alloc_device_table(its, dev_id)) 1319466b7d16SShanker Donthineni return NULL; 1320466b7d16SShanker Donthineni 132184a6a2e7SMarc Zyngier dev = kzalloc(sizeof(*dev), GFP_KERNEL); 1322c8481267SMarc Zyngier /* 1323c8481267SMarc Zyngier * At least one bit of EventID is being used, hence a minimum 1324c8481267SMarc Zyngier * of two entries. No, the architecture doesn't let you 1325c8481267SMarc Zyngier * express an ITT with a single entry. 1326c8481267SMarc Zyngier */ 132796555c47SWill Deacon nr_ites = max(2UL, roundup_pow_of_two(nvecs)); 1328c8481267SMarc Zyngier sz = nr_ites * its->ite_size; 132984a6a2e7SMarc Zyngier sz = max(sz, ITS_ITT_ALIGN) + ITS_ITT_ALIGN - 1; 13306c834125SYun Wu itt = kzalloc(sz, GFP_KERNEL); 133184a6a2e7SMarc Zyngier lpi_map = its_lpi_alloc_chunks(nvecs, &lpi_base, &nr_lpis); 1332591e5becSMarc Zyngier if (lpi_map) 1333591e5becSMarc Zyngier col_map = kzalloc(sizeof(*col_map) * nr_lpis, GFP_KERNEL); 133484a6a2e7SMarc Zyngier 1335591e5becSMarc Zyngier if (!dev || !itt || !lpi_map || !col_map) { 133684a6a2e7SMarc Zyngier kfree(dev); 133784a6a2e7SMarc Zyngier kfree(itt); 133884a6a2e7SMarc Zyngier kfree(lpi_map); 1339591e5becSMarc Zyngier kfree(col_map); 134084a6a2e7SMarc Zyngier return NULL; 134184a6a2e7SMarc Zyngier } 134284a6a2e7SMarc Zyngier 13435a9a8915SMarc Zyngier __flush_dcache_area(itt, sz); 13445a9a8915SMarc Zyngier 134584a6a2e7SMarc Zyngier dev->its = its; 134684a6a2e7SMarc Zyngier dev->itt = itt; 1347c8481267SMarc Zyngier dev->nr_ites = nr_ites; 1348591e5becSMarc Zyngier dev->event_map.lpi_map = lpi_map; 1349591e5becSMarc Zyngier dev->event_map.col_map = col_map; 1350591e5becSMarc Zyngier dev->event_map.lpi_base = lpi_base; 1351591e5becSMarc Zyngier dev->event_map.nr_lpis = nr_lpis; 135284a6a2e7SMarc Zyngier dev->device_id = dev_id; 135384a6a2e7SMarc Zyngier INIT_LIST_HEAD(&dev->entry); 135484a6a2e7SMarc Zyngier 13553e39e8f5SMarc Zyngier raw_spin_lock_irqsave(&its->lock, flags); 135684a6a2e7SMarc Zyngier list_add(&dev->entry, &its->its_device_list); 13573e39e8f5SMarc Zyngier raw_spin_unlock_irqrestore(&its->lock, flags); 135884a6a2e7SMarc Zyngier 135984a6a2e7SMarc Zyngier /* Map device to its ITT */ 136084a6a2e7SMarc Zyngier its_send_mapd(dev, 1); 136184a6a2e7SMarc Zyngier 136284a6a2e7SMarc Zyngier return dev; 136384a6a2e7SMarc Zyngier } 136484a6a2e7SMarc Zyngier 136584a6a2e7SMarc Zyngier static void its_free_device(struct its_device *its_dev) 136684a6a2e7SMarc Zyngier { 13673e39e8f5SMarc Zyngier unsigned long flags; 13683e39e8f5SMarc Zyngier 13693e39e8f5SMarc Zyngier raw_spin_lock_irqsave(&its_dev->its->lock, flags); 137084a6a2e7SMarc Zyngier list_del(&its_dev->entry); 13713e39e8f5SMarc Zyngier raw_spin_unlock_irqrestore(&its_dev->its->lock, flags); 137284a6a2e7SMarc Zyngier kfree(its_dev->itt); 137384a6a2e7SMarc Zyngier kfree(its_dev); 137484a6a2e7SMarc Zyngier } 1375b48ac83dSMarc Zyngier 1376b48ac83dSMarc Zyngier static int its_alloc_device_irq(struct its_device *dev, irq_hw_number_t *hwirq) 1377b48ac83dSMarc Zyngier { 1378b48ac83dSMarc Zyngier int idx; 1379b48ac83dSMarc Zyngier 1380591e5becSMarc Zyngier idx = find_first_zero_bit(dev->event_map.lpi_map, 1381591e5becSMarc Zyngier dev->event_map.nr_lpis); 1382591e5becSMarc Zyngier if (idx == dev->event_map.nr_lpis) 1383b48ac83dSMarc Zyngier return -ENOSPC; 1384b48ac83dSMarc Zyngier 1385591e5becSMarc Zyngier *hwirq = dev->event_map.lpi_base + idx; 1386591e5becSMarc Zyngier set_bit(idx, dev->event_map.lpi_map); 1387b48ac83dSMarc Zyngier 1388b48ac83dSMarc Zyngier return 0; 1389b48ac83dSMarc Zyngier } 1390b48ac83dSMarc Zyngier 139154456db9SMarc Zyngier static int its_msi_prepare(struct irq_domain *domain, struct device *dev, 1392b48ac83dSMarc Zyngier int nvec, msi_alloc_info_t *info) 1393b48ac83dSMarc Zyngier { 1394b48ac83dSMarc Zyngier struct its_node *its; 1395b48ac83dSMarc Zyngier struct its_device *its_dev; 139654456db9SMarc Zyngier struct msi_domain_info *msi_info; 139754456db9SMarc Zyngier u32 dev_id; 1398b48ac83dSMarc Zyngier 139954456db9SMarc Zyngier /* 140054456db9SMarc Zyngier * We ignore "dev" entierely, and rely on the dev_id that has 140154456db9SMarc Zyngier * been passed via the scratchpad. This limits this domain's 140254456db9SMarc Zyngier * usefulness to upper layers that definitely know that they 140354456db9SMarc Zyngier * are built on top of the ITS. 140454456db9SMarc Zyngier */ 140554456db9SMarc Zyngier dev_id = info->scratchpad[0].ul; 140654456db9SMarc Zyngier 140754456db9SMarc Zyngier msi_info = msi_get_domain_info(domain); 140854456db9SMarc Zyngier its = msi_info->data; 140954456db9SMarc Zyngier 1410f130420eSMarc Zyngier its_dev = its_find_device(its, dev_id); 1411e8137f4fSMarc Zyngier if (its_dev) { 1412e8137f4fSMarc Zyngier /* 1413e8137f4fSMarc Zyngier * We already have seen this ID, probably through 1414e8137f4fSMarc Zyngier * another alias (PCI bridge of some sort). No need to 1415e8137f4fSMarc Zyngier * create the device. 1416e8137f4fSMarc Zyngier */ 1417f130420eSMarc Zyngier pr_debug("Reusing ITT for devID %x\n", dev_id); 1418e8137f4fSMarc Zyngier goto out; 1419e8137f4fSMarc Zyngier } 1420b48ac83dSMarc Zyngier 1421f130420eSMarc Zyngier its_dev = its_create_device(its, dev_id, nvec); 1422b48ac83dSMarc Zyngier if (!its_dev) 1423b48ac83dSMarc Zyngier return -ENOMEM; 1424b48ac83dSMarc Zyngier 1425f130420eSMarc Zyngier pr_debug("ITT %d entries, %d bits\n", nvec, ilog2(nvec)); 1426e8137f4fSMarc Zyngier out: 1427b48ac83dSMarc Zyngier info->scratchpad[0].ptr = its_dev; 1428b48ac83dSMarc Zyngier return 0; 1429b48ac83dSMarc Zyngier } 1430b48ac83dSMarc Zyngier 143154456db9SMarc Zyngier static struct msi_domain_ops its_msi_domain_ops = { 143254456db9SMarc Zyngier .msi_prepare = its_msi_prepare, 143354456db9SMarc Zyngier }; 143454456db9SMarc Zyngier 1435b48ac83dSMarc Zyngier static int its_irq_gic_domain_alloc(struct irq_domain *domain, 1436b48ac83dSMarc Zyngier unsigned int virq, 1437b48ac83dSMarc Zyngier irq_hw_number_t hwirq) 1438b48ac83dSMarc Zyngier { 1439f833f57fSMarc Zyngier struct irq_fwspec fwspec; 1440b48ac83dSMarc Zyngier 1441f833f57fSMarc Zyngier if (irq_domain_get_of_node(domain->parent)) { 1442f833f57fSMarc Zyngier fwspec.fwnode = domain->parent->fwnode; 1443f833f57fSMarc Zyngier fwspec.param_count = 3; 1444f833f57fSMarc Zyngier fwspec.param[0] = GIC_IRQ_TYPE_LPI; 1445f833f57fSMarc Zyngier fwspec.param[1] = hwirq; 1446f833f57fSMarc Zyngier fwspec.param[2] = IRQ_TYPE_EDGE_RISING; 14473f010cf1STomasz Nowicki } else if (is_fwnode_irqchip(domain->parent->fwnode)) { 14483f010cf1STomasz Nowicki fwspec.fwnode = domain->parent->fwnode; 14493f010cf1STomasz Nowicki fwspec.param_count = 2; 14503f010cf1STomasz Nowicki fwspec.param[0] = hwirq; 14513f010cf1STomasz Nowicki fwspec.param[1] = IRQ_TYPE_EDGE_RISING; 1452f833f57fSMarc Zyngier } else { 1453f833f57fSMarc Zyngier return -EINVAL; 1454f833f57fSMarc Zyngier } 1455b48ac83dSMarc Zyngier 1456f833f57fSMarc Zyngier return irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec); 1457b48ac83dSMarc Zyngier } 1458b48ac83dSMarc Zyngier 1459b48ac83dSMarc Zyngier static int its_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, 1460b48ac83dSMarc Zyngier unsigned int nr_irqs, void *args) 1461b48ac83dSMarc Zyngier { 1462b48ac83dSMarc Zyngier msi_alloc_info_t *info = args; 1463b48ac83dSMarc Zyngier struct its_device *its_dev = info->scratchpad[0].ptr; 1464b48ac83dSMarc Zyngier irq_hw_number_t hwirq; 1465b48ac83dSMarc Zyngier int err; 1466b48ac83dSMarc Zyngier int i; 1467b48ac83dSMarc Zyngier 1468b48ac83dSMarc Zyngier for (i = 0; i < nr_irqs; i++) { 1469b48ac83dSMarc Zyngier err = its_alloc_device_irq(its_dev, &hwirq); 1470b48ac83dSMarc Zyngier if (err) 1471b48ac83dSMarc Zyngier return err; 1472b48ac83dSMarc Zyngier 1473b48ac83dSMarc Zyngier err = its_irq_gic_domain_alloc(domain, virq + i, hwirq); 1474b48ac83dSMarc Zyngier if (err) 1475b48ac83dSMarc Zyngier return err; 1476b48ac83dSMarc Zyngier 1477b48ac83dSMarc Zyngier irq_domain_set_hwirq_and_chip(domain, virq + i, 1478b48ac83dSMarc Zyngier hwirq, &its_irq_chip, its_dev); 1479f130420eSMarc Zyngier pr_debug("ID:%d pID:%d vID:%d\n", 1480591e5becSMarc Zyngier (int)(hwirq - its_dev->event_map.lpi_base), 1481591e5becSMarc Zyngier (int) hwirq, virq + i); 1482b48ac83dSMarc Zyngier } 1483b48ac83dSMarc Zyngier 1484b48ac83dSMarc Zyngier return 0; 1485b48ac83dSMarc Zyngier } 1486b48ac83dSMarc Zyngier 1487aca268dfSMarc Zyngier static void its_irq_domain_activate(struct irq_domain *domain, 1488aca268dfSMarc Zyngier struct irq_data *d) 1489aca268dfSMarc Zyngier { 1490aca268dfSMarc Zyngier struct its_device *its_dev = irq_data_get_irq_chip_data(d); 1491aca268dfSMarc Zyngier u32 event = its_get_event_id(d); 1492fbf8f40eSGanapatrao Kulkarni const struct cpumask *cpu_mask = cpu_online_mask; 1493fbf8f40eSGanapatrao Kulkarni 1494fbf8f40eSGanapatrao Kulkarni /* get the cpu_mask of local node */ 1495fbf8f40eSGanapatrao Kulkarni if (its_dev->its->numa_node >= 0) 1496fbf8f40eSGanapatrao Kulkarni cpu_mask = cpumask_of_node(its_dev->its->numa_node); 1497aca268dfSMarc Zyngier 1498591e5becSMarc Zyngier /* Bind the LPI to the first possible CPU */ 1499fbf8f40eSGanapatrao Kulkarni its_dev->event_map.col_map[event] = cpumask_first(cpu_mask); 1500591e5becSMarc Zyngier 1501aca268dfSMarc Zyngier /* Map the GIC IRQ and event to the device */ 1502aca268dfSMarc Zyngier its_send_mapvi(its_dev, d->hwirq, event); 1503aca268dfSMarc Zyngier } 1504aca268dfSMarc Zyngier 1505aca268dfSMarc Zyngier static void its_irq_domain_deactivate(struct irq_domain *domain, 1506aca268dfSMarc Zyngier struct irq_data *d) 1507aca268dfSMarc Zyngier { 1508aca268dfSMarc Zyngier struct its_device *its_dev = irq_data_get_irq_chip_data(d); 1509aca268dfSMarc Zyngier u32 event = its_get_event_id(d); 1510aca268dfSMarc Zyngier 1511aca268dfSMarc Zyngier /* Stop the delivery of interrupts */ 1512aca268dfSMarc Zyngier its_send_discard(its_dev, event); 1513aca268dfSMarc Zyngier } 1514aca268dfSMarc Zyngier 1515b48ac83dSMarc Zyngier static void its_irq_domain_free(struct irq_domain *domain, unsigned int virq, 1516b48ac83dSMarc Zyngier unsigned int nr_irqs) 1517b48ac83dSMarc Zyngier { 1518b48ac83dSMarc Zyngier struct irq_data *d = irq_domain_get_irq_data(domain, virq); 1519b48ac83dSMarc Zyngier struct its_device *its_dev = irq_data_get_irq_chip_data(d); 1520b48ac83dSMarc Zyngier int i; 1521b48ac83dSMarc Zyngier 1522b48ac83dSMarc Zyngier for (i = 0; i < nr_irqs; i++) { 1523b48ac83dSMarc Zyngier struct irq_data *data = irq_domain_get_irq_data(domain, 1524b48ac83dSMarc Zyngier virq + i); 1525aca268dfSMarc Zyngier u32 event = its_get_event_id(data); 1526b48ac83dSMarc Zyngier 1527b48ac83dSMarc Zyngier /* Mark interrupt index as unused */ 1528591e5becSMarc Zyngier clear_bit(event, its_dev->event_map.lpi_map); 1529b48ac83dSMarc Zyngier 1530b48ac83dSMarc Zyngier /* Nuke the entry in the domain */ 15312da39949SMarc Zyngier irq_domain_reset_irq_data(data); 1532b48ac83dSMarc Zyngier } 1533b48ac83dSMarc Zyngier 1534b48ac83dSMarc Zyngier /* If all interrupts have been freed, start mopping the floor */ 1535591e5becSMarc Zyngier if (bitmap_empty(its_dev->event_map.lpi_map, 1536591e5becSMarc Zyngier its_dev->event_map.nr_lpis)) { 1537591e5becSMarc Zyngier its_lpi_free(&its_dev->event_map); 1538b48ac83dSMarc Zyngier 1539b48ac83dSMarc Zyngier /* Unmap device/itt */ 1540b48ac83dSMarc Zyngier its_send_mapd(its_dev, 0); 1541b48ac83dSMarc Zyngier its_free_device(its_dev); 1542b48ac83dSMarc Zyngier } 1543b48ac83dSMarc Zyngier 1544b48ac83dSMarc Zyngier irq_domain_free_irqs_parent(domain, virq, nr_irqs); 1545b48ac83dSMarc Zyngier } 1546b48ac83dSMarc Zyngier 1547b48ac83dSMarc Zyngier static const struct irq_domain_ops its_domain_ops = { 1548b48ac83dSMarc Zyngier .alloc = its_irq_domain_alloc, 1549b48ac83dSMarc Zyngier .free = its_irq_domain_free, 1550aca268dfSMarc Zyngier .activate = its_irq_domain_activate, 1551aca268dfSMarc Zyngier .deactivate = its_irq_domain_deactivate, 1552b48ac83dSMarc Zyngier }; 15534c21f3c2SMarc Zyngier 15544559fbb3SYun Wu static int its_force_quiescent(void __iomem *base) 15554559fbb3SYun Wu { 15564559fbb3SYun Wu u32 count = 1000000; /* 1s */ 15574559fbb3SYun Wu u32 val; 15584559fbb3SYun Wu 15594559fbb3SYun Wu val = readl_relaxed(base + GITS_CTLR); 15607611da86SDavid Daney /* 15617611da86SDavid Daney * GIC architecture specification requires the ITS to be both 15627611da86SDavid Daney * disabled and quiescent for writes to GITS_BASER<n> or 15637611da86SDavid Daney * GITS_CBASER to not have UNPREDICTABLE results. 15647611da86SDavid Daney */ 15657611da86SDavid Daney if ((val & GITS_CTLR_QUIESCENT) && !(val & GITS_CTLR_ENABLE)) 15664559fbb3SYun Wu return 0; 15674559fbb3SYun Wu 15684559fbb3SYun Wu /* Disable the generation of all interrupts to this ITS */ 15694559fbb3SYun Wu val &= ~GITS_CTLR_ENABLE; 15704559fbb3SYun Wu writel_relaxed(val, base + GITS_CTLR); 15714559fbb3SYun Wu 15724559fbb3SYun Wu /* Poll GITS_CTLR and wait until ITS becomes quiescent */ 15734559fbb3SYun Wu while (1) { 15744559fbb3SYun Wu val = readl_relaxed(base + GITS_CTLR); 15754559fbb3SYun Wu if (val & GITS_CTLR_QUIESCENT) 15764559fbb3SYun Wu return 0; 15774559fbb3SYun Wu 15784559fbb3SYun Wu count--; 15794559fbb3SYun Wu if (!count) 15804559fbb3SYun Wu return -EBUSY; 15814559fbb3SYun Wu 15824559fbb3SYun Wu cpu_relax(); 15834559fbb3SYun Wu udelay(1); 15844559fbb3SYun Wu } 15854559fbb3SYun Wu } 15864559fbb3SYun Wu 158794100970SRobert Richter static void __maybe_unused its_enable_quirk_cavium_22375(void *data) 158894100970SRobert Richter { 158994100970SRobert Richter struct its_node *its = data; 159094100970SRobert Richter 159194100970SRobert Richter its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_22375; 159294100970SRobert Richter } 159394100970SRobert Richter 1594fbf8f40eSGanapatrao Kulkarni static void __maybe_unused its_enable_quirk_cavium_23144(void *data) 1595fbf8f40eSGanapatrao Kulkarni { 1596fbf8f40eSGanapatrao Kulkarni struct its_node *its = data; 1597fbf8f40eSGanapatrao Kulkarni 1598fbf8f40eSGanapatrao Kulkarni its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_23144; 1599fbf8f40eSGanapatrao Kulkarni } 1600fbf8f40eSGanapatrao Kulkarni 160167510ccaSRobert Richter static const struct gic_quirk its_quirks[] = { 160294100970SRobert Richter #ifdef CONFIG_CAVIUM_ERRATUM_22375 160394100970SRobert Richter { 160494100970SRobert Richter .desc = "ITS: Cavium errata 22375, 24313", 160594100970SRobert Richter .iidr = 0xa100034c, /* ThunderX pass 1.x */ 160694100970SRobert Richter .mask = 0xffff0fff, 160794100970SRobert Richter .init = its_enable_quirk_cavium_22375, 160894100970SRobert Richter }, 160994100970SRobert Richter #endif 1610fbf8f40eSGanapatrao Kulkarni #ifdef CONFIG_CAVIUM_ERRATUM_23144 1611fbf8f40eSGanapatrao Kulkarni { 1612fbf8f40eSGanapatrao Kulkarni .desc = "ITS: Cavium erratum 23144", 1613fbf8f40eSGanapatrao Kulkarni .iidr = 0xa100034c, /* ThunderX pass 1.x */ 1614fbf8f40eSGanapatrao Kulkarni .mask = 0xffff0fff, 1615fbf8f40eSGanapatrao Kulkarni .init = its_enable_quirk_cavium_23144, 1616fbf8f40eSGanapatrao Kulkarni }, 1617fbf8f40eSGanapatrao Kulkarni #endif 161867510ccaSRobert Richter { 161967510ccaSRobert Richter } 162067510ccaSRobert Richter }; 162167510ccaSRobert Richter 162267510ccaSRobert Richter static void its_enable_quirks(struct its_node *its) 162367510ccaSRobert Richter { 162467510ccaSRobert Richter u32 iidr = readl_relaxed(its->base + GITS_IIDR); 162567510ccaSRobert Richter 162667510ccaSRobert Richter gic_enable_quirks(iidr, its_quirks, its); 162767510ccaSRobert Richter } 162867510ccaSRobert Richter 1629db40f0a7STomasz Nowicki static int its_init_domain(struct fwnode_handle *handle, struct its_node *its) 1630d14ae5e6STomasz Nowicki { 1631d14ae5e6STomasz Nowicki struct irq_domain *inner_domain; 1632d14ae5e6STomasz Nowicki struct msi_domain_info *info; 1633d14ae5e6STomasz Nowicki 1634d14ae5e6STomasz Nowicki info = kzalloc(sizeof(*info), GFP_KERNEL); 1635d14ae5e6STomasz Nowicki if (!info) 1636d14ae5e6STomasz Nowicki return -ENOMEM; 1637d14ae5e6STomasz Nowicki 1638db40f0a7STomasz Nowicki inner_domain = irq_domain_create_tree(handle, &its_domain_ops, its); 1639d14ae5e6STomasz Nowicki if (!inner_domain) { 1640d14ae5e6STomasz Nowicki kfree(info); 1641d14ae5e6STomasz Nowicki return -ENOMEM; 1642d14ae5e6STomasz Nowicki } 1643d14ae5e6STomasz Nowicki 1644db40f0a7STomasz Nowicki inner_domain->parent = its_parent; 1645d14ae5e6STomasz Nowicki inner_domain->bus_token = DOMAIN_BUS_NEXUS; 1646d14ae5e6STomasz Nowicki info->ops = &its_msi_domain_ops; 1647d14ae5e6STomasz Nowicki info->data = its; 1648d14ae5e6STomasz Nowicki inner_domain->host_data = info; 1649d14ae5e6STomasz Nowicki 1650d14ae5e6STomasz Nowicki return 0; 1651d14ae5e6STomasz Nowicki } 1652d14ae5e6STomasz Nowicki 1653db40f0a7STomasz Nowicki static int __init its_probe_one(struct resource *res, 1654db40f0a7STomasz Nowicki struct fwnode_handle *handle, int numa_node) 16554c21f3c2SMarc Zyngier { 16564c21f3c2SMarc Zyngier struct its_node *its; 16574c21f3c2SMarc Zyngier void __iomem *its_base; 16584c21f3c2SMarc Zyngier u32 val; 16594c21f3c2SMarc Zyngier u64 baser, tmp; 16604c21f3c2SMarc Zyngier int err; 16614c21f3c2SMarc Zyngier 1662db40f0a7STomasz Nowicki its_base = ioremap(res->start, resource_size(res)); 16634c21f3c2SMarc Zyngier if (!its_base) { 1664db40f0a7STomasz Nowicki pr_warn("ITS@%pa: Unable to map ITS registers\n", &res->start); 16654c21f3c2SMarc Zyngier return -ENOMEM; 16664c21f3c2SMarc Zyngier } 16674c21f3c2SMarc Zyngier 16684c21f3c2SMarc Zyngier val = readl_relaxed(its_base + GITS_PIDR2) & GIC_PIDR2_ARCH_MASK; 16694c21f3c2SMarc Zyngier if (val != 0x30 && val != 0x40) { 1670db40f0a7STomasz Nowicki pr_warn("ITS@%pa: No ITS detected, giving up\n", &res->start); 16714c21f3c2SMarc Zyngier err = -ENODEV; 16724c21f3c2SMarc Zyngier goto out_unmap; 16734c21f3c2SMarc Zyngier } 16744c21f3c2SMarc Zyngier 16754559fbb3SYun Wu err = its_force_quiescent(its_base); 16764559fbb3SYun Wu if (err) { 1677db40f0a7STomasz Nowicki pr_warn("ITS@%pa: Failed to quiesce, giving up\n", &res->start); 16784559fbb3SYun Wu goto out_unmap; 16794559fbb3SYun Wu } 16804559fbb3SYun Wu 1681db40f0a7STomasz Nowicki pr_info("ITS %pR\n", res); 16824c21f3c2SMarc Zyngier 16834c21f3c2SMarc Zyngier its = kzalloc(sizeof(*its), GFP_KERNEL); 16844c21f3c2SMarc Zyngier if (!its) { 16854c21f3c2SMarc Zyngier err = -ENOMEM; 16864c21f3c2SMarc Zyngier goto out_unmap; 16874c21f3c2SMarc Zyngier } 16884c21f3c2SMarc Zyngier 16894c21f3c2SMarc Zyngier raw_spin_lock_init(&its->lock); 16904c21f3c2SMarc Zyngier INIT_LIST_HEAD(&its->entry); 16914c21f3c2SMarc Zyngier INIT_LIST_HEAD(&its->its_device_list); 16924c21f3c2SMarc Zyngier its->base = its_base; 1693db40f0a7STomasz Nowicki its->phys_base = res->start; 1694589ce5f4SMarc Zyngier its->ite_size = ((gic_read_typer(its_base + GITS_TYPER) >> 4) & 0xf) + 1; 1695db40f0a7STomasz Nowicki its->numa_node = numa_node; 16964c21f3c2SMarc Zyngier 16974c21f3c2SMarc Zyngier its->cmd_base = kzalloc(ITS_CMD_QUEUE_SZ, GFP_KERNEL); 16984c21f3c2SMarc Zyngier if (!its->cmd_base) { 16994c21f3c2SMarc Zyngier err = -ENOMEM; 17004c21f3c2SMarc Zyngier goto out_free_its; 17014c21f3c2SMarc Zyngier } 17024c21f3c2SMarc Zyngier its->cmd_write = its->cmd_base; 17034c21f3c2SMarc Zyngier 170467510ccaSRobert Richter its_enable_quirks(its); 170567510ccaSRobert Richter 17060e0b0f69SShanker Donthineni err = its_alloc_tables(its); 17074c21f3c2SMarc Zyngier if (err) 17084c21f3c2SMarc Zyngier goto out_free_cmd; 17094c21f3c2SMarc Zyngier 17104c21f3c2SMarc Zyngier err = its_alloc_collections(its); 17114c21f3c2SMarc Zyngier if (err) 17124c21f3c2SMarc Zyngier goto out_free_tables; 17134c21f3c2SMarc Zyngier 17144c21f3c2SMarc Zyngier baser = (virt_to_phys(its->cmd_base) | 17154c21f3c2SMarc Zyngier GITS_CBASER_WaWb | 17164c21f3c2SMarc Zyngier GITS_CBASER_InnerShareable | 17174c21f3c2SMarc Zyngier (ITS_CMD_QUEUE_SZ / SZ_4K - 1) | 17184c21f3c2SMarc Zyngier GITS_CBASER_VALID); 17194c21f3c2SMarc Zyngier 17204c21f3c2SMarc Zyngier writeq_relaxed(baser, its->base + GITS_CBASER); 17214c21f3c2SMarc Zyngier tmp = readq_relaxed(its->base + GITS_CBASER); 17224c21f3c2SMarc Zyngier 17234ad3e363SMarc Zyngier if ((tmp ^ baser) & GITS_CBASER_SHAREABILITY_MASK) { 1724241a386cSMarc Zyngier if (!(tmp & GITS_CBASER_SHAREABILITY_MASK)) { 1725241a386cSMarc Zyngier /* 1726241a386cSMarc Zyngier * The HW reports non-shareable, we must 1727241a386cSMarc Zyngier * remove the cacheability attributes as 1728241a386cSMarc Zyngier * well. 1729241a386cSMarc Zyngier */ 1730241a386cSMarc Zyngier baser &= ~(GITS_CBASER_SHAREABILITY_MASK | 1731241a386cSMarc Zyngier GITS_CBASER_CACHEABILITY_MASK); 1732241a386cSMarc Zyngier baser |= GITS_CBASER_nC; 1733241a386cSMarc Zyngier writeq_relaxed(baser, its->base + GITS_CBASER); 1734241a386cSMarc Zyngier } 17354c21f3c2SMarc Zyngier pr_info("ITS: using cache flushing for cmd queue\n"); 17364c21f3c2SMarc Zyngier its->flags |= ITS_FLAGS_CMDQ_NEEDS_FLUSHING; 17374c21f3c2SMarc Zyngier } 17384c21f3c2SMarc Zyngier 1739241a386cSMarc Zyngier writeq_relaxed(0, its->base + GITS_CWRITER); 1740241a386cSMarc Zyngier writel_relaxed(GITS_CTLR_ENABLE, its->base + GITS_CTLR); 1741241a386cSMarc Zyngier 1742db40f0a7STomasz Nowicki err = its_init_domain(handle, its); 1743d14ae5e6STomasz Nowicki if (err) 174454456db9SMarc Zyngier goto out_free_tables; 17454c21f3c2SMarc Zyngier 17464c21f3c2SMarc Zyngier spin_lock(&its_lock); 17474c21f3c2SMarc Zyngier list_add(&its->entry, &its_nodes); 17484c21f3c2SMarc Zyngier spin_unlock(&its_lock); 17494c21f3c2SMarc Zyngier 17504c21f3c2SMarc Zyngier return 0; 17514c21f3c2SMarc Zyngier 17524c21f3c2SMarc Zyngier out_free_tables: 17534c21f3c2SMarc Zyngier its_free_tables(its); 17544c21f3c2SMarc Zyngier out_free_cmd: 17554c21f3c2SMarc Zyngier kfree(its->cmd_base); 17564c21f3c2SMarc Zyngier out_free_its: 17574c21f3c2SMarc Zyngier kfree(its); 17584c21f3c2SMarc Zyngier out_unmap: 17594c21f3c2SMarc Zyngier iounmap(its_base); 1760db40f0a7STomasz Nowicki pr_err("ITS@%pa: failed probing (%d)\n", &res->start, err); 17614c21f3c2SMarc Zyngier return err; 17624c21f3c2SMarc Zyngier } 17634c21f3c2SMarc Zyngier 17644c21f3c2SMarc Zyngier static bool gic_rdists_supports_plpis(void) 17654c21f3c2SMarc Zyngier { 1766589ce5f4SMarc Zyngier return !!(gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER) & GICR_TYPER_PLPIS); 17674c21f3c2SMarc Zyngier } 17684c21f3c2SMarc Zyngier 17694c21f3c2SMarc Zyngier int its_cpu_init(void) 17704c21f3c2SMarc Zyngier { 177116acae72SVladimir Murzin if (!list_empty(&its_nodes)) { 17724c21f3c2SMarc Zyngier if (!gic_rdists_supports_plpis()) { 17734c21f3c2SMarc Zyngier pr_info("CPU%d: LPIs not supported\n", smp_processor_id()); 17744c21f3c2SMarc Zyngier return -ENXIO; 17754c21f3c2SMarc Zyngier } 17764c21f3c2SMarc Zyngier its_cpu_init_lpis(); 17774c21f3c2SMarc Zyngier its_cpu_init_collection(); 17784c21f3c2SMarc Zyngier } 17794c21f3c2SMarc Zyngier 17804c21f3c2SMarc Zyngier return 0; 17814c21f3c2SMarc Zyngier } 17824c21f3c2SMarc Zyngier 17834c21f3c2SMarc Zyngier static struct of_device_id its_device_id[] = { 17844c21f3c2SMarc Zyngier { .compatible = "arm,gic-v3-its", }, 17854c21f3c2SMarc Zyngier {}, 17864c21f3c2SMarc Zyngier }; 17874c21f3c2SMarc Zyngier 1788db40f0a7STomasz Nowicki static int __init its_of_probe(struct device_node *node) 17894c21f3c2SMarc Zyngier { 17904c21f3c2SMarc Zyngier struct device_node *np; 1791db40f0a7STomasz Nowicki struct resource res; 17924c21f3c2SMarc Zyngier 17934c21f3c2SMarc Zyngier for (np = of_find_matching_node(node, its_device_id); np; 17944c21f3c2SMarc Zyngier np = of_find_matching_node(np, its_device_id)) { 1795d14ae5e6STomasz Nowicki if (!of_property_read_bool(np, "msi-controller")) { 1796d14ae5e6STomasz Nowicki pr_warn("%s: no msi-controller property, ITS ignored\n", 1797d14ae5e6STomasz Nowicki np->full_name); 1798d14ae5e6STomasz Nowicki continue; 1799d14ae5e6STomasz Nowicki } 1800d14ae5e6STomasz Nowicki 1801db40f0a7STomasz Nowicki if (of_address_to_resource(np, 0, &res)) { 1802db40f0a7STomasz Nowicki pr_warn("%s: no regs?\n", np->full_name); 1803db40f0a7STomasz Nowicki continue; 18044c21f3c2SMarc Zyngier } 18054c21f3c2SMarc Zyngier 1806db40f0a7STomasz Nowicki its_probe_one(&res, &np->fwnode, of_node_to_nid(np)); 1807db40f0a7STomasz Nowicki } 1808db40f0a7STomasz Nowicki return 0; 1809db40f0a7STomasz Nowicki } 1810db40f0a7STomasz Nowicki 18113f010cf1STomasz Nowicki #ifdef CONFIG_ACPI 18123f010cf1STomasz Nowicki 18133f010cf1STomasz Nowicki #define ACPI_GICV3_ITS_MEM_SIZE (SZ_128K) 18143f010cf1STomasz Nowicki 18153f010cf1STomasz Nowicki static int __init gic_acpi_parse_madt_its(struct acpi_subtable_header *header, 18163f010cf1STomasz Nowicki const unsigned long end) 18173f010cf1STomasz Nowicki { 18183f010cf1STomasz Nowicki struct acpi_madt_generic_translator *its_entry; 18193f010cf1STomasz Nowicki struct fwnode_handle *dom_handle; 18203f010cf1STomasz Nowicki struct resource res; 18213f010cf1STomasz Nowicki int err; 18223f010cf1STomasz Nowicki 18233f010cf1STomasz Nowicki its_entry = (struct acpi_madt_generic_translator *)header; 18243f010cf1STomasz Nowicki memset(&res, 0, sizeof(res)); 18253f010cf1STomasz Nowicki res.start = its_entry->base_address; 18263f010cf1STomasz Nowicki res.end = its_entry->base_address + ACPI_GICV3_ITS_MEM_SIZE - 1; 18273f010cf1STomasz Nowicki res.flags = IORESOURCE_MEM; 18283f010cf1STomasz Nowicki 18293f010cf1STomasz Nowicki dom_handle = irq_domain_alloc_fwnode((void *)its_entry->base_address); 18303f010cf1STomasz Nowicki if (!dom_handle) { 18313f010cf1STomasz Nowicki pr_err("ITS@%pa: Unable to allocate GICv3 ITS domain token\n", 18323f010cf1STomasz Nowicki &res.start); 18333f010cf1STomasz Nowicki return -ENOMEM; 18343f010cf1STomasz Nowicki } 18353f010cf1STomasz Nowicki 18363f010cf1STomasz Nowicki err = iort_register_domain_token(its_entry->translation_id, dom_handle); 18373f010cf1STomasz Nowicki if (err) { 18383f010cf1STomasz Nowicki pr_err("ITS@%pa: Unable to register GICv3 ITS domain token (ITS ID %d) to IORT\n", 18393f010cf1STomasz Nowicki &res.start, its_entry->translation_id); 18403f010cf1STomasz Nowicki goto dom_err; 18413f010cf1STomasz Nowicki } 18423f010cf1STomasz Nowicki 18433f010cf1STomasz Nowicki err = its_probe_one(&res, dom_handle, NUMA_NO_NODE); 18443f010cf1STomasz Nowicki if (!err) 18453f010cf1STomasz Nowicki return 0; 18463f010cf1STomasz Nowicki 18473f010cf1STomasz Nowicki iort_deregister_domain_token(its_entry->translation_id); 18483f010cf1STomasz Nowicki dom_err: 18493f010cf1STomasz Nowicki irq_domain_free_fwnode(dom_handle); 18503f010cf1STomasz Nowicki return err; 18513f010cf1STomasz Nowicki } 18523f010cf1STomasz Nowicki 18533f010cf1STomasz Nowicki static void __init its_acpi_probe(void) 18543f010cf1STomasz Nowicki { 18553f010cf1STomasz Nowicki acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_TRANSLATOR, 18563f010cf1STomasz Nowicki gic_acpi_parse_madt_its, 0); 18573f010cf1STomasz Nowicki } 18583f010cf1STomasz Nowicki #else 18593f010cf1STomasz Nowicki static void __init its_acpi_probe(void) { } 18603f010cf1STomasz Nowicki #endif 18613f010cf1STomasz Nowicki 1862db40f0a7STomasz Nowicki int __init its_init(struct fwnode_handle *handle, struct rdists *rdists, 1863db40f0a7STomasz Nowicki struct irq_domain *parent_domain) 1864db40f0a7STomasz Nowicki { 1865db40f0a7STomasz Nowicki struct device_node *of_node; 1866db40f0a7STomasz Nowicki 1867db40f0a7STomasz Nowicki its_parent = parent_domain; 1868db40f0a7STomasz Nowicki of_node = to_of_node(handle); 1869db40f0a7STomasz Nowicki if (of_node) 1870db40f0a7STomasz Nowicki its_of_probe(of_node); 1871db40f0a7STomasz Nowicki else 18723f010cf1STomasz Nowicki its_acpi_probe(); 1873db40f0a7STomasz Nowicki 18744c21f3c2SMarc Zyngier if (list_empty(&its_nodes)) { 18754c21f3c2SMarc Zyngier pr_warn("ITS: No ITS available, not enabling LPIs\n"); 18764c21f3c2SMarc Zyngier return -ENXIO; 18774c21f3c2SMarc Zyngier } 18784c21f3c2SMarc Zyngier 18794c21f3c2SMarc Zyngier gic_rdists = rdists; 18804c21f3c2SMarc Zyngier its_alloc_lpi_tables(); 18814c21f3c2SMarc Zyngier its_lpi_init(rdists->id_bits); 18824c21f3c2SMarc Zyngier 18834c21f3c2SMarc Zyngier return 0; 18844c21f3c2SMarc Zyngier } 1885