1 /* 2 * Copyright (C) 2002 ARM Limited, All Rights Reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 17 #include <linux/interrupt.h> 18 #include <linux/io.h> 19 #include <linux/irq.h> 20 #include <linux/irqchip/arm-gic.h> 21 22 #include "irq-gic-common.h" 23 24 static DEFINE_RAW_SPINLOCK(irq_controller_lock); 25 26 static const struct gic_kvm_info *gic_kvm_info; 27 28 const struct gic_kvm_info *gic_get_kvm_info(void) 29 { 30 return gic_kvm_info; 31 } 32 33 void gic_set_kvm_info(const struct gic_kvm_info *info) 34 { 35 BUG_ON(gic_kvm_info != NULL); 36 gic_kvm_info = info; 37 } 38 39 void gic_enable_of_quirks(const struct device_node *np, 40 const struct gic_quirk *quirks, void *data) 41 { 42 for (; quirks->desc; quirks++) { 43 if (!of_device_is_compatible(np, quirks->compatible)) 44 continue; 45 if (quirks->init(data)) 46 pr_info("GIC: enabling workaround for %s\n", 47 quirks->desc); 48 } 49 } 50 51 void gic_enable_quirks(u32 iidr, const struct gic_quirk *quirks, 52 void *data) 53 { 54 for (; quirks->desc; quirks++) { 55 if (quirks->iidr != (quirks->mask & iidr)) 56 continue; 57 if (quirks->init(data)) 58 pr_info("GIC: enabling workaround for %s\n", 59 quirks->desc); 60 } 61 } 62 63 int gic_configure_irq(unsigned int irq, unsigned int type, 64 void __iomem *base, void (*sync_access)(void)) 65 { 66 u32 confmask = 0x2 << ((irq % 16) * 2); 67 u32 confoff = (irq / 16) * 4; 68 u32 val, oldval; 69 int ret = 0; 70 unsigned long flags; 71 72 /* 73 * Read current configuration register, and insert the config 74 * for "irq", depending on "type". 75 */ 76 raw_spin_lock_irqsave(&irq_controller_lock, flags); 77 val = oldval = readl_relaxed(base + GIC_DIST_CONFIG + confoff); 78 if (type & IRQ_TYPE_LEVEL_MASK) 79 val &= ~confmask; 80 else if (type & IRQ_TYPE_EDGE_BOTH) 81 val |= confmask; 82 83 /* If the current configuration is the same, then we are done */ 84 if (val == oldval) { 85 raw_spin_unlock_irqrestore(&irq_controller_lock, flags); 86 return 0; 87 } 88 89 /* 90 * Write back the new configuration, and possibly re-enable 91 * the interrupt. If we fail to write a new configuration for 92 * an SPI then WARN and return an error. If we fail to write the 93 * configuration for a PPI this is most likely because the GIC 94 * does not allow us to set the configuration or we are in a 95 * non-secure mode, and hence it may not be catastrophic. 96 */ 97 writel_relaxed(val, base + GIC_DIST_CONFIG + confoff); 98 if (readl_relaxed(base + GIC_DIST_CONFIG + confoff) != val) { 99 if (WARN_ON(irq >= 32)) 100 ret = -EINVAL; 101 else 102 pr_warn("GIC: PPI%d is secure or misconfigured\n", 103 irq - 16); 104 } 105 raw_spin_unlock_irqrestore(&irq_controller_lock, flags); 106 107 if (sync_access) 108 sync_access(); 109 110 return ret; 111 } 112 113 void gic_dist_config(void __iomem *base, int gic_irqs, 114 void (*sync_access)(void)) 115 { 116 unsigned int i; 117 118 /* 119 * Set all global interrupts to be level triggered, active low. 120 */ 121 for (i = 32; i < gic_irqs; i += 16) 122 writel_relaxed(GICD_INT_ACTLOW_LVLTRIG, 123 base + GIC_DIST_CONFIG + i / 4); 124 125 /* 126 * Set priority on all global interrupts. 127 */ 128 for (i = 32; i < gic_irqs; i += 4) 129 writel_relaxed(GICD_INT_DEF_PRI_X4, base + GIC_DIST_PRI + i); 130 131 /* 132 * Deactivate and disable all SPIs. Leave the PPI and SGIs 133 * alone as they are in the redistributor registers on GICv3. 134 */ 135 for (i = 32; i < gic_irqs; i += 32) { 136 writel_relaxed(GICD_INT_EN_CLR_X32, 137 base + GIC_DIST_ACTIVE_CLEAR + i / 8); 138 writel_relaxed(GICD_INT_EN_CLR_X32, 139 base + GIC_DIST_ENABLE_CLEAR + i / 8); 140 } 141 142 if (sync_access) 143 sync_access(); 144 } 145 146 void gic_cpu_config(void __iomem *base, void (*sync_access)(void)) 147 { 148 int i; 149 150 /* 151 * Deal with the banked PPI and SGI interrupts - disable all 152 * PPI interrupts, ensure all SGI interrupts are enabled. 153 * Make sure everything is deactivated. 154 */ 155 writel_relaxed(GICD_INT_EN_CLR_X32, base + GIC_DIST_ACTIVE_CLEAR); 156 writel_relaxed(GICD_INT_EN_CLR_PPI, base + GIC_DIST_ENABLE_CLEAR); 157 writel_relaxed(GICD_INT_EN_SET_SGI, base + GIC_DIST_ENABLE_SET); 158 159 /* 160 * Set priority on PPI and SGI interrupts 161 */ 162 for (i = 0; i < 32; i += 4) 163 writel_relaxed(GICD_INT_DEF_PRI_X4, 164 base + GIC_DIST_PRI + i * 4 / 4); 165 166 if (sync_access) 167 sync_access(); 168 } 169