1edff1b48SGuo Ren // SPDX-License-Identifier: GPL-2.0 2edff1b48SGuo Ren // Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd. 3edff1b48SGuo Ren 4edff1b48SGuo Ren #include <linux/kernel.h> 5edff1b48SGuo Ren #include <linux/init.h> 6edff1b48SGuo Ren #include <linux/of.h> 7edff1b48SGuo Ren #include <linux/of_address.h> 8edff1b48SGuo Ren #include <linux/module.h> 9edff1b48SGuo Ren #include <linux/irqdomain.h> 10edff1b48SGuo Ren #include <linux/irqchip.h> 11edff1b48SGuo Ren #include <linux/irq.h> 12edff1b48SGuo Ren #include <linux/interrupt.h> 13edff1b48SGuo Ren #include <linux/io.h> 14edff1b48SGuo Ren #include <asm/irq.h> 15edff1b48SGuo Ren 16edff1b48SGuo Ren #define INTC_IRQS 64 17edff1b48SGuo Ren 18edff1b48SGuo Ren #define CK_INTC_ICR 0x00 19edff1b48SGuo Ren #define CK_INTC_PEN31_00 0x14 20edff1b48SGuo Ren #define CK_INTC_PEN63_32 0x2c 21edff1b48SGuo Ren #define CK_INTC_NEN31_00 0x10 22edff1b48SGuo Ren #define CK_INTC_NEN63_32 0x28 23edff1b48SGuo Ren #define CK_INTC_SOURCE 0x40 24edff1b48SGuo Ren #define CK_INTC_DUAL_BASE 0x100 25edff1b48SGuo Ren 26edff1b48SGuo Ren #define GX_INTC_PEN31_00 0x00 27edff1b48SGuo Ren #define GX_INTC_PEN63_32 0x04 28edff1b48SGuo Ren #define GX_INTC_NEN31_00 0x40 29edff1b48SGuo Ren #define GX_INTC_NEN63_32 0x44 30edff1b48SGuo Ren #define GX_INTC_NMASK31_00 0x50 31edff1b48SGuo Ren #define GX_INTC_NMASK63_32 0x54 32edff1b48SGuo Ren #define GX_INTC_SOURCE 0x60 33edff1b48SGuo Ren 34edff1b48SGuo Ren static void __iomem *reg_base; 35edff1b48SGuo Ren static struct irq_domain *root_domain; 36edff1b48SGuo Ren 37edff1b48SGuo Ren static int nr_irq = INTC_IRQS; 38edff1b48SGuo Ren 39edff1b48SGuo Ren /* 40edff1b48SGuo Ren * When controller support pulse signal, the PEN_reg will hold on signal 41edff1b48SGuo Ren * without software trigger. 42edff1b48SGuo Ren * 43edff1b48SGuo Ren * So, to support pulse signal we need to clear IFR_reg and the address of 44edff1b48SGuo Ren * IFR_offset is NEN_offset - 8. 45edff1b48SGuo Ren */ 46edff1b48SGuo Ren static void irq_ck_mask_set_bit(struct irq_data *d) 47edff1b48SGuo Ren { 48edff1b48SGuo Ren struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 49edff1b48SGuo Ren struct irq_chip_type *ct = irq_data_get_chip_type(d); 50edff1b48SGuo Ren unsigned long ifr = ct->regs.mask - 8; 51edff1b48SGuo Ren u32 mask = d->mask; 52edff1b48SGuo Ren 53edff1b48SGuo Ren irq_gc_lock(gc); 54edff1b48SGuo Ren *ct->mask_cache |= mask; 55edff1b48SGuo Ren irq_reg_writel(gc, *ct->mask_cache, ct->regs.mask); 56edff1b48SGuo Ren irq_reg_writel(gc, irq_reg_readl(gc, ifr) & ~mask, ifr); 57edff1b48SGuo Ren irq_gc_unlock(gc); 58edff1b48SGuo Ren } 59edff1b48SGuo Ren 60edff1b48SGuo Ren static void __init ck_set_gc(struct device_node *node, void __iomem *reg_base, 61edff1b48SGuo Ren u32 mask_reg, u32 irq_base) 62edff1b48SGuo Ren { 63edff1b48SGuo Ren struct irq_chip_generic *gc; 64edff1b48SGuo Ren 65edff1b48SGuo Ren gc = irq_get_domain_generic_chip(root_domain, irq_base); 66edff1b48SGuo Ren gc->reg_base = reg_base; 67edff1b48SGuo Ren gc->chip_types[0].regs.mask = mask_reg; 68edff1b48SGuo Ren gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit; 69edff1b48SGuo Ren gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit; 70edff1b48SGuo Ren 71edff1b48SGuo Ren if (of_find_property(node, "csky,support-pulse-signal", NULL)) 72edff1b48SGuo Ren gc->chip_types[0].chip.irq_unmask = irq_ck_mask_set_bit; 73edff1b48SGuo Ren } 74edff1b48SGuo Ren 75edff1b48SGuo Ren static inline u32 build_channel_val(u32 idx, u32 magic) 76edff1b48SGuo Ren { 77edff1b48SGuo Ren u32 res; 78edff1b48SGuo Ren 79edff1b48SGuo Ren /* 80edff1b48SGuo Ren * Set the same index for each channel 81edff1b48SGuo Ren */ 82edff1b48SGuo Ren res = idx | (idx << 8) | (idx << 16) | (idx << 24); 83edff1b48SGuo Ren 84edff1b48SGuo Ren /* 85edff1b48SGuo Ren * Set the channel magic number in descending order. 86edff1b48SGuo Ren * The magic is 0x00010203 for ck-intc 87edff1b48SGuo Ren * The magic is 0x03020100 for gx6605s-intc 88edff1b48SGuo Ren */ 89edff1b48SGuo Ren return res | magic; 90edff1b48SGuo Ren } 91edff1b48SGuo Ren 92edff1b48SGuo Ren static inline void setup_irq_channel(u32 magic, void __iomem *reg_addr) 93edff1b48SGuo Ren { 94edff1b48SGuo Ren u32 i; 95edff1b48SGuo Ren 96edff1b48SGuo Ren /* Setup 64 channel slots */ 97edff1b48SGuo Ren for (i = 0; i < INTC_IRQS; i += 4) 9856752b21SGuo Ren writel(build_channel_val(i, magic), reg_addr + i); 99edff1b48SGuo Ren } 100edff1b48SGuo Ren 101edff1b48SGuo Ren static int __init 102edff1b48SGuo Ren ck_intc_init_comm(struct device_node *node, struct device_node *parent) 103edff1b48SGuo Ren { 104edff1b48SGuo Ren int ret; 105edff1b48SGuo Ren 106edff1b48SGuo Ren if (parent) { 107edff1b48SGuo Ren pr_err("C-SKY Intc not a root irq controller\n"); 108edff1b48SGuo Ren return -EINVAL; 109edff1b48SGuo Ren } 110edff1b48SGuo Ren 111edff1b48SGuo Ren reg_base = of_iomap(node, 0); 112edff1b48SGuo Ren if (!reg_base) { 113edff1b48SGuo Ren pr_err("C-SKY Intc unable to map: %p.\n", node); 114edff1b48SGuo Ren return -EINVAL; 115edff1b48SGuo Ren } 116edff1b48SGuo Ren 117edff1b48SGuo Ren root_domain = irq_domain_add_linear(node, nr_irq, 118edff1b48SGuo Ren &irq_generic_chip_ops, NULL); 119edff1b48SGuo Ren if (!root_domain) { 120edff1b48SGuo Ren pr_err("C-SKY Intc irq_domain_add failed.\n"); 121edff1b48SGuo Ren return -ENOMEM; 122edff1b48SGuo Ren } 123edff1b48SGuo Ren 124edff1b48SGuo Ren ret = irq_alloc_domain_generic_chips(root_domain, 32, 1, 125edff1b48SGuo Ren "csky_intc", handle_level_irq, 126edff1b48SGuo Ren IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN, 0, 0); 127edff1b48SGuo Ren if (ret) { 128edff1b48SGuo Ren pr_err("C-SKY Intc irq_alloc_gc failed.\n"); 129edff1b48SGuo Ren return -ENOMEM; 130edff1b48SGuo Ren } 131edff1b48SGuo Ren 132edff1b48SGuo Ren return 0; 133edff1b48SGuo Ren } 134edff1b48SGuo Ren 135edff1b48SGuo Ren static inline bool handle_irq_perbit(struct pt_regs *regs, u32 hwirq, 136edff1b48SGuo Ren u32 irq_base) 137edff1b48SGuo Ren { 138edff1b48SGuo Ren if (hwirq == 0) 139edff1b48SGuo Ren return 0; 140edff1b48SGuo Ren 141*0953fb26SMark Rutland generic_handle_domain_irq(root_domain, irq_base + __fls(hwirq)); 142edff1b48SGuo Ren 143edff1b48SGuo Ren return 1; 144edff1b48SGuo Ren } 145edff1b48SGuo Ren 146edff1b48SGuo Ren /* gx6605s 64 irqs interrupt controller */ 147edff1b48SGuo Ren static void gx_irq_handler(struct pt_regs *regs) 148edff1b48SGuo Ren { 149edff1b48SGuo Ren bool ret; 150edff1b48SGuo Ren 15156752b21SGuo Ren retry: 152edff1b48SGuo Ren ret = handle_irq_perbit(regs, 15356752b21SGuo Ren readl(reg_base + GX_INTC_PEN63_32), 32); 15456752b21SGuo Ren if (ret) 15556752b21SGuo Ren goto retry; 15656752b21SGuo Ren 15756752b21SGuo Ren ret = handle_irq_perbit(regs, 15856752b21SGuo Ren readl(reg_base + GX_INTC_PEN31_00), 0); 15956752b21SGuo Ren if (ret) 16056752b21SGuo Ren goto retry; 161edff1b48SGuo Ren } 162edff1b48SGuo Ren 163edff1b48SGuo Ren static int __init 164edff1b48SGuo Ren gx_intc_init(struct device_node *node, struct device_node *parent) 165edff1b48SGuo Ren { 166edff1b48SGuo Ren int ret; 167edff1b48SGuo Ren 168edff1b48SGuo Ren ret = ck_intc_init_comm(node, parent); 169edff1b48SGuo Ren if (ret) 170edff1b48SGuo Ren return ret; 171edff1b48SGuo Ren 172edff1b48SGuo Ren /* 173edff1b48SGuo Ren * Initial enable reg to disable all interrupts 174edff1b48SGuo Ren */ 17556752b21SGuo Ren writel(0x0, reg_base + GX_INTC_NEN31_00); 17656752b21SGuo Ren writel(0x0, reg_base + GX_INTC_NEN63_32); 177edff1b48SGuo Ren 178edff1b48SGuo Ren /* 179a359f757SIngo Molnar * Initial mask reg with all unmasked, because we only use enable reg 180edff1b48SGuo Ren */ 18156752b21SGuo Ren writel(0x0, reg_base + GX_INTC_NMASK31_00); 18256752b21SGuo Ren writel(0x0, reg_base + GX_INTC_NMASK63_32); 183edff1b48SGuo Ren 184edff1b48SGuo Ren setup_irq_channel(0x03020100, reg_base + GX_INTC_SOURCE); 185edff1b48SGuo Ren 186edff1b48SGuo Ren ck_set_gc(node, reg_base, GX_INTC_NEN31_00, 0); 187edff1b48SGuo Ren ck_set_gc(node, reg_base, GX_INTC_NEN63_32, 32); 188edff1b48SGuo Ren 189edff1b48SGuo Ren set_handle_irq(gx_irq_handler); 190edff1b48SGuo Ren 191edff1b48SGuo Ren return 0; 192edff1b48SGuo Ren } 193edff1b48SGuo Ren IRQCHIP_DECLARE(csky_gx6605s_intc, "csky,gx6605s-intc", gx_intc_init); 194edff1b48SGuo Ren 195edff1b48SGuo Ren /* 196edff1b48SGuo Ren * C-SKY simple 64 irqs interrupt controller, dual-together could support 128 197edff1b48SGuo Ren * irqs. 198edff1b48SGuo Ren */ 199edff1b48SGuo Ren static void ck_irq_handler(struct pt_regs *regs) 200edff1b48SGuo Ren { 201edff1b48SGuo Ren bool ret; 202edff1b48SGuo Ren void __iomem *reg_pen_lo = reg_base + CK_INTC_PEN31_00; 203edff1b48SGuo Ren void __iomem *reg_pen_hi = reg_base + CK_INTC_PEN63_32; 204edff1b48SGuo Ren 20556752b21SGuo Ren retry: 20656752b21SGuo Ren /* handle 0 - 63 irqs */ 20756752b21SGuo Ren ret = handle_irq_perbit(regs, readl(reg_pen_hi), 32); 20856752b21SGuo Ren if (ret) 20956752b21SGuo Ren goto retry; 21056752b21SGuo Ren 21156752b21SGuo Ren ret = handle_irq_perbit(regs, readl(reg_pen_lo), 0); 21256752b21SGuo Ren if (ret) 21356752b21SGuo Ren goto retry; 214edff1b48SGuo Ren 215edff1b48SGuo Ren if (nr_irq == INTC_IRQS) 21656752b21SGuo Ren return; 217edff1b48SGuo Ren 218edff1b48SGuo Ren /* handle 64 - 127 irqs */ 21956752b21SGuo Ren ret = handle_irq_perbit(regs, 22056752b21SGuo Ren readl(reg_pen_hi + CK_INTC_DUAL_BASE), 96); 22156752b21SGuo Ren if (ret) 22256752b21SGuo Ren goto retry; 22356752b21SGuo Ren 22456752b21SGuo Ren ret = handle_irq_perbit(regs, 22556752b21SGuo Ren readl(reg_pen_lo + CK_INTC_DUAL_BASE), 64); 22656752b21SGuo Ren if (ret) 22756752b21SGuo Ren goto retry; 228edff1b48SGuo Ren } 229edff1b48SGuo Ren 230edff1b48SGuo Ren static int __init 231edff1b48SGuo Ren ck_intc_init(struct device_node *node, struct device_node *parent) 232edff1b48SGuo Ren { 233edff1b48SGuo Ren int ret; 234edff1b48SGuo Ren 235edff1b48SGuo Ren ret = ck_intc_init_comm(node, parent); 236edff1b48SGuo Ren if (ret) 237edff1b48SGuo Ren return ret; 238edff1b48SGuo Ren 239edff1b48SGuo Ren /* Initial enable reg to disable all interrupts */ 24056752b21SGuo Ren writel(0, reg_base + CK_INTC_NEN31_00); 24156752b21SGuo Ren writel(0, reg_base + CK_INTC_NEN63_32); 242edff1b48SGuo Ren 243edff1b48SGuo Ren /* Enable irq intc */ 24456752b21SGuo Ren writel(BIT(31), reg_base + CK_INTC_ICR); 245edff1b48SGuo Ren 246edff1b48SGuo Ren ck_set_gc(node, reg_base, CK_INTC_NEN31_00, 0); 247edff1b48SGuo Ren ck_set_gc(node, reg_base, CK_INTC_NEN63_32, 32); 248edff1b48SGuo Ren 249edff1b48SGuo Ren setup_irq_channel(0x00010203, reg_base + CK_INTC_SOURCE); 250edff1b48SGuo Ren 251edff1b48SGuo Ren set_handle_irq(ck_irq_handler); 252edff1b48SGuo Ren 253edff1b48SGuo Ren return 0; 254edff1b48SGuo Ren } 255edff1b48SGuo Ren IRQCHIP_DECLARE(ck_intc, "csky,apb-intc", ck_intc_init); 256edff1b48SGuo Ren 257edff1b48SGuo Ren static int __init 258edff1b48SGuo Ren ck_dual_intc_init(struct device_node *node, struct device_node *parent) 259edff1b48SGuo Ren { 260edff1b48SGuo Ren int ret; 261edff1b48SGuo Ren 262edff1b48SGuo Ren /* dual-apb-intc up to 128 irq sources*/ 263edff1b48SGuo Ren nr_irq = INTC_IRQS * 2; 264edff1b48SGuo Ren 265edff1b48SGuo Ren ret = ck_intc_init(node, parent); 266edff1b48SGuo Ren if (ret) 267edff1b48SGuo Ren return ret; 268edff1b48SGuo Ren 269edff1b48SGuo Ren /* Initial enable reg to disable all interrupts */ 27056752b21SGuo Ren writel(0, reg_base + CK_INTC_NEN31_00 + CK_INTC_DUAL_BASE); 27156752b21SGuo Ren writel(0, reg_base + CK_INTC_NEN63_32 + CK_INTC_DUAL_BASE); 272edff1b48SGuo Ren 273edff1b48SGuo Ren ck_set_gc(node, reg_base + CK_INTC_DUAL_BASE, CK_INTC_NEN31_00, 64); 274edff1b48SGuo Ren ck_set_gc(node, reg_base + CK_INTC_DUAL_BASE, CK_INTC_NEN63_32, 96); 275edff1b48SGuo Ren 276edff1b48SGuo Ren setup_irq_channel(0x00010203, 277edff1b48SGuo Ren reg_base + CK_INTC_SOURCE + CK_INTC_DUAL_BASE); 278edff1b48SGuo Ren 279edff1b48SGuo Ren return 0; 280edff1b48SGuo Ren } 281edff1b48SGuo Ren IRQCHIP_DECLARE(ck_dual_intc, "csky,dual-apb-intc", ck_dual_intc_init); 282