1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Broadcom BCM7038 style Level 1 interrupt controller driver 4 * 5 * Copyright (C) 2014 Broadcom Corporation 6 * Author: Kevin Cernekee 7 */ 8 9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 10 11 #include <linux/bitops.h> 12 #include <linux/kernel.h> 13 #include <linux/init.h> 14 #include <linux/interrupt.h> 15 #include <linux/io.h> 16 #include <linux/ioport.h> 17 #include <linux/irq.h> 18 #include <linux/irqdomain.h> 19 #include <linux/module.h> 20 #include <linux/of.h> 21 #include <linux/of_irq.h> 22 #include <linux/of_address.h> 23 #include <linux/of_platform.h> 24 #include <linux/platform_device.h> 25 #include <linux/slab.h> 26 #include <linux/smp.h> 27 #include <linux/types.h> 28 #include <linux/irqchip.h> 29 #include <linux/irqchip/chained_irq.h> 30 #include <linux/syscore_ops.h> 31 32 #define IRQS_PER_WORD 32 33 #define REG_BYTES_PER_IRQ_WORD (sizeof(u32) * 4) 34 #define MAX_WORDS 8 35 36 struct bcm7038_l1_cpu; 37 38 struct bcm7038_l1_chip { 39 raw_spinlock_t lock; 40 unsigned int n_words; 41 struct irq_domain *domain; 42 struct bcm7038_l1_cpu *cpus[NR_CPUS]; 43 #ifdef CONFIG_PM_SLEEP 44 struct list_head list; 45 u32 wake_mask[MAX_WORDS]; 46 #endif 47 u32 irq_fwd_mask[MAX_WORDS]; 48 u8 affinity[MAX_WORDS * IRQS_PER_WORD]; 49 }; 50 51 struct bcm7038_l1_cpu { 52 void __iomem *map_base; 53 u32 mask_cache[]; 54 }; 55 56 /* 57 * STATUS/MASK_STATUS/MASK_SET/MASK_CLEAR are packed one right after another: 58 * 59 * 7038: 60 * 0x1000_1400: W0_STATUS 61 * 0x1000_1404: W1_STATUS 62 * 0x1000_1408: W0_MASK_STATUS 63 * 0x1000_140c: W1_MASK_STATUS 64 * 0x1000_1410: W0_MASK_SET 65 * 0x1000_1414: W1_MASK_SET 66 * 0x1000_1418: W0_MASK_CLEAR 67 * 0x1000_141c: W1_MASK_CLEAR 68 * 69 * 7445: 70 * 0xf03e_1500: W0_STATUS 71 * 0xf03e_1504: W1_STATUS 72 * 0xf03e_1508: W2_STATUS 73 * 0xf03e_150c: W3_STATUS 74 * 0xf03e_1510: W4_STATUS 75 * 0xf03e_1514: W0_MASK_STATUS 76 * 0xf03e_1518: W1_MASK_STATUS 77 * [...] 78 */ 79 80 static inline unsigned int reg_status(struct bcm7038_l1_chip *intc, 81 unsigned int word) 82 { 83 return (0 * intc->n_words + word) * sizeof(u32); 84 } 85 86 static inline unsigned int reg_mask_status(struct bcm7038_l1_chip *intc, 87 unsigned int word) 88 { 89 return (1 * intc->n_words + word) * sizeof(u32); 90 } 91 92 static inline unsigned int reg_mask_set(struct bcm7038_l1_chip *intc, 93 unsigned int word) 94 { 95 return (2 * intc->n_words + word) * sizeof(u32); 96 } 97 98 static inline unsigned int reg_mask_clr(struct bcm7038_l1_chip *intc, 99 unsigned int word) 100 { 101 return (3 * intc->n_words + word) * sizeof(u32); 102 } 103 104 static inline u32 l1_readl(void __iomem *reg) 105 { 106 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) 107 return ioread32be(reg); 108 else 109 return readl(reg); 110 } 111 112 static inline void l1_writel(u32 val, void __iomem *reg) 113 { 114 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) 115 iowrite32be(val, reg); 116 else 117 writel(val, reg); 118 } 119 120 static void bcm7038_l1_irq_handle(struct irq_desc *desc) 121 { 122 struct bcm7038_l1_chip *intc = irq_desc_get_handler_data(desc); 123 struct bcm7038_l1_cpu *cpu; 124 struct irq_chip *chip = irq_desc_get_chip(desc); 125 unsigned int idx; 126 127 #ifdef CONFIG_SMP 128 cpu = intc->cpus[cpu_logical_map(smp_processor_id())]; 129 #else 130 cpu = intc->cpus[0]; 131 #endif 132 133 chained_irq_enter(chip, desc); 134 135 for (idx = 0; idx < intc->n_words; idx++) { 136 int base = idx * IRQS_PER_WORD; 137 unsigned long pending, flags; 138 int hwirq; 139 140 raw_spin_lock_irqsave(&intc->lock, flags); 141 pending = l1_readl(cpu->map_base + reg_status(intc, idx)) & 142 ~cpu->mask_cache[idx]; 143 raw_spin_unlock_irqrestore(&intc->lock, flags); 144 145 for_each_set_bit(hwirq, &pending, IRQS_PER_WORD) { 146 generic_handle_irq(irq_find_mapping(intc->domain, 147 base + hwirq)); 148 } 149 } 150 151 chained_irq_exit(chip, desc); 152 } 153 154 static void __bcm7038_l1_unmask(struct irq_data *d, unsigned int cpu_idx) 155 { 156 struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d); 157 u32 word = d->hwirq / IRQS_PER_WORD; 158 u32 mask = BIT(d->hwirq % IRQS_PER_WORD); 159 160 intc->cpus[cpu_idx]->mask_cache[word] &= ~mask; 161 l1_writel(mask, intc->cpus[cpu_idx]->map_base + 162 reg_mask_clr(intc, word)); 163 } 164 165 static void __bcm7038_l1_mask(struct irq_data *d, unsigned int cpu_idx) 166 { 167 struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d); 168 u32 word = d->hwirq / IRQS_PER_WORD; 169 u32 mask = BIT(d->hwirq % IRQS_PER_WORD); 170 171 intc->cpus[cpu_idx]->mask_cache[word] |= mask; 172 l1_writel(mask, intc->cpus[cpu_idx]->map_base + 173 reg_mask_set(intc, word)); 174 } 175 176 static void bcm7038_l1_unmask(struct irq_data *d) 177 { 178 struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d); 179 unsigned long flags; 180 181 raw_spin_lock_irqsave(&intc->lock, flags); 182 __bcm7038_l1_unmask(d, intc->affinity[d->hwirq]); 183 raw_spin_unlock_irqrestore(&intc->lock, flags); 184 } 185 186 static void bcm7038_l1_mask(struct irq_data *d) 187 { 188 struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d); 189 unsigned long flags; 190 191 raw_spin_lock_irqsave(&intc->lock, flags); 192 __bcm7038_l1_mask(d, intc->affinity[d->hwirq]); 193 raw_spin_unlock_irqrestore(&intc->lock, flags); 194 } 195 196 static int bcm7038_l1_set_affinity(struct irq_data *d, 197 const struct cpumask *dest, 198 bool force) 199 { 200 struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d); 201 unsigned long flags; 202 irq_hw_number_t hw = d->hwirq; 203 u32 word = hw / IRQS_PER_WORD; 204 u32 mask = BIT(hw % IRQS_PER_WORD); 205 unsigned int first_cpu = cpumask_any_and(dest, cpu_online_mask); 206 bool was_disabled; 207 208 raw_spin_lock_irqsave(&intc->lock, flags); 209 210 was_disabled = !!(intc->cpus[intc->affinity[hw]]->mask_cache[word] & 211 mask); 212 __bcm7038_l1_mask(d, intc->affinity[hw]); 213 intc->affinity[hw] = first_cpu; 214 if (!was_disabled) 215 __bcm7038_l1_unmask(d, first_cpu); 216 217 raw_spin_unlock_irqrestore(&intc->lock, flags); 218 irq_data_update_effective_affinity(d, cpumask_of(first_cpu)); 219 220 return 0; 221 } 222 223 #ifdef CONFIG_SMP 224 static void bcm7038_l1_cpu_offline(struct irq_data *d) 225 { 226 struct cpumask *mask = irq_data_get_affinity_mask(d); 227 int cpu = smp_processor_id(); 228 cpumask_t new_affinity; 229 230 /* This CPU was not on the affinity mask */ 231 if (!cpumask_test_cpu(cpu, mask)) 232 return; 233 234 if (cpumask_weight(mask) > 1) { 235 /* 236 * Multiple CPU affinity, remove this CPU from the affinity 237 * mask 238 */ 239 cpumask_copy(&new_affinity, mask); 240 cpumask_clear_cpu(cpu, &new_affinity); 241 } else { 242 /* Only CPU, put on the lowest online CPU */ 243 cpumask_clear(&new_affinity); 244 cpumask_set_cpu(cpumask_first(cpu_online_mask), &new_affinity); 245 } 246 irq_set_affinity_locked(d, &new_affinity, false); 247 } 248 #endif 249 250 static int __init bcm7038_l1_init_one(struct device_node *dn, 251 unsigned int idx, 252 struct bcm7038_l1_chip *intc) 253 { 254 struct resource res; 255 resource_size_t sz; 256 struct bcm7038_l1_cpu *cpu; 257 unsigned int i, n_words, parent_irq; 258 int ret; 259 260 if (of_address_to_resource(dn, idx, &res)) 261 return -EINVAL; 262 sz = resource_size(&res); 263 n_words = sz / REG_BYTES_PER_IRQ_WORD; 264 265 if (n_words > MAX_WORDS) 266 return -EINVAL; 267 else if (!intc->n_words) 268 intc->n_words = n_words; 269 else if (intc->n_words != n_words) 270 return -EINVAL; 271 272 ret = of_property_read_u32_array(dn , "brcm,int-fwd-mask", 273 intc->irq_fwd_mask, n_words); 274 if (ret != 0 && ret != -EINVAL) { 275 /* property exists but has the wrong number of words */ 276 pr_err("invalid brcm,int-fwd-mask property\n"); 277 return -EINVAL; 278 } 279 280 cpu = intc->cpus[idx] = kzalloc(sizeof(*cpu) + n_words * sizeof(u32), 281 GFP_KERNEL); 282 if (!cpu) 283 return -ENOMEM; 284 285 cpu->map_base = ioremap(res.start, sz); 286 if (!cpu->map_base) 287 return -ENOMEM; 288 289 for (i = 0; i < n_words; i++) { 290 l1_writel(~intc->irq_fwd_mask[i], 291 cpu->map_base + reg_mask_set(intc, i)); 292 l1_writel(intc->irq_fwd_mask[i], 293 cpu->map_base + reg_mask_clr(intc, i)); 294 cpu->mask_cache[i] = ~intc->irq_fwd_mask[i]; 295 } 296 297 parent_irq = irq_of_parse_and_map(dn, idx); 298 if (!parent_irq) { 299 pr_err("failed to map parent interrupt %d\n", parent_irq); 300 return -EINVAL; 301 } 302 303 if (of_property_read_bool(dn, "brcm,irq-can-wake")) 304 enable_irq_wake(parent_irq); 305 306 irq_set_chained_handler_and_data(parent_irq, bcm7038_l1_irq_handle, 307 intc); 308 309 return 0; 310 } 311 312 #ifdef CONFIG_PM_SLEEP 313 /* 314 * We keep a list of bcm7038_l1_chip used for suspend/resume. This hack is 315 * used because the struct chip_type suspend/resume hooks are not called 316 * unless chip_type is hooked onto a generic_chip. Since this driver does 317 * not use generic_chip, we need to manually hook our resume/suspend to 318 * syscore_ops. 319 */ 320 static LIST_HEAD(bcm7038_l1_intcs_list); 321 static DEFINE_RAW_SPINLOCK(bcm7038_l1_intcs_lock); 322 323 static int bcm7038_l1_suspend(void) 324 { 325 struct bcm7038_l1_chip *intc; 326 int boot_cpu, word; 327 u32 val; 328 329 /* Wakeup interrupt should only come from the boot cpu */ 330 boot_cpu = cpu_logical_map(0); 331 332 list_for_each_entry(intc, &bcm7038_l1_intcs_list, list) { 333 for (word = 0; word < intc->n_words; word++) { 334 val = intc->wake_mask[word] | intc->irq_fwd_mask[word]; 335 l1_writel(~val, 336 intc->cpus[boot_cpu]->map_base + reg_mask_set(intc, word)); 337 l1_writel(val, 338 intc->cpus[boot_cpu]->map_base + reg_mask_clr(intc, word)); 339 } 340 } 341 342 return 0; 343 } 344 345 static void bcm7038_l1_resume(void) 346 { 347 struct bcm7038_l1_chip *intc; 348 int boot_cpu, word; 349 350 boot_cpu = cpu_logical_map(0); 351 352 list_for_each_entry(intc, &bcm7038_l1_intcs_list, list) { 353 for (word = 0; word < intc->n_words; word++) { 354 l1_writel(intc->cpus[boot_cpu]->mask_cache[word], 355 intc->cpus[boot_cpu]->map_base + reg_mask_set(intc, word)); 356 l1_writel(~intc->cpus[boot_cpu]->mask_cache[word], 357 intc->cpus[boot_cpu]->map_base + reg_mask_clr(intc, word)); 358 } 359 } 360 } 361 362 static struct syscore_ops bcm7038_l1_syscore_ops = { 363 .suspend = bcm7038_l1_suspend, 364 .resume = bcm7038_l1_resume, 365 }; 366 367 static int bcm7038_l1_set_wake(struct irq_data *d, unsigned int on) 368 { 369 struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d); 370 unsigned long flags; 371 u32 word = d->hwirq / IRQS_PER_WORD; 372 u32 mask = BIT(d->hwirq % IRQS_PER_WORD); 373 374 raw_spin_lock_irqsave(&intc->lock, flags); 375 if (on) 376 intc->wake_mask[word] |= mask; 377 else 378 intc->wake_mask[word] &= ~mask; 379 raw_spin_unlock_irqrestore(&intc->lock, flags); 380 381 return 0; 382 } 383 #endif 384 385 static struct irq_chip bcm7038_l1_irq_chip = { 386 .name = "bcm7038-l1", 387 .irq_mask = bcm7038_l1_mask, 388 .irq_unmask = bcm7038_l1_unmask, 389 .irq_set_affinity = bcm7038_l1_set_affinity, 390 #ifdef CONFIG_SMP 391 .irq_cpu_offline = bcm7038_l1_cpu_offline, 392 #endif 393 #ifdef CONFIG_PM_SLEEP 394 .irq_set_wake = bcm7038_l1_set_wake, 395 #endif 396 }; 397 398 static int bcm7038_l1_map(struct irq_domain *d, unsigned int virq, 399 irq_hw_number_t hw_irq) 400 { 401 struct bcm7038_l1_chip *intc = d->host_data; 402 u32 mask = BIT(hw_irq % IRQS_PER_WORD); 403 u32 word = hw_irq / IRQS_PER_WORD; 404 405 if (intc->irq_fwd_mask[word] & mask) 406 return -EPERM; 407 408 irq_set_chip_and_handler(virq, &bcm7038_l1_irq_chip, handle_level_irq); 409 irq_set_chip_data(virq, d->host_data); 410 irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(virq))); 411 return 0; 412 } 413 414 static const struct irq_domain_ops bcm7038_l1_domain_ops = { 415 .xlate = irq_domain_xlate_onecell, 416 .map = bcm7038_l1_map, 417 }; 418 419 static int __init bcm7038_l1_of_init(struct device_node *dn, 420 struct device_node *parent) 421 { 422 struct bcm7038_l1_chip *intc; 423 int idx, ret; 424 425 intc = kzalloc(sizeof(*intc), GFP_KERNEL); 426 if (!intc) 427 return -ENOMEM; 428 429 raw_spin_lock_init(&intc->lock); 430 for_each_possible_cpu(idx) { 431 ret = bcm7038_l1_init_one(dn, idx, intc); 432 if (ret < 0) { 433 if (idx) 434 break; 435 pr_err("failed to remap intc L1 registers\n"); 436 goto out_free; 437 } 438 } 439 440 intc->domain = irq_domain_add_linear(dn, IRQS_PER_WORD * intc->n_words, 441 &bcm7038_l1_domain_ops, 442 intc); 443 if (!intc->domain) { 444 ret = -ENOMEM; 445 goto out_unmap; 446 } 447 448 #ifdef CONFIG_PM_SLEEP 449 /* Add bcm7038_l1_chip into a list */ 450 raw_spin_lock(&bcm7038_l1_intcs_lock); 451 list_add_tail(&intc->list, &bcm7038_l1_intcs_list); 452 raw_spin_unlock(&bcm7038_l1_intcs_lock); 453 454 if (list_is_singular(&bcm7038_l1_intcs_list)) 455 register_syscore_ops(&bcm7038_l1_syscore_ops); 456 #endif 457 458 pr_info("registered BCM7038 L1 intc (%pOF, IRQs: %d)\n", 459 dn, IRQS_PER_WORD * intc->n_words); 460 461 return 0; 462 463 out_unmap: 464 for_each_possible_cpu(idx) { 465 struct bcm7038_l1_cpu *cpu = intc->cpus[idx]; 466 467 if (cpu) { 468 if (cpu->map_base) 469 iounmap(cpu->map_base); 470 kfree(cpu); 471 } 472 } 473 out_free: 474 kfree(intc); 475 return ret; 476 } 477 478 IRQCHIP_DECLARE(bcm7038_l1, "brcm,bcm7038-l1-intc", bcm7038_l1_of_init); 479