1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Broadcom BCM6345 style Level 1 interrupt controller driver 4 * 5 * Copyright (C) 2014 Broadcom Corporation 6 * Copyright 2015 Simon Arlott 7 * 8 * This is based on the BCM7038 (which supports SMP) but with a single 9 * enable register instead of separate mask/set/clear registers. 10 * 11 * The BCM3380 has a similar mask/status register layout, but each pair 12 * of words is at separate locations (and SMP is not supported). 13 * 14 * ENABLE/STATUS words are packed next to each other for each CPU: 15 * 16 * BCM6368: 17 * 0x1000_0020: CPU0_W0_ENABLE 18 * 0x1000_0024: CPU0_W1_ENABLE 19 * 0x1000_0028: CPU0_W0_STATUS IRQs 31-63 20 * 0x1000_002c: CPU0_W1_STATUS IRQs 0-31 21 * 0x1000_0030: CPU1_W0_ENABLE 22 * 0x1000_0034: CPU1_W1_ENABLE 23 * 0x1000_0038: CPU1_W0_STATUS IRQs 31-63 24 * 0x1000_003c: CPU1_W1_STATUS IRQs 0-31 25 * 26 * BCM63168: 27 * 0x1000_0020: CPU0_W0_ENABLE 28 * 0x1000_0024: CPU0_W1_ENABLE 29 * 0x1000_0028: CPU0_W2_ENABLE 30 * 0x1000_002c: CPU0_W3_ENABLE 31 * 0x1000_0030: CPU0_W0_STATUS IRQs 96-127 32 * 0x1000_0034: CPU0_W1_STATUS IRQs 64-95 33 * 0x1000_0038: CPU0_W2_STATUS IRQs 32-63 34 * 0x1000_003c: CPU0_W3_STATUS IRQs 0-31 35 * 0x1000_0040: CPU1_W0_ENABLE 36 * 0x1000_0044: CPU1_W1_ENABLE 37 * 0x1000_0048: CPU1_W2_ENABLE 38 * 0x1000_004c: CPU1_W3_ENABLE 39 * 0x1000_0050: CPU1_W0_STATUS IRQs 96-127 40 * 0x1000_0054: CPU1_W1_STATUS IRQs 64-95 41 * 0x1000_0058: CPU1_W2_STATUS IRQs 32-63 42 * 0x1000_005c: CPU1_W3_STATUS IRQs 0-31 43 * 44 * IRQs are numbered in CPU native endian order 45 * (which is big-endian in these examples) 46 */ 47 48 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 49 50 #include <linux/bitops.h> 51 #include <linux/cpumask.h> 52 #include <linux/kernel.h> 53 #include <linux/init.h> 54 #include <linux/interrupt.h> 55 #include <linux/io.h> 56 #include <linux/ioport.h> 57 #include <linux/irq.h> 58 #include <linux/irqdomain.h> 59 #include <linux/module.h> 60 #include <linux/of.h> 61 #include <linux/of_irq.h> 62 #include <linux/of_address.h> 63 #include <linux/of_platform.h> 64 #include <linux/platform_device.h> 65 #include <linux/slab.h> 66 #include <linux/smp.h> 67 #include <linux/types.h> 68 #include <linux/irqchip.h> 69 #include <linux/irqchip/chained_irq.h> 70 71 #define IRQS_PER_WORD 32 72 #define REG_BYTES_PER_IRQ_WORD (sizeof(u32) * 2) 73 74 struct bcm6345_l1_cpu; 75 76 struct bcm6345_l1_chip { 77 raw_spinlock_t lock; 78 unsigned int n_words; 79 struct irq_domain *domain; 80 struct cpumask cpumask; 81 struct bcm6345_l1_cpu *cpus[NR_CPUS]; 82 }; 83 84 struct bcm6345_l1_cpu { 85 struct bcm6345_l1_chip *intc; 86 void __iomem *map_base; 87 unsigned int parent_irq; 88 u32 enable_cache[]; 89 }; 90 91 static inline unsigned int reg_enable(struct bcm6345_l1_chip *intc, 92 unsigned int word) 93 { 94 #ifdef __BIG_ENDIAN 95 return (1 * intc->n_words - word - 1) * sizeof(u32); 96 #else 97 return (0 * intc->n_words + word) * sizeof(u32); 98 #endif 99 } 100 101 static inline unsigned int reg_status(struct bcm6345_l1_chip *intc, 102 unsigned int word) 103 { 104 #ifdef __BIG_ENDIAN 105 return (2 * intc->n_words - word - 1) * sizeof(u32); 106 #else 107 return (1 * intc->n_words + word) * sizeof(u32); 108 #endif 109 } 110 111 static inline unsigned int cpu_for_irq(struct bcm6345_l1_chip *intc, 112 struct irq_data *d) 113 { 114 return cpumask_first_and(&intc->cpumask, irq_data_get_affinity_mask(d)); 115 } 116 117 static void bcm6345_l1_irq_handle(struct irq_desc *desc) 118 { 119 struct bcm6345_l1_cpu *cpu = irq_desc_get_handler_data(desc); 120 struct bcm6345_l1_chip *intc = cpu->intc; 121 struct irq_chip *chip = irq_desc_get_chip(desc); 122 unsigned int idx; 123 124 chained_irq_enter(chip, desc); 125 126 for (idx = 0; idx < intc->n_words; idx++) { 127 int base = idx * IRQS_PER_WORD; 128 unsigned long pending; 129 irq_hw_number_t hwirq; 130 131 pending = __raw_readl(cpu->map_base + reg_status(intc, idx)); 132 pending &= __raw_readl(cpu->map_base + reg_enable(intc, idx)); 133 134 for_each_set_bit(hwirq, &pending, IRQS_PER_WORD) { 135 if (generic_handle_domain_irq(intc->domain, base + hwirq)) 136 spurious_interrupt(); 137 } 138 } 139 140 chained_irq_exit(chip, desc); 141 } 142 143 static inline void __bcm6345_l1_unmask(struct irq_data *d) 144 { 145 struct bcm6345_l1_chip *intc = irq_data_get_irq_chip_data(d); 146 u32 word = d->hwirq / IRQS_PER_WORD; 147 u32 mask = BIT(d->hwirq % IRQS_PER_WORD); 148 unsigned int cpu_idx = cpu_for_irq(intc, d); 149 150 intc->cpus[cpu_idx]->enable_cache[word] |= mask; 151 __raw_writel(intc->cpus[cpu_idx]->enable_cache[word], 152 intc->cpus[cpu_idx]->map_base + reg_enable(intc, word)); 153 } 154 155 static inline void __bcm6345_l1_mask(struct irq_data *d) 156 { 157 struct bcm6345_l1_chip *intc = irq_data_get_irq_chip_data(d); 158 u32 word = d->hwirq / IRQS_PER_WORD; 159 u32 mask = BIT(d->hwirq % IRQS_PER_WORD); 160 unsigned int cpu_idx = cpu_for_irq(intc, d); 161 162 intc->cpus[cpu_idx]->enable_cache[word] &= ~mask; 163 __raw_writel(intc->cpus[cpu_idx]->enable_cache[word], 164 intc->cpus[cpu_idx]->map_base + reg_enable(intc, word)); 165 } 166 167 static void bcm6345_l1_unmask(struct irq_data *d) 168 { 169 struct bcm6345_l1_chip *intc = irq_data_get_irq_chip_data(d); 170 unsigned long flags; 171 172 raw_spin_lock_irqsave(&intc->lock, flags); 173 __bcm6345_l1_unmask(d); 174 raw_spin_unlock_irqrestore(&intc->lock, flags); 175 } 176 177 static void bcm6345_l1_mask(struct irq_data *d) 178 { 179 struct bcm6345_l1_chip *intc = irq_data_get_irq_chip_data(d); 180 unsigned long flags; 181 182 raw_spin_lock_irqsave(&intc->lock, flags); 183 __bcm6345_l1_mask(d); 184 raw_spin_unlock_irqrestore(&intc->lock, flags); 185 } 186 187 static int bcm6345_l1_set_affinity(struct irq_data *d, 188 const struct cpumask *dest, 189 bool force) 190 { 191 struct bcm6345_l1_chip *intc = irq_data_get_irq_chip_data(d); 192 u32 word = d->hwirq / IRQS_PER_WORD; 193 u32 mask = BIT(d->hwirq % IRQS_PER_WORD); 194 unsigned int old_cpu = cpu_for_irq(intc, d); 195 unsigned int new_cpu; 196 struct cpumask valid; 197 unsigned long flags; 198 bool enabled; 199 200 if (!cpumask_and(&valid, &intc->cpumask, dest)) 201 return -EINVAL; 202 203 new_cpu = cpumask_any_and(&valid, cpu_online_mask); 204 if (new_cpu >= nr_cpu_ids) 205 return -EINVAL; 206 207 dest = cpumask_of(new_cpu); 208 209 raw_spin_lock_irqsave(&intc->lock, flags); 210 if (old_cpu != new_cpu) { 211 enabled = intc->cpus[old_cpu]->enable_cache[word] & mask; 212 if (enabled) 213 __bcm6345_l1_mask(d); 214 irq_data_update_affinity(d, dest); 215 if (enabled) 216 __bcm6345_l1_unmask(d); 217 } else { 218 irq_data_update_affinity(d, dest); 219 } 220 raw_spin_unlock_irqrestore(&intc->lock, flags); 221 222 irq_data_update_effective_affinity(d, cpumask_of(new_cpu)); 223 224 return IRQ_SET_MASK_OK_NOCOPY; 225 } 226 227 static int __init bcm6345_l1_init_one(struct device_node *dn, 228 unsigned int idx, 229 struct bcm6345_l1_chip *intc) 230 { 231 struct resource res; 232 resource_size_t sz; 233 struct bcm6345_l1_cpu *cpu; 234 unsigned int i, n_words; 235 236 if (of_address_to_resource(dn, idx, &res)) 237 return -EINVAL; 238 sz = resource_size(&res); 239 n_words = sz / REG_BYTES_PER_IRQ_WORD; 240 241 if (!intc->n_words) 242 intc->n_words = n_words; 243 else if (intc->n_words != n_words) 244 return -EINVAL; 245 246 cpu = intc->cpus[idx] = kzalloc(sizeof(*cpu) + n_words * sizeof(u32), 247 GFP_KERNEL); 248 if (!cpu) 249 return -ENOMEM; 250 251 cpu->intc = intc; 252 cpu->map_base = ioremap(res.start, sz); 253 if (!cpu->map_base) 254 return -ENOMEM; 255 256 if (!request_mem_region(res.start, sz, res.name)) 257 pr_err("failed to request intc memory"); 258 259 for (i = 0; i < n_words; i++) { 260 cpu->enable_cache[i] = 0; 261 __raw_writel(0, cpu->map_base + reg_enable(intc, i)); 262 } 263 264 cpu->parent_irq = irq_of_parse_and_map(dn, idx); 265 if (!cpu->parent_irq) { 266 pr_err("failed to map parent interrupt %d\n", cpu->parent_irq); 267 return -EINVAL; 268 } 269 irq_set_chained_handler_and_data(cpu->parent_irq, 270 bcm6345_l1_irq_handle, cpu); 271 272 return 0; 273 } 274 275 static struct irq_chip bcm6345_l1_irq_chip = { 276 .name = "bcm6345-l1", 277 .irq_mask = bcm6345_l1_mask, 278 .irq_unmask = bcm6345_l1_unmask, 279 .irq_set_affinity = bcm6345_l1_set_affinity, 280 }; 281 282 static int bcm6345_l1_map(struct irq_domain *d, unsigned int virq, 283 irq_hw_number_t hw_irq) 284 { 285 irq_set_chip_and_handler(virq, 286 &bcm6345_l1_irq_chip, handle_percpu_irq); 287 irq_set_chip_data(virq, d->host_data); 288 irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(virq))); 289 return 0; 290 } 291 292 static const struct irq_domain_ops bcm6345_l1_domain_ops = { 293 .xlate = irq_domain_xlate_onecell, 294 .map = bcm6345_l1_map, 295 }; 296 297 static int __init bcm6345_l1_of_init(struct device_node *dn, 298 struct device_node *parent) 299 { 300 struct bcm6345_l1_chip *intc; 301 unsigned int idx; 302 int ret; 303 304 intc = kzalloc(sizeof(*intc), GFP_KERNEL); 305 if (!intc) 306 return -ENOMEM; 307 308 for_each_possible_cpu(idx) { 309 ret = bcm6345_l1_init_one(dn, idx, intc); 310 if (ret) 311 pr_err("failed to init intc L1 for cpu %d: %d\n", 312 idx, ret); 313 else 314 cpumask_set_cpu(idx, &intc->cpumask); 315 } 316 317 if (cpumask_empty(&intc->cpumask)) { 318 ret = -ENODEV; 319 goto out_free; 320 } 321 322 raw_spin_lock_init(&intc->lock); 323 324 intc->domain = irq_domain_add_linear(dn, IRQS_PER_WORD * intc->n_words, 325 &bcm6345_l1_domain_ops, 326 intc); 327 if (!intc->domain) { 328 ret = -ENOMEM; 329 goto out_unmap; 330 } 331 332 pr_info("registered BCM6345 L1 intc (IRQs: %d)\n", 333 IRQS_PER_WORD * intc->n_words); 334 for_each_cpu(idx, &intc->cpumask) { 335 struct bcm6345_l1_cpu *cpu = intc->cpus[idx]; 336 337 pr_info(" CPU%u (irq = %d)\n", idx, cpu->parent_irq); 338 } 339 340 return 0; 341 342 out_unmap: 343 for_each_possible_cpu(idx) { 344 struct bcm6345_l1_cpu *cpu = intc->cpus[idx]; 345 346 if (cpu) { 347 if (cpu->map_base) 348 iounmap(cpu->map_base); 349 kfree(cpu); 350 } 351 } 352 out_free: 353 kfree(intc); 354 return ret; 355 } 356 357 IRQCHIP_DECLARE(bcm6345_l1, "brcm,bcm6345-l1-intc", bcm6345_l1_of_init); 358