1 /* 2 * Root interrupt controller for the BCM2836 (Raspberry Pi 2). 3 * 4 * Copyright 2015 Broadcom 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 */ 16 17 #include <linux/cpu.h> 18 #include <linux/of_address.h> 19 #include <linux/of_irq.h> 20 #include <linux/irqchip.h> 21 #include <linux/irqdomain.h> 22 #include <linux/irqchip/irq-bcm2836.h> 23 24 #include <asm/exception.h> 25 26 struct bcm2836_arm_irqchip_intc { 27 struct irq_domain *domain; 28 void __iomem *base; 29 }; 30 31 static struct bcm2836_arm_irqchip_intc intc __read_mostly; 32 33 static void bcm2836_arm_irqchip_mask_per_cpu_irq(unsigned int reg_offset, 34 unsigned int bit, 35 int cpu) 36 { 37 void __iomem *reg = intc.base + reg_offset + 4 * cpu; 38 39 writel(readl(reg) & ~BIT(bit), reg); 40 } 41 42 static void bcm2836_arm_irqchip_unmask_per_cpu_irq(unsigned int reg_offset, 43 unsigned int bit, 44 int cpu) 45 { 46 void __iomem *reg = intc.base + reg_offset + 4 * cpu; 47 48 writel(readl(reg) | BIT(bit), reg); 49 } 50 51 static void bcm2836_arm_irqchip_mask_timer_irq(struct irq_data *d) 52 { 53 bcm2836_arm_irqchip_mask_per_cpu_irq(LOCAL_TIMER_INT_CONTROL0, 54 d->hwirq - LOCAL_IRQ_CNTPSIRQ, 55 smp_processor_id()); 56 } 57 58 static void bcm2836_arm_irqchip_unmask_timer_irq(struct irq_data *d) 59 { 60 bcm2836_arm_irqchip_unmask_per_cpu_irq(LOCAL_TIMER_INT_CONTROL0, 61 d->hwirq - LOCAL_IRQ_CNTPSIRQ, 62 smp_processor_id()); 63 } 64 65 static struct irq_chip bcm2836_arm_irqchip_timer = { 66 .name = "bcm2836-timer", 67 .irq_mask = bcm2836_arm_irqchip_mask_timer_irq, 68 .irq_unmask = bcm2836_arm_irqchip_unmask_timer_irq, 69 }; 70 71 static void bcm2836_arm_irqchip_mask_pmu_irq(struct irq_data *d) 72 { 73 writel(1 << smp_processor_id(), intc.base + LOCAL_PM_ROUTING_CLR); 74 } 75 76 static void bcm2836_arm_irqchip_unmask_pmu_irq(struct irq_data *d) 77 { 78 writel(1 << smp_processor_id(), intc.base + LOCAL_PM_ROUTING_SET); 79 } 80 81 static struct irq_chip bcm2836_arm_irqchip_pmu = { 82 .name = "bcm2836-pmu", 83 .irq_mask = bcm2836_arm_irqchip_mask_pmu_irq, 84 .irq_unmask = bcm2836_arm_irqchip_unmask_pmu_irq, 85 }; 86 87 static void bcm2836_arm_irqchip_mask_gpu_irq(struct irq_data *d) 88 { 89 } 90 91 static void bcm2836_arm_irqchip_unmask_gpu_irq(struct irq_data *d) 92 { 93 } 94 95 static struct irq_chip bcm2836_arm_irqchip_gpu = { 96 .name = "bcm2836-gpu", 97 .irq_mask = bcm2836_arm_irqchip_mask_gpu_irq, 98 .irq_unmask = bcm2836_arm_irqchip_unmask_gpu_irq, 99 }; 100 101 static int bcm2836_map(struct irq_domain *d, unsigned int irq, 102 irq_hw_number_t hw) 103 { 104 struct irq_chip *chip; 105 106 switch (hw) { 107 case LOCAL_IRQ_CNTPSIRQ: 108 case LOCAL_IRQ_CNTPNSIRQ: 109 case LOCAL_IRQ_CNTHPIRQ: 110 case LOCAL_IRQ_CNTVIRQ: 111 chip = &bcm2836_arm_irqchip_timer; 112 break; 113 case LOCAL_IRQ_GPU_FAST: 114 chip = &bcm2836_arm_irqchip_gpu; 115 break; 116 case LOCAL_IRQ_PMU_FAST: 117 chip = &bcm2836_arm_irqchip_pmu; 118 break; 119 default: 120 pr_warn_once("Unexpected hw irq: %lu\n", hw); 121 return -EINVAL; 122 } 123 124 irq_set_percpu_devid(irq); 125 irq_domain_set_info(d, irq, hw, chip, d->host_data, 126 handle_percpu_devid_irq, NULL, NULL); 127 irq_set_status_flags(irq, IRQ_NOAUTOEN); 128 129 return 0; 130 } 131 132 static void 133 __exception_irq_entry bcm2836_arm_irqchip_handle_irq(struct pt_regs *regs) 134 { 135 int cpu = smp_processor_id(); 136 u32 stat; 137 138 stat = readl_relaxed(intc.base + LOCAL_IRQ_PENDING0 + 4 * cpu); 139 if (stat & BIT(LOCAL_IRQ_MAILBOX0)) { 140 #ifdef CONFIG_SMP 141 void __iomem *mailbox0 = (intc.base + 142 LOCAL_MAILBOX0_CLR0 + 16 * cpu); 143 u32 mbox_val = readl(mailbox0); 144 u32 ipi = ffs(mbox_val) - 1; 145 146 writel(1 << ipi, mailbox0); 147 handle_IPI(ipi, regs); 148 #endif 149 } else if (stat) { 150 u32 hwirq = ffs(stat) - 1; 151 152 handle_domain_irq(intc.domain, hwirq, regs); 153 } 154 } 155 156 #ifdef CONFIG_SMP 157 static void bcm2836_arm_irqchip_send_ipi(const struct cpumask *mask, 158 unsigned int ipi) 159 { 160 int cpu; 161 void __iomem *mailbox0_base = intc.base + LOCAL_MAILBOX0_SET0; 162 163 /* 164 * Ensure that stores to normal memory are visible to the 165 * other CPUs before issuing the IPI. 166 */ 167 smp_wmb(); 168 169 for_each_cpu(cpu, mask) { 170 writel(1 << ipi, mailbox0_base + 16 * cpu); 171 } 172 } 173 174 static int bcm2836_cpu_starting(unsigned int cpu) 175 { 176 bcm2836_arm_irqchip_unmask_per_cpu_irq(LOCAL_MAILBOX_INT_CONTROL0, 0, 177 cpu); 178 return 0; 179 } 180 181 static int bcm2836_cpu_dying(unsigned int cpu) 182 { 183 bcm2836_arm_irqchip_mask_per_cpu_irq(LOCAL_MAILBOX_INT_CONTROL0, 0, 184 cpu); 185 return 0; 186 } 187 #endif 188 189 static const struct irq_domain_ops bcm2836_arm_irqchip_intc_ops = { 190 .xlate = irq_domain_xlate_onetwocell, 191 .map = bcm2836_map, 192 }; 193 194 static void 195 bcm2836_arm_irqchip_smp_init(void) 196 { 197 #ifdef CONFIG_SMP 198 /* Unmask IPIs to the boot CPU. */ 199 cpuhp_setup_state(CPUHP_AP_IRQ_BCM2836_STARTING, 200 "irqchip/bcm2836:starting", bcm2836_cpu_starting, 201 bcm2836_cpu_dying); 202 203 set_smp_cross_call(bcm2836_arm_irqchip_send_ipi); 204 #endif 205 } 206 207 /* 208 * The LOCAL_IRQ_CNT* timer firings are based off of the external 209 * oscillator with some scaling. The firmware sets up CNTFRQ to 210 * report 19.2Mhz, but doesn't set up the scaling registers. 211 */ 212 static void bcm2835_init_local_timer_frequency(void) 213 { 214 /* 215 * Set the timer to source from the 19.2Mhz crystal clock (bit 216 * 8 unset), and only increment by 1 instead of 2 (bit 9 217 * unset). 218 */ 219 writel(0, intc.base + LOCAL_CONTROL); 220 221 /* 222 * Set the timer prescaler to 1:1 (timer freq = input freq * 223 * 2**31 / prescaler) 224 */ 225 writel(0x80000000, intc.base + LOCAL_PRESCALER); 226 } 227 228 static int __init bcm2836_arm_irqchip_l1_intc_of_init(struct device_node *node, 229 struct device_node *parent) 230 { 231 intc.base = of_iomap(node, 0); 232 if (!intc.base) { 233 panic("%pOF: unable to map local interrupt registers\n", node); 234 } 235 236 bcm2835_init_local_timer_frequency(); 237 238 intc.domain = irq_domain_add_linear(node, LAST_IRQ + 1, 239 &bcm2836_arm_irqchip_intc_ops, 240 NULL); 241 if (!intc.domain) 242 panic("%pOF: unable to create IRQ domain\n", node); 243 244 bcm2836_arm_irqchip_smp_init(); 245 246 set_handle_irq(bcm2836_arm_irqchip_handle_irq); 247 return 0; 248 } 249 250 IRQCHIP_DECLARE(bcm2836_arm_irqchip_l1_intc, "brcm,bcm2836-l1-intc", 251 bcm2836_arm_irqchip_l1_intc_of_init); 252