1 /* 2 * Atheros AR71xx/AR724x/AR913x MISC interrupt controller 3 * 4 * Copyright (C) 2015 Alban Bedel <albeu@free.fr> 5 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com> 6 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org> 7 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> 8 * 9 * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of the GNU General Public License version 2 as published 13 * by the Free Software Foundation. 14 */ 15 16 #include <linux/irqchip.h> 17 #include <linux/irqchip/chained_irq.h> 18 #include <linux/of_address.h> 19 #include <linux/of_irq.h> 20 21 #define AR71XX_RESET_REG_MISC_INT_STATUS 0 22 #define AR71XX_RESET_REG_MISC_INT_ENABLE 4 23 24 #define ATH79_MISC_IRQ_COUNT 32 25 #define ATH79_MISC_PERF_IRQ 5 26 27 static int ath79_perfcount_irq; 28 29 int get_c0_perfcount_int(void) 30 { 31 return ath79_perfcount_irq; 32 } 33 EXPORT_SYMBOL_GPL(get_c0_perfcount_int); 34 35 static void ath79_misc_irq_handler(struct irq_desc *desc) 36 { 37 struct irq_domain *domain = irq_desc_get_handler_data(desc); 38 struct irq_chip *chip = irq_desc_get_chip(desc); 39 void __iomem *base = domain->host_data; 40 u32 pending; 41 42 chained_irq_enter(chip, desc); 43 44 pending = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS) & 45 __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); 46 47 if (!pending) { 48 spurious_interrupt(); 49 chained_irq_exit(chip, desc); 50 return; 51 } 52 53 while (pending) { 54 int bit = __ffs(pending); 55 56 generic_handle_irq(irq_linear_revmap(domain, bit)); 57 pending &= ~BIT(bit); 58 } 59 60 chained_irq_exit(chip, desc); 61 } 62 63 static void ar71xx_misc_irq_unmask(struct irq_data *d) 64 { 65 void __iomem *base = irq_data_get_irq_chip_data(d); 66 unsigned int irq = d->hwirq; 67 u32 t; 68 69 t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); 70 __raw_writel(t | BIT(irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE); 71 72 /* flush write */ 73 __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); 74 } 75 76 static void ar71xx_misc_irq_mask(struct irq_data *d) 77 { 78 void __iomem *base = irq_data_get_irq_chip_data(d); 79 unsigned int irq = d->hwirq; 80 u32 t; 81 82 t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); 83 __raw_writel(t & ~BIT(irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE); 84 85 /* flush write */ 86 __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); 87 } 88 89 static void ar724x_misc_irq_ack(struct irq_data *d) 90 { 91 void __iomem *base = irq_data_get_irq_chip_data(d); 92 unsigned int irq = d->hwirq; 93 u32 t; 94 95 t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS); 96 __raw_writel(t & ~BIT(irq), base + AR71XX_RESET_REG_MISC_INT_STATUS); 97 98 /* flush write */ 99 __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS); 100 } 101 102 static struct irq_chip ath79_misc_irq_chip = { 103 .name = "MISC", 104 .irq_unmask = ar71xx_misc_irq_unmask, 105 .irq_mask = ar71xx_misc_irq_mask, 106 }; 107 108 static int misc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw) 109 { 110 irq_set_chip_and_handler(irq, &ath79_misc_irq_chip, handle_level_irq); 111 irq_set_chip_data(irq, d->host_data); 112 return 0; 113 } 114 115 static const struct irq_domain_ops misc_irq_domain_ops = { 116 .xlate = irq_domain_xlate_onecell, 117 .map = misc_map, 118 }; 119 120 static void __init ath79_misc_intc_domain_init( 121 struct irq_domain *domain, int irq) 122 { 123 void __iomem *base = domain->host_data; 124 125 ath79_perfcount_irq = irq_create_mapping(domain, ATH79_MISC_PERF_IRQ); 126 127 /* Disable and clear all interrupts */ 128 __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_ENABLE); 129 __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_STATUS); 130 131 irq_set_chained_handler_and_data(irq, ath79_misc_irq_handler, domain); 132 } 133 134 static int __init ath79_misc_intc_of_init( 135 struct device_node *node, struct device_node *parent) 136 { 137 struct irq_domain *domain; 138 void __iomem *base; 139 int irq; 140 141 irq = irq_of_parse_and_map(node, 0); 142 if (!irq) { 143 pr_err("Failed to get MISC IRQ\n"); 144 return -EINVAL; 145 } 146 147 base = of_iomap(node, 0); 148 if (!base) { 149 pr_err("Failed to get MISC IRQ registers\n"); 150 return -ENOMEM; 151 } 152 153 domain = irq_domain_add_linear(node, ATH79_MISC_IRQ_COUNT, 154 &misc_irq_domain_ops, base); 155 if (!domain) { 156 pr_err("Failed to add MISC irqdomain\n"); 157 return -EINVAL; 158 } 159 160 ath79_misc_intc_domain_init(domain, irq); 161 return 0; 162 } 163 164 static int __init ar7100_misc_intc_of_init( 165 struct device_node *node, struct device_node *parent) 166 { 167 ath79_misc_irq_chip.irq_mask_ack = ar71xx_misc_irq_mask; 168 return ath79_misc_intc_of_init(node, parent); 169 } 170 171 IRQCHIP_DECLARE(ar7100_misc_intc, "qca,ar7100-misc-intc", 172 ar7100_misc_intc_of_init); 173 174 static int __init ar7240_misc_intc_of_init( 175 struct device_node *node, struct device_node *parent) 176 { 177 ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack; 178 return ath79_misc_intc_of_init(node, parent); 179 } 180 181 IRQCHIP_DECLARE(ar7240_misc_intc, "qca,ar7240-misc-intc", 182 ar7240_misc_intc_of_init); 183 184 void __init ath79_misc_irq_init(void __iomem *regs, int irq, 185 int irq_base, bool is_ar71xx) 186 { 187 struct irq_domain *domain; 188 189 if (is_ar71xx) 190 ath79_misc_irq_chip.irq_mask_ack = ar71xx_misc_irq_mask; 191 else 192 ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack; 193 194 domain = irq_domain_add_legacy(NULL, ATH79_MISC_IRQ_COUNT, 195 irq_base, 0, &misc_irq_domain_ops, regs); 196 if (!domain) 197 panic("Failed to create MISC irqdomain"); 198 199 ath79_misc_intc_domain_init(domain, irq); 200 } 201