1 /* 2 * Marvell Armada 370 and Armada XP SoC IRQ handling 3 * 4 * Copyright (C) 2012 Marvell 5 * 6 * Lior Amsalem <alior@marvell.com> 7 * Gregory CLEMENT <gregory.clement@free-electrons.com> 8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 9 * Ben Dooks <ben.dooks@codethink.co.uk> 10 * 11 * This file is licensed under the terms of the GNU General Public 12 * License version 2. This program is licensed "as is" without any 13 * warranty of any kind, whether express or implied. 14 */ 15 16 #include <linux/kernel.h> 17 #include <linux/module.h> 18 #include <linux/init.h> 19 #include <linux/irq.h> 20 #include <linux/interrupt.h> 21 #include <linux/irqchip.h> 22 #include <linux/irqchip/chained_irq.h> 23 #include <linux/cpu.h> 24 #include <linux/io.h> 25 #include <linux/of_address.h> 26 #include <linux/of_irq.h> 27 #include <linux/of_pci.h> 28 #include <linux/irqdomain.h> 29 #include <linux/slab.h> 30 #include <linux/syscore_ops.h> 31 #include <linux/msi.h> 32 #include <asm/mach/arch.h> 33 #include <asm/exception.h> 34 #include <asm/smp_plat.h> 35 #include <asm/mach/irq.h> 36 37 /* 38 * Overall diagram of the Armada XP interrupt controller: 39 * 40 * To CPU 0 To CPU 1 41 * 42 * /\ /\ 43 * || || 44 * +---------------+ +---------------+ 45 * | | | | 46 * | per-CPU | | per-CPU | 47 * | mask/unmask | | mask/unmask | 48 * | CPU0 | | CPU1 | 49 * | | | | 50 * +---------------+ +---------------+ 51 * /\ /\ 52 * || || 53 * \\_______________________// 54 * || 55 * +-------------------+ 56 * | | 57 * | Global interrupt | 58 * | mask/unmask | 59 * | | 60 * +-------------------+ 61 * /\ 62 * || 63 * interrupt from 64 * device 65 * 66 * The "global interrupt mask/unmask" is modified using the 67 * ARMADA_370_XP_INT_SET_ENABLE_OFFS and 68 * ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS registers, which are relative 69 * to "main_int_base". 70 * 71 * The "per-CPU mask/unmask" is modified using the 72 * ARMADA_370_XP_INT_SET_MASK_OFFS and 73 * ARMADA_370_XP_INT_CLEAR_MASK_OFFS registers, which are relative to 74 * "per_cpu_int_base". This base address points to a special address, 75 * which automatically accesses the registers of the current CPU. 76 * 77 * The per-CPU mask/unmask can also be adjusted using the global 78 * per-interrupt ARMADA_370_XP_INT_SOURCE_CTL register, which we use 79 * to configure interrupt affinity. 80 * 81 * Due to this model, all interrupts need to be mask/unmasked at two 82 * different levels: at the global level and at the per-CPU level. 83 * 84 * This driver takes the following approach to deal with this: 85 * 86 * - For global interrupts: 87 * 88 * At ->map() time, a global interrupt is unmasked at the per-CPU 89 * mask/unmask level. It is therefore unmasked at this level for 90 * the current CPU, running the ->map() code. This allows to have 91 * the interrupt unmasked at this level in non-SMP 92 * configurations. In SMP configurations, the ->set_affinity() 93 * callback is called, which using the 94 * ARMADA_370_XP_INT_SOURCE_CTL() readjusts the per-CPU mask/unmask 95 * for the interrupt. 96 * 97 * The ->mask() and ->unmask() operations only mask/unmask the 98 * interrupt at the "global" level. 99 * 100 * So, a global interrupt is enabled at the per-CPU level as soon 101 * as it is mapped. At run time, the masking/unmasking takes place 102 * at the global level. 103 * 104 * - For per-CPU interrupts 105 * 106 * At ->map() time, a per-CPU interrupt is unmasked at the global 107 * mask/unmask level. 108 * 109 * The ->mask() and ->unmask() operations mask/unmask the interrupt 110 * at the per-CPU level. 111 * 112 * So, a per-CPU interrupt is enabled at the global level as soon 113 * as it is mapped. At run time, the masking/unmasking takes place 114 * at the per-CPU level. 115 */ 116 117 /* Registers relative to main_int_base */ 118 #define ARMADA_370_XP_INT_CONTROL (0x00) 119 #define ARMADA_370_XP_SW_TRIG_INT_OFFS (0x04) 120 #define ARMADA_370_XP_INT_SET_ENABLE_OFFS (0x30) 121 #define ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS (0x34) 122 #define ARMADA_370_XP_INT_SOURCE_CTL(irq) (0x100 + irq*4) 123 #define ARMADA_370_XP_INT_SOURCE_CPU_MASK 0xF 124 #define ARMADA_370_XP_INT_IRQ_FIQ_MASK(cpuid) ((BIT(0) | BIT(8)) << cpuid) 125 126 /* Registers relative to per_cpu_int_base */ 127 #define ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS (0x08) 128 #define ARMADA_370_XP_IN_DRBEL_MSK_OFFS (0x0c) 129 #define ARMADA_375_PPI_CAUSE (0x10) 130 #define ARMADA_370_XP_CPU_INTACK_OFFS (0x44) 131 #define ARMADA_370_XP_INT_SET_MASK_OFFS (0x48) 132 #define ARMADA_370_XP_INT_CLEAR_MASK_OFFS (0x4C) 133 #define ARMADA_370_XP_INT_FABRIC_MASK_OFFS (0x54) 134 #define ARMADA_370_XP_INT_CAUSE_PERF(cpu) (1 << cpu) 135 136 #define ARMADA_370_XP_MAX_PER_CPU_IRQS (28) 137 138 #define IPI_DOORBELL_START (0) 139 #define IPI_DOORBELL_END (8) 140 #define IPI_DOORBELL_MASK 0xFF 141 #define PCI_MSI_DOORBELL_START (16) 142 #define PCI_MSI_DOORBELL_NR (16) 143 #define PCI_MSI_DOORBELL_END (32) 144 #define PCI_MSI_DOORBELL_MASK 0xFFFF0000 145 146 static void __iomem *per_cpu_int_base; 147 static void __iomem *main_int_base; 148 static struct irq_domain *armada_370_xp_mpic_domain; 149 static u32 doorbell_mask_reg; 150 static int parent_irq; 151 #ifdef CONFIG_PCI_MSI 152 static struct irq_domain *armada_370_xp_msi_domain; 153 static struct irq_domain *armada_370_xp_msi_inner_domain; 154 static DECLARE_BITMAP(msi_used, PCI_MSI_DOORBELL_NR); 155 static DEFINE_MUTEX(msi_used_lock); 156 static phys_addr_t msi_doorbell_addr; 157 #endif 158 159 static inline bool is_percpu_irq(irq_hw_number_t irq) 160 { 161 if (irq <= ARMADA_370_XP_MAX_PER_CPU_IRQS) 162 return true; 163 164 return false; 165 } 166 167 /* 168 * In SMP mode: 169 * For shared global interrupts, mask/unmask global enable bit 170 * For CPU interrupts, mask/unmask the calling CPU's bit 171 */ 172 static void armada_370_xp_irq_mask(struct irq_data *d) 173 { 174 irq_hw_number_t hwirq = irqd_to_hwirq(d); 175 176 if (!is_percpu_irq(hwirq)) 177 writel(hwirq, main_int_base + 178 ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS); 179 else 180 writel(hwirq, per_cpu_int_base + 181 ARMADA_370_XP_INT_SET_MASK_OFFS); 182 } 183 184 static void armada_370_xp_irq_unmask(struct irq_data *d) 185 { 186 irq_hw_number_t hwirq = irqd_to_hwirq(d); 187 188 if (!is_percpu_irq(hwirq)) 189 writel(hwirq, main_int_base + 190 ARMADA_370_XP_INT_SET_ENABLE_OFFS); 191 else 192 writel(hwirq, per_cpu_int_base + 193 ARMADA_370_XP_INT_CLEAR_MASK_OFFS); 194 } 195 196 #ifdef CONFIG_PCI_MSI 197 198 static struct irq_chip armada_370_xp_msi_irq_chip = { 199 .name = "MPIC MSI", 200 .irq_mask = pci_msi_mask_irq, 201 .irq_unmask = pci_msi_unmask_irq, 202 }; 203 204 static struct msi_domain_info armada_370_xp_msi_domain_info = { 205 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | 206 MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX), 207 .chip = &armada_370_xp_msi_irq_chip, 208 }; 209 210 static void armada_370_xp_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) 211 { 212 unsigned int cpu = cpumask_first(irq_data_get_effective_affinity_mask(data)); 213 214 msg->address_lo = lower_32_bits(msi_doorbell_addr); 215 msg->address_hi = upper_32_bits(msi_doorbell_addr); 216 msg->data = BIT(cpu + 8) | (data->hwirq + PCI_MSI_DOORBELL_START); 217 } 218 219 static int armada_370_xp_msi_set_affinity(struct irq_data *irq_data, 220 const struct cpumask *mask, bool force) 221 { 222 unsigned int cpu; 223 224 if (!force) 225 cpu = cpumask_any_and(mask, cpu_online_mask); 226 else 227 cpu = cpumask_first(mask); 228 229 if (cpu >= nr_cpu_ids) 230 return -EINVAL; 231 232 irq_data_update_effective_affinity(irq_data, cpumask_of(cpu)); 233 234 return IRQ_SET_MASK_OK; 235 } 236 237 static struct irq_chip armada_370_xp_msi_bottom_irq_chip = { 238 .name = "MPIC MSI", 239 .irq_compose_msi_msg = armada_370_xp_compose_msi_msg, 240 .irq_set_affinity = armada_370_xp_msi_set_affinity, 241 }; 242 243 static int armada_370_xp_msi_alloc(struct irq_domain *domain, unsigned int virq, 244 unsigned int nr_irqs, void *args) 245 { 246 int hwirq, i; 247 248 mutex_lock(&msi_used_lock); 249 hwirq = bitmap_find_free_region(msi_used, PCI_MSI_DOORBELL_NR, 250 order_base_2(nr_irqs)); 251 mutex_unlock(&msi_used_lock); 252 253 if (hwirq < 0) 254 return -ENOSPC; 255 256 for (i = 0; i < nr_irqs; i++) { 257 irq_domain_set_info(domain, virq + i, hwirq + i, 258 &armada_370_xp_msi_bottom_irq_chip, 259 domain->host_data, handle_simple_irq, 260 NULL, NULL); 261 } 262 263 return 0; 264 } 265 266 static void armada_370_xp_msi_free(struct irq_domain *domain, 267 unsigned int virq, unsigned int nr_irqs) 268 { 269 struct irq_data *d = irq_domain_get_irq_data(domain, virq); 270 271 mutex_lock(&msi_used_lock); 272 bitmap_release_region(msi_used, d->hwirq, order_base_2(nr_irqs)); 273 mutex_unlock(&msi_used_lock); 274 } 275 276 static const struct irq_domain_ops armada_370_xp_msi_domain_ops = { 277 .alloc = armada_370_xp_msi_alloc, 278 .free = armada_370_xp_msi_free, 279 }; 280 281 static void armada_370_xp_msi_reenable_percpu(void) 282 { 283 u32 reg; 284 285 /* Enable MSI doorbell mask and combined cpu local interrupt */ 286 reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS) 287 | PCI_MSI_DOORBELL_MASK; 288 writel(reg, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS); 289 /* Unmask local doorbell interrupt */ 290 writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS); 291 } 292 293 static int armada_370_xp_msi_init(struct device_node *node, 294 phys_addr_t main_int_phys_base) 295 { 296 msi_doorbell_addr = main_int_phys_base + 297 ARMADA_370_XP_SW_TRIG_INT_OFFS; 298 299 armada_370_xp_msi_inner_domain = 300 irq_domain_add_linear(NULL, PCI_MSI_DOORBELL_NR, 301 &armada_370_xp_msi_domain_ops, NULL); 302 if (!armada_370_xp_msi_inner_domain) 303 return -ENOMEM; 304 305 armada_370_xp_msi_domain = 306 pci_msi_create_irq_domain(of_node_to_fwnode(node), 307 &armada_370_xp_msi_domain_info, 308 armada_370_xp_msi_inner_domain); 309 if (!armada_370_xp_msi_domain) { 310 irq_domain_remove(armada_370_xp_msi_inner_domain); 311 return -ENOMEM; 312 } 313 314 armada_370_xp_msi_reenable_percpu(); 315 316 return 0; 317 } 318 #else 319 static void armada_370_xp_msi_reenable_percpu(void) {} 320 321 static inline int armada_370_xp_msi_init(struct device_node *node, 322 phys_addr_t main_int_phys_base) 323 { 324 return 0; 325 } 326 #endif 327 328 static void armada_xp_mpic_perf_init(void) 329 { 330 unsigned long cpuid = cpu_logical_map(smp_processor_id()); 331 332 /* Enable Performance Counter Overflow interrupts */ 333 writel(ARMADA_370_XP_INT_CAUSE_PERF(cpuid), 334 per_cpu_int_base + ARMADA_370_XP_INT_FABRIC_MASK_OFFS); 335 } 336 337 #ifdef CONFIG_SMP 338 static struct irq_domain *ipi_domain; 339 340 static void armada_370_xp_ipi_mask(struct irq_data *d) 341 { 342 u32 reg; 343 reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS); 344 reg &= ~BIT(d->hwirq); 345 writel(reg, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS); 346 } 347 348 static void armada_370_xp_ipi_unmask(struct irq_data *d) 349 { 350 u32 reg; 351 reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS); 352 reg |= BIT(d->hwirq); 353 writel(reg, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS); 354 } 355 356 static void armada_370_xp_ipi_send_mask(struct irq_data *d, 357 const struct cpumask *mask) 358 { 359 unsigned long map = 0; 360 int cpu; 361 362 /* Convert our logical CPU mask into a physical one. */ 363 for_each_cpu(cpu, mask) 364 map |= 1 << cpu_logical_map(cpu); 365 366 /* 367 * Ensure that stores to Normal memory are visible to the 368 * other CPUs before issuing the IPI. 369 */ 370 dsb(); 371 372 /* submit softirq */ 373 writel((map << 8) | d->hwirq, main_int_base + 374 ARMADA_370_XP_SW_TRIG_INT_OFFS); 375 } 376 377 static void armada_370_xp_ipi_ack(struct irq_data *d) 378 { 379 writel(~BIT(d->hwirq), per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS); 380 } 381 382 static struct irq_chip ipi_irqchip = { 383 .name = "IPI", 384 .irq_ack = armada_370_xp_ipi_ack, 385 .irq_mask = armada_370_xp_ipi_mask, 386 .irq_unmask = armada_370_xp_ipi_unmask, 387 .ipi_send_mask = armada_370_xp_ipi_send_mask, 388 }; 389 390 static int armada_370_xp_ipi_alloc(struct irq_domain *d, 391 unsigned int virq, 392 unsigned int nr_irqs, void *args) 393 { 394 int i; 395 396 for (i = 0; i < nr_irqs; i++) { 397 irq_set_percpu_devid(virq + i); 398 irq_domain_set_info(d, virq + i, i, &ipi_irqchip, 399 d->host_data, 400 handle_percpu_devid_irq, 401 NULL, NULL); 402 } 403 404 return 0; 405 } 406 407 static void armada_370_xp_ipi_free(struct irq_domain *d, 408 unsigned int virq, 409 unsigned int nr_irqs) 410 { 411 /* Not freeing IPIs */ 412 } 413 414 static const struct irq_domain_ops ipi_domain_ops = { 415 .alloc = armada_370_xp_ipi_alloc, 416 .free = armada_370_xp_ipi_free, 417 }; 418 419 static void ipi_resume(void) 420 { 421 int i; 422 423 for (i = 0; i < IPI_DOORBELL_END; i++) { 424 int irq; 425 426 irq = irq_find_mapping(ipi_domain, i); 427 if (irq <= 0) 428 continue; 429 if (irq_percpu_is_enabled(irq)) { 430 struct irq_data *d; 431 d = irq_domain_get_irq_data(ipi_domain, irq); 432 armada_370_xp_ipi_unmask(d); 433 } 434 } 435 } 436 437 static __init void armada_xp_ipi_init(struct device_node *node) 438 { 439 int base_ipi; 440 441 ipi_domain = irq_domain_create_linear(of_node_to_fwnode(node), 442 IPI_DOORBELL_END, 443 &ipi_domain_ops, NULL); 444 if (WARN_ON(!ipi_domain)) 445 return; 446 447 irq_domain_update_bus_token(ipi_domain, DOMAIN_BUS_IPI); 448 base_ipi = __irq_domain_alloc_irqs(ipi_domain, -1, IPI_DOORBELL_END, 449 NUMA_NO_NODE, NULL, false, NULL); 450 if (WARN_ON(!base_ipi)) 451 return; 452 453 set_smp_ipi_range(base_ipi, IPI_DOORBELL_END); 454 } 455 456 static DEFINE_RAW_SPINLOCK(irq_controller_lock); 457 458 static int armada_xp_set_affinity(struct irq_data *d, 459 const struct cpumask *mask_val, bool force) 460 { 461 irq_hw_number_t hwirq = irqd_to_hwirq(d); 462 unsigned long reg, mask; 463 int cpu; 464 465 /* Select a single core from the affinity mask which is online */ 466 cpu = cpumask_any_and(mask_val, cpu_online_mask); 467 mask = 1UL << cpu_logical_map(cpu); 468 469 raw_spin_lock(&irq_controller_lock); 470 reg = readl(main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq)); 471 reg = (reg & (~ARMADA_370_XP_INT_SOURCE_CPU_MASK)) | mask; 472 writel(reg, main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq)); 473 raw_spin_unlock(&irq_controller_lock); 474 475 irq_data_update_effective_affinity(d, cpumask_of(cpu)); 476 477 return IRQ_SET_MASK_OK; 478 } 479 480 static void armada_xp_mpic_smp_cpu_init(void) 481 { 482 u32 control; 483 int nr_irqs, i; 484 485 control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL); 486 nr_irqs = (control >> 2) & 0x3ff; 487 488 for (i = 0; i < nr_irqs; i++) 489 writel(i, per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK_OFFS); 490 491 /* Disable all IPIs */ 492 writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS); 493 494 /* Clear pending IPIs */ 495 writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS); 496 497 /* Unmask IPI interrupt */ 498 writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS); 499 } 500 501 static void armada_xp_mpic_reenable_percpu(void) 502 { 503 unsigned int irq; 504 505 /* Re-enable per-CPU interrupts that were enabled before suspend */ 506 for (irq = 0; irq < ARMADA_370_XP_MAX_PER_CPU_IRQS; irq++) { 507 struct irq_data *data; 508 int virq; 509 510 virq = irq_linear_revmap(armada_370_xp_mpic_domain, irq); 511 if (virq == 0) 512 continue; 513 514 data = irq_get_irq_data(virq); 515 516 if (!irq_percpu_is_enabled(virq)) 517 continue; 518 519 armada_370_xp_irq_unmask(data); 520 } 521 522 ipi_resume(); 523 524 armada_370_xp_msi_reenable_percpu(); 525 } 526 527 static int armada_xp_mpic_starting_cpu(unsigned int cpu) 528 { 529 armada_xp_mpic_perf_init(); 530 armada_xp_mpic_smp_cpu_init(); 531 armada_xp_mpic_reenable_percpu(); 532 return 0; 533 } 534 535 static int mpic_cascaded_starting_cpu(unsigned int cpu) 536 { 537 armada_xp_mpic_perf_init(); 538 armada_xp_mpic_reenable_percpu(); 539 enable_percpu_irq(parent_irq, IRQ_TYPE_NONE); 540 return 0; 541 } 542 #else 543 static void armada_xp_mpic_smp_cpu_init(void) {} 544 static void ipi_resume(void) {} 545 #endif 546 547 static struct irq_chip armada_370_xp_irq_chip = { 548 .name = "MPIC", 549 .irq_mask = armada_370_xp_irq_mask, 550 .irq_mask_ack = armada_370_xp_irq_mask, 551 .irq_unmask = armada_370_xp_irq_unmask, 552 #ifdef CONFIG_SMP 553 .irq_set_affinity = armada_xp_set_affinity, 554 #endif 555 .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND, 556 }; 557 558 static int armada_370_xp_mpic_irq_map(struct irq_domain *h, 559 unsigned int virq, irq_hw_number_t hw) 560 { 561 armada_370_xp_irq_mask(irq_get_irq_data(virq)); 562 if (!is_percpu_irq(hw)) 563 writel(hw, per_cpu_int_base + 564 ARMADA_370_XP_INT_CLEAR_MASK_OFFS); 565 else 566 writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS); 567 irq_set_status_flags(virq, IRQ_LEVEL); 568 569 if (is_percpu_irq(hw)) { 570 irq_set_percpu_devid(virq); 571 irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip, 572 handle_percpu_devid_irq); 573 } else { 574 irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip, 575 handle_level_irq); 576 irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(virq))); 577 } 578 irq_set_probe(virq); 579 580 return 0; 581 } 582 583 static const struct irq_domain_ops armada_370_xp_mpic_irq_ops = { 584 .map = armada_370_xp_mpic_irq_map, 585 .xlate = irq_domain_xlate_onecell, 586 }; 587 588 #ifdef CONFIG_PCI_MSI 589 static void armada_370_xp_handle_msi_irq(struct pt_regs *regs, bool is_chained) 590 { 591 u32 msimask, msinr; 592 593 msimask = readl_relaxed(per_cpu_int_base + 594 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS) 595 & PCI_MSI_DOORBELL_MASK; 596 597 writel(~msimask, per_cpu_int_base + 598 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS); 599 600 for (msinr = PCI_MSI_DOORBELL_START; 601 msinr < PCI_MSI_DOORBELL_END; msinr++) { 602 unsigned int irq; 603 604 if (!(msimask & BIT(msinr))) 605 continue; 606 607 irq = msinr - PCI_MSI_DOORBELL_START; 608 609 generic_handle_domain_irq(armada_370_xp_msi_inner_domain, irq); 610 } 611 } 612 #else 613 static void armada_370_xp_handle_msi_irq(struct pt_regs *r, bool b) {} 614 #endif 615 616 static void armada_370_xp_mpic_handle_cascade_irq(struct irq_desc *desc) 617 { 618 struct irq_chip *chip = irq_desc_get_chip(desc); 619 unsigned long irqmap, irqn, irqsrc, cpuid; 620 621 chained_irq_enter(chip, desc); 622 623 irqmap = readl_relaxed(per_cpu_int_base + ARMADA_375_PPI_CAUSE); 624 cpuid = cpu_logical_map(smp_processor_id()); 625 626 for_each_set_bit(irqn, &irqmap, BITS_PER_LONG) { 627 irqsrc = readl_relaxed(main_int_base + 628 ARMADA_370_XP_INT_SOURCE_CTL(irqn)); 629 630 /* Check if the interrupt is not masked on current CPU. 631 * Test IRQ (0-1) and FIQ (8-9) mask bits. 632 */ 633 if (!(irqsrc & ARMADA_370_XP_INT_IRQ_FIQ_MASK(cpuid))) 634 continue; 635 636 if (irqn == 1) { 637 armada_370_xp_handle_msi_irq(NULL, true); 638 continue; 639 } 640 641 generic_handle_domain_irq(armada_370_xp_mpic_domain, irqn); 642 } 643 644 chained_irq_exit(chip, desc); 645 } 646 647 static void __exception_irq_entry 648 armada_370_xp_handle_irq(struct pt_regs *regs) 649 { 650 u32 irqstat, irqnr; 651 652 do { 653 irqstat = readl_relaxed(per_cpu_int_base + 654 ARMADA_370_XP_CPU_INTACK_OFFS); 655 irqnr = irqstat & 0x3FF; 656 657 if (irqnr > 1022) 658 break; 659 660 if (irqnr > 1) { 661 generic_handle_domain_irq(armada_370_xp_mpic_domain, 662 irqnr); 663 continue; 664 } 665 666 /* MSI handling */ 667 if (irqnr == 1) 668 armada_370_xp_handle_msi_irq(regs, false); 669 670 #ifdef CONFIG_SMP 671 /* IPI Handling */ 672 if (irqnr == 0) { 673 unsigned long ipimask; 674 int ipi; 675 676 ipimask = readl_relaxed(per_cpu_int_base + 677 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS) 678 & IPI_DOORBELL_MASK; 679 680 for_each_set_bit(ipi, &ipimask, IPI_DOORBELL_END) 681 generic_handle_domain_irq(ipi_domain, ipi); 682 } 683 #endif 684 685 } while (1); 686 } 687 688 static int armada_370_xp_mpic_suspend(void) 689 { 690 doorbell_mask_reg = readl(per_cpu_int_base + 691 ARMADA_370_XP_IN_DRBEL_MSK_OFFS); 692 return 0; 693 } 694 695 static void armada_370_xp_mpic_resume(void) 696 { 697 int nirqs; 698 irq_hw_number_t irq; 699 700 /* Re-enable interrupts */ 701 nirqs = (readl(main_int_base + ARMADA_370_XP_INT_CONTROL) >> 2) & 0x3ff; 702 for (irq = 0; irq < nirqs; irq++) { 703 struct irq_data *data; 704 int virq; 705 706 virq = irq_linear_revmap(armada_370_xp_mpic_domain, irq); 707 if (virq == 0) 708 continue; 709 710 data = irq_get_irq_data(virq); 711 712 if (!is_percpu_irq(irq)) { 713 /* Non per-CPU interrupts */ 714 writel(irq, per_cpu_int_base + 715 ARMADA_370_XP_INT_CLEAR_MASK_OFFS); 716 if (!irqd_irq_disabled(data)) 717 armada_370_xp_irq_unmask(data); 718 } else { 719 /* Per-CPU interrupts */ 720 writel(irq, main_int_base + 721 ARMADA_370_XP_INT_SET_ENABLE_OFFS); 722 723 /* 724 * Re-enable on the current CPU, 725 * armada_xp_mpic_reenable_percpu() will take 726 * care of secondary CPUs when they come up. 727 */ 728 if (irq_percpu_is_enabled(virq)) 729 armada_370_xp_irq_unmask(data); 730 } 731 } 732 733 /* Reconfigure doorbells for IPIs and MSIs */ 734 writel(doorbell_mask_reg, 735 per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS); 736 if (doorbell_mask_reg & IPI_DOORBELL_MASK) 737 writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS); 738 if (doorbell_mask_reg & PCI_MSI_DOORBELL_MASK) 739 writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS); 740 741 ipi_resume(); 742 } 743 744 static struct syscore_ops armada_370_xp_mpic_syscore_ops = { 745 .suspend = armada_370_xp_mpic_suspend, 746 .resume = armada_370_xp_mpic_resume, 747 }; 748 749 static int __init armada_370_xp_mpic_of_init(struct device_node *node, 750 struct device_node *parent) 751 { 752 struct resource main_int_res, per_cpu_int_res; 753 int nr_irqs, i; 754 u32 control; 755 756 BUG_ON(of_address_to_resource(node, 0, &main_int_res)); 757 BUG_ON(of_address_to_resource(node, 1, &per_cpu_int_res)); 758 759 BUG_ON(!request_mem_region(main_int_res.start, 760 resource_size(&main_int_res), 761 node->full_name)); 762 BUG_ON(!request_mem_region(per_cpu_int_res.start, 763 resource_size(&per_cpu_int_res), 764 node->full_name)); 765 766 main_int_base = ioremap(main_int_res.start, 767 resource_size(&main_int_res)); 768 BUG_ON(!main_int_base); 769 770 per_cpu_int_base = ioremap(per_cpu_int_res.start, 771 resource_size(&per_cpu_int_res)); 772 BUG_ON(!per_cpu_int_base); 773 774 control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL); 775 nr_irqs = (control >> 2) & 0x3ff; 776 777 for (i = 0; i < nr_irqs; i++) 778 writel(i, main_int_base + ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS); 779 780 armada_370_xp_mpic_domain = 781 irq_domain_add_linear(node, nr_irqs, 782 &armada_370_xp_mpic_irq_ops, NULL); 783 BUG_ON(!armada_370_xp_mpic_domain); 784 irq_domain_update_bus_token(armada_370_xp_mpic_domain, DOMAIN_BUS_WIRED); 785 786 /* Setup for the boot CPU */ 787 armada_xp_mpic_perf_init(); 788 armada_xp_mpic_smp_cpu_init(); 789 790 armada_370_xp_msi_init(node, main_int_res.start); 791 792 parent_irq = irq_of_parse_and_map(node, 0); 793 if (parent_irq <= 0) { 794 irq_set_default_host(armada_370_xp_mpic_domain); 795 set_handle_irq(armada_370_xp_handle_irq); 796 #ifdef CONFIG_SMP 797 armada_xp_ipi_init(node); 798 cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_ARMADA_XP_STARTING, 799 "irqchip/armada/ipi:starting", 800 armada_xp_mpic_starting_cpu, NULL); 801 #endif 802 } else { 803 #ifdef CONFIG_SMP 804 cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_ARMADA_XP_STARTING, 805 "irqchip/armada/cascade:starting", 806 mpic_cascaded_starting_cpu, NULL); 807 #endif 808 irq_set_chained_handler(parent_irq, 809 armada_370_xp_mpic_handle_cascade_irq); 810 } 811 812 register_syscore_ops(&armada_370_xp_mpic_syscore_ops); 813 814 return 0; 815 } 816 817 IRQCHIP_DECLARE(armada_370_xp_mpic, "marvell,mpic", armada_370_xp_mpic_of_init); 818