1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright The Asahi Linux Contributors 4 * 5 * Based on irq-lpc32xx: 6 * Copyright 2015-2016 Vladimir Zapolskiy <vz@mleia.com> 7 * Based on irq-bcm2836: 8 * Copyright 2015 Broadcom 9 */ 10 11 /* 12 * AIC is a fairly simple interrupt controller with the following features: 13 * 14 * - 896 level-triggered hardware IRQs 15 * - Single mask bit per IRQ 16 * - Per-IRQ affinity setting 17 * - Automatic masking on event delivery (auto-ack) 18 * - Software triggering (ORed with hw line) 19 * - 2 per-CPU IPIs (meant as "self" and "other", but they are 20 * interchangeable if not symmetric) 21 * - Automatic prioritization (single event/ack register per CPU, lower IRQs = 22 * higher priority) 23 * - Automatic masking on ack 24 * - Default "this CPU" register view and explicit per-CPU views 25 * 26 * In addition, this driver also handles FIQs, as these are routed to the same 27 * IRQ vector. These are used for Fast IPIs, the ARMv8 timer IRQs, and 28 * performance counters (TODO). 29 * 30 * Implementation notes: 31 * 32 * - This driver creates two IRQ domains, one for HW IRQs and internal FIQs, 33 * and one for IPIs. 34 * - Since Linux needs more than 2 IPIs, we implement a software IRQ controller 35 * and funnel all IPIs into one per-CPU IPI (the second "self" IPI is unused). 36 * - FIQ hwirq numbers are assigned after true hwirqs, and are per-cpu. 37 * - DT bindings use 3-cell form (like GIC): 38 * - <0 nr flags> - hwirq #nr 39 * - <1 nr flags> - FIQ #nr 40 * - nr=0 Physical HV timer 41 * - nr=1 Virtual HV timer 42 * - nr=2 Physical guest timer 43 * - nr=3 Virtual guest timer 44 */ 45 46 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 47 48 #include <linux/bits.h> 49 #include <linux/bitfield.h> 50 #include <linux/cpuhotplug.h> 51 #include <linux/io.h> 52 #include <linux/irqchip.h> 53 #include <linux/irqchip/arm-vgic-info.h> 54 #include <linux/irqdomain.h> 55 #include <linux/jump_label.h> 56 #include <linux/limits.h> 57 #include <linux/of_address.h> 58 #include <linux/slab.h> 59 #include <asm/apple_m1_pmu.h> 60 #include <asm/cputype.h> 61 #include <asm/exception.h> 62 #include <asm/sysreg.h> 63 #include <asm/virt.h> 64 65 #include <dt-bindings/interrupt-controller/apple-aic.h> 66 67 /* 68 * AIC v1 registers (MMIO) 69 */ 70 71 #define AIC_INFO 0x0004 72 #define AIC_INFO_NR_IRQ GENMASK(15, 0) 73 74 #define AIC_CONFIG 0x0010 75 76 #define AIC_WHOAMI 0x2000 77 #define AIC_EVENT 0x2004 78 #define AIC_EVENT_DIE GENMASK(31, 24) 79 #define AIC_EVENT_TYPE GENMASK(23, 16) 80 #define AIC_EVENT_NUM GENMASK(15, 0) 81 82 #define AIC_EVENT_TYPE_FIQ 0 /* Software use */ 83 #define AIC_EVENT_TYPE_IRQ 1 84 #define AIC_EVENT_TYPE_IPI 4 85 #define AIC_EVENT_IPI_OTHER 1 86 #define AIC_EVENT_IPI_SELF 2 87 88 #define AIC_IPI_SEND 0x2008 89 #define AIC_IPI_ACK 0x200c 90 #define AIC_IPI_MASK_SET 0x2024 91 #define AIC_IPI_MASK_CLR 0x2028 92 93 #define AIC_IPI_SEND_CPU(cpu) BIT(cpu) 94 95 #define AIC_IPI_OTHER BIT(0) 96 #define AIC_IPI_SELF BIT(31) 97 98 #define AIC_TARGET_CPU 0x3000 99 100 #define AIC_CPU_IPI_SET(cpu) (0x5008 + ((cpu) << 7)) 101 #define AIC_CPU_IPI_CLR(cpu) (0x500c + ((cpu) << 7)) 102 #define AIC_CPU_IPI_MASK_SET(cpu) (0x5024 + ((cpu) << 7)) 103 #define AIC_CPU_IPI_MASK_CLR(cpu) (0x5028 + ((cpu) << 7)) 104 105 #define AIC_MAX_IRQ 0x400 106 107 /* 108 * AIC v2 registers (MMIO) 109 */ 110 111 #define AIC2_VERSION 0x0000 112 #define AIC2_VERSION_VER GENMASK(7, 0) 113 114 #define AIC2_INFO1 0x0004 115 #define AIC2_INFO1_NR_IRQ GENMASK(15, 0) 116 #define AIC2_INFO1_LAST_DIE GENMASK(27, 24) 117 118 #define AIC2_INFO2 0x0008 119 120 #define AIC2_INFO3 0x000c 121 #define AIC2_INFO3_MAX_IRQ GENMASK(15, 0) 122 #define AIC2_INFO3_MAX_DIE GENMASK(27, 24) 123 124 #define AIC2_RESET 0x0010 125 #define AIC2_RESET_RESET BIT(0) 126 127 #define AIC2_CONFIG 0x0014 128 #define AIC2_CONFIG_ENABLE BIT(0) 129 #define AIC2_CONFIG_PREFER_PCPU BIT(28) 130 131 #define AIC2_TIMEOUT 0x0028 132 #define AIC2_CLUSTER_PRIO 0x0030 133 #define AIC2_DELAY_GROUPS 0x0100 134 135 #define AIC2_IRQ_CFG 0x2000 136 137 /* 138 * AIC2 registers are laid out like this, starting at AIC2_IRQ_CFG: 139 * 140 * Repeat for each die: 141 * IRQ_CFG: u32 * MAX_IRQS 142 * SW_SET: u32 * (MAX_IRQS / 32) 143 * SW_CLR: u32 * (MAX_IRQS / 32) 144 * MASK_SET: u32 * (MAX_IRQS / 32) 145 * MASK_CLR: u32 * (MAX_IRQS / 32) 146 * HW_STATE: u32 * (MAX_IRQS / 32) 147 * 148 * This is followed by a set of event registers, each 16K page aligned. 149 * The first one is the AP event register we will use. Unfortunately, 150 * the actual implemented die count is not specified anywhere in the 151 * capability registers, so we have to explicitly specify the event 152 * register as a second reg entry in the device tree to remain 153 * forward-compatible. 154 */ 155 156 #define AIC2_IRQ_CFG_TARGET GENMASK(3, 0) 157 #define AIC2_IRQ_CFG_DELAY_IDX GENMASK(7, 5) 158 159 #define MASK_REG(x) (4 * ((x) >> 5)) 160 #define MASK_BIT(x) BIT((x) & GENMASK(4, 0)) 161 162 /* 163 * IMP-DEF sysregs that control FIQ sources 164 */ 165 166 /* IPI request registers */ 167 #define SYS_IMP_APL_IPI_RR_LOCAL_EL1 sys_reg(3, 5, 15, 0, 0) 168 #define SYS_IMP_APL_IPI_RR_GLOBAL_EL1 sys_reg(3, 5, 15, 0, 1) 169 #define IPI_RR_CPU GENMASK(7, 0) 170 /* Cluster only used for the GLOBAL register */ 171 #define IPI_RR_CLUSTER GENMASK(23, 16) 172 #define IPI_RR_TYPE GENMASK(29, 28) 173 #define IPI_RR_IMMEDIATE 0 174 #define IPI_RR_RETRACT 1 175 #define IPI_RR_DEFERRED 2 176 #define IPI_RR_NOWAKE 3 177 178 /* IPI status register */ 179 #define SYS_IMP_APL_IPI_SR_EL1 sys_reg(3, 5, 15, 1, 1) 180 #define IPI_SR_PENDING BIT(0) 181 182 /* Guest timer FIQ enable register */ 183 #define SYS_IMP_APL_VM_TMR_FIQ_ENA_EL2 sys_reg(3, 5, 15, 1, 3) 184 #define VM_TMR_FIQ_ENABLE_V BIT(0) 185 #define VM_TMR_FIQ_ENABLE_P BIT(1) 186 187 /* Deferred IPI countdown register */ 188 #define SYS_IMP_APL_IPI_CR_EL1 sys_reg(3, 5, 15, 3, 1) 189 190 /* Uncore PMC control register */ 191 #define SYS_IMP_APL_UPMCR0_EL1 sys_reg(3, 7, 15, 0, 4) 192 #define UPMCR0_IMODE GENMASK(18, 16) 193 #define UPMCR0_IMODE_OFF 0 194 #define UPMCR0_IMODE_AIC 2 195 #define UPMCR0_IMODE_HALT 3 196 #define UPMCR0_IMODE_FIQ 4 197 198 /* Uncore PMC status register */ 199 #define SYS_IMP_APL_UPMSR_EL1 sys_reg(3, 7, 15, 6, 4) 200 #define UPMSR_IACT BIT(0) 201 202 /* MPIDR fields */ 203 #define MPIDR_CPU(x) MPIDR_AFFINITY_LEVEL(x, 0) 204 #define MPIDR_CLUSTER(x) MPIDR_AFFINITY_LEVEL(x, 1) 205 206 #define AIC_IRQ_HWIRQ(die, irq) (FIELD_PREP(AIC_EVENT_DIE, die) | \ 207 FIELD_PREP(AIC_EVENT_TYPE, AIC_EVENT_TYPE_IRQ) | \ 208 FIELD_PREP(AIC_EVENT_NUM, irq)) 209 #define AIC_FIQ_HWIRQ(x) (FIELD_PREP(AIC_EVENT_TYPE, AIC_EVENT_TYPE_FIQ) | \ 210 FIELD_PREP(AIC_EVENT_NUM, x)) 211 #define AIC_HWIRQ_IRQ(x) FIELD_GET(AIC_EVENT_NUM, x) 212 #define AIC_HWIRQ_DIE(x) FIELD_GET(AIC_EVENT_DIE, x) 213 #define AIC_NR_FIQ 6 214 #define AIC_NR_SWIPI 32 215 216 /* 217 * FIQ hwirq index definitions: FIQ sources use the DT binding defines 218 * directly, except that timers are special. At the irqchip level, the 219 * two timer types are represented by their access method: _EL0 registers 220 * or _EL02 registers. In the DT binding, the timers are represented 221 * by their purpose (HV or guest). This mapping is for when the kernel is 222 * running at EL2 (with VHE). When the kernel is running at EL1, the 223 * mapping differs and aic_irq_domain_translate() performs the remapping. 224 */ 225 226 #define AIC_TMR_EL0_PHYS AIC_TMR_HV_PHYS 227 #define AIC_TMR_EL0_VIRT AIC_TMR_HV_VIRT 228 #define AIC_TMR_EL02_PHYS AIC_TMR_GUEST_PHYS 229 #define AIC_TMR_EL02_VIRT AIC_TMR_GUEST_VIRT 230 231 static DEFINE_STATIC_KEY_TRUE(use_fast_ipi); 232 233 struct aic_info { 234 int version; 235 236 /* Register offsets */ 237 u32 event; 238 u32 target_cpu; 239 u32 irq_cfg; 240 u32 sw_set; 241 u32 sw_clr; 242 u32 mask_set; 243 u32 mask_clr; 244 245 u32 die_stride; 246 247 /* Features */ 248 bool fast_ipi; 249 }; 250 251 static const struct aic_info aic1_info __initconst = { 252 .version = 1, 253 254 .event = AIC_EVENT, 255 .target_cpu = AIC_TARGET_CPU, 256 }; 257 258 static const struct aic_info aic1_fipi_info __initconst = { 259 .version = 1, 260 261 .event = AIC_EVENT, 262 .target_cpu = AIC_TARGET_CPU, 263 264 .fast_ipi = true, 265 }; 266 267 static const struct aic_info aic2_info __initconst = { 268 .version = 2, 269 270 .irq_cfg = AIC2_IRQ_CFG, 271 272 .fast_ipi = true, 273 }; 274 275 static const struct of_device_id aic_info_match[] = { 276 { 277 .compatible = "apple,t8103-aic", 278 .data = &aic1_fipi_info, 279 }, 280 { 281 .compatible = "apple,aic", 282 .data = &aic1_info, 283 }, 284 { 285 .compatible = "apple,aic2", 286 .data = &aic2_info, 287 }, 288 {} 289 }; 290 291 struct aic_irq_chip { 292 void __iomem *base; 293 void __iomem *event; 294 struct irq_domain *hw_domain; 295 struct { 296 cpumask_t aff; 297 } *fiq_aff[AIC_NR_FIQ]; 298 299 int nr_irq; 300 int max_irq; 301 int nr_die; 302 int max_die; 303 304 struct aic_info info; 305 }; 306 307 static DEFINE_PER_CPU(uint32_t, aic_fiq_unmasked); 308 309 static struct aic_irq_chip *aic_irqc; 310 311 static void aic_handle_ipi(struct pt_regs *regs); 312 313 static u32 aic_ic_read(struct aic_irq_chip *ic, u32 reg) 314 { 315 return readl_relaxed(ic->base + reg); 316 } 317 318 static void aic_ic_write(struct aic_irq_chip *ic, u32 reg, u32 val) 319 { 320 writel_relaxed(val, ic->base + reg); 321 } 322 323 /* 324 * IRQ irqchip 325 */ 326 327 static void aic_irq_mask(struct irq_data *d) 328 { 329 irq_hw_number_t hwirq = irqd_to_hwirq(d); 330 struct aic_irq_chip *ic = irq_data_get_irq_chip_data(d); 331 332 u32 off = AIC_HWIRQ_DIE(hwirq) * ic->info.die_stride; 333 u32 irq = AIC_HWIRQ_IRQ(hwirq); 334 335 aic_ic_write(ic, ic->info.mask_set + off + MASK_REG(irq), MASK_BIT(irq)); 336 } 337 338 static void aic_irq_unmask(struct irq_data *d) 339 { 340 irq_hw_number_t hwirq = irqd_to_hwirq(d); 341 struct aic_irq_chip *ic = irq_data_get_irq_chip_data(d); 342 343 u32 off = AIC_HWIRQ_DIE(hwirq) * ic->info.die_stride; 344 u32 irq = AIC_HWIRQ_IRQ(hwirq); 345 346 aic_ic_write(ic, ic->info.mask_clr + off + MASK_REG(irq), MASK_BIT(irq)); 347 } 348 349 static void aic_irq_eoi(struct irq_data *d) 350 { 351 /* 352 * Reading the interrupt reason automatically acknowledges and masks 353 * the IRQ, so we just unmask it here if needed. 354 */ 355 if (!irqd_irq_masked(d)) 356 aic_irq_unmask(d); 357 } 358 359 static void __exception_irq_entry aic_handle_irq(struct pt_regs *regs) 360 { 361 struct aic_irq_chip *ic = aic_irqc; 362 u32 event, type, irq; 363 364 do { 365 /* 366 * We cannot use a relaxed read here, as reads from DMA buffers 367 * need to be ordered after the IRQ fires. 368 */ 369 event = readl(ic->event + ic->info.event); 370 type = FIELD_GET(AIC_EVENT_TYPE, event); 371 irq = FIELD_GET(AIC_EVENT_NUM, event); 372 373 if (type == AIC_EVENT_TYPE_IRQ) 374 generic_handle_domain_irq(aic_irqc->hw_domain, event); 375 else if (type == AIC_EVENT_TYPE_IPI && irq == 1) 376 aic_handle_ipi(regs); 377 else if (event != 0) 378 pr_err_ratelimited("Unknown IRQ event %d, %d\n", type, irq); 379 } while (event); 380 381 /* 382 * vGIC maintenance interrupts end up here too, so we need to check 383 * for them separately. This should never trigger if KVM is working 384 * properly, because it will have already taken care of clearing it 385 * on guest exit before this handler runs. 386 */ 387 if (is_kernel_in_hyp_mode() && (read_sysreg_s(SYS_ICH_HCR_EL2) & ICH_HCR_EN) && 388 read_sysreg_s(SYS_ICH_MISR_EL2) != 0) { 389 pr_err_ratelimited("vGIC IRQ fired and not handled by KVM, disabling.\n"); 390 sysreg_clear_set_s(SYS_ICH_HCR_EL2, ICH_HCR_EN, 0); 391 } 392 } 393 394 static int aic_irq_set_affinity(struct irq_data *d, 395 const struct cpumask *mask_val, bool force) 396 { 397 irq_hw_number_t hwirq = irqd_to_hwirq(d); 398 struct aic_irq_chip *ic = irq_data_get_irq_chip_data(d); 399 int cpu; 400 401 BUG_ON(!ic->info.target_cpu); 402 403 if (force) 404 cpu = cpumask_first(mask_val); 405 else 406 cpu = cpumask_any_and(mask_val, cpu_online_mask); 407 408 aic_ic_write(ic, ic->info.target_cpu + AIC_HWIRQ_IRQ(hwirq) * 4, BIT(cpu)); 409 irq_data_update_effective_affinity(d, cpumask_of(cpu)); 410 411 return IRQ_SET_MASK_OK; 412 } 413 414 static int aic_irq_set_type(struct irq_data *d, unsigned int type) 415 { 416 /* 417 * Some IRQs (e.g. MSIs) implicitly have edge semantics, and we don't 418 * have a way to find out the type of any given IRQ, so just allow both. 419 */ 420 return (type == IRQ_TYPE_LEVEL_HIGH || type == IRQ_TYPE_EDGE_RISING) ? 0 : -EINVAL; 421 } 422 423 static struct irq_chip aic_chip = { 424 .name = "AIC", 425 .irq_mask = aic_irq_mask, 426 .irq_unmask = aic_irq_unmask, 427 .irq_eoi = aic_irq_eoi, 428 .irq_set_affinity = aic_irq_set_affinity, 429 .irq_set_type = aic_irq_set_type, 430 }; 431 432 static struct irq_chip aic2_chip = { 433 .name = "AIC2", 434 .irq_mask = aic_irq_mask, 435 .irq_unmask = aic_irq_unmask, 436 .irq_eoi = aic_irq_eoi, 437 .irq_set_type = aic_irq_set_type, 438 }; 439 440 /* 441 * FIQ irqchip 442 */ 443 444 static unsigned long aic_fiq_get_idx(struct irq_data *d) 445 { 446 return AIC_HWIRQ_IRQ(irqd_to_hwirq(d)); 447 } 448 449 static void aic_fiq_set_mask(struct irq_data *d) 450 { 451 /* Only the guest timers have real mask bits, unfortunately. */ 452 switch (aic_fiq_get_idx(d)) { 453 case AIC_TMR_EL02_PHYS: 454 sysreg_clear_set_s(SYS_IMP_APL_VM_TMR_FIQ_ENA_EL2, VM_TMR_FIQ_ENABLE_P, 0); 455 isb(); 456 break; 457 case AIC_TMR_EL02_VIRT: 458 sysreg_clear_set_s(SYS_IMP_APL_VM_TMR_FIQ_ENA_EL2, VM_TMR_FIQ_ENABLE_V, 0); 459 isb(); 460 break; 461 default: 462 break; 463 } 464 } 465 466 static void aic_fiq_clear_mask(struct irq_data *d) 467 { 468 switch (aic_fiq_get_idx(d)) { 469 case AIC_TMR_EL02_PHYS: 470 sysreg_clear_set_s(SYS_IMP_APL_VM_TMR_FIQ_ENA_EL2, 0, VM_TMR_FIQ_ENABLE_P); 471 isb(); 472 break; 473 case AIC_TMR_EL02_VIRT: 474 sysreg_clear_set_s(SYS_IMP_APL_VM_TMR_FIQ_ENA_EL2, 0, VM_TMR_FIQ_ENABLE_V); 475 isb(); 476 break; 477 default: 478 break; 479 } 480 } 481 482 static void aic_fiq_mask(struct irq_data *d) 483 { 484 aic_fiq_set_mask(d); 485 __this_cpu_and(aic_fiq_unmasked, ~BIT(aic_fiq_get_idx(d))); 486 } 487 488 static void aic_fiq_unmask(struct irq_data *d) 489 { 490 aic_fiq_clear_mask(d); 491 __this_cpu_or(aic_fiq_unmasked, BIT(aic_fiq_get_idx(d))); 492 } 493 494 static void aic_fiq_eoi(struct irq_data *d) 495 { 496 /* We mask to ack (where we can), so we need to unmask at EOI. */ 497 if (__this_cpu_read(aic_fiq_unmasked) & BIT(aic_fiq_get_idx(d))) 498 aic_fiq_clear_mask(d); 499 } 500 501 #define TIMER_FIRING(x) \ 502 (((x) & (ARCH_TIMER_CTRL_ENABLE | ARCH_TIMER_CTRL_IT_MASK | \ 503 ARCH_TIMER_CTRL_IT_STAT)) == \ 504 (ARCH_TIMER_CTRL_ENABLE | ARCH_TIMER_CTRL_IT_STAT)) 505 506 static void __exception_irq_entry aic_handle_fiq(struct pt_regs *regs) 507 { 508 /* 509 * It would be really nice if we had a system register that lets us get 510 * the FIQ source state without having to peek down into sources... 511 * but such a register does not seem to exist. 512 * 513 * So, we have these potential sources to test for: 514 * - Fast IPIs (not yet used) 515 * - The 4 timers (CNTP, CNTV for each of HV and guest) 516 * - Per-core PMCs (not yet supported) 517 * - Per-cluster uncore PMCs (not yet supported) 518 * 519 * Since not dealing with any of these results in a FIQ storm, 520 * we check for everything here, even things we don't support yet. 521 */ 522 523 if (read_sysreg_s(SYS_IMP_APL_IPI_SR_EL1) & IPI_SR_PENDING) { 524 if (static_branch_likely(&use_fast_ipi)) { 525 aic_handle_ipi(regs); 526 } else { 527 pr_err_ratelimited("Fast IPI fired. Acking.\n"); 528 write_sysreg_s(IPI_SR_PENDING, SYS_IMP_APL_IPI_SR_EL1); 529 } 530 } 531 532 if (TIMER_FIRING(read_sysreg(cntp_ctl_el0))) 533 generic_handle_domain_irq(aic_irqc->hw_domain, 534 AIC_FIQ_HWIRQ(AIC_TMR_EL0_PHYS)); 535 536 if (TIMER_FIRING(read_sysreg(cntv_ctl_el0))) 537 generic_handle_domain_irq(aic_irqc->hw_domain, 538 AIC_FIQ_HWIRQ(AIC_TMR_EL0_VIRT)); 539 540 if (is_kernel_in_hyp_mode()) { 541 uint64_t enabled = read_sysreg_s(SYS_IMP_APL_VM_TMR_FIQ_ENA_EL2); 542 543 if ((enabled & VM_TMR_FIQ_ENABLE_P) && 544 TIMER_FIRING(read_sysreg_s(SYS_CNTP_CTL_EL02))) 545 generic_handle_domain_irq(aic_irqc->hw_domain, 546 AIC_FIQ_HWIRQ(AIC_TMR_EL02_PHYS)); 547 548 if ((enabled & VM_TMR_FIQ_ENABLE_V) && 549 TIMER_FIRING(read_sysreg_s(SYS_CNTV_CTL_EL02))) 550 generic_handle_domain_irq(aic_irqc->hw_domain, 551 AIC_FIQ_HWIRQ(AIC_TMR_EL02_VIRT)); 552 } 553 554 if (read_sysreg_s(SYS_IMP_APL_PMCR0_EL1) & PMCR0_IACT) { 555 int irq; 556 if (cpumask_test_cpu(smp_processor_id(), 557 &aic_irqc->fiq_aff[AIC_CPU_PMU_P]->aff)) 558 irq = AIC_CPU_PMU_P; 559 else 560 irq = AIC_CPU_PMU_E; 561 generic_handle_domain_irq(aic_irqc->hw_domain, 562 AIC_FIQ_HWIRQ(irq)); 563 } 564 565 if (FIELD_GET(UPMCR0_IMODE, read_sysreg_s(SYS_IMP_APL_UPMCR0_EL1)) == UPMCR0_IMODE_FIQ && 566 (read_sysreg_s(SYS_IMP_APL_UPMSR_EL1) & UPMSR_IACT)) { 567 /* Same story with uncore PMCs */ 568 pr_err_ratelimited("Uncore PMC FIQ fired. Masking.\n"); 569 sysreg_clear_set_s(SYS_IMP_APL_UPMCR0_EL1, UPMCR0_IMODE, 570 FIELD_PREP(UPMCR0_IMODE, UPMCR0_IMODE_OFF)); 571 } 572 } 573 574 static int aic_fiq_set_type(struct irq_data *d, unsigned int type) 575 { 576 return (type == IRQ_TYPE_LEVEL_HIGH) ? 0 : -EINVAL; 577 } 578 579 static struct irq_chip fiq_chip = { 580 .name = "AIC-FIQ", 581 .irq_mask = aic_fiq_mask, 582 .irq_unmask = aic_fiq_unmask, 583 .irq_ack = aic_fiq_set_mask, 584 .irq_eoi = aic_fiq_eoi, 585 .irq_set_type = aic_fiq_set_type, 586 }; 587 588 /* 589 * Main IRQ domain 590 */ 591 592 static int aic_irq_domain_map(struct irq_domain *id, unsigned int irq, 593 irq_hw_number_t hw) 594 { 595 struct aic_irq_chip *ic = id->host_data; 596 u32 type = FIELD_GET(AIC_EVENT_TYPE, hw); 597 struct irq_chip *chip = &aic_chip; 598 599 if (ic->info.version == 2) 600 chip = &aic2_chip; 601 602 if (type == AIC_EVENT_TYPE_IRQ) { 603 irq_domain_set_info(id, irq, hw, chip, id->host_data, 604 handle_fasteoi_irq, NULL, NULL); 605 irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(irq))); 606 } else { 607 int fiq = FIELD_GET(AIC_EVENT_NUM, hw); 608 609 switch (fiq) { 610 case AIC_CPU_PMU_P: 611 case AIC_CPU_PMU_E: 612 irq_set_percpu_devid_partition(irq, &ic->fiq_aff[fiq]->aff); 613 break; 614 default: 615 irq_set_percpu_devid(irq); 616 break; 617 } 618 619 irq_domain_set_info(id, irq, hw, &fiq_chip, id->host_data, 620 handle_percpu_devid_irq, NULL, NULL); 621 } 622 623 return 0; 624 } 625 626 static int aic_irq_domain_translate(struct irq_domain *id, 627 struct irq_fwspec *fwspec, 628 unsigned long *hwirq, 629 unsigned int *type) 630 { 631 struct aic_irq_chip *ic = id->host_data; 632 u32 *args; 633 u32 die = 0; 634 635 if (fwspec->param_count < 3 || fwspec->param_count > 4 || 636 !is_of_node(fwspec->fwnode)) 637 return -EINVAL; 638 639 args = &fwspec->param[1]; 640 641 if (fwspec->param_count == 4) { 642 die = args[0]; 643 args++; 644 } 645 646 switch (fwspec->param[0]) { 647 case AIC_IRQ: 648 if (die >= ic->nr_die) 649 return -EINVAL; 650 if (args[0] >= ic->nr_irq) 651 return -EINVAL; 652 *hwirq = AIC_IRQ_HWIRQ(die, args[0]); 653 break; 654 case AIC_FIQ: 655 if (die != 0) 656 return -EINVAL; 657 if (args[0] >= AIC_NR_FIQ) 658 return -EINVAL; 659 *hwirq = AIC_FIQ_HWIRQ(args[0]); 660 661 /* 662 * In EL1 the non-redirected registers are the guest's, 663 * not EL2's, so remap the hwirqs to match. 664 */ 665 if (!is_kernel_in_hyp_mode()) { 666 switch (args[0]) { 667 case AIC_TMR_GUEST_PHYS: 668 *hwirq = AIC_FIQ_HWIRQ(AIC_TMR_EL0_PHYS); 669 break; 670 case AIC_TMR_GUEST_VIRT: 671 *hwirq = AIC_FIQ_HWIRQ(AIC_TMR_EL0_VIRT); 672 break; 673 case AIC_TMR_HV_PHYS: 674 case AIC_TMR_HV_VIRT: 675 return -ENOENT; 676 default: 677 break; 678 } 679 } 680 break; 681 default: 682 return -EINVAL; 683 } 684 685 *type = args[1] & IRQ_TYPE_SENSE_MASK; 686 687 return 0; 688 } 689 690 static int aic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, 691 unsigned int nr_irqs, void *arg) 692 { 693 unsigned int type = IRQ_TYPE_NONE; 694 struct irq_fwspec *fwspec = arg; 695 irq_hw_number_t hwirq; 696 int i, ret; 697 698 ret = aic_irq_domain_translate(domain, fwspec, &hwirq, &type); 699 if (ret) 700 return ret; 701 702 for (i = 0; i < nr_irqs; i++) { 703 ret = aic_irq_domain_map(domain, virq + i, hwirq + i); 704 if (ret) 705 return ret; 706 } 707 708 return 0; 709 } 710 711 static void aic_irq_domain_free(struct irq_domain *domain, unsigned int virq, 712 unsigned int nr_irqs) 713 { 714 int i; 715 716 for (i = 0; i < nr_irqs; i++) { 717 struct irq_data *d = irq_domain_get_irq_data(domain, virq + i); 718 719 irq_set_handler(virq + i, NULL); 720 irq_domain_reset_irq_data(d); 721 } 722 } 723 724 static const struct irq_domain_ops aic_irq_domain_ops = { 725 .translate = aic_irq_domain_translate, 726 .alloc = aic_irq_domain_alloc, 727 .free = aic_irq_domain_free, 728 }; 729 730 /* 731 * IPI irqchip 732 */ 733 734 static void aic_ipi_send_fast(int cpu) 735 { 736 u64 mpidr = cpu_logical_map(cpu); 737 u64 my_mpidr = read_cpuid_mpidr(); 738 u64 cluster = MPIDR_CLUSTER(mpidr); 739 u64 idx = MPIDR_CPU(mpidr); 740 741 if (MPIDR_CLUSTER(my_mpidr) == cluster) 742 write_sysreg_s(FIELD_PREP(IPI_RR_CPU, idx), 743 SYS_IMP_APL_IPI_RR_LOCAL_EL1); 744 else 745 write_sysreg_s(FIELD_PREP(IPI_RR_CPU, idx) | FIELD_PREP(IPI_RR_CLUSTER, cluster), 746 SYS_IMP_APL_IPI_RR_GLOBAL_EL1); 747 isb(); 748 } 749 750 static void aic_handle_ipi(struct pt_regs *regs) 751 { 752 /* 753 * Ack the IPI. We need to order this after the AIC event read, but 754 * that is enforced by normal MMIO ordering guarantees. 755 * 756 * For the Fast IPI case, this needs to be ordered before the vIPI 757 * handling below, so we need to isb(); 758 */ 759 if (static_branch_likely(&use_fast_ipi)) { 760 write_sysreg_s(IPI_SR_PENDING, SYS_IMP_APL_IPI_SR_EL1); 761 isb(); 762 } else { 763 aic_ic_write(aic_irqc, AIC_IPI_ACK, AIC_IPI_OTHER); 764 } 765 766 ipi_mux_process(); 767 768 /* 769 * No ordering needed here; at worst this just changes the timing of 770 * when the next IPI will be delivered. 771 */ 772 if (!static_branch_likely(&use_fast_ipi)) 773 aic_ic_write(aic_irqc, AIC_IPI_MASK_CLR, AIC_IPI_OTHER); 774 } 775 776 static void aic_ipi_send_single(unsigned int cpu) 777 { 778 if (static_branch_likely(&use_fast_ipi)) 779 aic_ipi_send_fast(cpu); 780 else 781 aic_ic_write(aic_irqc, AIC_IPI_SEND, AIC_IPI_SEND_CPU(cpu)); 782 } 783 784 static int __init aic_init_smp(struct aic_irq_chip *irqc, struct device_node *node) 785 { 786 int base_ipi; 787 788 base_ipi = ipi_mux_create(AIC_NR_SWIPI, aic_ipi_send_single); 789 if (WARN_ON(base_ipi <= 0)) 790 return -ENODEV; 791 792 set_smp_ipi_range(base_ipi, AIC_NR_SWIPI); 793 794 return 0; 795 } 796 797 static int aic_init_cpu(unsigned int cpu) 798 { 799 /* Mask all hard-wired per-CPU IRQ/FIQ sources */ 800 801 /* Pending Fast IPI FIQs */ 802 write_sysreg_s(IPI_SR_PENDING, SYS_IMP_APL_IPI_SR_EL1); 803 804 /* Timer FIQs */ 805 sysreg_clear_set(cntp_ctl_el0, 0, ARCH_TIMER_CTRL_IT_MASK); 806 sysreg_clear_set(cntv_ctl_el0, 0, ARCH_TIMER_CTRL_IT_MASK); 807 808 /* EL2-only (VHE mode) IRQ sources */ 809 if (is_kernel_in_hyp_mode()) { 810 /* Guest timers */ 811 sysreg_clear_set_s(SYS_IMP_APL_VM_TMR_FIQ_ENA_EL2, 812 VM_TMR_FIQ_ENABLE_V | VM_TMR_FIQ_ENABLE_P, 0); 813 814 /* vGIC maintenance IRQ */ 815 sysreg_clear_set_s(SYS_ICH_HCR_EL2, ICH_HCR_EN, 0); 816 } 817 818 /* PMC FIQ */ 819 sysreg_clear_set_s(SYS_IMP_APL_PMCR0_EL1, PMCR0_IMODE | PMCR0_IACT, 820 FIELD_PREP(PMCR0_IMODE, PMCR0_IMODE_OFF)); 821 822 /* Uncore PMC FIQ */ 823 sysreg_clear_set_s(SYS_IMP_APL_UPMCR0_EL1, UPMCR0_IMODE, 824 FIELD_PREP(UPMCR0_IMODE, UPMCR0_IMODE_OFF)); 825 826 /* Commit all of the above */ 827 isb(); 828 829 if (aic_irqc->info.version == 1) { 830 /* 831 * Make sure the kernel's idea of logical CPU order is the same as AIC's 832 * If we ever end up with a mismatch here, we will have to introduce 833 * a mapping table similar to what other irqchip drivers do. 834 */ 835 WARN_ON(aic_ic_read(aic_irqc, AIC_WHOAMI) != smp_processor_id()); 836 837 /* 838 * Always keep IPIs unmasked at the hardware level (except auto-masking 839 * by AIC during processing). We manage masks at the vIPI level. 840 * These registers only exist on AICv1, AICv2 always uses fast IPIs. 841 */ 842 aic_ic_write(aic_irqc, AIC_IPI_ACK, AIC_IPI_SELF | AIC_IPI_OTHER); 843 if (static_branch_likely(&use_fast_ipi)) { 844 aic_ic_write(aic_irqc, AIC_IPI_MASK_SET, AIC_IPI_SELF | AIC_IPI_OTHER); 845 } else { 846 aic_ic_write(aic_irqc, AIC_IPI_MASK_SET, AIC_IPI_SELF); 847 aic_ic_write(aic_irqc, AIC_IPI_MASK_CLR, AIC_IPI_OTHER); 848 } 849 } 850 851 /* Initialize the local mask state */ 852 __this_cpu_write(aic_fiq_unmasked, 0); 853 854 return 0; 855 } 856 857 static struct gic_kvm_info vgic_info __initdata = { 858 .type = GIC_V3, 859 .no_maint_irq_mask = true, 860 .no_hw_deactivation = true, 861 }; 862 863 static void build_fiq_affinity(struct aic_irq_chip *ic, struct device_node *aff) 864 { 865 int i, n; 866 u32 fiq; 867 868 if (of_property_read_u32(aff, "apple,fiq-index", &fiq) || 869 WARN_ON(fiq >= AIC_NR_FIQ) || ic->fiq_aff[fiq]) 870 return; 871 872 n = of_property_count_elems_of_size(aff, "cpus", sizeof(u32)); 873 if (WARN_ON(n < 0)) 874 return; 875 876 ic->fiq_aff[fiq] = kzalloc(sizeof(*ic->fiq_aff[fiq]), GFP_KERNEL); 877 if (!ic->fiq_aff[fiq]) 878 return; 879 880 for (i = 0; i < n; i++) { 881 struct device_node *cpu_node; 882 u32 cpu_phandle; 883 int cpu; 884 885 if (of_property_read_u32_index(aff, "cpus", i, &cpu_phandle)) 886 continue; 887 888 cpu_node = of_find_node_by_phandle(cpu_phandle); 889 if (WARN_ON(!cpu_node)) 890 continue; 891 892 cpu = of_cpu_node_to_id(cpu_node); 893 of_node_put(cpu_node); 894 if (WARN_ON(cpu < 0)) 895 continue; 896 897 cpumask_set_cpu(cpu, &ic->fiq_aff[fiq]->aff); 898 } 899 } 900 901 static int __init aic_of_ic_init(struct device_node *node, struct device_node *parent) 902 { 903 int i, die; 904 u32 off, start_off; 905 void __iomem *regs; 906 struct aic_irq_chip *irqc; 907 struct device_node *affs; 908 const struct of_device_id *match; 909 910 regs = of_iomap(node, 0); 911 if (WARN_ON(!regs)) 912 return -EIO; 913 914 irqc = kzalloc(sizeof(*irqc), GFP_KERNEL); 915 if (!irqc) { 916 iounmap(regs); 917 return -ENOMEM; 918 } 919 920 irqc->base = regs; 921 922 match = of_match_node(aic_info_match, node); 923 if (!match) 924 goto err_unmap; 925 926 irqc->info = *(struct aic_info *)match->data; 927 928 aic_irqc = irqc; 929 930 switch (irqc->info.version) { 931 case 1: { 932 u32 info; 933 934 info = aic_ic_read(irqc, AIC_INFO); 935 irqc->nr_irq = FIELD_GET(AIC_INFO_NR_IRQ, info); 936 irqc->max_irq = AIC_MAX_IRQ; 937 irqc->nr_die = irqc->max_die = 1; 938 939 off = start_off = irqc->info.target_cpu; 940 off += sizeof(u32) * irqc->max_irq; /* TARGET_CPU */ 941 942 irqc->event = irqc->base; 943 944 break; 945 } 946 case 2: { 947 u32 info1, info3; 948 949 info1 = aic_ic_read(irqc, AIC2_INFO1); 950 info3 = aic_ic_read(irqc, AIC2_INFO3); 951 952 irqc->nr_irq = FIELD_GET(AIC2_INFO1_NR_IRQ, info1); 953 irqc->max_irq = FIELD_GET(AIC2_INFO3_MAX_IRQ, info3); 954 irqc->nr_die = FIELD_GET(AIC2_INFO1_LAST_DIE, info1) + 1; 955 irqc->max_die = FIELD_GET(AIC2_INFO3_MAX_DIE, info3); 956 957 off = start_off = irqc->info.irq_cfg; 958 off += sizeof(u32) * irqc->max_irq; /* IRQ_CFG */ 959 960 irqc->event = of_iomap(node, 1); 961 if (WARN_ON(!irqc->event)) 962 goto err_unmap; 963 964 break; 965 } 966 } 967 968 irqc->info.sw_set = off; 969 off += sizeof(u32) * (irqc->max_irq >> 5); /* SW_SET */ 970 irqc->info.sw_clr = off; 971 off += sizeof(u32) * (irqc->max_irq >> 5); /* SW_CLR */ 972 irqc->info.mask_set = off; 973 off += sizeof(u32) * (irqc->max_irq >> 5); /* MASK_SET */ 974 irqc->info.mask_clr = off; 975 off += sizeof(u32) * (irqc->max_irq >> 5); /* MASK_CLR */ 976 off += sizeof(u32) * (irqc->max_irq >> 5); /* HW_STATE */ 977 978 if (irqc->info.fast_ipi) 979 static_branch_enable(&use_fast_ipi); 980 else 981 static_branch_disable(&use_fast_ipi); 982 983 irqc->info.die_stride = off - start_off; 984 985 irqc->hw_domain = irq_domain_create_tree(of_node_to_fwnode(node), 986 &aic_irq_domain_ops, irqc); 987 if (WARN_ON(!irqc->hw_domain)) 988 goto err_unmap; 989 990 irq_domain_update_bus_token(irqc->hw_domain, DOMAIN_BUS_WIRED); 991 992 if (aic_init_smp(irqc, node)) 993 goto err_remove_domain; 994 995 affs = of_get_child_by_name(node, "affinities"); 996 if (affs) { 997 struct device_node *chld; 998 999 for_each_child_of_node(affs, chld) 1000 build_fiq_affinity(irqc, chld); 1001 } 1002 of_node_put(affs); 1003 1004 set_handle_irq(aic_handle_irq); 1005 set_handle_fiq(aic_handle_fiq); 1006 1007 off = 0; 1008 for (die = 0; die < irqc->nr_die; die++) { 1009 for (i = 0; i < BITS_TO_U32(irqc->nr_irq); i++) 1010 aic_ic_write(irqc, irqc->info.mask_set + off + i * 4, U32_MAX); 1011 for (i = 0; i < BITS_TO_U32(irqc->nr_irq); i++) 1012 aic_ic_write(irqc, irqc->info.sw_clr + off + i * 4, U32_MAX); 1013 if (irqc->info.target_cpu) 1014 for (i = 0; i < irqc->nr_irq; i++) 1015 aic_ic_write(irqc, irqc->info.target_cpu + off + i * 4, 1); 1016 off += irqc->info.die_stride; 1017 } 1018 1019 if (irqc->info.version == 2) { 1020 u32 config = aic_ic_read(irqc, AIC2_CONFIG); 1021 1022 config |= AIC2_CONFIG_ENABLE; 1023 aic_ic_write(irqc, AIC2_CONFIG, config); 1024 } 1025 1026 if (!is_kernel_in_hyp_mode()) 1027 pr_info("Kernel running in EL1, mapping interrupts"); 1028 1029 if (static_branch_likely(&use_fast_ipi)) 1030 pr_info("Using Fast IPIs"); 1031 1032 cpuhp_setup_state(CPUHP_AP_IRQ_APPLE_AIC_STARTING, 1033 "irqchip/apple-aic/ipi:starting", 1034 aic_init_cpu, NULL); 1035 1036 vgic_set_kvm_info(&vgic_info); 1037 1038 pr_info("Initialized with %d/%d IRQs * %d/%d die(s), %d FIQs, %d vIPIs", 1039 irqc->nr_irq, irqc->max_irq, irqc->nr_die, irqc->max_die, AIC_NR_FIQ, AIC_NR_SWIPI); 1040 1041 return 0; 1042 1043 err_remove_domain: 1044 irq_domain_remove(irqc->hw_domain); 1045 err_unmap: 1046 if (irqc->event && irqc->event != irqc->base) 1047 iounmap(irqc->event); 1048 iounmap(irqc->base); 1049 kfree(irqc); 1050 return -ENODEV; 1051 } 1052 1053 IRQCHIP_DECLARE(apple_aic, "apple,aic", aic_of_ic_init); 1054 IRQCHIP_DECLARE(apple_aic2, "apple,aic2", aic_of_ic_init); 1055