1 /* 2 * Copyright (C) 2014 Oleksij Rempel <linux@rempel-privat.de> 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 */ 9 10 #ifndef _ALPHASCALE_ASM9260_ICOLL_H 11 #define _ALPHASCALE_ASM9260_ICOLL_H 12 13 #define ASM9260_NUM_IRQS 64 14 /* 15 * this device provide 4 offsets for each register: 16 * 0x0 - plain read write mode 17 * 0x4 - set mode, OR logic. 18 * 0x8 - clr mode, XOR logic. 19 * 0xc - togle mode. 20 */ 21 22 #define ASM9260_HW_ICOLL_VECTOR 0x0000 23 /* 24 * bits 31:2 25 * This register presents the vector address for the interrupt currently 26 * active on the CPU IRQ input. Writing to this register notifies the 27 * interrupt collector that the interrupt service routine for the current 28 * interrupt has been entered. 29 * The exception trap should have a LDPC instruction from this address: 30 * LDPC ASM9260_HW_ICOLL_VECTOR_ADDR; IRQ exception at 0xffff0018 31 */ 32 33 /* 34 * The Interrupt Collector Level Acknowledge Register is used by software to 35 * indicate the completion of an interrupt on a specific level. 36 * This register is written at the very end of an interrupt service routine. If 37 * nesting is used then the CPU irq must be turned on before writing to this 38 * register to avoid a race condition in the CPU interrupt hardware. 39 */ 40 #define ASM9260_HW_ICOLL_LEVELACK 0x0010 41 #define ASM9260_BM_LEVELn(nr) BIT(nr) 42 43 #define ASM9260_HW_ICOLL_CTRL 0x0020 44 /* 45 * ASM9260_BM_CTRL_SFTRST and ASM9260_BM_CTRL_CLKGATE are not available on 46 * asm9260. 47 */ 48 #define ASM9260_BM_CTRL_SFTRST BIT(31) 49 #define ASM9260_BM_CTRL_CLKGATE BIT(30) 50 /* disable interrupt level nesting */ 51 #define ASM9260_BM_CTRL_NO_NESTING BIT(19) 52 /* 53 * Set this bit to one enable the RISC32-style read side effect associated with 54 * the vector address register. In this mode, interrupt in-service is signaled 55 * by the read of the ASM9260_HW_ICOLL_VECTOR register to acquire the interrupt 56 * vector address. Set this bit to zero for normal operation, in which the ISR 57 * signals in-service explicitly by means of a write to the 58 * ASM9260_HW_ICOLL_VECTOR register. 59 * 0 - Must Write to Vector register to go in-service. 60 * 1 - Go in-service as a read side effect 61 */ 62 #define ASM9260_BM_CTRL_ARM_RSE_MODE BIT(18) 63 #define ASM9260_BM_CTRL_IRQ_ENABLE BIT(16) 64 65 #define ASM9260_HW_ICOLL_STAT_OFFSET 0x0030 66 /* 67 * bits 5:0 68 * Vector number of current interrupt. Multiply by 4 and add to vector base 69 * address to obtain the value in ASM9260_HW_ICOLL_VECTOR. 70 */ 71 72 /* 73 * RAW0 and RAW1 provides a read-only view of the raw interrupt request lines 74 * coming from various parts of the chip. Its purpose is to improve diagnostic 75 * observability. 76 */ 77 #define ASM9260_HW_ICOLL_RAW0 0x0040 78 #define ASM9260_HW_ICOLL_RAW1 0x0050 79 80 #define ASM9260_HW_ICOLL_INTERRUPT0 0x0060 81 #define ASM9260_HW_ICOLL_INTERRUPTn(n) (0x0060 + ((n) >> 2) * 0x10) 82 /* 83 * WARNING: Modifying the priority of an enabled interrupt may result in 84 * undefined behavior. 85 */ 86 #define ASM9260_BM_INT_PRIORITY_MASK 0x3 87 #define ASM9260_BM_INT_ENABLE BIT(2) 88 #define ASM9260_BM_INT_SOFTIRQ BIT(3) 89 90 #define ASM9260_BM_ICOLL_INTERRUPTn_SHIFT(n) (((n) & 0x3) << 3) 91 #define ASM9260_BM_ICOLL_INTERRUPTn_ENABLE(n) (1 << (2 + \ 92 ASM9260_BM_ICOLL_INTERRUPTn_SHIFT(n))) 93 94 #define ASM9260_HW_ICOLL_VBASE 0x0160 95 /* 96 * bits 31:2 97 * This bitfield holds the upper 30 bits of the base address of the vector 98 * table. 99 */ 100 101 #define ASM9260_HW_ICOLL_CLEAR0 0x01d0 102 #define ASM9260_HW_ICOLL_CLEAR1 0x01e0 103 #define ASM9260_HW_ICOLL_CLEARn(n) (((n >> 5) * 0x10) \ 104 + SET_REG) 105 #define ASM9260_BM_CLEAR_BIT(n) BIT(n & 0x1f) 106 107 /* Scratchpad */ 108 #define ASM9260_HW_ICOLL_UNDEF_VECTOR 0x01f0 109 #endif 110