1config IRQCHIP 2 def_bool y 3 depends on OF_IRQ 4 5config ARM_GIC 6 bool 7 select IRQ_DOMAIN 8 select IRQ_DOMAIN_HIERARCHY 9 select MULTI_IRQ_HANDLER 10 11config ARM_GIC_PM 12 bool 13 depends on PM 14 select ARM_GIC 15 select PM_CLK 16 17config ARM_GIC_MAX_NR 18 int 19 default 2 if ARCH_REALVIEW 20 default 1 21 22config ARM_GIC_V2M 23 bool 24 depends on PCI 25 select ARM_GIC 26 select PCI_MSI 27 28config GIC_NON_BANKED 29 bool 30 31config ARM_GIC_V3 32 bool 33 select IRQ_DOMAIN 34 select MULTI_IRQ_HANDLER 35 select IRQ_DOMAIN_HIERARCHY 36 select PARTITION_PERCPU 37 38config ARM_GIC_V3_ITS 39 bool 40 depends on PCI 41 depends on PCI_MSI 42 select ACPI_IORT if ACPI 43 44config ARM_NVIC 45 bool 46 select IRQ_DOMAIN 47 select IRQ_DOMAIN_HIERARCHY 48 select GENERIC_IRQ_CHIP 49 50config ARM_VIC 51 bool 52 select IRQ_DOMAIN 53 select MULTI_IRQ_HANDLER 54 55config ARM_VIC_NR 56 int 57 default 4 if ARCH_S5PV210 58 default 2 59 depends on ARM_VIC 60 help 61 The maximum number of VICs available in the system, for 62 power management. 63 64config ARMADA_370_XP_IRQ 65 bool 66 select GENERIC_IRQ_CHIP 67 select PCI_MSI if PCI 68 69config ALPINE_MSI 70 bool 71 depends on PCI 72 select PCI_MSI 73 select GENERIC_IRQ_CHIP 74 75config ATMEL_AIC_IRQ 76 bool 77 select GENERIC_IRQ_CHIP 78 select IRQ_DOMAIN 79 select MULTI_IRQ_HANDLER 80 select SPARSE_IRQ 81 82config ATMEL_AIC5_IRQ 83 bool 84 select GENERIC_IRQ_CHIP 85 select IRQ_DOMAIN 86 select MULTI_IRQ_HANDLER 87 select SPARSE_IRQ 88 89config I8259 90 bool 91 select IRQ_DOMAIN 92 93config BCM6345_L1_IRQ 94 bool 95 select GENERIC_IRQ_CHIP 96 select IRQ_DOMAIN 97 98config BCM7038_L1_IRQ 99 bool 100 select GENERIC_IRQ_CHIP 101 select IRQ_DOMAIN 102 103config BCM7120_L2_IRQ 104 bool 105 select GENERIC_IRQ_CHIP 106 select IRQ_DOMAIN 107 108config BRCMSTB_L2_IRQ 109 bool 110 select GENERIC_IRQ_CHIP 111 select IRQ_DOMAIN 112 113config DW_APB_ICTL 114 bool 115 select GENERIC_IRQ_CHIP 116 select IRQ_DOMAIN 117 118config FARADAY_FTINTC010 119 bool 120 select IRQ_DOMAIN 121 select MULTI_IRQ_HANDLER 122 select SPARSE_IRQ 123 124config HISILICON_IRQ_MBIGEN 125 bool 126 select ARM_GIC_V3 127 select ARM_GIC_V3_ITS 128 129config IMGPDC_IRQ 130 bool 131 select GENERIC_IRQ_CHIP 132 select IRQ_DOMAIN 133 134config IRQ_MIPS_CPU 135 bool 136 select GENERIC_IRQ_CHIP 137 select GENERIC_IRQ_IPI if SYS_SUPPORTS_MULTITHREADING 138 select IRQ_DOMAIN 139 select IRQ_DOMAIN_HIERARCHY if GENERIC_IRQ_IPI 140 141config CLPS711X_IRQCHIP 142 bool 143 depends on ARCH_CLPS711X 144 select IRQ_DOMAIN 145 select MULTI_IRQ_HANDLER 146 select SPARSE_IRQ 147 default y 148 149config OR1K_PIC 150 bool 151 select IRQ_DOMAIN 152 153config OMAP_IRQCHIP 154 bool 155 select GENERIC_IRQ_CHIP 156 select IRQ_DOMAIN 157 158config ORION_IRQCHIP 159 bool 160 select IRQ_DOMAIN 161 select MULTI_IRQ_HANDLER 162 163config PIC32_EVIC 164 bool 165 select GENERIC_IRQ_CHIP 166 select IRQ_DOMAIN 167 168config JCORE_AIC 169 bool "J-Core integrated AIC" if COMPILE_TEST 170 depends on OF 171 select IRQ_DOMAIN 172 help 173 Support for the J-Core integrated AIC. 174 175config RENESAS_INTC_IRQPIN 176 bool 177 select IRQ_DOMAIN 178 179config RENESAS_IRQC 180 bool 181 select GENERIC_IRQ_CHIP 182 select IRQ_DOMAIN 183 184config ST_IRQCHIP 185 bool 186 select REGMAP 187 select MFD_SYSCON 188 help 189 Enables SysCfg Controlled IRQs on STi based platforms. 190 191config TANGO_IRQ 192 bool 193 select IRQ_DOMAIN 194 select GENERIC_IRQ_CHIP 195 196config TB10X_IRQC 197 bool 198 select IRQ_DOMAIN 199 select GENERIC_IRQ_CHIP 200 201config TS4800_IRQ 202 tristate "TS-4800 IRQ controller" 203 select IRQ_DOMAIN 204 depends on HAS_IOMEM 205 depends on SOC_IMX51 || COMPILE_TEST 206 help 207 Support for the TS-4800 FPGA IRQ controller 208 209config VERSATILE_FPGA_IRQ 210 bool 211 select IRQ_DOMAIN 212 213config VERSATILE_FPGA_IRQ_NR 214 int 215 default 4 216 depends on VERSATILE_FPGA_IRQ 217 218config XTENSA_MX 219 bool 220 select IRQ_DOMAIN 221 222config XILINX_INTC 223 bool 224 select IRQ_DOMAIN 225 226config IRQ_CROSSBAR 227 bool 228 help 229 Support for a CROSSBAR ip that precedes the main interrupt controller. 230 The primary irqchip invokes the crossbar's callback which inturn allocates 231 a free irq and configures the IP. Thus the peripheral interrupts are 232 routed to one of the free irqchip interrupt lines. 233 234config KEYSTONE_IRQ 235 tristate "Keystone 2 IRQ controller IP" 236 depends on ARCH_KEYSTONE 237 help 238 Support for Texas Instruments Keystone 2 IRQ controller IP which 239 is part of the Keystone 2 IPC mechanism 240 241config MIPS_GIC 242 bool 243 select GENERIC_IRQ_IPI 244 select IRQ_DOMAIN_HIERARCHY 245 select MIPS_CM 246 247config INGENIC_IRQ 248 bool 249 depends on MACH_INGENIC 250 default y 251 252config RENESAS_H8300H_INTC 253 bool 254 select IRQ_DOMAIN 255 256config RENESAS_H8S_INTC 257 bool 258 select IRQ_DOMAIN 259 260config IMX_GPCV2 261 bool 262 select IRQ_DOMAIN 263 help 264 Enables the wakeup IRQs for IMX platforms with GPCv2 block 265 266config IRQ_MXS 267 def_bool y if MACH_ASM9260 || ARCH_MXS 268 select IRQ_DOMAIN 269 select STMP_DEVICE 270 271config MVEBU_ODMI 272 bool 273 select GENERIC_MSI_IRQ_DOMAIN 274 275config MVEBU_PIC 276 bool 277 278config LS_SCFG_MSI 279 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 280 depends on PCI && PCI_MSI 281 282config PARTITION_PERCPU 283 bool 284 285config EZNPS_GIC 286 bool "NPS400 Global Interrupt Manager (GIM)" 287 depends on ARC || (COMPILE_TEST && !64BIT) 288 select IRQ_DOMAIN 289 help 290 Support the EZchip NPS400 global interrupt controller 291 292config STM32_EXTI 293 bool 294 select IRQ_DOMAIN 295 296config QCOM_IRQ_COMBINER 297 bool "QCOM IRQ combiner support" 298 depends on ARCH_QCOM && ACPI 299 select IRQ_DOMAIN 300 select IRQ_DOMAIN_HIERARCHY 301 help 302 Say yes here to add support for the IRQ combiner devices embedded 303 in Qualcomm Technologies chips. 304