1menu "IRQ chip support" 2 3config IRQCHIP 4 def_bool y 5 depends on OF_IRQ 6 7config ARM_GIC 8 bool 9 select IRQ_DOMAIN 10 select IRQ_DOMAIN_HIERARCHY 11 select MULTI_IRQ_HANDLER 12 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 13 14config ARM_GIC_PM 15 bool 16 depends on PM 17 select ARM_GIC 18 select PM_CLK 19 20config ARM_GIC_MAX_NR 21 int 22 default 2 if ARCH_REALVIEW 23 default 1 24 25config ARM_GIC_V2M 26 bool 27 depends on PCI 28 select ARM_GIC 29 select PCI_MSI 30 31config GIC_NON_BANKED 32 bool 33 34config ARM_GIC_V3 35 bool 36 select IRQ_DOMAIN 37 select MULTI_IRQ_HANDLER 38 select IRQ_DOMAIN_HIERARCHY 39 select PARTITION_PERCPU 40 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 41 42config ARM_GIC_V3_ITS 43 bool 44 select GENERIC_MSI_IRQ_DOMAIN 45 default ARM_GIC_V3 46 47config ARM_GIC_V3_ITS_PCI 48 bool 49 depends on ARM_GIC_V3_ITS 50 depends on PCI 51 depends on PCI_MSI 52 default ARM_GIC_V3_ITS 53 54config ARM_NVIC 55 bool 56 select IRQ_DOMAIN 57 select IRQ_DOMAIN_HIERARCHY 58 select GENERIC_IRQ_CHIP 59 60config ARM_VIC 61 bool 62 select IRQ_DOMAIN 63 select MULTI_IRQ_HANDLER 64 65config ARM_VIC_NR 66 int 67 default 4 if ARCH_S5PV210 68 default 2 69 depends on ARM_VIC 70 help 71 The maximum number of VICs available in the system, for 72 power management. 73 74config ARMADA_370_XP_IRQ 75 bool 76 select GENERIC_IRQ_CHIP 77 select PCI_MSI if PCI 78 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 79 80config ALPINE_MSI 81 bool 82 depends on PCI 83 select PCI_MSI 84 select GENERIC_IRQ_CHIP 85 86config ATMEL_AIC_IRQ 87 bool 88 select GENERIC_IRQ_CHIP 89 select IRQ_DOMAIN 90 select MULTI_IRQ_HANDLER 91 select SPARSE_IRQ 92 93config ATMEL_AIC5_IRQ 94 bool 95 select GENERIC_IRQ_CHIP 96 select IRQ_DOMAIN 97 select MULTI_IRQ_HANDLER 98 select SPARSE_IRQ 99 100config I8259 101 bool 102 select IRQ_DOMAIN 103 104config BCM6345_L1_IRQ 105 bool 106 select GENERIC_IRQ_CHIP 107 select IRQ_DOMAIN 108 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 109 110config BCM7038_L1_IRQ 111 bool 112 select GENERIC_IRQ_CHIP 113 select IRQ_DOMAIN 114 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 115 116config BCM7120_L2_IRQ 117 bool 118 select GENERIC_IRQ_CHIP 119 select IRQ_DOMAIN 120 121config BRCMSTB_L2_IRQ 122 bool 123 select GENERIC_IRQ_CHIP 124 select IRQ_DOMAIN 125 126config DW_APB_ICTL 127 bool 128 select GENERIC_IRQ_CHIP 129 select IRQ_DOMAIN 130 131config FARADAY_FTINTC010 132 bool 133 select IRQ_DOMAIN 134 select MULTI_IRQ_HANDLER 135 select SPARSE_IRQ 136 137config HISILICON_IRQ_MBIGEN 138 bool 139 select ARM_GIC_V3 140 select ARM_GIC_V3_ITS 141 142config IMGPDC_IRQ 143 bool 144 select GENERIC_IRQ_CHIP 145 select IRQ_DOMAIN 146 147config IRQ_MIPS_CPU 148 bool 149 select GENERIC_IRQ_CHIP 150 select GENERIC_IRQ_IPI if SYS_SUPPORTS_MULTITHREADING 151 select IRQ_DOMAIN 152 select IRQ_DOMAIN_HIERARCHY if GENERIC_IRQ_IPI 153 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 154 155config CLPS711X_IRQCHIP 156 bool 157 depends on ARCH_CLPS711X 158 select IRQ_DOMAIN 159 select MULTI_IRQ_HANDLER 160 select SPARSE_IRQ 161 default y 162 163config OMPIC 164 bool 165 166config OR1K_PIC 167 bool 168 select IRQ_DOMAIN 169 170config OMAP_IRQCHIP 171 bool 172 select GENERIC_IRQ_CHIP 173 select IRQ_DOMAIN 174 175config ORION_IRQCHIP 176 bool 177 select IRQ_DOMAIN 178 select MULTI_IRQ_HANDLER 179 180config PIC32_EVIC 181 bool 182 select GENERIC_IRQ_CHIP 183 select IRQ_DOMAIN 184 185config JCORE_AIC 186 bool "J-Core integrated AIC" if COMPILE_TEST 187 depends on OF 188 select IRQ_DOMAIN 189 help 190 Support for the J-Core integrated AIC. 191 192config RENESAS_INTC_IRQPIN 193 bool 194 select IRQ_DOMAIN 195 196config RENESAS_IRQC 197 bool 198 select GENERIC_IRQ_CHIP 199 select IRQ_DOMAIN 200 201config ST_IRQCHIP 202 bool 203 select REGMAP 204 select MFD_SYSCON 205 help 206 Enables SysCfg Controlled IRQs on STi based platforms. 207 208config TANGO_IRQ 209 bool 210 select IRQ_DOMAIN 211 select GENERIC_IRQ_CHIP 212 213config TB10X_IRQC 214 bool 215 select IRQ_DOMAIN 216 select GENERIC_IRQ_CHIP 217 218config TS4800_IRQ 219 tristate "TS-4800 IRQ controller" 220 select IRQ_DOMAIN 221 depends on HAS_IOMEM 222 depends on SOC_IMX51 || COMPILE_TEST 223 help 224 Support for the TS-4800 FPGA IRQ controller 225 226config VERSATILE_FPGA_IRQ 227 bool 228 select IRQ_DOMAIN 229 230config VERSATILE_FPGA_IRQ_NR 231 int 232 default 4 233 depends on VERSATILE_FPGA_IRQ 234 235config XTENSA_MX 236 bool 237 select IRQ_DOMAIN 238 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 239 240config XILINX_INTC 241 bool 242 select IRQ_DOMAIN 243 244config IRQ_CROSSBAR 245 bool 246 help 247 Support for a CROSSBAR ip that precedes the main interrupt controller. 248 The primary irqchip invokes the crossbar's callback which inturn allocates 249 a free irq and configures the IP. Thus the peripheral interrupts are 250 routed to one of the free irqchip interrupt lines. 251 252config KEYSTONE_IRQ 253 tristate "Keystone 2 IRQ controller IP" 254 depends on ARCH_KEYSTONE 255 help 256 Support for Texas Instruments Keystone 2 IRQ controller IP which 257 is part of the Keystone 2 IPC mechanism 258 259config MIPS_GIC 260 bool 261 select GENERIC_IRQ_IPI 262 select IRQ_DOMAIN_HIERARCHY 263 select MIPS_CM 264 265config INGENIC_IRQ 266 bool 267 depends on MACH_INGENIC 268 default y 269 270config RENESAS_H8300H_INTC 271 bool 272 select IRQ_DOMAIN 273 274config RENESAS_H8S_INTC 275 bool 276 select IRQ_DOMAIN 277 278config IMX_GPCV2 279 bool 280 select IRQ_DOMAIN 281 help 282 Enables the wakeup IRQs for IMX platforms with GPCv2 block 283 284config IRQ_MXS 285 def_bool y if MACH_ASM9260 || ARCH_MXS 286 select IRQ_DOMAIN 287 select STMP_DEVICE 288 289config MVEBU_GICP 290 bool 291 292config MVEBU_ICU 293 bool 294 295config MVEBU_ODMI 296 bool 297 select GENERIC_MSI_IRQ_DOMAIN 298 299config MVEBU_PIC 300 bool 301 302config LS_SCFG_MSI 303 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 304 depends on PCI && PCI_MSI 305 306config PARTITION_PERCPU 307 bool 308 309config EZNPS_GIC 310 bool "NPS400 Global Interrupt Manager (GIM)" 311 depends on ARC || (COMPILE_TEST && !64BIT) 312 select IRQ_DOMAIN 313 help 314 Support the EZchip NPS400 global interrupt controller 315 316config STM32_EXTI 317 bool 318 select IRQ_DOMAIN 319 select GENERIC_IRQ_CHIP 320 321config QCOM_IRQ_COMBINER 322 bool "QCOM IRQ combiner support" 323 depends on ARCH_QCOM && ACPI 324 select IRQ_DOMAIN 325 select IRQ_DOMAIN_HIERARCHY 326 help 327 Say yes here to add support for the IRQ combiner devices embedded 328 in Qualcomm Technologies chips. 329 330config IRQ_UNIPHIER_AIDET 331 bool "UniPhier AIDET support" if COMPILE_TEST 332 depends on ARCH_UNIPHIER || COMPILE_TEST 333 default ARCH_UNIPHIER 334 select IRQ_DOMAIN_HIERARCHY 335 help 336 Support for the UniPhier AIDET (ARM Interrupt Detector). 337 338config MESON_IRQ_GPIO 339 bool "Meson GPIO Interrupt Multiplexer" 340 depends on ARCH_MESON 341 select IRQ_DOMAIN 342 select IRQ_DOMAIN_HIERARCHY 343 help 344 Support Meson SoC Family GPIO Interrupt Multiplexer 345 346config GOLDFISH_PIC 347 bool "Goldfish programmable interrupt controller" 348 depends on MIPS && (GOLDFISH || COMPILE_TEST) 349 select IRQ_DOMAIN 350 help 351 Say yes here to enable Goldfish interrupt controller driver used 352 for Goldfish based virtual platforms. 353 354endmenu 355