1# SPDX-License-Identifier: GPL-2.0-only 2menu "IRQ chip support" 3 4config IRQCHIP 5 def_bool y 6 depends on OF_IRQ 7 8config ARM_GIC 9 bool 10 select IRQ_DOMAIN_HIERARCHY 11 select GENERIC_IRQ_MULTI_HANDLER 12 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 13 14config ARM_GIC_PM 15 bool 16 depends on PM 17 select ARM_GIC 18 19config ARM_GIC_MAX_NR 20 int 21 depends on ARM_GIC 22 default 2 if ARCH_REALVIEW 23 default 1 24 25config ARM_GIC_V2M 26 bool 27 depends on PCI 28 select ARM_GIC 29 select PCI_MSI 30 31config GIC_NON_BANKED 32 bool 33 34config ARM_GIC_V3 35 bool 36 select GENERIC_IRQ_MULTI_HANDLER 37 select IRQ_DOMAIN_HIERARCHY 38 select PARTITION_PERCPU 39 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 40 41config ARM_GIC_V3_ITS 42 bool 43 select GENERIC_MSI_IRQ_DOMAIN 44 default ARM_GIC_V3 45 46config ARM_GIC_V3_ITS_PCI 47 bool 48 depends on ARM_GIC_V3_ITS 49 depends on PCI 50 depends on PCI_MSI 51 default ARM_GIC_V3_ITS 52 53config ARM_GIC_V3_ITS_FSL_MC 54 bool 55 depends on ARM_GIC_V3_ITS 56 depends on FSL_MC_BUS 57 default ARM_GIC_V3_ITS 58 59config ARM_NVIC 60 bool 61 select IRQ_DOMAIN_HIERARCHY 62 select GENERIC_IRQ_CHIP 63 64config ARM_VIC 65 bool 66 select IRQ_DOMAIN 67 select GENERIC_IRQ_MULTI_HANDLER 68 69config ARM_VIC_NR 70 int 71 default 4 if ARCH_S5PV210 72 default 2 73 depends on ARM_VIC 74 help 75 The maximum number of VICs available in the system, for 76 power management. 77 78config ARMADA_370_XP_IRQ 79 bool 80 select GENERIC_IRQ_CHIP 81 select PCI_MSI if PCI 82 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 83 84config ALPINE_MSI 85 bool 86 depends on PCI 87 select PCI_MSI 88 select GENERIC_IRQ_CHIP 89 90config AL_FIC 91 bool "Amazon's Annapurna Labs Fabric Interrupt Controller" 92 depends on OF || COMPILE_TEST 93 select GENERIC_IRQ_CHIP 94 select IRQ_DOMAIN 95 help 96 Support Amazon's Annapurna Labs Fabric Interrupt Controller. 97 98config ATMEL_AIC_IRQ 99 bool 100 select GENERIC_IRQ_CHIP 101 select IRQ_DOMAIN 102 select GENERIC_IRQ_MULTI_HANDLER 103 select SPARSE_IRQ 104 105config ATMEL_AIC5_IRQ 106 bool 107 select GENERIC_IRQ_CHIP 108 select IRQ_DOMAIN 109 select GENERIC_IRQ_MULTI_HANDLER 110 select SPARSE_IRQ 111 112config I8259 113 bool 114 select IRQ_DOMAIN 115 116config BCM6345_L1_IRQ 117 bool 118 select GENERIC_IRQ_CHIP 119 select IRQ_DOMAIN 120 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 121 122config BCM7038_L1_IRQ 123 bool 124 select GENERIC_IRQ_CHIP 125 select IRQ_DOMAIN 126 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 127 128config BCM7120_L2_IRQ 129 bool 130 select GENERIC_IRQ_CHIP 131 select IRQ_DOMAIN 132 133config BRCMSTB_L2_IRQ 134 bool 135 select GENERIC_IRQ_CHIP 136 select IRQ_DOMAIN 137 138config DAVINCI_AINTC 139 bool 140 select GENERIC_IRQ_CHIP 141 select IRQ_DOMAIN 142 143config DAVINCI_CP_INTC 144 bool 145 select GENERIC_IRQ_CHIP 146 select IRQ_DOMAIN 147 148config DW_APB_ICTL 149 bool 150 select GENERIC_IRQ_CHIP 151 select IRQ_DOMAIN_HIERARCHY 152 153config FARADAY_FTINTC010 154 bool 155 select IRQ_DOMAIN 156 select GENERIC_IRQ_MULTI_HANDLER 157 select SPARSE_IRQ 158 159config HISILICON_IRQ_MBIGEN 160 bool 161 select ARM_GIC_V3 162 select ARM_GIC_V3_ITS 163 164config IMGPDC_IRQ 165 bool 166 select GENERIC_IRQ_CHIP 167 select IRQ_DOMAIN 168 169config IXP4XX_IRQ 170 bool 171 select IRQ_DOMAIN 172 select GENERIC_IRQ_MULTI_HANDLER 173 select SPARSE_IRQ 174 175config MADERA_IRQ 176 tristate 177 178config IRQ_MIPS_CPU 179 bool 180 select GENERIC_IRQ_CHIP 181 select GENERIC_IRQ_IPI if SYS_SUPPORTS_MULTITHREADING 182 select IRQ_DOMAIN 183 select IRQ_DOMAIN_HIERARCHY if GENERIC_IRQ_IPI 184 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 185 186config CLPS711X_IRQCHIP 187 bool 188 depends on ARCH_CLPS711X 189 select IRQ_DOMAIN 190 select GENERIC_IRQ_MULTI_HANDLER 191 select SPARSE_IRQ 192 default y 193 194config OMPIC 195 bool 196 197config OR1K_PIC 198 bool 199 select IRQ_DOMAIN 200 201config OMAP_IRQCHIP 202 bool 203 select GENERIC_IRQ_CHIP 204 select IRQ_DOMAIN 205 206config ORION_IRQCHIP 207 bool 208 select IRQ_DOMAIN 209 select GENERIC_IRQ_MULTI_HANDLER 210 211config PIC32_EVIC 212 bool 213 select GENERIC_IRQ_CHIP 214 select IRQ_DOMAIN 215 216config JCORE_AIC 217 bool "J-Core integrated AIC" if COMPILE_TEST 218 depends on OF 219 select IRQ_DOMAIN 220 help 221 Support for the J-Core integrated AIC. 222 223config RDA_INTC 224 bool 225 select IRQ_DOMAIN 226 227config RENESAS_INTC_IRQPIN 228 bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST 229 select IRQ_DOMAIN 230 help 231 Enable support for the Renesas Interrupt Controller for external 232 interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs. 233 234config RENESAS_IRQC 235 bool "Renesas R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} IRQC support" if COMPILE_TEST 236 select GENERIC_IRQ_CHIP 237 select IRQ_DOMAIN 238 help 239 Enable support for the Renesas Interrupt Controller for external 240 devices, as found on R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} SoCs. 241 242config RENESAS_RZA1_IRQC 243 bool "Renesas RZ/A1 IRQC support" if COMPILE_TEST 244 select IRQ_DOMAIN_HIERARCHY 245 help 246 Enable support for the Renesas RZ/A1 Interrupt Controller, to use up 247 to 8 external interrupts with configurable sense select. 248 249config SL28CPLD_INTC 250 bool "Kontron sl28cpld IRQ controller" 251 depends on MFD_SL28CPLD=y || COMPILE_TEST 252 select REGMAP_IRQ 253 help 254 Interrupt controller driver for the board management controller 255 found on the Kontron sl28 CPLD. 256 257config ST_IRQCHIP 258 bool 259 select REGMAP 260 select MFD_SYSCON 261 help 262 Enables SysCfg Controlled IRQs on STi based platforms. 263 264config TANGO_IRQ 265 bool 266 select IRQ_DOMAIN 267 select GENERIC_IRQ_CHIP 268 269config TB10X_IRQC 270 bool 271 select IRQ_DOMAIN 272 select GENERIC_IRQ_CHIP 273 274config TS4800_IRQ 275 tristate "TS-4800 IRQ controller" 276 select IRQ_DOMAIN 277 depends on HAS_IOMEM 278 depends on SOC_IMX51 || COMPILE_TEST 279 help 280 Support for the TS-4800 FPGA IRQ controller 281 282config VERSATILE_FPGA_IRQ 283 bool 284 select IRQ_DOMAIN 285 286config VERSATILE_FPGA_IRQ_NR 287 int 288 default 4 289 depends on VERSATILE_FPGA_IRQ 290 291config XTENSA_MX 292 bool 293 select IRQ_DOMAIN 294 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 295 296config XILINX_INTC 297 bool 298 select IRQ_DOMAIN 299 300config IRQ_CROSSBAR 301 bool 302 help 303 Support for a CROSSBAR ip that precedes the main interrupt controller. 304 The primary irqchip invokes the crossbar's callback which inturn allocates 305 a free irq and configures the IP. Thus the peripheral interrupts are 306 routed to one of the free irqchip interrupt lines. 307 308config KEYSTONE_IRQ 309 tristate "Keystone 2 IRQ controller IP" 310 depends on ARCH_KEYSTONE 311 help 312 Support for Texas Instruments Keystone 2 IRQ controller IP which 313 is part of the Keystone 2 IPC mechanism 314 315config MIPS_GIC 316 bool 317 select GENERIC_IRQ_IPI 318 select IRQ_DOMAIN_HIERARCHY 319 select MIPS_CM 320 321config INGENIC_IRQ 322 bool 323 depends on MACH_INGENIC 324 default y 325 326config INGENIC_TCU_IRQ 327 bool "Ingenic JZ47xx TCU interrupt controller" 328 default MACH_INGENIC 329 depends on MIPS || COMPILE_TEST 330 select MFD_SYSCON 331 select GENERIC_IRQ_CHIP 332 help 333 Support for interrupts in the Timer/Counter Unit (TCU) of the Ingenic 334 JZ47xx SoCs. 335 336 If unsure, say N. 337 338config RENESAS_H8300H_INTC 339 bool 340 select IRQ_DOMAIN 341 342config RENESAS_H8S_INTC 343 bool "Renesas H8S Interrupt Controller Support" if COMPILE_TEST 344 select IRQ_DOMAIN 345 help 346 Enable support for the Renesas H8/300 Interrupt Controller, as found 347 on Renesas H8S SoCs. 348 349config IMX_GPCV2 350 bool 351 select IRQ_DOMAIN 352 help 353 Enables the wakeup IRQs for IMX platforms with GPCv2 block 354 355config IRQ_MXS 356 def_bool y if MACH_ASM9260 || ARCH_MXS 357 select IRQ_DOMAIN 358 select STMP_DEVICE 359 360config MSCC_OCELOT_IRQ 361 bool 362 select IRQ_DOMAIN 363 select GENERIC_IRQ_CHIP 364 365config MVEBU_GICP 366 bool 367 368config MVEBU_ICU 369 bool 370 371config MVEBU_ODMI 372 bool 373 select GENERIC_MSI_IRQ_DOMAIN 374 375config MVEBU_PIC 376 bool 377 378config MVEBU_SEI 379 bool 380 381config LS_EXTIRQ 382 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 383 select MFD_SYSCON 384 385config LS_SCFG_MSI 386 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 387 depends on PCI && PCI_MSI 388 389config PARTITION_PERCPU 390 bool 391 392config EZNPS_GIC 393 bool "NPS400 Global Interrupt Manager (GIM)" 394 depends on ARC || (COMPILE_TEST && !64BIT) 395 select IRQ_DOMAIN 396 help 397 Support the EZchip NPS400 global interrupt controller 398 399config STM32_EXTI 400 bool 401 select IRQ_DOMAIN 402 select GENERIC_IRQ_CHIP 403 404config QCOM_IRQ_COMBINER 405 bool "QCOM IRQ combiner support" 406 depends on ARCH_QCOM && ACPI 407 select IRQ_DOMAIN_HIERARCHY 408 help 409 Say yes here to add support for the IRQ combiner devices embedded 410 in Qualcomm Technologies chips. 411 412config IRQ_UNIPHIER_AIDET 413 bool "UniPhier AIDET support" if COMPILE_TEST 414 depends on ARCH_UNIPHIER || COMPILE_TEST 415 default ARCH_UNIPHIER 416 select IRQ_DOMAIN_HIERARCHY 417 help 418 Support for the UniPhier AIDET (ARM Interrupt Detector). 419 420config MESON_IRQ_GPIO 421 bool "Meson GPIO Interrupt Multiplexer" 422 depends on ARCH_MESON 423 select IRQ_DOMAIN_HIERARCHY 424 help 425 Support Meson SoC Family GPIO Interrupt Multiplexer 426 427config GOLDFISH_PIC 428 bool "Goldfish programmable interrupt controller" 429 depends on MIPS && (GOLDFISH || COMPILE_TEST) 430 select IRQ_DOMAIN 431 help 432 Say yes here to enable Goldfish interrupt controller driver used 433 for Goldfish based virtual platforms. 434 435config QCOM_PDC 436 bool "QCOM PDC" 437 depends on ARCH_QCOM 438 select IRQ_DOMAIN_HIERARCHY 439 help 440 Power Domain Controller driver to manage and configure wakeup 441 IRQs for Qualcomm Technologies Inc (QTI) mobile chips. 442 443config CSKY_MPINTC 444 bool "C-SKY Multi Processor Interrupt Controller" 445 depends on CSKY 446 help 447 Say yes here to enable C-SKY SMP interrupt controller driver used 448 for C-SKY SMP system. 449 In fact it's not mmio map in hardware and it uses ld/st to visit the 450 controller's register inside CPU. 451 452config CSKY_APB_INTC 453 bool "C-SKY APB Interrupt Controller" 454 depends on CSKY 455 help 456 Say yes here to enable C-SKY APB interrupt controller driver used 457 by C-SKY single core SOC system. It uses mmio map apb-bus to visit 458 the controller's register. 459 460config IMX_IRQSTEER 461 bool "i.MX IRQSTEER support" 462 depends on ARCH_MXC || COMPILE_TEST 463 default ARCH_MXC 464 select IRQ_DOMAIN 465 help 466 Support for the i.MX IRQSTEER interrupt multiplexer/remapper. 467 468config IMX_INTMUX 469 def_bool y if ARCH_MXC || COMPILE_TEST 470 select IRQ_DOMAIN 471 help 472 Support for the i.MX INTMUX interrupt multiplexer. 473 474config LS1X_IRQ 475 bool "Loongson-1 Interrupt Controller" 476 depends on MACH_LOONGSON32 477 default y 478 select IRQ_DOMAIN 479 select GENERIC_IRQ_CHIP 480 help 481 Support for the Loongson-1 platform Interrupt Controller. 482 483config TI_SCI_INTR_IRQCHIP 484 bool 485 depends on TI_SCI_PROTOCOL 486 select IRQ_DOMAIN_HIERARCHY 487 help 488 This enables the irqchip driver support for K3 Interrupt router 489 over TI System Control Interface available on some new TI's SoCs. 490 If you wish to use interrupt router irq resources managed by the 491 TI System Controller, say Y here. Otherwise, say N. 492 493config TI_SCI_INTA_IRQCHIP 494 bool 495 depends on TI_SCI_PROTOCOL 496 select IRQ_DOMAIN_HIERARCHY 497 select TI_SCI_INTA_MSI_DOMAIN 498 help 499 This enables the irqchip driver support for K3 Interrupt aggregator 500 over TI System Control Interface available on some new TI's SoCs. 501 If you wish to use interrupt aggregator irq resources managed by the 502 TI System Controller, say Y here. Otherwise, say N. 503 504config TI_PRUSS_INTC 505 tristate "TI PRU-ICSS Interrupt Controller" 506 depends on ARCH_DAVINCI || SOC_AM33XX || SOC_AM43XX || SOC_DRA7XX || ARCH_KEYSTONE || ARCH_K3 507 select IRQ_DOMAIN 508 help 509 This enables support for the PRU-ICSS Local Interrupt Controller 510 present within a PRU-ICSS subsystem present on various TI SoCs. 511 The PRUSS INTC enables various interrupts to be routed to multiple 512 different processors within the SoC. 513 514config RISCV_INTC 515 bool "RISC-V Local Interrupt Controller" 516 depends on RISCV 517 default y 518 help 519 This enables support for the per-HART local interrupt controller 520 found in standard RISC-V systems. The per-HART local interrupt 521 controller handles timer interrupts, software interrupts, and 522 hardware interrupts. Without a per-HART local interrupt controller, 523 a RISC-V system will be unable to handle any interrupts. 524 525 If you don't know what to do here, say Y. 526 527config SIFIVE_PLIC 528 bool "SiFive Platform-Level Interrupt Controller" 529 depends on RISCV 530 select IRQ_DOMAIN_HIERARCHY 531 help 532 This enables support for the PLIC chip found in SiFive (and 533 potentially other) RISC-V systems. The PLIC controls devices 534 interrupts and connects them to each core's local interrupt 535 controller. Aside from timer and software interrupts, all other 536 interrupt sources are subordinate to the PLIC. 537 538 If you don't know what to do here, say Y. 539 540config EXYNOS_IRQ_COMBINER 541 bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST 542 depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST 543 help 544 Say yes here to add support for the IRQ combiner devices embedded 545 in Samsung Exynos chips. 546 547config LOONGSON_LIOINTC 548 bool "Loongson Local I/O Interrupt Controller" 549 depends on MACH_LOONGSON64 550 default y 551 select IRQ_DOMAIN 552 select GENERIC_IRQ_CHIP 553 help 554 Support for the Loongson Local I/O Interrupt Controller. 555 556config LOONGSON_HTPIC 557 bool "Loongson3 HyperTransport PIC Controller" 558 depends on MACH_LOONGSON64 559 default y 560 select IRQ_DOMAIN 561 select GENERIC_IRQ_CHIP 562 help 563 Support for the Loongson-3 HyperTransport PIC Controller. 564 565config LOONGSON_HTVEC 566 bool "Loongson3 HyperTransport Interrupt Vector Controller" 567 depends on MACH_LOONGSON64 568 default MACH_LOONGSON64 569 select IRQ_DOMAIN_HIERARCHY 570 help 571 Support for the Loongson3 HyperTransport Interrupt Vector Controller. 572 573config LOONGSON_PCH_PIC 574 bool "Loongson PCH PIC Controller" 575 depends on MACH_LOONGSON64 || COMPILE_TEST 576 default MACH_LOONGSON64 577 select IRQ_DOMAIN_HIERARCHY 578 select IRQ_FASTEOI_HIERARCHY_HANDLERS 579 help 580 Support for the Loongson PCH PIC Controller. 581 582config LOONGSON_PCH_MSI 583 bool "Loongson PCH MSI Controller" 584 depends on MACH_LOONGSON64 || COMPILE_TEST 585 depends on PCI 586 default MACH_LOONGSON64 587 select IRQ_DOMAIN_HIERARCHY 588 select PCI_MSI 589 help 590 Support for the Loongson PCH MSI Controller. 591 592config MST_IRQ 593 bool "MStar Interrupt Controller" 594 default ARCH_MEDIATEK 595 select IRQ_DOMAIN 596 select IRQ_DOMAIN_HIERARCHY 597 help 598 Support MStar Interrupt Controller. 599 600endmenu 601