1# SPDX-License-Identifier: GPL-2.0-only 2menu "IRQ chip support" 3 4config IRQCHIP 5 def_bool y 6 depends on OF_IRQ 7 8config ARM_GIC 9 bool 10 select IRQ_DOMAIN_HIERARCHY 11 select GENERIC_IRQ_MULTI_HANDLER 12 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 13 14config ARM_GIC_PM 15 bool 16 depends on PM 17 select ARM_GIC 18 19config ARM_GIC_MAX_NR 20 int 21 depends on ARM_GIC 22 default 2 if ARCH_REALVIEW 23 default 1 24 25config ARM_GIC_V2M 26 bool 27 depends on PCI 28 select ARM_GIC 29 select PCI_MSI 30 31config GIC_NON_BANKED 32 bool 33 34config ARM_GIC_V3 35 bool 36 select GENERIC_IRQ_MULTI_HANDLER 37 select IRQ_DOMAIN_HIERARCHY 38 select PARTITION_PERCPU 39 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 40 41config ARM_GIC_V3_ITS 42 bool 43 select GENERIC_MSI_IRQ_DOMAIN 44 default ARM_GIC_V3 45 46config ARM_GIC_V3_ITS_PCI 47 bool 48 depends on ARM_GIC_V3_ITS 49 depends on PCI 50 depends on PCI_MSI 51 default ARM_GIC_V3_ITS 52 53config ARM_GIC_V3_ITS_FSL_MC 54 bool 55 depends on ARM_GIC_V3_ITS 56 depends on FSL_MC_BUS 57 default ARM_GIC_V3_ITS 58 59config ARM_NVIC 60 bool 61 select IRQ_DOMAIN_HIERARCHY 62 select GENERIC_IRQ_CHIP 63 64config ARM_VIC 65 bool 66 select IRQ_DOMAIN 67 select GENERIC_IRQ_MULTI_HANDLER 68 69config ARM_VIC_NR 70 int 71 default 4 if ARCH_S5PV210 72 default 2 73 depends on ARM_VIC 74 help 75 The maximum number of VICs available in the system, for 76 power management. 77 78config ARMADA_370_XP_IRQ 79 bool 80 select GENERIC_IRQ_CHIP 81 select PCI_MSI if PCI 82 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 83 84config ALPINE_MSI 85 bool 86 depends on PCI 87 select PCI_MSI 88 select GENERIC_IRQ_CHIP 89 90config AL_FIC 91 bool "Amazon's Annapurna Labs Fabric Interrupt Controller" 92 depends on OF || COMPILE_TEST 93 select GENERIC_IRQ_CHIP 94 select IRQ_DOMAIN 95 help 96 Support Amazon's Annapurna Labs Fabric Interrupt Controller. 97 98config ATMEL_AIC_IRQ 99 bool 100 select GENERIC_IRQ_CHIP 101 select IRQ_DOMAIN 102 select GENERIC_IRQ_MULTI_HANDLER 103 select SPARSE_IRQ 104 105config ATMEL_AIC5_IRQ 106 bool 107 select GENERIC_IRQ_CHIP 108 select IRQ_DOMAIN 109 select GENERIC_IRQ_MULTI_HANDLER 110 select SPARSE_IRQ 111 112config I8259 113 bool 114 select IRQ_DOMAIN 115 116config BCM6345_L1_IRQ 117 bool 118 select GENERIC_IRQ_CHIP 119 select IRQ_DOMAIN 120 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 121 122config BCM7038_L1_IRQ 123 bool 124 select GENERIC_IRQ_CHIP 125 select IRQ_DOMAIN 126 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 127 128config BCM7120_L2_IRQ 129 bool 130 select GENERIC_IRQ_CHIP 131 select IRQ_DOMAIN 132 133config BRCMSTB_L2_IRQ 134 bool 135 select GENERIC_IRQ_CHIP 136 select IRQ_DOMAIN 137 138config DAVINCI_AINTC 139 bool 140 select GENERIC_IRQ_CHIP 141 select IRQ_DOMAIN 142 143config DAVINCI_CP_INTC 144 bool 145 select GENERIC_IRQ_CHIP 146 select IRQ_DOMAIN 147 148config DW_APB_ICTL 149 bool 150 select GENERIC_IRQ_CHIP 151 select IRQ_DOMAIN_HIERARCHY 152 153config FARADAY_FTINTC010 154 bool 155 select IRQ_DOMAIN 156 select GENERIC_IRQ_MULTI_HANDLER 157 select SPARSE_IRQ 158 159config HISILICON_IRQ_MBIGEN 160 bool 161 select ARM_GIC_V3 162 select ARM_GIC_V3_ITS 163 164config IMGPDC_IRQ 165 bool 166 select GENERIC_IRQ_CHIP 167 select IRQ_DOMAIN 168 169config IXP4XX_IRQ 170 bool 171 select IRQ_DOMAIN 172 select GENERIC_IRQ_MULTI_HANDLER 173 select SPARSE_IRQ 174 175config MADERA_IRQ 176 tristate 177 178config IRQ_MIPS_CPU 179 bool 180 select GENERIC_IRQ_CHIP 181 select GENERIC_IRQ_IPI if SYS_SUPPORTS_MULTITHREADING 182 select IRQ_DOMAIN 183 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 184 185config CLPS711X_IRQCHIP 186 bool 187 depends on ARCH_CLPS711X 188 select IRQ_DOMAIN 189 select GENERIC_IRQ_MULTI_HANDLER 190 select SPARSE_IRQ 191 default y 192 193config OMPIC 194 bool 195 196config OR1K_PIC 197 bool 198 select IRQ_DOMAIN 199 200config OMAP_IRQCHIP 201 bool 202 select GENERIC_IRQ_CHIP 203 select IRQ_DOMAIN 204 205config ORION_IRQCHIP 206 bool 207 select IRQ_DOMAIN 208 select GENERIC_IRQ_MULTI_HANDLER 209 210config PIC32_EVIC 211 bool 212 select GENERIC_IRQ_CHIP 213 select IRQ_DOMAIN 214 215config JCORE_AIC 216 bool "J-Core integrated AIC" if COMPILE_TEST 217 depends on OF 218 select IRQ_DOMAIN 219 help 220 Support for the J-Core integrated AIC. 221 222config RDA_INTC 223 bool 224 select IRQ_DOMAIN 225 226config RENESAS_INTC_IRQPIN 227 bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST 228 select IRQ_DOMAIN 229 help 230 Enable support for the Renesas Interrupt Controller for external 231 interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs. 232 233config RENESAS_IRQC 234 bool "Renesas R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} IRQC support" if COMPILE_TEST 235 select GENERIC_IRQ_CHIP 236 select IRQ_DOMAIN 237 help 238 Enable support for the Renesas Interrupt Controller for external 239 devices, as found on R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} SoCs. 240 241config RENESAS_RZA1_IRQC 242 bool "Renesas RZ/A1 IRQC support" if COMPILE_TEST 243 select IRQ_DOMAIN_HIERARCHY 244 help 245 Enable support for the Renesas RZ/A1 Interrupt Controller, to use up 246 to 8 external interrupts with configurable sense select. 247 248config SL28CPLD_INTC 249 bool "Kontron sl28cpld IRQ controller" 250 depends on MFD_SL28CPLD=y || COMPILE_TEST 251 select REGMAP_IRQ 252 help 253 Interrupt controller driver for the board management controller 254 found on the Kontron sl28 CPLD. 255 256config ST_IRQCHIP 257 bool 258 select REGMAP 259 select MFD_SYSCON 260 help 261 Enables SysCfg Controlled IRQs on STi based platforms. 262 263config TB10X_IRQC 264 bool 265 select IRQ_DOMAIN 266 select GENERIC_IRQ_CHIP 267 268config TS4800_IRQ 269 tristate "TS-4800 IRQ controller" 270 select IRQ_DOMAIN 271 depends on HAS_IOMEM 272 depends on SOC_IMX51 || COMPILE_TEST 273 help 274 Support for the TS-4800 FPGA IRQ controller 275 276config VERSATILE_FPGA_IRQ 277 bool 278 select IRQ_DOMAIN 279 280config VERSATILE_FPGA_IRQ_NR 281 int 282 default 4 283 depends on VERSATILE_FPGA_IRQ 284 285config XTENSA_MX 286 bool 287 select IRQ_DOMAIN 288 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 289 290config XILINX_INTC 291 bool 292 select IRQ_DOMAIN 293 294config IRQ_CROSSBAR 295 bool 296 help 297 Support for a CROSSBAR ip that precedes the main interrupt controller. 298 The primary irqchip invokes the crossbar's callback which inturn allocates 299 a free irq and configures the IP. Thus the peripheral interrupts are 300 routed to one of the free irqchip interrupt lines. 301 302config KEYSTONE_IRQ 303 tristate "Keystone 2 IRQ controller IP" 304 depends on ARCH_KEYSTONE 305 help 306 Support for Texas Instruments Keystone 2 IRQ controller IP which 307 is part of the Keystone 2 IPC mechanism 308 309config MIPS_GIC 310 bool 311 select GENERIC_IRQ_IPI 312 select MIPS_CM 313 314config INGENIC_IRQ 315 bool 316 depends on MACH_INGENIC 317 default y 318 319config INGENIC_TCU_IRQ 320 bool "Ingenic JZ47xx TCU interrupt controller" 321 default MACH_INGENIC 322 depends on MIPS || COMPILE_TEST 323 select MFD_SYSCON 324 select GENERIC_IRQ_CHIP 325 help 326 Support for interrupts in the Timer/Counter Unit (TCU) of the Ingenic 327 JZ47xx SoCs. 328 329 If unsure, say N. 330 331config RENESAS_H8300H_INTC 332 bool 333 select IRQ_DOMAIN 334 335config RENESAS_H8S_INTC 336 bool "Renesas H8S Interrupt Controller Support" if COMPILE_TEST 337 select IRQ_DOMAIN 338 help 339 Enable support for the Renesas H8/300 Interrupt Controller, as found 340 on Renesas H8S SoCs. 341 342config IMX_GPCV2 343 bool 344 select IRQ_DOMAIN 345 help 346 Enables the wakeup IRQs for IMX platforms with GPCv2 block 347 348config IRQ_MXS 349 def_bool y if MACH_ASM9260 || ARCH_MXS 350 select IRQ_DOMAIN 351 select STMP_DEVICE 352 353config MSCC_OCELOT_IRQ 354 bool 355 select IRQ_DOMAIN 356 select GENERIC_IRQ_CHIP 357 358config MVEBU_GICP 359 bool 360 361config MVEBU_ICU 362 bool 363 364config MVEBU_ODMI 365 bool 366 select GENERIC_MSI_IRQ_DOMAIN 367 368config MVEBU_PIC 369 bool 370 371config MVEBU_SEI 372 bool 373 374config LS_EXTIRQ 375 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 376 select MFD_SYSCON 377 378config LS_SCFG_MSI 379 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 380 depends on PCI && PCI_MSI 381 382config PARTITION_PERCPU 383 bool 384 385config STM32_EXTI 386 bool 387 select IRQ_DOMAIN 388 select GENERIC_IRQ_CHIP 389 390config QCOM_IRQ_COMBINER 391 bool "QCOM IRQ combiner support" 392 depends on ARCH_QCOM && ACPI 393 select IRQ_DOMAIN_HIERARCHY 394 help 395 Say yes here to add support for the IRQ combiner devices embedded 396 in Qualcomm Technologies chips. 397 398config IRQ_UNIPHIER_AIDET 399 bool "UniPhier AIDET support" if COMPILE_TEST 400 depends on ARCH_UNIPHIER || COMPILE_TEST 401 default ARCH_UNIPHIER 402 select IRQ_DOMAIN_HIERARCHY 403 help 404 Support for the UniPhier AIDET (ARM Interrupt Detector). 405 406config MESON_IRQ_GPIO 407 bool "Meson GPIO Interrupt Multiplexer" 408 depends on ARCH_MESON 409 select IRQ_DOMAIN_HIERARCHY 410 help 411 Support Meson SoC Family GPIO Interrupt Multiplexer 412 413config GOLDFISH_PIC 414 bool "Goldfish programmable interrupt controller" 415 depends on MIPS && (GOLDFISH || COMPILE_TEST) 416 select IRQ_DOMAIN 417 help 418 Say yes here to enable Goldfish interrupt controller driver used 419 for Goldfish based virtual platforms. 420 421config QCOM_PDC 422 bool "QCOM PDC" 423 depends on ARCH_QCOM 424 select IRQ_DOMAIN_HIERARCHY 425 help 426 Power Domain Controller driver to manage and configure wakeup 427 IRQs for Qualcomm Technologies Inc (QTI) mobile chips. 428 429config CSKY_MPINTC 430 bool 431 depends on CSKY 432 help 433 Say yes here to enable C-SKY SMP interrupt controller driver used 434 for C-SKY SMP system. 435 In fact it's not mmio map in hardware and it uses ld/st to visit the 436 controller's register inside CPU. 437 438config CSKY_APB_INTC 439 bool "C-SKY APB Interrupt Controller" 440 depends on CSKY 441 help 442 Say yes here to enable C-SKY APB interrupt controller driver used 443 by C-SKY single core SOC system. It uses mmio map apb-bus to visit 444 the controller's register. 445 446config IMX_IRQSTEER 447 bool "i.MX IRQSTEER support" 448 depends on ARCH_MXC || COMPILE_TEST 449 default ARCH_MXC 450 select IRQ_DOMAIN 451 help 452 Support for the i.MX IRQSTEER interrupt multiplexer/remapper. 453 454config IMX_INTMUX 455 bool "i.MX INTMUX support" if COMPILE_TEST 456 default y if ARCH_MXC 457 select IRQ_DOMAIN 458 help 459 Support for the i.MX INTMUX interrupt multiplexer. 460 461config LS1X_IRQ 462 bool "Loongson-1 Interrupt Controller" 463 depends on MACH_LOONGSON32 464 default y 465 select IRQ_DOMAIN 466 select GENERIC_IRQ_CHIP 467 help 468 Support for the Loongson-1 platform Interrupt Controller. 469 470config TI_SCI_INTR_IRQCHIP 471 bool 472 depends on TI_SCI_PROTOCOL 473 select IRQ_DOMAIN_HIERARCHY 474 help 475 This enables the irqchip driver support for K3 Interrupt router 476 over TI System Control Interface available on some new TI's SoCs. 477 If you wish to use interrupt router irq resources managed by the 478 TI System Controller, say Y here. Otherwise, say N. 479 480config TI_SCI_INTA_IRQCHIP 481 bool 482 depends on TI_SCI_PROTOCOL 483 select IRQ_DOMAIN_HIERARCHY 484 select TI_SCI_INTA_MSI_DOMAIN 485 help 486 This enables the irqchip driver support for K3 Interrupt aggregator 487 over TI System Control Interface available on some new TI's SoCs. 488 If you wish to use interrupt aggregator irq resources managed by the 489 TI System Controller, say Y here. Otherwise, say N. 490 491config TI_PRUSS_INTC 492 tristate 493 depends on TI_PRUSS 494 default TI_PRUSS 495 select IRQ_DOMAIN 496 help 497 This enables support for the PRU-ICSS Local Interrupt Controller 498 present within a PRU-ICSS subsystem present on various TI SoCs. 499 The PRUSS INTC enables various interrupts to be routed to multiple 500 different processors within the SoC. 501 502config RISCV_INTC 503 bool "RISC-V Local Interrupt Controller" 504 depends on RISCV 505 default y 506 help 507 This enables support for the per-HART local interrupt controller 508 found in standard RISC-V systems. The per-HART local interrupt 509 controller handles timer interrupts, software interrupts, and 510 hardware interrupts. Without a per-HART local interrupt controller, 511 a RISC-V system will be unable to handle any interrupts. 512 513 If you don't know what to do here, say Y. 514 515config SIFIVE_PLIC 516 bool "SiFive Platform-Level Interrupt Controller" 517 depends on RISCV 518 select IRQ_DOMAIN_HIERARCHY 519 help 520 This enables support for the PLIC chip found in SiFive (and 521 potentially other) RISC-V systems. The PLIC controls devices 522 interrupts and connects them to each core's local interrupt 523 controller. Aside from timer and software interrupts, all other 524 interrupt sources are subordinate to the PLIC. 525 526 If you don't know what to do here, say Y. 527 528config EXYNOS_IRQ_COMBINER 529 bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST 530 depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST 531 help 532 Say yes here to add support for the IRQ combiner devices embedded 533 in Samsung Exynos chips. 534 535config LOONGSON_LIOINTC 536 bool "Loongson Local I/O Interrupt Controller" 537 depends on MACH_LOONGSON64 538 default y 539 select IRQ_DOMAIN 540 select GENERIC_IRQ_CHIP 541 help 542 Support for the Loongson Local I/O Interrupt Controller. 543 544config LOONGSON_HTPIC 545 bool "Loongson3 HyperTransport PIC Controller" 546 depends on MACH_LOONGSON64 547 default y 548 select IRQ_DOMAIN 549 select GENERIC_IRQ_CHIP 550 help 551 Support for the Loongson-3 HyperTransport PIC Controller. 552 553config LOONGSON_HTVEC 554 bool "Loongson3 HyperTransport Interrupt Vector Controller" 555 depends on MACH_LOONGSON64 556 default MACH_LOONGSON64 557 select IRQ_DOMAIN_HIERARCHY 558 help 559 Support for the Loongson3 HyperTransport Interrupt Vector Controller. 560 561config LOONGSON_PCH_PIC 562 bool "Loongson PCH PIC Controller" 563 depends on MACH_LOONGSON64 || COMPILE_TEST 564 default MACH_LOONGSON64 565 select IRQ_DOMAIN_HIERARCHY 566 select IRQ_FASTEOI_HIERARCHY_HANDLERS 567 help 568 Support for the Loongson PCH PIC Controller. 569 570config LOONGSON_PCH_MSI 571 bool "Loongson PCH MSI Controller" 572 depends on MACH_LOONGSON64 || COMPILE_TEST 573 depends on PCI 574 default MACH_LOONGSON64 575 select IRQ_DOMAIN_HIERARCHY 576 select PCI_MSI 577 help 578 Support for the Loongson PCH MSI Controller. 579 580config MST_IRQ 581 bool "MStar Interrupt Controller" 582 depends on ARCH_MEDIATEK || ARCH_MSTARV7 || COMPILE_TEST 583 default ARCH_MEDIATEK 584 select IRQ_DOMAIN 585 select IRQ_DOMAIN_HIERARCHY 586 help 587 Support MStar Interrupt Controller. 588 589endmenu 590