1menu "IRQ chip support" 2 3config IRQCHIP 4 def_bool y 5 depends on OF_IRQ 6 7config ARM_GIC 8 bool 9 select IRQ_DOMAIN 10 select IRQ_DOMAIN_HIERARCHY 11 select GENERIC_IRQ_MULTI_HANDLER 12 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 13 14config ARM_GIC_PM 15 bool 16 depends on PM 17 select ARM_GIC 18 select PM_CLK 19 20config ARM_GIC_MAX_NR 21 int 22 default 2 if ARCH_REALVIEW 23 default 1 24 25config ARM_GIC_V2M 26 bool 27 depends on PCI 28 select ARM_GIC 29 select PCI_MSI 30 31config GIC_NON_BANKED 32 bool 33 34config ARM_GIC_V3 35 bool 36 select IRQ_DOMAIN 37 select GENERIC_IRQ_MULTI_HANDLER 38 select IRQ_DOMAIN_HIERARCHY 39 select PARTITION_PERCPU 40 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 41 42config ARM_GIC_V3_ITS 43 bool 44 select GENERIC_MSI_IRQ_DOMAIN 45 default ARM_GIC_V3 46 47config ARM_GIC_V3_ITS_PCI 48 bool 49 depends on ARM_GIC_V3_ITS 50 depends on PCI 51 depends on PCI_MSI 52 default ARM_GIC_V3_ITS 53 54config ARM_GIC_V3_ITS_FSL_MC 55 bool 56 depends on ARM_GIC_V3_ITS 57 depends on FSL_MC_BUS 58 default ARM_GIC_V3_ITS 59 60config ARM_NVIC 61 bool 62 select IRQ_DOMAIN 63 select IRQ_DOMAIN_HIERARCHY 64 select GENERIC_IRQ_CHIP 65 66config ARM_VIC 67 bool 68 select IRQ_DOMAIN 69 select GENERIC_IRQ_MULTI_HANDLER 70 71config ARM_VIC_NR 72 int 73 default 4 if ARCH_S5PV210 74 default 2 75 depends on ARM_VIC 76 help 77 The maximum number of VICs available in the system, for 78 power management. 79 80config ARMADA_370_XP_IRQ 81 bool 82 select GENERIC_IRQ_CHIP 83 select PCI_MSI if PCI 84 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 85 86config ALPINE_MSI 87 bool 88 depends on PCI 89 select PCI_MSI 90 select GENERIC_IRQ_CHIP 91 92config ATMEL_AIC_IRQ 93 bool 94 select GENERIC_IRQ_CHIP 95 select IRQ_DOMAIN 96 select GENERIC_IRQ_MULTI_HANDLER 97 select SPARSE_IRQ 98 99config ATMEL_AIC5_IRQ 100 bool 101 select GENERIC_IRQ_CHIP 102 select IRQ_DOMAIN 103 select GENERIC_IRQ_MULTI_HANDLER 104 select SPARSE_IRQ 105 106config I8259 107 bool 108 select IRQ_DOMAIN 109 110config BCM6345_L1_IRQ 111 bool 112 select GENERIC_IRQ_CHIP 113 select IRQ_DOMAIN 114 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 115 116config BCM7038_L1_IRQ 117 bool 118 select GENERIC_IRQ_CHIP 119 select IRQ_DOMAIN 120 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 121 122config BCM7120_L2_IRQ 123 bool 124 select GENERIC_IRQ_CHIP 125 select IRQ_DOMAIN 126 127config BRCMSTB_L2_IRQ 128 bool 129 select GENERIC_IRQ_CHIP 130 select IRQ_DOMAIN 131 132config DAVINCI_AINTC 133 bool 134 select GENERIC_IRQ_CHIP 135 select IRQ_DOMAIN 136 137config DAVINCI_CP_INTC 138 bool 139 select GENERIC_IRQ_CHIP 140 select IRQ_DOMAIN 141 142config DW_APB_ICTL 143 bool 144 select GENERIC_IRQ_CHIP 145 select IRQ_DOMAIN 146 147config FARADAY_FTINTC010 148 bool 149 select IRQ_DOMAIN 150 select GENERIC_IRQ_MULTI_HANDLER 151 select SPARSE_IRQ 152 153config HISILICON_IRQ_MBIGEN 154 bool 155 select ARM_GIC_V3 156 select ARM_GIC_V3_ITS 157 158config IMGPDC_IRQ 159 bool 160 select GENERIC_IRQ_CHIP 161 select IRQ_DOMAIN 162 163config MADERA_IRQ 164 tristate 165 166config IRQ_MIPS_CPU 167 bool 168 select GENERIC_IRQ_CHIP 169 select GENERIC_IRQ_IPI if SYS_SUPPORTS_MULTITHREADING 170 select IRQ_DOMAIN 171 select IRQ_DOMAIN_HIERARCHY if GENERIC_IRQ_IPI 172 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 173 174config CLPS711X_IRQCHIP 175 bool 176 depends on ARCH_CLPS711X 177 select IRQ_DOMAIN 178 select GENERIC_IRQ_MULTI_HANDLER 179 select SPARSE_IRQ 180 default y 181 182config OMPIC 183 bool 184 185config OR1K_PIC 186 bool 187 select IRQ_DOMAIN 188 189config OMAP_IRQCHIP 190 bool 191 select GENERIC_IRQ_CHIP 192 select IRQ_DOMAIN 193 194config ORION_IRQCHIP 195 bool 196 select IRQ_DOMAIN 197 select GENERIC_IRQ_MULTI_HANDLER 198 199config PIC32_EVIC 200 bool 201 select GENERIC_IRQ_CHIP 202 select IRQ_DOMAIN 203 204config JCORE_AIC 205 bool "J-Core integrated AIC" if COMPILE_TEST 206 depends on OF 207 select IRQ_DOMAIN 208 help 209 Support for the J-Core integrated AIC. 210 211config RDA_INTC 212 bool 213 select IRQ_DOMAIN 214 215config RENESAS_INTC_IRQPIN 216 bool 217 select IRQ_DOMAIN 218 219config RENESAS_IRQC 220 bool 221 select GENERIC_IRQ_CHIP 222 select IRQ_DOMAIN 223 224config ST_IRQCHIP 225 bool 226 select REGMAP 227 select MFD_SYSCON 228 help 229 Enables SysCfg Controlled IRQs on STi based platforms. 230 231config TANGO_IRQ 232 bool 233 select IRQ_DOMAIN 234 select GENERIC_IRQ_CHIP 235 236config TB10X_IRQC 237 bool 238 select IRQ_DOMAIN 239 select GENERIC_IRQ_CHIP 240 241config TS4800_IRQ 242 tristate "TS-4800 IRQ controller" 243 select IRQ_DOMAIN 244 depends on HAS_IOMEM 245 depends on SOC_IMX51 || COMPILE_TEST 246 help 247 Support for the TS-4800 FPGA IRQ controller 248 249config VERSATILE_FPGA_IRQ 250 bool 251 select IRQ_DOMAIN 252 253config VERSATILE_FPGA_IRQ_NR 254 int 255 default 4 256 depends on VERSATILE_FPGA_IRQ 257 258config XTENSA_MX 259 bool 260 select IRQ_DOMAIN 261 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 262 263config XILINX_INTC 264 bool 265 select IRQ_DOMAIN 266 267config IRQ_CROSSBAR 268 bool 269 help 270 Support for a CROSSBAR ip that precedes the main interrupt controller. 271 The primary irqchip invokes the crossbar's callback which inturn allocates 272 a free irq and configures the IP. Thus the peripheral interrupts are 273 routed to one of the free irqchip interrupt lines. 274 275config KEYSTONE_IRQ 276 tristate "Keystone 2 IRQ controller IP" 277 depends on ARCH_KEYSTONE 278 help 279 Support for Texas Instruments Keystone 2 IRQ controller IP which 280 is part of the Keystone 2 IPC mechanism 281 282config MIPS_GIC 283 bool 284 select GENERIC_IRQ_IPI 285 select IRQ_DOMAIN_HIERARCHY 286 select MIPS_CM 287 288config INGENIC_IRQ 289 bool 290 depends on MACH_INGENIC 291 default y 292 293config RENESAS_H8300H_INTC 294 bool 295 select IRQ_DOMAIN 296 297config RENESAS_H8S_INTC 298 bool 299 select IRQ_DOMAIN 300 301config IMX_GPCV2 302 bool 303 select IRQ_DOMAIN 304 help 305 Enables the wakeup IRQs for IMX platforms with GPCv2 block 306 307config IRQ_MXS 308 def_bool y if MACH_ASM9260 || ARCH_MXS 309 select IRQ_DOMAIN 310 select STMP_DEVICE 311 312config MSCC_OCELOT_IRQ 313 bool 314 select IRQ_DOMAIN 315 select GENERIC_IRQ_CHIP 316 317config MVEBU_GICP 318 bool 319 320config MVEBU_ICU 321 bool 322 323config MVEBU_ODMI 324 bool 325 select GENERIC_MSI_IRQ_DOMAIN 326 327config MVEBU_PIC 328 bool 329 330config MVEBU_SEI 331 bool 332 333config LS_SCFG_MSI 334 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 335 depends on PCI && PCI_MSI 336 337config PARTITION_PERCPU 338 bool 339 340config EZNPS_GIC 341 bool "NPS400 Global Interrupt Manager (GIM)" 342 depends on ARC || (COMPILE_TEST && !64BIT) 343 select IRQ_DOMAIN 344 help 345 Support the EZchip NPS400 global interrupt controller 346 347config STM32_EXTI 348 bool 349 select IRQ_DOMAIN 350 select GENERIC_IRQ_CHIP 351 352config QCOM_IRQ_COMBINER 353 bool "QCOM IRQ combiner support" 354 depends on ARCH_QCOM && ACPI 355 select IRQ_DOMAIN 356 select IRQ_DOMAIN_HIERARCHY 357 help 358 Say yes here to add support for the IRQ combiner devices embedded 359 in Qualcomm Technologies chips. 360 361config IRQ_UNIPHIER_AIDET 362 bool "UniPhier AIDET support" if COMPILE_TEST 363 depends on ARCH_UNIPHIER || COMPILE_TEST 364 default ARCH_UNIPHIER 365 select IRQ_DOMAIN_HIERARCHY 366 help 367 Support for the UniPhier AIDET (ARM Interrupt Detector). 368 369config MESON_IRQ_GPIO 370 bool "Meson GPIO Interrupt Multiplexer" 371 depends on ARCH_MESON 372 select IRQ_DOMAIN 373 select IRQ_DOMAIN_HIERARCHY 374 help 375 Support Meson SoC Family GPIO Interrupt Multiplexer 376 377config GOLDFISH_PIC 378 bool "Goldfish programmable interrupt controller" 379 depends on MIPS && (GOLDFISH || COMPILE_TEST) 380 select IRQ_DOMAIN 381 help 382 Say yes here to enable Goldfish interrupt controller driver used 383 for Goldfish based virtual platforms. 384 385config QCOM_PDC 386 bool "QCOM PDC" 387 depends on ARCH_QCOM 388 select IRQ_DOMAIN 389 select IRQ_DOMAIN_HIERARCHY 390 help 391 Power Domain Controller driver to manage and configure wakeup 392 IRQs for Qualcomm Technologies Inc (QTI) mobile chips. 393 394config CSKY_MPINTC 395 bool "C-SKY Multi Processor Interrupt Controller" 396 depends on CSKY 397 help 398 Say yes here to enable C-SKY SMP interrupt controller driver used 399 for C-SKY SMP system. 400 In fact it's not mmio map in hw and it use ld/st to visit the 401 controller's register inside CPU. 402 403config CSKY_APB_INTC 404 bool "C-SKY APB Interrupt Controller" 405 depends on CSKY 406 help 407 Say yes here to enable C-SKY APB interrupt controller driver used 408 by C-SKY single core SOC system. It use mmio map apb-bus to visit 409 the controller's register. 410 411config IMX_IRQSTEER 412 bool "i.MX IRQSTEER support" 413 depends on ARCH_MXC || COMPILE_TEST 414 default ARCH_MXC 415 select IRQ_DOMAIN 416 help 417 Support for the i.MX IRQSTEER interrupt multiplexer/remapper. 418 419config LS1X_IRQ 420 bool "Loongson-1 Interrupt Controller" 421 depends on MACH_LOONGSON32 422 default y 423 select IRQ_DOMAIN 424 select GENERIC_IRQ_CHIP 425 help 426 Support for the Loongson-1 platform Interrupt Controller. 427 428endmenu 429 430config SIFIVE_PLIC 431 bool "SiFive Platform-Level Interrupt Controller" 432 depends on RISCV 433 help 434 This enables support for the PLIC chip found in SiFive (and 435 potentially other) RISC-V systems. The PLIC controls devices 436 interrupts and connects them to each core's local interrupt 437 controller. Aside from timer and software interrupts, all other 438 interrupt sources are subordinate to the PLIC. 439 440 If you don't know what to do here, say Y. 441