1config IRQCHIP 2 def_bool y 3 depends on OF_IRQ 4 5config ARM_GIC 6 bool 7 select IRQ_DOMAIN 8 select MULTI_IRQ_HANDLER 9 10config GIC_NON_BANKED 11 bool 12 13config ARM_GIC_V3 14 bool 15 select IRQ_DOMAIN 16 select MULTI_IRQ_HANDLER 17 18config ARM_NVIC 19 bool 20 select IRQ_DOMAIN 21 select GENERIC_IRQ_CHIP 22 23config ARM_VIC 24 bool 25 select IRQ_DOMAIN 26 select MULTI_IRQ_HANDLER 27 28config ARM_VIC_NR 29 int 30 default 4 if ARCH_S5PV210 31 default 2 32 depends on ARM_VIC 33 help 34 The maximum number of VICs available in the system, for 35 power management. 36 37config ATMEL_AIC_IRQ 38 bool 39 select GENERIC_IRQ_CHIP 40 select IRQ_DOMAIN 41 select MULTI_IRQ_HANDLER 42 select SPARSE_IRQ 43 44config ATMEL_AIC5_IRQ 45 bool 46 select GENERIC_IRQ_CHIP 47 select IRQ_DOMAIN 48 select MULTI_IRQ_HANDLER 49 select SPARSE_IRQ 50 51config BRCMSTB_L2_IRQ 52 bool 53 depends on ARM 54 select GENERIC_IRQ_CHIP 55 select IRQ_DOMAIN 56 57config DW_APB_ICTL 58 bool 59 select IRQ_DOMAIN 60 61config IMGPDC_IRQ 62 bool 63 select GENERIC_IRQ_CHIP 64 select IRQ_DOMAIN 65 66config CLPS711X_IRQCHIP 67 bool 68 depends on ARCH_CLPS711X 69 select IRQ_DOMAIN 70 select MULTI_IRQ_HANDLER 71 select SPARSE_IRQ 72 default y 73 74config OR1K_PIC 75 bool 76 select IRQ_DOMAIN 77 78config OMAP_IRQCHIP 79 bool 80 select GENERIC_IRQ_CHIP 81 select IRQ_DOMAIN 82 83config ORION_IRQCHIP 84 bool 85 select IRQ_DOMAIN 86 select MULTI_IRQ_HANDLER 87 88config RENESAS_INTC_IRQPIN 89 bool 90 select IRQ_DOMAIN 91 92config RENESAS_IRQC 93 bool 94 select IRQ_DOMAIN 95 96config TB10X_IRQC 97 bool 98 select IRQ_DOMAIN 99 select GENERIC_IRQ_CHIP 100 101config VERSATILE_FPGA_IRQ 102 bool 103 select IRQ_DOMAIN 104 105config VERSATILE_FPGA_IRQ_NR 106 int 107 default 4 108 depends on VERSATILE_FPGA_IRQ 109 110config XTENSA_MX 111 bool 112 select IRQ_DOMAIN 113 114config IRQ_CROSSBAR 115 bool 116 help 117 Support for a CROSSBAR ip that precedes the main interrupt controller. 118 The primary irqchip invokes the crossbar's callback which inturn allocates 119 a free irq and configures the IP. Thus the peripheral interrupts are 120 routed to one of the free irqchip interrupt lines. 121 122config KEYSTONE_IRQ 123 tristate "Keystone 2 IRQ controller IP" 124 depends on ARCH_KEYSTONE 125 help 126 Support for Texas Instruments Keystone 2 IRQ controller IP which 127 is part of the Keystone 2 IPC mechanism 128