1# SPDX-License-Identifier: GPL-2.0-only 2menu "IRQ chip support" 3 4config IRQCHIP 5 def_bool y 6 depends on OF_IRQ 7 8config ARM_GIC 9 bool 10 select IRQ_DOMAIN_HIERARCHY 11 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 12 13config ARM_GIC_PM 14 bool 15 depends on PM 16 select ARM_GIC 17 18config ARM_GIC_MAX_NR 19 int 20 depends on ARM_GIC 21 default 2 if ARCH_REALVIEW 22 default 1 23 24config ARM_GIC_V2M 25 bool 26 depends on PCI 27 select ARM_GIC 28 select PCI_MSI 29 30config GIC_NON_BANKED 31 bool 32 33config ARM_GIC_V3 34 bool 35 select IRQ_DOMAIN_HIERARCHY 36 select PARTITION_PERCPU 37 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 38 39config ARM_GIC_V3_ITS 40 bool 41 select GENERIC_MSI_IRQ_DOMAIN 42 default ARM_GIC_V3 43 44config ARM_GIC_V3_ITS_PCI 45 bool 46 depends on ARM_GIC_V3_ITS 47 depends on PCI 48 depends on PCI_MSI 49 default ARM_GIC_V3_ITS 50 51config ARM_GIC_V3_ITS_FSL_MC 52 bool 53 depends on ARM_GIC_V3_ITS 54 depends on FSL_MC_BUS 55 default ARM_GIC_V3_ITS 56 57config ARM_NVIC 58 bool 59 select IRQ_DOMAIN_HIERARCHY 60 select GENERIC_IRQ_CHIP 61 62config ARM_VIC 63 bool 64 select IRQ_DOMAIN 65 66config ARM_VIC_NR 67 int 68 default 4 if ARCH_S5PV210 69 default 2 70 depends on ARM_VIC 71 help 72 The maximum number of VICs available in the system, for 73 power management. 74 75config ARMADA_370_XP_IRQ 76 bool 77 select GENERIC_IRQ_CHIP 78 select PCI_MSI if PCI 79 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 80 81config ALPINE_MSI 82 bool 83 depends on PCI 84 select PCI_MSI 85 select GENERIC_IRQ_CHIP 86 87config AL_FIC 88 bool "Amazon's Annapurna Labs Fabric Interrupt Controller" 89 depends on OF || COMPILE_TEST 90 select GENERIC_IRQ_CHIP 91 select IRQ_DOMAIN 92 help 93 Support Amazon's Annapurna Labs Fabric Interrupt Controller. 94 95config ATMEL_AIC_IRQ 96 bool 97 select GENERIC_IRQ_CHIP 98 select IRQ_DOMAIN 99 select SPARSE_IRQ 100 101config ATMEL_AIC5_IRQ 102 bool 103 select GENERIC_IRQ_CHIP 104 select IRQ_DOMAIN 105 select SPARSE_IRQ 106 107config I8259 108 bool 109 select IRQ_DOMAIN 110 111config BCM6345_L1_IRQ 112 bool 113 select GENERIC_IRQ_CHIP 114 select IRQ_DOMAIN 115 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 116 117config BCM7038_L1_IRQ 118 tristate "Broadcom STB 7038-style L1/L2 interrupt controller driver" 119 depends on ARCH_BRCMSTB || BMIPS_GENERIC 120 default ARCH_BRCMSTB || BMIPS_GENERIC 121 select GENERIC_IRQ_CHIP 122 select IRQ_DOMAIN 123 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 124 125config BCM7120_L2_IRQ 126 tristate "Broadcom STB 7120-style L2 interrupt controller driver" 127 depends on ARCH_BRCMSTB || BMIPS_GENERIC 128 default ARCH_BRCMSTB || BMIPS_GENERIC 129 select GENERIC_IRQ_CHIP 130 select IRQ_DOMAIN 131 132config BRCMSTB_L2_IRQ 133 tristate "Broadcom STB generic L2 interrupt controller driver" 134 depends on ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC 135 default ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC 136 select GENERIC_IRQ_CHIP 137 select IRQ_DOMAIN 138 139config DAVINCI_AINTC 140 bool 141 select GENERIC_IRQ_CHIP 142 select IRQ_DOMAIN 143 144config DAVINCI_CP_INTC 145 bool 146 select GENERIC_IRQ_CHIP 147 select IRQ_DOMAIN 148 149config DW_APB_ICTL 150 bool 151 select GENERIC_IRQ_CHIP 152 select IRQ_DOMAIN_HIERARCHY 153 154config FARADAY_FTINTC010 155 bool 156 select IRQ_DOMAIN 157 select SPARSE_IRQ 158 159config HISILICON_IRQ_MBIGEN 160 bool 161 select ARM_GIC_V3 162 select ARM_GIC_V3_ITS 163 164config IMGPDC_IRQ 165 bool 166 select GENERIC_IRQ_CHIP 167 select IRQ_DOMAIN 168 169config IXP4XX_IRQ 170 bool 171 select IRQ_DOMAIN 172 select SPARSE_IRQ 173 174config MADERA_IRQ 175 tristate 176 177config IRQ_MIPS_CPU 178 bool 179 select GENERIC_IRQ_CHIP 180 select GENERIC_IRQ_IPI if SMP && SYS_SUPPORTS_MULTITHREADING 181 select IRQ_DOMAIN 182 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 183 184config CLPS711X_IRQCHIP 185 bool 186 depends on ARCH_CLPS711X 187 select IRQ_DOMAIN 188 select SPARSE_IRQ 189 default y 190 191config OMPIC 192 bool 193 194config OR1K_PIC 195 bool 196 select IRQ_DOMAIN 197 198config OMAP_IRQCHIP 199 bool 200 select GENERIC_IRQ_CHIP 201 select IRQ_DOMAIN 202 203config ORION_IRQCHIP 204 bool 205 select IRQ_DOMAIN 206 207config PIC32_EVIC 208 bool 209 select GENERIC_IRQ_CHIP 210 select IRQ_DOMAIN 211 212config JCORE_AIC 213 bool "J-Core integrated AIC" if COMPILE_TEST 214 depends on OF 215 select IRQ_DOMAIN 216 help 217 Support for the J-Core integrated AIC. 218 219config RDA_INTC 220 bool 221 select IRQ_DOMAIN 222 223config RENESAS_INTC_IRQPIN 224 bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST 225 select IRQ_DOMAIN 226 help 227 Enable support for the Renesas Interrupt Controller for external 228 interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs. 229 230config RENESAS_IRQC 231 bool "Renesas R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} IRQC support" if COMPILE_TEST 232 select GENERIC_IRQ_CHIP 233 select IRQ_DOMAIN 234 help 235 Enable support for the Renesas Interrupt Controller for external 236 devices, as found on R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} SoCs. 237 238config RENESAS_RZA1_IRQC 239 bool "Renesas RZ/A1 IRQC support" if COMPILE_TEST 240 select IRQ_DOMAIN_HIERARCHY 241 help 242 Enable support for the Renesas RZ/A1 Interrupt Controller, to use up 243 to 8 external interrupts with configurable sense select. 244 245config RENESAS_RZG2L_IRQC 246 bool "Renesas RZ/G2L (and alike SoC) IRQC support" if COMPILE_TEST 247 select GENERIC_IRQ_CHIP 248 select IRQ_DOMAIN_HIERARCHY 249 help 250 Enable support for the Renesas RZ/G2L (and alike SoC) Interrupt Controller 251 for external devices. 252 253config SL28CPLD_INTC 254 bool "Kontron sl28cpld IRQ controller" 255 depends on MFD_SL28CPLD=y || COMPILE_TEST 256 select REGMAP_IRQ 257 help 258 Interrupt controller driver for the board management controller 259 found on the Kontron sl28 CPLD. 260 261config ST_IRQCHIP 262 bool 263 select REGMAP 264 select MFD_SYSCON 265 help 266 Enables SysCfg Controlled IRQs on STi based platforms. 267 268config SUN4I_INTC 269 bool 270 271config SUN6I_R_INTC 272 bool 273 select IRQ_DOMAIN_HIERARCHY 274 select IRQ_FASTEOI_HIERARCHY_HANDLERS 275 276config SUNXI_NMI_INTC 277 bool 278 select GENERIC_IRQ_CHIP 279 280config TB10X_IRQC 281 bool 282 select IRQ_DOMAIN 283 select GENERIC_IRQ_CHIP 284 285config TS4800_IRQ 286 tristate "TS-4800 IRQ controller" 287 select IRQ_DOMAIN 288 depends on HAS_IOMEM 289 depends on SOC_IMX51 || COMPILE_TEST 290 help 291 Support for the TS-4800 FPGA IRQ controller 292 293config VERSATILE_FPGA_IRQ 294 bool 295 select IRQ_DOMAIN 296 297config VERSATILE_FPGA_IRQ_NR 298 int 299 default 4 300 depends on VERSATILE_FPGA_IRQ 301 302config XTENSA_MX 303 bool 304 select IRQ_DOMAIN 305 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 306 307config XILINX_INTC 308 bool "Xilinx Interrupt Controller IP" 309 depends on OF_ADDRESS 310 select IRQ_DOMAIN 311 help 312 Support for the Xilinx Interrupt Controller IP core. 313 This is used as a primary controller with MicroBlaze and can also 314 be used as a secondary chained controller on other platforms. 315 316config IRQ_CROSSBAR 317 bool 318 help 319 Support for a CROSSBAR ip that precedes the main interrupt controller. 320 The primary irqchip invokes the crossbar's callback which inturn allocates 321 a free irq and configures the IP. Thus the peripheral interrupts are 322 routed to one of the free irqchip interrupt lines. 323 324config KEYSTONE_IRQ 325 tristate "Keystone 2 IRQ controller IP" 326 depends on ARCH_KEYSTONE 327 help 328 Support for Texas Instruments Keystone 2 IRQ controller IP which 329 is part of the Keystone 2 IPC mechanism 330 331config MIPS_GIC 332 bool 333 select GENERIC_IRQ_IPI if SMP 334 select IRQ_DOMAIN_HIERARCHY 335 select MIPS_CM 336 337config INGENIC_IRQ 338 bool 339 depends on MACH_INGENIC 340 default y 341 342config INGENIC_TCU_IRQ 343 bool "Ingenic JZ47xx TCU interrupt controller" 344 default MACH_INGENIC 345 depends on MIPS || COMPILE_TEST 346 select MFD_SYSCON 347 select GENERIC_IRQ_CHIP 348 help 349 Support for interrupts in the Timer/Counter Unit (TCU) of the Ingenic 350 JZ47xx SoCs. 351 352 If unsure, say N. 353 354config IMX_GPCV2 355 bool 356 select IRQ_DOMAIN 357 help 358 Enables the wakeup IRQs for IMX platforms with GPCv2 block 359 360config IRQ_MXS 361 def_bool y if MACH_ASM9260 || ARCH_MXS 362 select IRQ_DOMAIN 363 select STMP_DEVICE 364 365config MSCC_OCELOT_IRQ 366 bool 367 select IRQ_DOMAIN 368 select GENERIC_IRQ_CHIP 369 370config MVEBU_GICP 371 bool 372 373config MVEBU_ICU 374 bool 375 376config MVEBU_ODMI 377 bool 378 select GENERIC_MSI_IRQ_DOMAIN 379 380config MVEBU_PIC 381 bool 382 383config MVEBU_SEI 384 bool 385 386config LS_EXTIRQ 387 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 388 select MFD_SYSCON 389 390config LS_SCFG_MSI 391 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 392 depends on PCI && PCI_MSI 393 394config PARTITION_PERCPU 395 bool 396 397config STM32_EXTI 398 bool 399 select IRQ_DOMAIN 400 select GENERIC_IRQ_CHIP 401 402config QCOM_IRQ_COMBINER 403 bool "QCOM IRQ combiner support" 404 depends on ARCH_QCOM && ACPI 405 select IRQ_DOMAIN_HIERARCHY 406 help 407 Say yes here to add support for the IRQ combiner devices embedded 408 in Qualcomm Technologies chips. 409 410config IRQ_UNIPHIER_AIDET 411 bool "UniPhier AIDET support" if COMPILE_TEST 412 depends on ARCH_UNIPHIER || COMPILE_TEST 413 default ARCH_UNIPHIER 414 select IRQ_DOMAIN_HIERARCHY 415 help 416 Support for the UniPhier AIDET (ARM Interrupt Detector). 417 418config MESON_IRQ_GPIO 419 tristate "Meson GPIO Interrupt Multiplexer" 420 depends on ARCH_MESON || COMPILE_TEST 421 default ARCH_MESON 422 select IRQ_DOMAIN_HIERARCHY 423 help 424 Support Meson SoC Family GPIO Interrupt Multiplexer 425 426config GOLDFISH_PIC 427 bool "Goldfish programmable interrupt controller" 428 depends on MIPS && (GOLDFISH || COMPILE_TEST) 429 select GENERIC_IRQ_CHIP 430 select IRQ_DOMAIN 431 help 432 Say yes here to enable Goldfish interrupt controller driver used 433 for Goldfish based virtual platforms. 434 435config QCOM_PDC 436 tristate "QCOM PDC" 437 depends on ARCH_QCOM 438 select IRQ_DOMAIN_HIERARCHY 439 help 440 Power Domain Controller driver to manage and configure wakeup 441 IRQs for Qualcomm Technologies Inc (QTI) mobile chips. 442 443config QCOM_MPM 444 tristate "QCOM MPM" 445 depends on ARCH_QCOM 446 depends on MAILBOX 447 select IRQ_DOMAIN_HIERARCHY 448 help 449 MSM Power Manager driver to manage and configure wakeup 450 IRQs for Qualcomm Technologies Inc (QTI) mobile chips. 451 452config CSKY_MPINTC 453 bool 454 depends on CSKY 455 help 456 Say yes here to enable C-SKY SMP interrupt controller driver used 457 for C-SKY SMP system. 458 In fact it's not mmio map in hardware and it uses ld/st to visit the 459 controller's register inside CPU. 460 461config CSKY_APB_INTC 462 bool "C-SKY APB Interrupt Controller" 463 depends on CSKY 464 help 465 Say yes here to enable C-SKY APB interrupt controller driver used 466 by C-SKY single core SOC system. It uses mmio map apb-bus to visit 467 the controller's register. 468 469config IMX_IRQSTEER 470 bool "i.MX IRQSTEER support" 471 depends on ARCH_MXC || COMPILE_TEST 472 default ARCH_MXC 473 select IRQ_DOMAIN 474 help 475 Support for the i.MX IRQSTEER interrupt multiplexer/remapper. 476 477config IMX_INTMUX 478 bool "i.MX INTMUX support" if COMPILE_TEST 479 default y if ARCH_MXC 480 select IRQ_DOMAIN 481 help 482 Support for the i.MX INTMUX interrupt multiplexer. 483 484config LS1X_IRQ 485 bool "Loongson-1 Interrupt Controller" 486 depends on MACH_LOONGSON32 487 default y 488 select IRQ_DOMAIN 489 select GENERIC_IRQ_CHIP 490 help 491 Support for the Loongson-1 platform Interrupt Controller. 492 493config TI_SCI_INTR_IRQCHIP 494 bool 495 depends on TI_SCI_PROTOCOL 496 select IRQ_DOMAIN_HIERARCHY 497 help 498 This enables the irqchip driver support for K3 Interrupt router 499 over TI System Control Interface available on some new TI's SoCs. 500 If you wish to use interrupt router irq resources managed by the 501 TI System Controller, say Y here. Otherwise, say N. 502 503config TI_SCI_INTA_IRQCHIP 504 bool 505 depends on TI_SCI_PROTOCOL 506 select IRQ_DOMAIN_HIERARCHY 507 select TI_SCI_INTA_MSI_DOMAIN 508 help 509 This enables the irqchip driver support for K3 Interrupt aggregator 510 over TI System Control Interface available on some new TI's SoCs. 511 If you wish to use interrupt aggregator irq resources managed by the 512 TI System Controller, say Y here. Otherwise, say N. 513 514config TI_PRUSS_INTC 515 tristate 516 depends on TI_PRUSS 517 default TI_PRUSS 518 select IRQ_DOMAIN 519 help 520 This enables support for the PRU-ICSS Local Interrupt Controller 521 present within a PRU-ICSS subsystem present on various TI SoCs. 522 The PRUSS INTC enables various interrupts to be routed to multiple 523 different processors within the SoC. 524 525config RISCV_INTC 526 bool "RISC-V Local Interrupt Controller" 527 depends on RISCV 528 default y 529 help 530 This enables support for the per-HART local interrupt controller 531 found in standard RISC-V systems. The per-HART local interrupt 532 controller handles timer interrupts, software interrupts, and 533 hardware interrupts. Without a per-HART local interrupt controller, 534 a RISC-V system will be unable to handle any interrupts. 535 536 If you don't know what to do here, say Y. 537 538config SIFIVE_PLIC 539 bool "SiFive Platform-Level Interrupt Controller" 540 depends on RISCV 541 select IRQ_DOMAIN_HIERARCHY 542 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 543 help 544 This enables support for the PLIC chip found in SiFive (and 545 potentially other) RISC-V systems. The PLIC controls devices 546 interrupts and connects them to each core's local interrupt 547 controller. Aside from timer and software interrupts, all other 548 interrupt sources are subordinate to the PLIC. 549 550 If you don't know what to do here, say Y. 551 552config EXYNOS_IRQ_COMBINER 553 bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST 554 depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST 555 help 556 Say yes here to add support for the IRQ combiner devices embedded 557 in Samsung Exynos chips. 558 559config IRQ_LOONGARCH_CPU 560 bool 561 select GENERIC_IRQ_CHIP 562 select IRQ_DOMAIN 563 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 564 help 565 Support for the LoongArch CPU Interrupt Controller. For details of 566 irq chip hierarchy on LoongArch platforms please read the document 567 Documentation/loongarch/irq-chip-model.rst. 568 569config LOONGSON_LIOINTC 570 bool "Loongson Local I/O Interrupt Controller" 571 depends on MACH_LOONGSON64 572 default y 573 select IRQ_DOMAIN 574 select GENERIC_IRQ_CHIP 575 help 576 Support for the Loongson Local I/O Interrupt Controller. 577 578config LOONGSON_EIOINTC 579 bool "Loongson Extend I/O Interrupt Controller" 580 depends on LOONGARCH 581 depends on MACH_LOONGSON64 582 default MACH_LOONGSON64 583 select IRQ_DOMAIN_HIERARCHY 584 select GENERIC_IRQ_CHIP 585 help 586 Support for the Loongson3 Extend I/O Interrupt Vector Controller. 587 588config LOONGSON_HTPIC 589 bool "Loongson3 HyperTransport PIC Controller" 590 depends on MACH_LOONGSON64 && MIPS 591 default y 592 select IRQ_DOMAIN 593 select GENERIC_IRQ_CHIP 594 help 595 Support for the Loongson-3 HyperTransport PIC Controller. 596 597config LOONGSON_HTVEC 598 bool "Loongson HyperTransport Interrupt Vector Controller" 599 depends on MACH_LOONGSON64 600 default MACH_LOONGSON64 601 select IRQ_DOMAIN_HIERARCHY 602 help 603 Support for the Loongson HyperTransport Interrupt Vector Controller. 604 605config LOONGSON_PCH_PIC 606 bool "Loongson PCH PIC Controller" 607 depends on MACH_LOONGSON64 608 default MACH_LOONGSON64 609 select IRQ_DOMAIN_HIERARCHY 610 select IRQ_FASTEOI_HIERARCHY_HANDLERS 611 help 612 Support for the Loongson PCH PIC Controller. 613 614config LOONGSON_PCH_MSI 615 bool "Loongson PCH MSI Controller" 616 depends on MACH_LOONGSON64 617 depends on PCI 618 default MACH_LOONGSON64 619 select IRQ_DOMAIN_HIERARCHY 620 select PCI_MSI 621 help 622 Support for the Loongson PCH MSI Controller. 623 624config LOONGSON_PCH_LPC 625 bool "Loongson PCH LPC Controller" 626 depends on MACH_LOONGSON64 627 default (MACH_LOONGSON64 && LOONGARCH) 628 select IRQ_DOMAIN_HIERARCHY 629 help 630 Support for the Loongson PCH LPC Controller. 631 632config MST_IRQ 633 bool "MStar Interrupt Controller" 634 depends on ARCH_MEDIATEK || ARCH_MSTARV7 || COMPILE_TEST 635 default ARCH_MEDIATEK 636 select IRQ_DOMAIN 637 select IRQ_DOMAIN_HIERARCHY 638 help 639 Support MStar Interrupt Controller. 640 641config WPCM450_AIC 642 bool "Nuvoton WPCM450 Advanced Interrupt Controller" 643 depends on ARCH_WPCM450 644 help 645 Support for the interrupt controller in the Nuvoton WPCM450 BMC SoC. 646 647config IRQ_IDT3243X 648 bool 649 select GENERIC_IRQ_CHIP 650 select IRQ_DOMAIN 651 652config APPLE_AIC 653 bool "Apple Interrupt Controller (AIC)" 654 depends on ARM64 655 depends on ARCH_APPLE || COMPILE_TEST 656 help 657 Support for the Apple Interrupt Controller found on Apple Silicon SoCs, 658 such as the M1. 659 660config MCHP_EIC 661 bool "Microchip External Interrupt Controller" 662 depends on ARCH_AT91 || COMPILE_TEST 663 select IRQ_DOMAIN 664 select IRQ_DOMAIN_HIERARCHY 665 help 666 Support for Microchip External Interrupt Controller. 667 668config SUNPLUS_SP7021_INTC 669 bool "Sunplus SP7021 interrupt controller" if COMPILE_TEST 670 default SOC_SP7021 671 help 672 Support for the Sunplus SP7021 Interrupt Controller IP core. 673 SP7021 SoC has 2 Chips: C-Chip & P-Chip. This is used as a 674 chained controller, routing all interrupt source in P-Chip to 675 the primary controller on C-Chip. 676 677endmenu 678