1config IRQCHIP 2 def_bool y 3 depends on OF_IRQ 4 5config ARM_GIC 6 bool 7 select IRQ_DOMAIN 8 select MULTI_IRQ_HANDLER 9 10config GIC_NON_BANKED 11 bool 12 13config ARM_NVIC 14 bool 15 select IRQ_DOMAIN 16 select GENERIC_IRQ_CHIP 17 18config ARM_VIC 19 bool 20 select IRQ_DOMAIN 21 select MULTI_IRQ_HANDLER 22 23config ARM_VIC_NR 24 int 25 default 4 if ARCH_S5PV210 26 default 3 if ARCH_S5PC100 27 default 2 28 depends on ARM_VIC 29 help 30 The maximum number of VICs available in the system, for 31 power management. 32 33config BRCMSTB_L2_IRQ 34 bool 35 depends on ARM 36 select GENERIC_IRQ_CHIP 37 select IRQ_DOMAIN 38 39config DW_APB_ICTL 40 bool 41 select IRQ_DOMAIN 42 43config IMGPDC_IRQ 44 bool 45 select GENERIC_IRQ_CHIP 46 select IRQ_DOMAIN 47 48config CLPS711X_IRQCHIP 49 bool 50 depends on ARCH_CLPS711X 51 select IRQ_DOMAIN 52 select MULTI_IRQ_HANDLER 53 select SPARSE_IRQ 54 default y 55 56config ORION_IRQCHIP 57 bool 58 select IRQ_DOMAIN 59 select MULTI_IRQ_HANDLER 60 61config RENESAS_INTC_IRQPIN 62 bool 63 select IRQ_DOMAIN 64 65config RENESAS_IRQC 66 bool 67 select IRQ_DOMAIN 68 69config TB10X_IRQC 70 bool 71 select IRQ_DOMAIN 72 select GENERIC_IRQ_CHIP 73 74config VERSATILE_FPGA_IRQ 75 bool 76 select IRQ_DOMAIN 77 78config VERSATILE_FPGA_IRQ_NR 79 int 80 default 4 81 depends on VERSATILE_FPGA_IRQ 82 83config XTENSA_MX 84 bool 85 select IRQ_DOMAIN 86 87config IRQ_CROSSBAR 88 bool 89 help 90 Support for a CROSSBAR ip that preceeds the main interrupt controller. 91 The primary irqchip invokes the crossbar's callback which inturn allocates 92 a free irq and configures the IP. Thus the peripheral interrupts are 93 routed to one of the free irqchip interrupt lines. 94