1config IRQCHIP 2 def_bool y 3 depends on OF_IRQ 4 5config ARM_GIC 6 bool 7 select IRQ_DOMAIN 8 select IRQ_DOMAIN_HIERARCHY 9 select MULTI_IRQ_HANDLER 10 11config ARM_GIC_PM 12 bool 13 depends on PM 14 select ARM_GIC 15 select PM_CLK 16 17config ARM_GIC_MAX_NR 18 int 19 default 2 if ARCH_REALVIEW 20 default 1 21 22config ARM_GIC_V2M 23 bool 24 depends on PCI 25 select ARM_GIC 26 select PCI_MSI 27 28config GIC_NON_BANKED 29 bool 30 31config ARM_GIC_V3 32 bool 33 select IRQ_DOMAIN 34 select MULTI_IRQ_HANDLER 35 select IRQ_DOMAIN_HIERARCHY 36 select PARTITION_PERCPU 37 38config ARM_GIC_V3_ITS 39 bool 40 depends on PCI 41 depends on PCI_MSI 42 select ACPI_IORT if ACPI 43 44config ARM_NVIC 45 bool 46 select IRQ_DOMAIN 47 select IRQ_DOMAIN_HIERARCHY 48 select GENERIC_IRQ_CHIP 49 50config ARM_VIC 51 bool 52 select IRQ_DOMAIN 53 select MULTI_IRQ_HANDLER 54 55config ARM_VIC_NR 56 int 57 default 4 if ARCH_S5PV210 58 default 2 59 depends on ARM_VIC 60 help 61 The maximum number of VICs available in the system, for 62 power management. 63 64config ARMADA_370_XP_IRQ 65 bool 66 select GENERIC_IRQ_CHIP 67 select PCI_MSI if PCI 68 69config ALPINE_MSI 70 bool 71 depends on PCI 72 select PCI_MSI 73 select GENERIC_IRQ_CHIP 74 75config ATMEL_AIC_IRQ 76 bool 77 select GENERIC_IRQ_CHIP 78 select IRQ_DOMAIN 79 select MULTI_IRQ_HANDLER 80 select SPARSE_IRQ 81 82config ATMEL_AIC5_IRQ 83 bool 84 select GENERIC_IRQ_CHIP 85 select IRQ_DOMAIN 86 select MULTI_IRQ_HANDLER 87 select SPARSE_IRQ 88 89config I8259 90 bool 91 select IRQ_DOMAIN 92 93config BCM6345_L1_IRQ 94 bool 95 select GENERIC_IRQ_CHIP 96 select IRQ_DOMAIN 97 98config BCM7038_L1_IRQ 99 bool 100 select GENERIC_IRQ_CHIP 101 select IRQ_DOMAIN 102 103config BCM7120_L2_IRQ 104 bool 105 select GENERIC_IRQ_CHIP 106 select IRQ_DOMAIN 107 108config BRCMSTB_L2_IRQ 109 bool 110 select GENERIC_IRQ_CHIP 111 select IRQ_DOMAIN 112 113config DW_APB_ICTL 114 bool 115 select GENERIC_IRQ_CHIP 116 select IRQ_DOMAIN 117 118config FARADAY_FTINTC010 119 bool 120 select IRQ_DOMAIN 121 select MULTI_IRQ_HANDLER 122 select SPARSE_IRQ 123 124config HISILICON_IRQ_MBIGEN 125 bool 126 select ARM_GIC_V3 127 select ARM_GIC_V3_ITS 128 129config IMGPDC_IRQ 130 bool 131 select GENERIC_IRQ_CHIP 132 select IRQ_DOMAIN 133 134config IRQ_MIPS_CPU 135 bool 136 select GENERIC_IRQ_CHIP 137 select IRQ_DOMAIN 138 139config CLPS711X_IRQCHIP 140 bool 141 depends on ARCH_CLPS711X 142 select IRQ_DOMAIN 143 select MULTI_IRQ_HANDLER 144 select SPARSE_IRQ 145 default y 146 147config OR1K_PIC 148 bool 149 select IRQ_DOMAIN 150 151config OMAP_IRQCHIP 152 bool 153 select GENERIC_IRQ_CHIP 154 select IRQ_DOMAIN 155 156config ORION_IRQCHIP 157 bool 158 select IRQ_DOMAIN 159 select MULTI_IRQ_HANDLER 160 161config PIC32_EVIC 162 bool 163 select GENERIC_IRQ_CHIP 164 select IRQ_DOMAIN 165 166config JCORE_AIC 167 bool "J-Core integrated AIC" if COMPILE_TEST 168 depends on OF 169 select IRQ_DOMAIN 170 help 171 Support for the J-Core integrated AIC. 172 173config RENESAS_INTC_IRQPIN 174 bool 175 select IRQ_DOMAIN 176 177config RENESAS_IRQC 178 bool 179 select GENERIC_IRQ_CHIP 180 select IRQ_DOMAIN 181 182config ST_IRQCHIP 183 bool 184 select REGMAP 185 select MFD_SYSCON 186 help 187 Enables SysCfg Controlled IRQs on STi based platforms. 188 189config TANGO_IRQ 190 bool 191 select IRQ_DOMAIN 192 select GENERIC_IRQ_CHIP 193 194config TB10X_IRQC 195 bool 196 select IRQ_DOMAIN 197 select GENERIC_IRQ_CHIP 198 199config TS4800_IRQ 200 tristate "TS-4800 IRQ controller" 201 select IRQ_DOMAIN 202 depends on HAS_IOMEM 203 depends on SOC_IMX51 || COMPILE_TEST 204 help 205 Support for the TS-4800 FPGA IRQ controller 206 207config VERSATILE_FPGA_IRQ 208 bool 209 select IRQ_DOMAIN 210 211config VERSATILE_FPGA_IRQ_NR 212 int 213 default 4 214 depends on VERSATILE_FPGA_IRQ 215 216config XTENSA_MX 217 bool 218 select IRQ_DOMAIN 219 220config XILINX_INTC 221 bool 222 select IRQ_DOMAIN 223 224config IRQ_CROSSBAR 225 bool 226 help 227 Support for a CROSSBAR ip that precedes the main interrupt controller. 228 The primary irqchip invokes the crossbar's callback which inturn allocates 229 a free irq and configures the IP. Thus the peripheral interrupts are 230 routed to one of the free irqchip interrupt lines. 231 232config KEYSTONE_IRQ 233 tristate "Keystone 2 IRQ controller IP" 234 depends on ARCH_KEYSTONE 235 help 236 Support for Texas Instruments Keystone 2 IRQ controller IP which 237 is part of the Keystone 2 IPC mechanism 238 239config MIPS_GIC 240 bool 241 select GENERIC_IRQ_IPI 242 select IRQ_DOMAIN_HIERARCHY 243 select MIPS_CM 244 245config INGENIC_IRQ 246 bool 247 depends on MACH_INGENIC 248 default y 249 250config RENESAS_H8300H_INTC 251 bool 252 select IRQ_DOMAIN 253 254config RENESAS_H8S_INTC 255 bool 256 select IRQ_DOMAIN 257 258config IMX_GPCV2 259 bool 260 select IRQ_DOMAIN 261 help 262 Enables the wakeup IRQs for IMX platforms with GPCv2 block 263 264config IRQ_MXS 265 def_bool y if MACH_ASM9260 || ARCH_MXS 266 select IRQ_DOMAIN 267 select STMP_DEVICE 268 269config MVEBU_ODMI 270 bool 271 select GENERIC_MSI_IRQ_DOMAIN 272 273config MVEBU_PIC 274 bool 275 276config LS_SCFG_MSI 277 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 278 depends on PCI && PCI_MSI 279 280config PARTITION_PERCPU 281 bool 282 283config EZNPS_GIC 284 bool "NPS400 Global Interrupt Manager (GIM)" 285 depends on ARC || (COMPILE_TEST && !64BIT) 286 select IRQ_DOMAIN 287 help 288 Support the EZchip NPS400 global interrupt controller 289 290config STM32_EXTI 291 bool 292 select IRQ_DOMAIN 293 294config QCOM_IRQ_COMBINER 295 bool "QCOM IRQ combiner support" 296 depends on ARCH_QCOM && ACPI 297 select IRQ_DOMAIN 298 select IRQ_DOMAIN_HIERARCHY 299 help 300 Say yes here to add support for the IRQ combiner devices embedded 301 in Qualcomm Technologies chips. 302