1menu "IRQ chip support" 2 3config IRQCHIP 4 def_bool y 5 depends on OF_IRQ 6 7config ARM_GIC 8 bool 9 select IRQ_DOMAIN_HIERARCHY 10 select GENERIC_IRQ_MULTI_HANDLER 11 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 12 13config ARM_GIC_PM 14 bool 15 depends on PM 16 select ARM_GIC 17 select PM_CLK 18 19config ARM_GIC_MAX_NR 20 int 21 default 2 if ARCH_REALVIEW 22 default 1 23 24config ARM_GIC_V2M 25 bool 26 depends on PCI 27 select ARM_GIC 28 select PCI_MSI 29 30config GIC_NON_BANKED 31 bool 32 33config ARM_GIC_V3 34 bool 35 select GENERIC_IRQ_MULTI_HANDLER 36 select IRQ_DOMAIN_HIERARCHY 37 select PARTITION_PERCPU 38 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 39 40config ARM_GIC_V3_ITS 41 bool 42 select GENERIC_MSI_IRQ_DOMAIN 43 default ARM_GIC_V3 44 45config ARM_GIC_V3_ITS_PCI 46 bool 47 depends on ARM_GIC_V3_ITS 48 depends on PCI 49 depends on PCI_MSI 50 default ARM_GIC_V3_ITS 51 52config ARM_GIC_V3_ITS_FSL_MC 53 bool 54 depends on ARM_GIC_V3_ITS 55 depends on FSL_MC_BUS 56 default ARM_GIC_V3_ITS 57 58config ARM_NVIC 59 bool 60 select IRQ_DOMAIN_HIERARCHY 61 select GENERIC_IRQ_CHIP 62 63config ARM_VIC 64 bool 65 select IRQ_DOMAIN 66 select GENERIC_IRQ_MULTI_HANDLER 67 68config ARM_VIC_NR 69 int 70 default 4 if ARCH_S5PV210 71 default 2 72 depends on ARM_VIC 73 help 74 The maximum number of VICs available in the system, for 75 power management. 76 77config ARMADA_370_XP_IRQ 78 bool 79 select GENERIC_IRQ_CHIP 80 select PCI_MSI if PCI 81 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 82 83config ALPINE_MSI 84 bool 85 depends on PCI 86 select PCI_MSI 87 select GENERIC_IRQ_CHIP 88 89config ATMEL_AIC_IRQ 90 bool 91 select GENERIC_IRQ_CHIP 92 select IRQ_DOMAIN 93 select GENERIC_IRQ_MULTI_HANDLER 94 select SPARSE_IRQ 95 96config ATMEL_AIC5_IRQ 97 bool 98 select GENERIC_IRQ_CHIP 99 select IRQ_DOMAIN 100 select GENERIC_IRQ_MULTI_HANDLER 101 select SPARSE_IRQ 102 103config I8259 104 bool 105 select IRQ_DOMAIN 106 107config BCM6345_L1_IRQ 108 bool 109 select GENERIC_IRQ_CHIP 110 select IRQ_DOMAIN 111 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 112 113config BCM7038_L1_IRQ 114 bool 115 select GENERIC_IRQ_CHIP 116 select IRQ_DOMAIN 117 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 118 119config BCM7120_L2_IRQ 120 bool 121 select GENERIC_IRQ_CHIP 122 select IRQ_DOMAIN 123 124config BRCMSTB_L2_IRQ 125 bool 126 select GENERIC_IRQ_CHIP 127 select IRQ_DOMAIN 128 129config DAVINCI_AINTC 130 bool 131 select GENERIC_IRQ_CHIP 132 select IRQ_DOMAIN 133 134config DAVINCI_CP_INTC 135 bool 136 select GENERIC_IRQ_CHIP 137 select IRQ_DOMAIN 138 139config DW_APB_ICTL 140 bool 141 select GENERIC_IRQ_CHIP 142 select IRQ_DOMAIN 143 144config FARADAY_FTINTC010 145 bool 146 select IRQ_DOMAIN 147 select GENERIC_IRQ_MULTI_HANDLER 148 select SPARSE_IRQ 149 150config HISILICON_IRQ_MBIGEN 151 bool 152 select ARM_GIC_V3 153 select ARM_GIC_V3_ITS 154 155config IMGPDC_IRQ 156 bool 157 select GENERIC_IRQ_CHIP 158 select IRQ_DOMAIN 159 160config IXP4XX_IRQ 161 bool 162 select IRQ_DOMAIN 163 select GENERIC_IRQ_MULTI_HANDLER 164 select SPARSE_IRQ 165 166config MADERA_IRQ 167 tristate 168 169config IRQ_MIPS_CPU 170 bool 171 select GENERIC_IRQ_CHIP 172 select GENERIC_IRQ_IPI if SYS_SUPPORTS_MULTITHREADING 173 select IRQ_DOMAIN 174 select IRQ_DOMAIN_HIERARCHY if GENERIC_IRQ_IPI 175 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 176 177config CLPS711X_IRQCHIP 178 bool 179 depends on ARCH_CLPS711X 180 select IRQ_DOMAIN 181 select GENERIC_IRQ_MULTI_HANDLER 182 select SPARSE_IRQ 183 default y 184 185config OMPIC 186 bool 187 188config OR1K_PIC 189 bool 190 select IRQ_DOMAIN 191 192config OMAP_IRQCHIP 193 bool 194 select GENERIC_IRQ_CHIP 195 select IRQ_DOMAIN 196 197config ORION_IRQCHIP 198 bool 199 select IRQ_DOMAIN 200 select GENERIC_IRQ_MULTI_HANDLER 201 202config PIC32_EVIC 203 bool 204 select GENERIC_IRQ_CHIP 205 select IRQ_DOMAIN 206 207config JCORE_AIC 208 bool "J-Core integrated AIC" if COMPILE_TEST 209 depends on OF 210 select IRQ_DOMAIN 211 help 212 Support for the J-Core integrated AIC. 213 214config RDA_INTC 215 bool 216 select IRQ_DOMAIN 217 218config RENESAS_INTC_IRQPIN 219 bool 220 select IRQ_DOMAIN 221 222config RENESAS_IRQC 223 bool 224 select GENERIC_IRQ_CHIP 225 select IRQ_DOMAIN 226 227config ST_IRQCHIP 228 bool 229 select REGMAP 230 select MFD_SYSCON 231 help 232 Enables SysCfg Controlled IRQs on STi based platforms. 233 234config TANGO_IRQ 235 bool 236 select IRQ_DOMAIN 237 select GENERIC_IRQ_CHIP 238 239config TB10X_IRQC 240 bool 241 select IRQ_DOMAIN 242 select GENERIC_IRQ_CHIP 243 244config TS4800_IRQ 245 tristate "TS-4800 IRQ controller" 246 select IRQ_DOMAIN 247 depends on HAS_IOMEM 248 depends on SOC_IMX51 || COMPILE_TEST 249 help 250 Support for the TS-4800 FPGA IRQ controller 251 252config VERSATILE_FPGA_IRQ 253 bool 254 select IRQ_DOMAIN 255 256config VERSATILE_FPGA_IRQ_NR 257 int 258 default 4 259 depends on VERSATILE_FPGA_IRQ 260 261config XTENSA_MX 262 bool 263 select IRQ_DOMAIN 264 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 265 266config XILINX_INTC 267 bool 268 select IRQ_DOMAIN 269 270config IRQ_CROSSBAR 271 bool 272 help 273 Support for a CROSSBAR ip that precedes the main interrupt controller. 274 The primary irqchip invokes the crossbar's callback which inturn allocates 275 a free irq and configures the IP. Thus the peripheral interrupts are 276 routed to one of the free irqchip interrupt lines. 277 278config KEYSTONE_IRQ 279 tristate "Keystone 2 IRQ controller IP" 280 depends on ARCH_KEYSTONE 281 help 282 Support for Texas Instruments Keystone 2 IRQ controller IP which 283 is part of the Keystone 2 IPC mechanism 284 285config MIPS_GIC 286 bool 287 select GENERIC_IRQ_IPI 288 select IRQ_DOMAIN_HIERARCHY 289 select MIPS_CM 290 291config INGENIC_IRQ 292 bool 293 depends on MACH_INGENIC 294 default y 295 296config RENESAS_H8300H_INTC 297 bool 298 select IRQ_DOMAIN 299 300config RENESAS_H8S_INTC 301 bool 302 select IRQ_DOMAIN 303 304config IMX_GPCV2 305 bool 306 select IRQ_DOMAIN 307 help 308 Enables the wakeup IRQs for IMX platforms with GPCv2 block 309 310config IRQ_MXS 311 def_bool y if MACH_ASM9260 || ARCH_MXS 312 select IRQ_DOMAIN 313 select STMP_DEVICE 314 315config MSCC_OCELOT_IRQ 316 bool 317 select IRQ_DOMAIN 318 select GENERIC_IRQ_CHIP 319 320config MVEBU_GICP 321 bool 322 323config MVEBU_ICU 324 bool 325 326config MVEBU_ODMI 327 bool 328 select GENERIC_MSI_IRQ_DOMAIN 329 330config MVEBU_PIC 331 bool 332 333config MVEBU_SEI 334 bool 335 336config LS_SCFG_MSI 337 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 338 depends on PCI && PCI_MSI 339 340config PARTITION_PERCPU 341 bool 342 343config EZNPS_GIC 344 bool "NPS400 Global Interrupt Manager (GIM)" 345 depends on ARC || (COMPILE_TEST && !64BIT) 346 select IRQ_DOMAIN 347 help 348 Support the EZchip NPS400 global interrupt controller 349 350config STM32_EXTI 351 bool 352 select IRQ_DOMAIN 353 select GENERIC_IRQ_CHIP 354 355config QCOM_IRQ_COMBINER 356 bool "QCOM IRQ combiner support" 357 depends on ARCH_QCOM && ACPI 358 select IRQ_DOMAIN_HIERARCHY 359 help 360 Say yes here to add support for the IRQ combiner devices embedded 361 in Qualcomm Technologies chips. 362 363config IRQ_UNIPHIER_AIDET 364 bool "UniPhier AIDET support" if COMPILE_TEST 365 depends on ARCH_UNIPHIER || COMPILE_TEST 366 default ARCH_UNIPHIER 367 select IRQ_DOMAIN_HIERARCHY 368 help 369 Support for the UniPhier AIDET (ARM Interrupt Detector). 370 371config MESON_IRQ_GPIO 372 bool "Meson GPIO Interrupt Multiplexer" 373 depends on ARCH_MESON 374 select IRQ_DOMAIN_HIERARCHY 375 help 376 Support Meson SoC Family GPIO Interrupt Multiplexer 377 378config GOLDFISH_PIC 379 bool "Goldfish programmable interrupt controller" 380 depends on MIPS && (GOLDFISH || COMPILE_TEST) 381 select IRQ_DOMAIN 382 help 383 Say yes here to enable Goldfish interrupt controller driver used 384 for Goldfish based virtual platforms. 385 386config QCOM_PDC 387 bool "QCOM PDC" 388 depends on ARCH_QCOM 389 select IRQ_DOMAIN_HIERARCHY 390 help 391 Power Domain Controller driver to manage and configure wakeup 392 IRQs for Qualcomm Technologies Inc (QTI) mobile chips. 393 394config CSKY_MPINTC 395 bool "C-SKY Multi Processor Interrupt Controller" 396 depends on CSKY 397 help 398 Say yes here to enable C-SKY SMP interrupt controller driver used 399 for C-SKY SMP system. 400 In fact it's not mmio map in hw and it use ld/st to visit the 401 controller's register inside CPU. 402 403config CSKY_APB_INTC 404 bool "C-SKY APB Interrupt Controller" 405 depends on CSKY 406 help 407 Say yes here to enable C-SKY APB interrupt controller driver used 408 by C-SKY single core SOC system. It use mmio map apb-bus to visit 409 the controller's register. 410 411config IMX_IRQSTEER 412 bool "i.MX IRQSTEER support" 413 depends on ARCH_MXC || COMPILE_TEST 414 default ARCH_MXC 415 select IRQ_DOMAIN 416 help 417 Support for the i.MX IRQSTEER interrupt multiplexer/remapper. 418 419config LS1X_IRQ 420 bool "Loongson-1 Interrupt Controller" 421 depends on MACH_LOONGSON32 422 default y 423 select IRQ_DOMAIN 424 select GENERIC_IRQ_CHIP 425 help 426 Support for the Loongson-1 platform Interrupt Controller. 427 428config TI_SCI_INTR_IRQCHIP 429 bool 430 depends on TI_SCI_PROTOCOL 431 select IRQ_DOMAIN_HIERARCHY 432 help 433 This enables the irqchip driver support for K3 Interrupt router 434 over TI System Control Interface available on some new TI's SoCs. 435 If you wish to use interrupt router irq resources managed by the 436 TI System Controller, say Y here. Otherwise, say N. 437 438config TI_SCI_INTA_IRQCHIP 439 bool 440 depends on TI_SCI_PROTOCOL 441 select IRQ_DOMAIN_HIERARCHY 442 select TI_SCI_INTA_MSI_DOMAIN 443 help 444 This enables the irqchip driver support for K3 Interrupt aggregator 445 over TI System Control Interface available on some new TI's SoCs. 446 If you wish to use interrupt aggregator irq resources managed by the 447 TI System Controller, say Y here. Otherwise, say N. 448 449endmenu 450 451config SIFIVE_PLIC 452 bool "SiFive Platform-Level Interrupt Controller" 453 depends on RISCV 454 help 455 This enables support for the PLIC chip found in SiFive (and 456 potentially other) RISC-V systems. The PLIC controls devices 457 interrupts and connects them to each core's local interrupt 458 controller. Aside from timer and software interrupts, all other 459 interrupt sources are subordinate to the PLIC. 460 461 If you don't know what to do here, say Y. 462