1# SPDX-License-Identifier: GPL-2.0-only 2menu "IRQ chip support" 3 4config IRQCHIP 5 def_bool y 6 depends on (OF_IRQ || ACPI_GENERIC_GSI) 7 8config ARM_GIC 9 bool 10 depends on OF 11 select IRQ_DOMAIN_HIERARCHY 12 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 13 14config ARM_GIC_PM 15 bool 16 depends on PM 17 select ARM_GIC 18 19config ARM_GIC_MAX_NR 20 int 21 depends on ARM_GIC 22 default 2 if ARCH_REALVIEW 23 default 1 24 25config ARM_GIC_V2M 26 bool 27 depends on PCI 28 select ARM_GIC 29 select PCI_MSI 30 31config GIC_NON_BANKED 32 bool 33 34config ARM_GIC_V3 35 bool 36 select IRQ_DOMAIN_HIERARCHY 37 select PARTITION_PERCPU 38 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 39 select HAVE_ARM_SMCCC_DISCOVERY 40 41config ARM_GIC_V3_ITS 42 bool 43 select GENERIC_MSI_IRQ 44 default ARM_GIC_V3 45 46config ARM_GIC_V3_ITS_PCI 47 bool 48 depends on ARM_GIC_V3_ITS 49 depends on PCI 50 depends on PCI_MSI 51 default ARM_GIC_V3_ITS 52 53config ARM_GIC_V3_ITS_FSL_MC 54 bool 55 depends on ARM_GIC_V3_ITS 56 depends on FSL_MC_BUS 57 default ARM_GIC_V3_ITS 58 59config ARM_NVIC 60 bool 61 select IRQ_DOMAIN_HIERARCHY 62 select GENERIC_IRQ_CHIP 63 64config ARM_VIC 65 bool 66 select IRQ_DOMAIN 67 68config ARM_VIC_NR 69 int 70 default 4 if ARCH_S5PV210 71 default 2 72 depends on ARM_VIC 73 help 74 The maximum number of VICs available in the system, for 75 power management. 76 77config ARMADA_370_XP_IRQ 78 bool 79 select GENERIC_IRQ_CHIP 80 select PCI_MSI if PCI 81 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 82 83config ALPINE_MSI 84 bool 85 depends on PCI 86 select PCI_MSI 87 select GENERIC_IRQ_CHIP 88 89config AL_FIC 90 bool "Amazon's Annapurna Labs Fabric Interrupt Controller" 91 depends on OF 92 select GENERIC_IRQ_CHIP 93 select IRQ_DOMAIN 94 help 95 Support Amazon's Annapurna Labs Fabric Interrupt Controller. 96 97config ATMEL_AIC_IRQ 98 bool 99 select GENERIC_IRQ_CHIP 100 select IRQ_DOMAIN 101 select SPARSE_IRQ 102 103config ATMEL_AIC5_IRQ 104 bool 105 select GENERIC_IRQ_CHIP 106 select IRQ_DOMAIN 107 select SPARSE_IRQ 108 109config I8259 110 bool 111 select IRQ_DOMAIN 112 113config BCM6345_L1_IRQ 114 bool 115 select GENERIC_IRQ_CHIP 116 select IRQ_DOMAIN 117 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 118 119config BCM7038_L1_IRQ 120 tristate "Broadcom STB 7038-style L1/L2 interrupt controller driver" 121 depends on ARCH_BRCMSTB || BMIPS_GENERIC 122 default ARCH_BRCMSTB || BMIPS_GENERIC 123 select GENERIC_IRQ_CHIP 124 select IRQ_DOMAIN 125 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 126 127config BCM7120_L2_IRQ 128 tristate "Broadcom STB 7120-style L2 interrupt controller driver" 129 depends on ARCH_BRCMSTB || BMIPS_GENERIC 130 default ARCH_BRCMSTB || BMIPS_GENERIC 131 select GENERIC_IRQ_CHIP 132 select IRQ_DOMAIN 133 134config BRCMSTB_L2_IRQ 135 tristate "Broadcom STB generic L2 interrupt controller driver" 136 depends on ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC 137 default ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC 138 select GENERIC_IRQ_CHIP 139 select IRQ_DOMAIN 140 141config DAVINCI_CP_INTC 142 bool 143 select GENERIC_IRQ_CHIP 144 select IRQ_DOMAIN 145 146config DW_APB_ICTL 147 bool 148 select GENERIC_IRQ_CHIP 149 select IRQ_DOMAIN_HIERARCHY 150 151config FARADAY_FTINTC010 152 bool 153 select IRQ_DOMAIN 154 select SPARSE_IRQ 155 156config HISILICON_IRQ_MBIGEN 157 bool 158 select ARM_GIC_V3 159 select ARM_GIC_V3_ITS 160 161config IMGPDC_IRQ 162 bool 163 select GENERIC_IRQ_CHIP 164 select IRQ_DOMAIN 165 166config IXP4XX_IRQ 167 bool 168 select IRQ_DOMAIN 169 select SPARSE_IRQ 170 171config MADERA_IRQ 172 tristate 173 174config IRQ_MIPS_CPU 175 bool 176 select GENERIC_IRQ_CHIP 177 select GENERIC_IRQ_IPI if SMP && SYS_SUPPORTS_MULTITHREADING 178 select IRQ_DOMAIN 179 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 180 181config CLPS711X_IRQCHIP 182 bool 183 depends on ARCH_CLPS711X 184 select IRQ_DOMAIN 185 select SPARSE_IRQ 186 default y 187 188config OMPIC 189 bool 190 191config OR1K_PIC 192 bool 193 select IRQ_DOMAIN 194 195config OMAP_IRQCHIP 196 bool 197 select GENERIC_IRQ_CHIP 198 select IRQ_DOMAIN 199 200config ORION_IRQCHIP 201 bool 202 select IRQ_DOMAIN 203 204config PIC32_EVIC 205 bool 206 select GENERIC_IRQ_CHIP 207 select IRQ_DOMAIN 208 209config JCORE_AIC 210 bool "J-Core integrated AIC" if COMPILE_TEST 211 depends on OF 212 select IRQ_DOMAIN 213 help 214 Support for the J-Core integrated AIC. 215 216config RDA_INTC 217 bool 218 select IRQ_DOMAIN 219 220config RENESAS_INTC_IRQPIN 221 bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST 222 select IRQ_DOMAIN 223 help 224 Enable support for the Renesas Interrupt Controller for external 225 interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs. 226 227config RENESAS_IRQC 228 bool "Renesas R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} IRQC support" if COMPILE_TEST 229 select GENERIC_IRQ_CHIP 230 select IRQ_DOMAIN 231 help 232 Enable support for the Renesas Interrupt Controller for external 233 devices, as found on R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} SoCs. 234 235config RENESAS_RZA1_IRQC 236 bool "Renesas RZ/A1 IRQC support" if COMPILE_TEST 237 select IRQ_DOMAIN_HIERARCHY 238 help 239 Enable support for the Renesas RZ/A1 Interrupt Controller, to use up 240 to 8 external interrupts with configurable sense select. 241 242config RENESAS_RZG2L_IRQC 243 bool "Renesas RZ/G2L (and alike SoC) IRQC support" if COMPILE_TEST 244 select GENERIC_IRQ_CHIP 245 select IRQ_DOMAIN_HIERARCHY 246 help 247 Enable support for the Renesas RZ/G2L (and alike SoC) Interrupt Controller 248 for external devices. 249 250config SL28CPLD_INTC 251 bool "Kontron sl28cpld IRQ controller" 252 depends on MFD_SL28CPLD=y || COMPILE_TEST 253 select REGMAP_IRQ 254 help 255 Interrupt controller driver for the board management controller 256 found on the Kontron sl28 CPLD. 257 258config ST_IRQCHIP 259 bool 260 select REGMAP 261 select MFD_SYSCON 262 help 263 Enables SysCfg Controlled IRQs on STi based platforms. 264 265config SUN4I_INTC 266 bool 267 268config SUN6I_R_INTC 269 bool 270 select IRQ_DOMAIN_HIERARCHY 271 select IRQ_FASTEOI_HIERARCHY_HANDLERS 272 273config SUNXI_NMI_INTC 274 bool 275 select GENERIC_IRQ_CHIP 276 277config TB10X_IRQC 278 bool 279 select IRQ_DOMAIN 280 select GENERIC_IRQ_CHIP 281 282config TS4800_IRQ 283 tristate "TS-4800 IRQ controller" 284 select IRQ_DOMAIN 285 depends on HAS_IOMEM 286 depends on SOC_IMX51 || COMPILE_TEST 287 help 288 Support for the TS-4800 FPGA IRQ controller 289 290config VERSATILE_FPGA_IRQ 291 bool 292 select IRQ_DOMAIN 293 294config VERSATILE_FPGA_IRQ_NR 295 int 296 default 4 297 depends on VERSATILE_FPGA_IRQ 298 299config XTENSA_MX 300 bool 301 select IRQ_DOMAIN 302 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 303 304config XILINX_INTC 305 bool "Xilinx Interrupt Controller IP" 306 depends on OF_ADDRESS 307 select IRQ_DOMAIN 308 help 309 Support for the Xilinx Interrupt Controller IP core. 310 This is used as a primary controller with MicroBlaze and can also 311 be used as a secondary chained controller on other platforms. 312 313config IRQ_CROSSBAR 314 bool 315 help 316 Support for a CROSSBAR ip that precedes the main interrupt controller. 317 The primary irqchip invokes the crossbar's callback which inturn allocates 318 a free irq and configures the IP. Thus the peripheral interrupts are 319 routed to one of the free irqchip interrupt lines. 320 321config KEYSTONE_IRQ 322 tristate "Keystone 2 IRQ controller IP" 323 depends on ARCH_KEYSTONE 324 help 325 Support for Texas Instruments Keystone 2 IRQ controller IP which 326 is part of the Keystone 2 IPC mechanism 327 328config MIPS_GIC 329 bool 330 select GENERIC_IRQ_IPI if SMP 331 select IRQ_DOMAIN_HIERARCHY 332 select MIPS_CM 333 334config INGENIC_IRQ 335 bool 336 depends on MACH_INGENIC 337 default y 338 339config INGENIC_TCU_IRQ 340 bool "Ingenic JZ47xx TCU interrupt controller" 341 default MACH_INGENIC 342 depends on MIPS || COMPILE_TEST 343 select MFD_SYSCON 344 select GENERIC_IRQ_CHIP 345 help 346 Support for interrupts in the Timer/Counter Unit (TCU) of the Ingenic 347 JZ47xx SoCs. 348 349 If unsure, say N. 350 351config IMX_GPCV2 352 bool 353 select IRQ_DOMAIN 354 help 355 Enables the wakeup IRQs for IMX platforms with GPCv2 block 356 357config IRQ_MXS 358 def_bool y if MACH_ASM9260 || ARCH_MXS 359 select IRQ_DOMAIN 360 select STMP_DEVICE 361 362config MSCC_OCELOT_IRQ 363 bool 364 select IRQ_DOMAIN 365 select GENERIC_IRQ_CHIP 366 367config MVEBU_GICP 368 bool 369 370config MVEBU_ICU 371 bool 372 373config MVEBU_ODMI 374 bool 375 select GENERIC_MSI_IRQ 376 377config MVEBU_PIC 378 bool 379 380config MVEBU_SEI 381 bool 382 383config LS_EXTIRQ 384 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 385 select MFD_SYSCON 386 387config LS_SCFG_MSI 388 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 389 depends on PCI_MSI 390 391config PARTITION_PERCPU 392 bool 393 394config STM32_EXTI 395 bool 396 select IRQ_DOMAIN 397 select GENERIC_IRQ_CHIP 398 399config QCOM_IRQ_COMBINER 400 bool "QCOM IRQ combiner support" 401 depends on ARCH_QCOM && ACPI 402 select IRQ_DOMAIN_HIERARCHY 403 help 404 Say yes here to add support for the IRQ combiner devices embedded 405 in Qualcomm Technologies chips. 406 407config IRQ_UNIPHIER_AIDET 408 bool "UniPhier AIDET support" if COMPILE_TEST 409 depends on ARCH_UNIPHIER || COMPILE_TEST 410 default ARCH_UNIPHIER 411 select IRQ_DOMAIN_HIERARCHY 412 help 413 Support for the UniPhier AIDET (ARM Interrupt Detector). 414 415config MESON_IRQ_GPIO 416 tristate "Meson GPIO Interrupt Multiplexer" 417 depends on ARCH_MESON || COMPILE_TEST 418 default ARCH_MESON 419 select IRQ_DOMAIN_HIERARCHY 420 help 421 Support Meson SoC Family GPIO Interrupt Multiplexer 422 423config GOLDFISH_PIC 424 bool "Goldfish programmable interrupt controller" 425 depends on MIPS && (GOLDFISH || COMPILE_TEST) 426 select GENERIC_IRQ_CHIP 427 select IRQ_DOMAIN 428 help 429 Say yes here to enable Goldfish interrupt controller driver used 430 for Goldfish based virtual platforms. 431 432config QCOM_PDC 433 tristate "QCOM PDC" 434 depends on ARCH_QCOM 435 select IRQ_DOMAIN_HIERARCHY 436 help 437 Power Domain Controller driver to manage and configure wakeup 438 IRQs for Qualcomm Technologies Inc (QTI) mobile chips. 439 440config QCOM_MPM 441 tristate "QCOM MPM" 442 depends on ARCH_QCOM 443 depends on MAILBOX 444 select IRQ_DOMAIN_HIERARCHY 445 help 446 MSM Power Manager driver to manage and configure wakeup 447 IRQs for Qualcomm Technologies Inc (QTI) mobile chips. 448 449config CSKY_MPINTC 450 bool 451 depends on CSKY 452 help 453 Say yes here to enable C-SKY SMP interrupt controller driver used 454 for C-SKY SMP system. 455 In fact it's not mmio map in hardware and it uses ld/st to visit the 456 controller's register inside CPU. 457 458config CSKY_APB_INTC 459 bool "C-SKY APB Interrupt Controller" 460 depends on CSKY 461 help 462 Say yes here to enable C-SKY APB interrupt controller driver used 463 by C-SKY single core SOC system. It uses mmio map apb-bus to visit 464 the controller's register. 465 466config IMX_IRQSTEER 467 bool "i.MX IRQSTEER support" 468 depends on ARCH_MXC || COMPILE_TEST 469 default ARCH_MXC 470 select IRQ_DOMAIN 471 help 472 Support for the i.MX IRQSTEER interrupt multiplexer/remapper. 473 474config IMX_INTMUX 475 bool "i.MX INTMUX support" if COMPILE_TEST 476 default y if ARCH_MXC 477 select IRQ_DOMAIN 478 help 479 Support for the i.MX INTMUX interrupt multiplexer. 480 481config IMX_MU_MSI 482 tristate "i.MX MU used as MSI controller" 483 depends on OF && HAS_IOMEM 484 depends on ARCH_MXC || COMPILE_TEST 485 default m if ARCH_MXC 486 select IRQ_DOMAIN 487 select IRQ_DOMAIN_HIERARCHY 488 select GENERIC_MSI_IRQ 489 help 490 Provide a driver for the i.MX Messaging Unit block used as a 491 CPU-to-CPU MSI controller. This requires a specially crafted DT 492 to make use of this driver. 493 494 If unsure, say N 495 496config LS1X_IRQ 497 bool "Loongson-1 Interrupt Controller" 498 depends on MACH_LOONGSON32 499 default y 500 select IRQ_DOMAIN 501 select GENERIC_IRQ_CHIP 502 help 503 Support for the Loongson-1 platform Interrupt Controller. 504 505config TI_SCI_INTR_IRQCHIP 506 bool 507 depends on TI_SCI_PROTOCOL 508 select IRQ_DOMAIN_HIERARCHY 509 help 510 This enables the irqchip driver support for K3 Interrupt router 511 over TI System Control Interface available on some new TI's SoCs. 512 If you wish to use interrupt router irq resources managed by the 513 TI System Controller, say Y here. Otherwise, say N. 514 515config TI_SCI_INTA_IRQCHIP 516 bool 517 depends on TI_SCI_PROTOCOL 518 select IRQ_DOMAIN_HIERARCHY 519 select TI_SCI_INTA_MSI_DOMAIN 520 help 521 This enables the irqchip driver support for K3 Interrupt aggregator 522 over TI System Control Interface available on some new TI's SoCs. 523 If you wish to use interrupt aggregator irq resources managed by the 524 TI System Controller, say Y here. Otherwise, say N. 525 526config TI_PRUSS_INTC 527 tristate 528 depends on TI_PRUSS 529 default TI_PRUSS 530 select IRQ_DOMAIN 531 help 532 This enables support for the PRU-ICSS Local Interrupt Controller 533 present within a PRU-ICSS subsystem present on various TI SoCs. 534 The PRUSS INTC enables various interrupts to be routed to multiple 535 different processors within the SoC. 536 537config RISCV_INTC 538 bool 539 depends on RISCV 540 select IRQ_DOMAIN_HIERARCHY 541 542config SIFIVE_PLIC 543 bool 544 depends on RISCV 545 select IRQ_DOMAIN_HIERARCHY 546 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 547 548config EXYNOS_IRQ_COMBINER 549 bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST 550 depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST 551 help 552 Say yes here to add support for the IRQ combiner devices embedded 553 in Samsung Exynos chips. 554 555config IRQ_LOONGARCH_CPU 556 bool 557 select GENERIC_IRQ_CHIP 558 select IRQ_DOMAIN 559 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 560 select LOONGSON_HTVEC 561 select LOONGSON_LIOINTC 562 select LOONGSON_EIOINTC 563 select LOONGSON_PCH_PIC 564 select LOONGSON_PCH_MSI 565 select LOONGSON_PCH_LPC 566 help 567 Support for the LoongArch CPU Interrupt Controller. For details of 568 irq chip hierarchy on LoongArch platforms please read the document 569 Documentation/loongarch/irq-chip-model.rst. 570 571config LOONGSON_LIOINTC 572 bool "Loongson Local I/O Interrupt Controller" 573 depends on MACH_LOONGSON64 574 default y 575 select IRQ_DOMAIN 576 select GENERIC_IRQ_CHIP 577 help 578 Support for the Loongson Local I/O Interrupt Controller. 579 580config LOONGSON_EIOINTC 581 bool "Loongson Extend I/O Interrupt Controller" 582 depends on LOONGARCH 583 depends on MACH_LOONGSON64 584 default MACH_LOONGSON64 585 select IRQ_DOMAIN_HIERARCHY 586 select GENERIC_IRQ_CHIP 587 help 588 Support for the Loongson3 Extend I/O Interrupt Vector Controller. 589 590config LOONGSON_HTPIC 591 bool "Loongson3 HyperTransport PIC Controller" 592 depends on MACH_LOONGSON64 && MIPS 593 default y 594 select IRQ_DOMAIN 595 select GENERIC_IRQ_CHIP 596 help 597 Support for the Loongson-3 HyperTransport PIC Controller. 598 599config LOONGSON_HTVEC 600 bool "Loongson HyperTransport Interrupt Vector Controller" 601 depends on MACH_LOONGSON64 602 default MACH_LOONGSON64 603 select IRQ_DOMAIN_HIERARCHY 604 help 605 Support for the Loongson HyperTransport Interrupt Vector Controller. 606 607config LOONGSON_PCH_PIC 608 bool "Loongson PCH PIC Controller" 609 depends on MACH_LOONGSON64 610 default MACH_LOONGSON64 611 select IRQ_DOMAIN_HIERARCHY 612 select IRQ_FASTEOI_HIERARCHY_HANDLERS 613 help 614 Support for the Loongson PCH PIC Controller. 615 616config LOONGSON_PCH_MSI 617 bool "Loongson PCH MSI Controller" 618 depends on MACH_LOONGSON64 619 depends on PCI 620 default MACH_LOONGSON64 621 select IRQ_DOMAIN_HIERARCHY 622 select PCI_MSI 623 help 624 Support for the Loongson PCH MSI Controller. 625 626config LOONGSON_PCH_LPC 627 bool "Loongson PCH LPC Controller" 628 depends on LOONGARCH 629 depends on MACH_LOONGSON64 630 default MACH_LOONGSON64 631 select IRQ_DOMAIN_HIERARCHY 632 help 633 Support for the Loongson PCH LPC Controller. 634 635config MST_IRQ 636 bool "MStar Interrupt Controller" 637 depends on ARCH_MEDIATEK || ARCH_MSTARV7 || COMPILE_TEST 638 default ARCH_MEDIATEK 639 select IRQ_DOMAIN 640 select IRQ_DOMAIN_HIERARCHY 641 help 642 Support MStar Interrupt Controller. 643 644config WPCM450_AIC 645 bool "Nuvoton WPCM450 Advanced Interrupt Controller" 646 depends on ARCH_WPCM450 647 help 648 Support for the interrupt controller in the Nuvoton WPCM450 BMC SoC. 649 650config IRQ_IDT3243X 651 bool 652 select GENERIC_IRQ_CHIP 653 select IRQ_DOMAIN 654 655config APPLE_AIC 656 bool "Apple Interrupt Controller (AIC)" 657 depends on ARM64 658 depends on ARCH_APPLE || COMPILE_TEST 659 select GENERIC_IRQ_IPI_MUX 660 help 661 Support for the Apple Interrupt Controller found on Apple Silicon SoCs, 662 such as the M1. 663 664config MCHP_EIC 665 bool "Microchip External Interrupt Controller" 666 depends on ARCH_AT91 || COMPILE_TEST 667 select IRQ_DOMAIN 668 select IRQ_DOMAIN_HIERARCHY 669 help 670 Support for Microchip External Interrupt Controller. 671 672config SUNPLUS_SP7021_INTC 673 bool "Sunplus SP7021 interrupt controller" if COMPILE_TEST 674 default SOC_SP7021 675 help 676 Support for the Sunplus SP7021 Interrupt Controller IP core. 677 SP7021 SoC has 2 Chips: C-Chip & P-Chip. This is used as a 678 chained controller, routing all interrupt source in P-Chip to 679 the primary controller on C-Chip. 680 681endmenu 682