1c94fb639SRandy Dunlapmenu "IRQ chip support" 2c94fb639SRandy Dunlap 3f6e916b8SThomas Petazzoniconfig IRQCHIP 4f6e916b8SThomas Petazzoni def_bool y 5f6e916b8SThomas Petazzoni depends on OF_IRQ 6f6e916b8SThomas Petazzoni 781243e44SRob Herringconfig ARM_GIC 881243e44SRob Herring bool 981243e44SRob Herring select IRQ_DOMAIN 109a1091efSYingjoe Chen select IRQ_DOMAIN_HIERARCHY 114f7799d9SPalmer Dabbelt select GENERIC_IRQ_MULTI_HANDLER 120c9e4982SMarc Zyngier select GENERIC_IRQ_EFFECTIVE_AFF_MASK 1381243e44SRob Herring 149c8edddfSJon Hunterconfig ARM_GIC_PM 159c8edddfSJon Hunter bool 169c8edddfSJon Hunter depends on PM 179c8edddfSJon Hunter select ARM_GIC 189c8edddfSJon Hunter select PM_CLK 199c8edddfSJon Hunter 20a27d21e0SLinus Walleijconfig ARM_GIC_MAX_NR 21a27d21e0SLinus Walleij int 22a27d21e0SLinus Walleij default 2 if ARCH_REALVIEW 23a27d21e0SLinus Walleij default 1 24a27d21e0SLinus Walleij 25853a33ceSSuravee Suthikulpanitconfig ARM_GIC_V2M 26853a33ceSSuravee Suthikulpanit bool 273ee80364SArnd Bergmann depends on PCI 283ee80364SArnd Bergmann select ARM_GIC 293ee80364SArnd Bergmann select PCI_MSI 30853a33ceSSuravee Suthikulpanit 3181243e44SRob Herringconfig GIC_NON_BANKED 3281243e44SRob Herring bool 3381243e44SRob Herring 34021f6537SMarc Zyngierconfig ARM_GIC_V3 35021f6537SMarc Zyngier bool 36021f6537SMarc Zyngier select IRQ_DOMAIN 374f7799d9SPalmer Dabbelt select GENERIC_IRQ_MULTI_HANDLER 38443acc4fSMarc Zyngier select IRQ_DOMAIN_HIERARCHY 39e3825ba1SMarc Zyngier select PARTITION_PERCPU 40956ae91aSMarc Zyngier select GENERIC_IRQ_EFFECTIVE_AFF_MASK 41021f6537SMarc Zyngier 4219812729SMarc Zyngierconfig ARM_GIC_V3_ITS 4319812729SMarc Zyngier bool 4429f41139SMarc Zyngier select GENERIC_MSI_IRQ_DOMAIN 4529f41139SMarc Zyngier default ARM_GIC_V3 4629f41139SMarc Zyngier 4729f41139SMarc Zyngierconfig ARM_GIC_V3_ITS_PCI 4829f41139SMarc Zyngier bool 4929f41139SMarc Zyngier depends on ARM_GIC_V3_ITS 503ee80364SArnd Bergmann depends on PCI 513ee80364SArnd Bergmann depends on PCI_MSI 5229f41139SMarc Zyngier default ARM_GIC_V3_ITS 53292ec080SUwe Kleine-König 547afe031cSBogdan Purcareataconfig ARM_GIC_V3_ITS_FSL_MC 557afe031cSBogdan Purcareata bool 567afe031cSBogdan Purcareata depends on ARM_GIC_V3_ITS 577afe031cSBogdan Purcareata depends on FSL_MC_BUS 587afe031cSBogdan Purcareata default ARM_GIC_V3_ITS 597afe031cSBogdan Purcareata 6044430ec0SRob Herringconfig ARM_NVIC 6144430ec0SRob Herring bool 6244430ec0SRob Herring select IRQ_DOMAIN 632d9f59f7SStefan Agner select IRQ_DOMAIN_HIERARCHY 6444430ec0SRob Herring select GENERIC_IRQ_CHIP 6544430ec0SRob Herring 6644430ec0SRob Herringconfig ARM_VIC 6744430ec0SRob Herring bool 6844430ec0SRob Herring select IRQ_DOMAIN 694f7799d9SPalmer Dabbelt select GENERIC_IRQ_MULTI_HANDLER 7044430ec0SRob Herring 7144430ec0SRob Herringconfig ARM_VIC_NR 7244430ec0SRob Herring int 7344430ec0SRob Herring default 4 if ARCH_S5PV210 7444430ec0SRob Herring default 2 7544430ec0SRob Herring depends on ARM_VIC 7644430ec0SRob Herring help 7744430ec0SRob Herring The maximum number of VICs available in the system, for 7844430ec0SRob Herring power management. 7944430ec0SRob Herring 80fed6d336SThomas Petazzoniconfig ARMADA_370_XP_IRQ 81fed6d336SThomas Petazzoni bool 82fed6d336SThomas Petazzoni select GENERIC_IRQ_CHIP 833ee80364SArnd Bergmann select PCI_MSI if PCI 84e31793a3SMarc Zyngier select GENERIC_IRQ_EFFECTIVE_AFF_MASK 85fed6d336SThomas Petazzoni 86e6b78f2cSAntoine Tenartconfig ALPINE_MSI 87e6b78f2cSAntoine Tenart bool 883ee80364SArnd Bergmann depends on PCI 893ee80364SArnd Bergmann select PCI_MSI 90e6b78f2cSAntoine Tenart select GENERIC_IRQ_CHIP 91e6b78f2cSAntoine Tenart 92b1479ebbSBoris BREZILLONconfig ATMEL_AIC_IRQ 93b1479ebbSBoris BREZILLON bool 94b1479ebbSBoris BREZILLON select GENERIC_IRQ_CHIP 95b1479ebbSBoris BREZILLON select IRQ_DOMAIN 964f7799d9SPalmer Dabbelt select GENERIC_IRQ_MULTI_HANDLER 97b1479ebbSBoris BREZILLON select SPARSE_IRQ 98b1479ebbSBoris BREZILLON 99b1479ebbSBoris BREZILLONconfig ATMEL_AIC5_IRQ 100b1479ebbSBoris BREZILLON bool 101b1479ebbSBoris BREZILLON select GENERIC_IRQ_CHIP 102b1479ebbSBoris BREZILLON select IRQ_DOMAIN 1034f7799d9SPalmer Dabbelt select GENERIC_IRQ_MULTI_HANDLER 104b1479ebbSBoris BREZILLON select SPARSE_IRQ 105b1479ebbSBoris BREZILLON 1060509cfdeSRalf Baechleconfig I8259 1070509cfdeSRalf Baechle bool 1080509cfdeSRalf Baechle select IRQ_DOMAIN 1090509cfdeSRalf Baechle 110c7c42ec2SSimon Arlottconfig BCM6345_L1_IRQ 111c7c42ec2SSimon Arlott bool 112c7c42ec2SSimon Arlott select GENERIC_IRQ_CHIP 113c7c42ec2SSimon Arlott select IRQ_DOMAIN 114d0ed5e8eSMarc Zyngier select GENERIC_IRQ_EFFECTIVE_AFF_MASK 115c7c42ec2SSimon Arlott 1165f7f0317SKevin Cernekeeconfig BCM7038_L1_IRQ 1175f7f0317SKevin Cernekee bool 1185f7f0317SKevin Cernekee select GENERIC_IRQ_CHIP 1195f7f0317SKevin Cernekee select IRQ_DOMAIN 120b8d9884aSMarc Zyngier select GENERIC_IRQ_EFFECTIVE_AFF_MASK 1215f7f0317SKevin Cernekee 122a4fcbb86SKevin Cernekeeconfig BCM7120_L2_IRQ 123a4fcbb86SKevin Cernekee bool 124a4fcbb86SKevin Cernekee select GENERIC_IRQ_CHIP 125a4fcbb86SKevin Cernekee select IRQ_DOMAIN 126a4fcbb86SKevin Cernekee 1277f646e92SFlorian Fainelliconfig BRCMSTB_L2_IRQ 1287f646e92SFlorian Fainelli bool 1297f646e92SFlorian Fainelli select GENERIC_IRQ_CHIP 1307f646e92SFlorian Fainelli select IRQ_DOMAIN 1317f646e92SFlorian Fainelli 132350d71b9SSebastian Hesselbarthconfig DW_APB_ICTL 133350d71b9SSebastian Hesselbarth bool 134e1588490SJisheng Zhang select GENERIC_IRQ_CHIP 135350d71b9SSebastian Hesselbarth select IRQ_DOMAIN 136350d71b9SSebastian Hesselbarth 1376ee532e2SLinus Walleijconfig FARADAY_FTINTC010 1386ee532e2SLinus Walleij bool 1396ee532e2SLinus Walleij select IRQ_DOMAIN 1404f7799d9SPalmer Dabbelt select GENERIC_IRQ_MULTI_HANDLER 1416ee532e2SLinus Walleij select SPARSE_IRQ 1426ee532e2SLinus Walleij 1439a7c4abdSMaJunconfig HISILICON_IRQ_MBIGEN 1449a7c4abdSMaJun bool 1459a7c4abdSMaJun select ARM_GIC_V3 1469a7c4abdSMaJun select ARM_GIC_V3_ITS 1479a7c4abdSMaJun 148b6ef9161SJames Hoganconfig IMGPDC_IRQ 149b6ef9161SJames Hogan bool 150b6ef9161SJames Hogan select GENERIC_IRQ_CHIP 151b6ef9161SJames Hogan select IRQ_DOMAIN 152b6ef9161SJames Hogan 153da0abe1aSRichard Fitzgeraldconfig MADERA_IRQ 154da0abe1aSRichard Fitzgerald tristate 155da0abe1aSRichard Fitzgerald 15667e38cf2SRalf Baechleconfig IRQ_MIPS_CPU 15767e38cf2SRalf Baechle bool 15867e38cf2SRalf Baechle select GENERIC_IRQ_CHIP 1593838a547SPaul Burton select GENERIC_IRQ_IPI if SYS_SUPPORTS_MULTITHREADING 16067e38cf2SRalf Baechle select IRQ_DOMAIN 1613838a547SPaul Burton select IRQ_DOMAIN_HIERARCHY if GENERIC_IRQ_IPI 16218416e45SMarc Zyngier select GENERIC_IRQ_EFFECTIVE_AFF_MASK 16367e38cf2SRalf Baechle 164afc98d90SAlexander Shiyanconfig CLPS711X_IRQCHIP 165afc98d90SAlexander Shiyan bool 166afc98d90SAlexander Shiyan depends on ARCH_CLPS711X 167afc98d90SAlexander Shiyan select IRQ_DOMAIN 1684f7799d9SPalmer Dabbelt select GENERIC_IRQ_MULTI_HANDLER 169afc98d90SAlexander Shiyan select SPARSE_IRQ 170afc98d90SAlexander Shiyan default y 171afc98d90SAlexander Shiyan 1729b54470aSStafford Horneconfig OMPIC 1739b54470aSStafford Horne bool 1749b54470aSStafford Horne 1754db8e6d2SStefan Kristianssonconfig OR1K_PIC 1764db8e6d2SStefan Kristiansson bool 1774db8e6d2SStefan Kristiansson select IRQ_DOMAIN 1784db8e6d2SStefan Kristiansson 1798598066cSFelipe Balbiconfig OMAP_IRQCHIP 1808598066cSFelipe Balbi bool 1818598066cSFelipe Balbi select GENERIC_IRQ_CHIP 1828598066cSFelipe Balbi select IRQ_DOMAIN 1838598066cSFelipe Balbi 1849dbd90f1SSebastian Hesselbarthconfig ORION_IRQCHIP 1859dbd90f1SSebastian Hesselbarth bool 1869dbd90f1SSebastian Hesselbarth select IRQ_DOMAIN 1874f7799d9SPalmer Dabbelt select GENERIC_IRQ_MULTI_HANDLER 1889dbd90f1SSebastian Hesselbarth 189aaa8666aSCristian Birsanconfig PIC32_EVIC 190aaa8666aSCristian Birsan bool 191aaa8666aSCristian Birsan select GENERIC_IRQ_CHIP 192aaa8666aSCristian Birsan select IRQ_DOMAIN 193aaa8666aSCristian Birsan 194981b58f6SRich Felkerconfig JCORE_AIC 1953602ffdeSRich Felker bool "J-Core integrated AIC" if COMPILE_TEST 1963602ffdeSRich Felker depends on OF 197981b58f6SRich Felker select IRQ_DOMAIN 198981b58f6SRich Felker help 199981b58f6SRich Felker Support for the J-Core integrated AIC. 200981b58f6SRich Felker 201d852e62aSManivannan Sadhasivamconfig RDA_INTC 202d852e62aSManivannan Sadhasivam bool 203d852e62aSManivannan Sadhasivam select IRQ_DOMAIN 204d852e62aSManivannan Sadhasivam 20544358048SMagnus Dammconfig RENESAS_INTC_IRQPIN 20644358048SMagnus Damm bool 20744358048SMagnus Damm select IRQ_DOMAIN 20844358048SMagnus Damm 209fbc83b7fSMagnus Dammconfig RENESAS_IRQC 210fbc83b7fSMagnus Damm bool 21199c221dfSMagnus Damm select GENERIC_IRQ_CHIP 212fbc83b7fSMagnus Damm select IRQ_DOMAIN 213fbc83b7fSMagnus Damm 21407088484SLee Jonesconfig ST_IRQCHIP 21507088484SLee Jones bool 21607088484SLee Jones select REGMAP 21707088484SLee Jones select MFD_SYSCON 21807088484SLee Jones help 21907088484SLee Jones Enables SysCfg Controlled IRQs on STi based platforms. 22007088484SLee Jones 2214bba6689SMans Rullgardconfig TANGO_IRQ 2224bba6689SMans Rullgard bool 2234bba6689SMans Rullgard select IRQ_DOMAIN 2244bba6689SMans Rullgard select GENERIC_IRQ_CHIP 2254bba6689SMans Rullgard 226b06eb017SChristian Ruppertconfig TB10X_IRQC 227b06eb017SChristian Ruppert bool 228b06eb017SChristian Ruppert select IRQ_DOMAIN 229b06eb017SChristian Ruppert select GENERIC_IRQ_CHIP 230b06eb017SChristian Ruppert 231d01f8633SDamien Riegelconfig TS4800_IRQ 232d01f8633SDamien Riegel tristate "TS-4800 IRQ controller" 233d01f8633SDamien Riegel select IRQ_DOMAIN 2340df337cfSRichard Weinberger depends on HAS_IOMEM 235d2b383dcSJean Delvare depends on SOC_IMX51 || COMPILE_TEST 236d01f8633SDamien Riegel help 237d01f8633SDamien Riegel Support for the TS-4800 FPGA IRQ controller 238d01f8633SDamien Riegel 2392389d501SLinus Walleijconfig VERSATILE_FPGA_IRQ 2402389d501SLinus Walleij bool 2412389d501SLinus Walleij select IRQ_DOMAIN 2422389d501SLinus Walleij 2432389d501SLinus Walleijconfig VERSATILE_FPGA_IRQ_NR 2442389d501SLinus Walleij int 2452389d501SLinus Walleij default 4 2462389d501SLinus Walleij depends on VERSATILE_FPGA_IRQ 24726a8e96aSMax Filippov 24826a8e96aSMax Filippovconfig XTENSA_MX 24926a8e96aSMax Filippov bool 25026a8e96aSMax Filippov select IRQ_DOMAIN 25150091212SMarc Zyngier select GENERIC_IRQ_EFFECTIVE_AFF_MASK 25296ca848eSSricharan R 2530547dc78SZubair Lutfullah Kakakhelconfig XILINX_INTC 2540547dc78SZubair Lutfullah Kakakhel bool 2550547dc78SZubair Lutfullah Kakakhel select IRQ_DOMAIN 2560547dc78SZubair Lutfullah Kakakhel 25796ca848eSSricharan Rconfig IRQ_CROSSBAR 25896ca848eSSricharan R bool 25996ca848eSSricharan R help 260f54619f2SMasanari Iida Support for a CROSSBAR ip that precedes the main interrupt controller. 26196ca848eSSricharan R The primary irqchip invokes the crossbar's callback which inturn allocates 26296ca848eSSricharan R a free irq and configures the IP. Thus the peripheral interrupts are 26396ca848eSSricharan R routed to one of the free irqchip interrupt lines. 26489323f8cSGrygorii Strashko 26589323f8cSGrygorii Strashkoconfig KEYSTONE_IRQ 26689323f8cSGrygorii Strashko tristate "Keystone 2 IRQ controller IP" 26789323f8cSGrygorii Strashko depends on ARCH_KEYSTONE 26889323f8cSGrygorii Strashko help 26989323f8cSGrygorii Strashko Support for Texas Instruments Keystone 2 IRQ controller IP which 27089323f8cSGrygorii Strashko is part of the Keystone 2 IPC mechanism 2718a19b8f1SAndrew Bresticker 2728a19b8f1SAndrew Brestickerconfig MIPS_GIC 2738a19b8f1SAndrew Bresticker bool 274bb11cff3SQais Yousef select GENERIC_IRQ_IPI 2752af70a96SQais Yousef select IRQ_DOMAIN_HIERARCHY 2768a19b8f1SAndrew Bresticker select MIPS_CM 2778a764482SYoshinori Sato 27844e08e70SPaul Burtonconfig INGENIC_IRQ 27944e08e70SPaul Burton bool 28044e08e70SPaul Burton depends on MACH_INGENIC 28144e08e70SPaul Burton default y 28278c10e55SLinus Torvalds 2838a764482SYoshinori Satoconfig RENESAS_H8300H_INTC 2848a764482SYoshinori Sato bool 2858a764482SYoshinori Sato select IRQ_DOMAIN 2868a764482SYoshinori Sato 2878a764482SYoshinori Satoconfig RENESAS_H8S_INTC 2888a764482SYoshinori Sato bool 2898a764482SYoshinori Sato select IRQ_DOMAIN 290e324c4dcSShenwei Wang 291e324c4dcSShenwei Wangconfig IMX_GPCV2 292e324c4dcSShenwei Wang bool 293e324c4dcSShenwei Wang select IRQ_DOMAIN 294e324c4dcSShenwei Wang help 295e324c4dcSShenwei Wang Enables the wakeup IRQs for IMX platforms with GPCv2 block 2967e4ac676SOleksij Rempel 2977e4ac676SOleksij Rempelconfig IRQ_MXS 2987e4ac676SOleksij Rempel def_bool y if MACH_ASM9260 || ARCH_MXS 2997e4ac676SOleksij Rempel select IRQ_DOMAIN 3007e4ac676SOleksij Rempel select STMP_DEVICE 301c27f29bbSThomas Petazzoni 30219d99164SAlexandre Belloniconfig MSCC_OCELOT_IRQ 30319d99164SAlexandre Belloni bool 30419d99164SAlexandre Belloni select IRQ_DOMAIN 30519d99164SAlexandre Belloni select GENERIC_IRQ_CHIP 30619d99164SAlexandre Belloni 307a68a63cbSThomas Petazzoniconfig MVEBU_GICP 308a68a63cbSThomas Petazzoni bool 309a68a63cbSThomas Petazzoni 310e0de91a9SThomas Petazzoniconfig MVEBU_ICU 311e0de91a9SThomas Petazzoni bool 312e0de91a9SThomas Petazzoni 313c27f29bbSThomas Petazzoniconfig MVEBU_ODMI 314c27f29bbSThomas Petazzoni bool 315fa23b9d1SArnd Bergmann select GENERIC_MSI_IRQ_DOMAIN 3169e2c986cSMarc Zyngier 317a109893bSThomas Petazzoniconfig MVEBU_PIC 318a109893bSThomas Petazzoni bool 319a109893bSThomas Petazzoni 32061ce8d8dSMiquel Raynalconfig MVEBU_SEI 32161ce8d8dSMiquel Raynal bool 32261ce8d8dSMiquel Raynal 323b8f3ebe6SMinghuan Lianconfig LS_SCFG_MSI 324b8f3ebe6SMinghuan Lian def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 325b8f3ebe6SMinghuan Lian depends on PCI && PCI_MSI 326b8f3ebe6SMinghuan Lian 3279e2c986cSMarc Zyngierconfig PARTITION_PERCPU 3289e2c986cSMarc Zyngier bool 3290efacbbaSLinus Torvalds 33044df427cSNoam Camusconfig EZNPS_GIC 33144df427cSNoam Camus bool "NPS400 Global Interrupt Manager (GIM)" 332ffd565e3SArnd Bergmann depends on ARC || (COMPILE_TEST && !64BIT) 33344df427cSNoam Camus select IRQ_DOMAIN 33444df427cSNoam Camus help 33544df427cSNoam Camus Support the EZchip NPS400 global interrupt controller 336e0720416SAlexandre TORGUE 337e0720416SAlexandre TORGUEconfig STM32_EXTI 338e0720416SAlexandre TORGUE bool 339e0720416SAlexandre TORGUE select IRQ_DOMAIN 3400e7d7807SLudovic Barre select GENERIC_IRQ_CHIP 341f20cc9b0SAgustin Vega-Frias 342f20cc9b0SAgustin Vega-Friasconfig QCOM_IRQ_COMBINER 343f20cc9b0SAgustin Vega-Frias bool "QCOM IRQ combiner support" 344f20cc9b0SAgustin Vega-Frias depends on ARCH_QCOM && ACPI 345f20cc9b0SAgustin Vega-Frias select IRQ_DOMAIN 346f20cc9b0SAgustin Vega-Frias select IRQ_DOMAIN_HIERARCHY 347f20cc9b0SAgustin Vega-Frias help 348f20cc9b0SAgustin Vega-Frias Say yes here to add support for the IRQ combiner devices embedded 349f20cc9b0SAgustin Vega-Frias in Qualcomm Technologies chips. 3505ed34d3aSMasahiro Yamada 3515ed34d3aSMasahiro Yamadaconfig IRQ_UNIPHIER_AIDET 3525ed34d3aSMasahiro Yamada bool "UniPhier AIDET support" if COMPILE_TEST 3535ed34d3aSMasahiro Yamada depends on ARCH_UNIPHIER || COMPILE_TEST 3545ed34d3aSMasahiro Yamada default ARCH_UNIPHIER 3555ed34d3aSMasahiro Yamada select IRQ_DOMAIN_HIERARCHY 3565ed34d3aSMasahiro Yamada help 3575ed34d3aSMasahiro Yamada Support for the UniPhier AIDET (ARM Interrupt Detector). 358c94fb639SRandy Dunlap 359215f4cc0SJerome Brunetconfig MESON_IRQ_GPIO 360215f4cc0SJerome Brunet bool "Meson GPIO Interrupt Multiplexer" 361d9ee91c1SThomas Gleixner depends on ARCH_MESON 362215f4cc0SJerome Brunet select IRQ_DOMAIN 363215f4cc0SJerome Brunet select IRQ_DOMAIN_HIERARCHY 364215f4cc0SJerome Brunet help 365215f4cc0SJerome Brunet Support Meson SoC Family GPIO Interrupt Multiplexer 366215f4cc0SJerome Brunet 3674235ff50SMiodrag Dinicconfig GOLDFISH_PIC 3684235ff50SMiodrag Dinic bool "Goldfish programmable interrupt controller" 3694235ff50SMiodrag Dinic depends on MIPS && (GOLDFISH || COMPILE_TEST) 3704235ff50SMiodrag Dinic select IRQ_DOMAIN 3714235ff50SMiodrag Dinic help 3724235ff50SMiodrag Dinic Say yes here to enable Goldfish interrupt controller driver used 3734235ff50SMiodrag Dinic for Goldfish based virtual platforms. 3744235ff50SMiodrag Dinic 375f55c73aeSArchana Sathyakumarconfig QCOM_PDC 376f55c73aeSArchana Sathyakumar bool "QCOM PDC" 377f55c73aeSArchana Sathyakumar depends on ARCH_QCOM 378f55c73aeSArchana Sathyakumar select IRQ_DOMAIN 379f55c73aeSArchana Sathyakumar select IRQ_DOMAIN_HIERARCHY 380f55c73aeSArchana Sathyakumar help 381f55c73aeSArchana Sathyakumar Power Domain Controller driver to manage and configure wakeup 382f55c73aeSArchana Sathyakumar IRQs for Qualcomm Technologies Inc (QTI) mobile chips. 383f55c73aeSArchana Sathyakumar 384d8a5f5f7SGuo Renconfig CSKY_MPINTC 385d8a5f5f7SGuo Ren bool "C-SKY Multi Processor Interrupt Controller" 386d8a5f5f7SGuo Ren depends on CSKY 387d8a5f5f7SGuo Ren help 388d8a5f5f7SGuo Ren Say yes here to enable C-SKY SMP interrupt controller driver used 389d8a5f5f7SGuo Ren for C-SKY SMP system. 390d8a5f5f7SGuo Ren In fact it's not mmio map in hw and it use ld/st to visit the 391d8a5f5f7SGuo Ren controller's register inside CPU. 392d8a5f5f7SGuo Ren 393edff1b48SGuo Renconfig CSKY_APB_INTC 394edff1b48SGuo Ren bool "C-SKY APB Interrupt Controller" 395edff1b48SGuo Ren depends on CSKY 396edff1b48SGuo Ren help 397edff1b48SGuo Ren Say yes here to enable C-SKY APB interrupt controller driver used 398edff1b48SGuo Ren by C-SKY single core SOC system. It use mmio map apb-bus to visit 399edff1b48SGuo Ren the controller's register. 400edff1b48SGuo Ren 4010136afa0SLucas Stachconfig IMX_IRQSTEER 4020136afa0SLucas Stach bool "i.MX IRQSTEER support" 4030136afa0SLucas Stach depends on ARCH_MXC || COMPILE_TEST 4040136afa0SLucas Stach default ARCH_MXC 4050136afa0SLucas Stach select IRQ_DOMAIN 4060136afa0SLucas Stach help 4070136afa0SLucas Stach Support for the i.MX IRQSTEER interrupt multiplexer/remapper. 4080136afa0SLucas Stach 4099e543e22SJiaxun Yangconfig LS1X_IRQ 4109e543e22SJiaxun Yang bool "Loongson-1 Interrupt Controller" 4119e543e22SJiaxun Yang depends on MACH_LOONGSON32 4129e543e22SJiaxun Yang default y 4139e543e22SJiaxun Yang select IRQ_DOMAIN 4149e543e22SJiaxun Yang select GENERIC_IRQ_CHIP 4159e543e22SJiaxun Yang help 4169e543e22SJiaxun Yang Support for the Loongson-1 platform Interrupt Controller. 4179e543e22SJiaxun Yang 418c94fb639SRandy Dunlapendmenu 4198237f8bcSChristoph Hellwig 4208237f8bcSChristoph Hellwigconfig SIFIVE_PLIC 4218237f8bcSChristoph Hellwig bool "SiFive Platform-Level Interrupt Controller" 4228237f8bcSChristoph Hellwig depends on RISCV 4238237f8bcSChristoph Hellwig help 4248237f8bcSChristoph Hellwig This enables support for the PLIC chip found in SiFive (and 4258237f8bcSChristoph Hellwig potentially other) RISC-V systems. The PLIC controls devices 4268237f8bcSChristoph Hellwig interrupts and connects them to each core's local interrupt 4278237f8bcSChristoph Hellwig controller. Aside from timer and software interrupts, all other 4288237f8bcSChristoph Hellwig interrupt sources are subordinate to the PLIC. 4298237f8bcSChristoph Hellwig 4308237f8bcSChristoph Hellwig If you don't know what to do here, say Y. 431