1ec8f24b7SThomas Gleixner# SPDX-License-Identifier: GPL-2.0-only 2c94fb639SRandy Dunlapmenu "IRQ chip support" 3c94fb639SRandy Dunlap 4f6e916b8SThomas Petazzoniconfig IRQCHIP 5f6e916b8SThomas Petazzoni def_bool y 6f6e916b8SThomas Petazzoni depends on OF_IRQ 7f6e916b8SThomas Petazzoni 881243e44SRob Herringconfig ARM_GIC 981243e44SRob Herring bool 109a1091efSYingjoe Chen select IRQ_DOMAIN_HIERARCHY 114f7799d9SPalmer Dabbelt select GENERIC_IRQ_MULTI_HANDLER 120c9e4982SMarc Zyngier select GENERIC_IRQ_EFFECTIVE_AFF_MASK 1381243e44SRob Herring 149c8edddfSJon Hunterconfig ARM_GIC_PM 159c8edddfSJon Hunter bool 169c8edddfSJon Hunter depends on PM 179c8edddfSJon Hunter select ARM_GIC 189c8edddfSJon Hunter 19a27d21e0SLinus Walleijconfig ARM_GIC_MAX_NR 20a27d21e0SLinus Walleij int 2170265523SJiangfeng Xiao depends on ARM_GIC 22a27d21e0SLinus Walleij default 2 if ARCH_REALVIEW 23a27d21e0SLinus Walleij default 1 24a27d21e0SLinus Walleij 25853a33ceSSuravee Suthikulpanitconfig ARM_GIC_V2M 26853a33ceSSuravee Suthikulpanit bool 273ee80364SArnd Bergmann depends on PCI 283ee80364SArnd Bergmann select ARM_GIC 293ee80364SArnd Bergmann select PCI_MSI 30853a33ceSSuravee Suthikulpanit 3181243e44SRob Herringconfig GIC_NON_BANKED 3281243e44SRob Herring bool 3381243e44SRob Herring 34021f6537SMarc Zyngierconfig ARM_GIC_V3 35021f6537SMarc Zyngier bool 364f7799d9SPalmer Dabbelt select GENERIC_IRQ_MULTI_HANDLER 37443acc4fSMarc Zyngier select IRQ_DOMAIN_HIERARCHY 38e3825ba1SMarc Zyngier select PARTITION_PERCPU 39956ae91aSMarc Zyngier select GENERIC_IRQ_EFFECTIVE_AFF_MASK 40021f6537SMarc Zyngier 4119812729SMarc Zyngierconfig ARM_GIC_V3_ITS 4219812729SMarc Zyngier bool 4329f41139SMarc Zyngier select GENERIC_MSI_IRQ_DOMAIN 4429f41139SMarc Zyngier default ARM_GIC_V3 4529f41139SMarc Zyngier 4629f41139SMarc Zyngierconfig ARM_GIC_V3_ITS_PCI 4729f41139SMarc Zyngier bool 4829f41139SMarc Zyngier depends on ARM_GIC_V3_ITS 493ee80364SArnd Bergmann depends on PCI 503ee80364SArnd Bergmann depends on PCI_MSI 5129f41139SMarc Zyngier default ARM_GIC_V3_ITS 52292ec080SUwe Kleine-König 537afe031cSBogdan Purcareataconfig ARM_GIC_V3_ITS_FSL_MC 547afe031cSBogdan Purcareata bool 557afe031cSBogdan Purcareata depends on ARM_GIC_V3_ITS 567afe031cSBogdan Purcareata depends on FSL_MC_BUS 577afe031cSBogdan Purcareata default ARM_GIC_V3_ITS 587afe031cSBogdan Purcareata 5944430ec0SRob Herringconfig ARM_NVIC 6044430ec0SRob Herring bool 612d9f59f7SStefan Agner select IRQ_DOMAIN_HIERARCHY 6244430ec0SRob Herring select GENERIC_IRQ_CHIP 6344430ec0SRob Herring 6444430ec0SRob Herringconfig ARM_VIC 6544430ec0SRob Herring bool 6644430ec0SRob Herring select IRQ_DOMAIN 674f7799d9SPalmer Dabbelt select GENERIC_IRQ_MULTI_HANDLER 6844430ec0SRob Herring 6944430ec0SRob Herringconfig ARM_VIC_NR 7044430ec0SRob Herring int 7144430ec0SRob Herring default 4 if ARCH_S5PV210 7244430ec0SRob Herring default 2 7344430ec0SRob Herring depends on ARM_VIC 7444430ec0SRob Herring help 7544430ec0SRob Herring The maximum number of VICs available in the system, for 7644430ec0SRob Herring power management. 7744430ec0SRob Herring 78fed6d336SThomas Petazzoniconfig ARMADA_370_XP_IRQ 79fed6d336SThomas Petazzoni bool 80fed6d336SThomas Petazzoni select GENERIC_IRQ_CHIP 813ee80364SArnd Bergmann select PCI_MSI if PCI 82e31793a3SMarc Zyngier select GENERIC_IRQ_EFFECTIVE_AFF_MASK 83fed6d336SThomas Petazzoni 84e6b78f2cSAntoine Tenartconfig ALPINE_MSI 85e6b78f2cSAntoine Tenart bool 863ee80364SArnd Bergmann depends on PCI 873ee80364SArnd Bergmann select PCI_MSI 88e6b78f2cSAntoine Tenart select GENERIC_IRQ_CHIP 89e6b78f2cSAntoine Tenart 901eb77c3bSTalel Shenharconfig AL_FIC 911eb77c3bSTalel Shenhar bool "Amazon's Annapurna Labs Fabric Interrupt Controller" 921eb77c3bSTalel Shenhar depends on OF || COMPILE_TEST 931eb77c3bSTalel Shenhar select GENERIC_IRQ_CHIP 941eb77c3bSTalel Shenhar select IRQ_DOMAIN 951eb77c3bSTalel Shenhar help 961eb77c3bSTalel Shenhar Support Amazon's Annapurna Labs Fabric Interrupt Controller. 971eb77c3bSTalel Shenhar 98b1479ebbSBoris BREZILLONconfig ATMEL_AIC_IRQ 99b1479ebbSBoris BREZILLON bool 100b1479ebbSBoris BREZILLON select GENERIC_IRQ_CHIP 101b1479ebbSBoris BREZILLON select IRQ_DOMAIN 1024f7799d9SPalmer Dabbelt select GENERIC_IRQ_MULTI_HANDLER 103b1479ebbSBoris BREZILLON select SPARSE_IRQ 104b1479ebbSBoris BREZILLON 105b1479ebbSBoris BREZILLONconfig ATMEL_AIC5_IRQ 106b1479ebbSBoris BREZILLON bool 107b1479ebbSBoris BREZILLON select GENERIC_IRQ_CHIP 108b1479ebbSBoris BREZILLON select IRQ_DOMAIN 1094f7799d9SPalmer Dabbelt select GENERIC_IRQ_MULTI_HANDLER 110b1479ebbSBoris BREZILLON select SPARSE_IRQ 111b1479ebbSBoris BREZILLON 1120509cfdeSRalf Baechleconfig I8259 1130509cfdeSRalf Baechle bool 1140509cfdeSRalf Baechle select IRQ_DOMAIN 1150509cfdeSRalf Baechle 116c7c42ec2SSimon Arlottconfig BCM6345_L1_IRQ 117c7c42ec2SSimon Arlott bool 118c7c42ec2SSimon Arlott select GENERIC_IRQ_CHIP 119c7c42ec2SSimon Arlott select IRQ_DOMAIN 120d0ed5e8eSMarc Zyngier select GENERIC_IRQ_EFFECTIVE_AFF_MASK 121c7c42ec2SSimon Arlott 1225f7f0317SKevin Cernekeeconfig BCM7038_L1_IRQ 1235f7f0317SKevin Cernekee bool 1245f7f0317SKevin Cernekee select GENERIC_IRQ_CHIP 1255f7f0317SKevin Cernekee select IRQ_DOMAIN 126b8d9884aSMarc Zyngier select GENERIC_IRQ_EFFECTIVE_AFF_MASK 1275f7f0317SKevin Cernekee 128a4fcbb86SKevin Cernekeeconfig BCM7120_L2_IRQ 129a4fcbb86SKevin Cernekee bool 130a4fcbb86SKevin Cernekee select GENERIC_IRQ_CHIP 131a4fcbb86SKevin Cernekee select IRQ_DOMAIN 132a4fcbb86SKevin Cernekee 1337f646e92SFlorian Fainelliconfig BRCMSTB_L2_IRQ 1347f646e92SFlorian Fainelli bool 1357f646e92SFlorian Fainelli select GENERIC_IRQ_CHIP 1367f646e92SFlorian Fainelli select IRQ_DOMAIN 1377f646e92SFlorian Fainelli 1380145beedSBartosz Golaszewskiconfig DAVINCI_AINTC 1390145beedSBartosz Golaszewski bool 1400145beedSBartosz Golaszewski select GENERIC_IRQ_CHIP 1410145beedSBartosz Golaszewski select IRQ_DOMAIN 1420145beedSBartosz Golaszewski 1430fc3d74cSBartosz Golaszewskiconfig DAVINCI_CP_INTC 1440fc3d74cSBartosz Golaszewski bool 1450fc3d74cSBartosz Golaszewski select GENERIC_IRQ_CHIP 1460fc3d74cSBartosz Golaszewski select IRQ_DOMAIN 1470fc3d74cSBartosz Golaszewski 148350d71b9SSebastian Hesselbarthconfig DW_APB_ICTL 149350d71b9SSebastian Hesselbarth bool 150e1588490SJisheng Zhang select GENERIC_IRQ_CHIP 15154a38440SZhen Lei select IRQ_DOMAIN_HIERARCHY 152350d71b9SSebastian Hesselbarth 1536ee532e2SLinus Walleijconfig FARADAY_FTINTC010 1546ee532e2SLinus Walleij bool 1556ee532e2SLinus Walleij select IRQ_DOMAIN 1564f7799d9SPalmer Dabbelt select GENERIC_IRQ_MULTI_HANDLER 1576ee532e2SLinus Walleij select SPARSE_IRQ 1586ee532e2SLinus Walleij 1599a7c4abdSMaJunconfig HISILICON_IRQ_MBIGEN 1609a7c4abdSMaJun bool 1619a7c4abdSMaJun select ARM_GIC_V3 1629a7c4abdSMaJun select ARM_GIC_V3_ITS 1639a7c4abdSMaJun 164b6ef9161SJames Hoganconfig IMGPDC_IRQ 165b6ef9161SJames Hogan bool 166b6ef9161SJames Hogan select GENERIC_IRQ_CHIP 167b6ef9161SJames Hogan select IRQ_DOMAIN 168b6ef9161SJames Hogan 1695b978c10SLinus Walleijconfig IXP4XX_IRQ 1705b978c10SLinus Walleij bool 1715b978c10SLinus Walleij select IRQ_DOMAIN 1725b978c10SLinus Walleij select GENERIC_IRQ_MULTI_HANDLER 1735b978c10SLinus Walleij select SPARSE_IRQ 1745b978c10SLinus Walleij 175da0abe1aSRichard Fitzgeraldconfig MADERA_IRQ 176da0abe1aSRichard Fitzgerald tristate 177da0abe1aSRichard Fitzgerald 17867e38cf2SRalf Baechleconfig IRQ_MIPS_CPU 17967e38cf2SRalf Baechle bool 18067e38cf2SRalf Baechle select GENERIC_IRQ_CHIP 1813838a547SPaul Burton select GENERIC_IRQ_IPI if SYS_SUPPORTS_MULTITHREADING 18267e38cf2SRalf Baechle select IRQ_DOMAIN 1833838a547SPaul Burton select IRQ_DOMAIN_HIERARCHY if GENERIC_IRQ_IPI 18418416e45SMarc Zyngier select GENERIC_IRQ_EFFECTIVE_AFF_MASK 18567e38cf2SRalf Baechle 186afc98d90SAlexander Shiyanconfig CLPS711X_IRQCHIP 187afc98d90SAlexander Shiyan bool 188afc98d90SAlexander Shiyan depends on ARCH_CLPS711X 189afc98d90SAlexander Shiyan select IRQ_DOMAIN 1904f7799d9SPalmer Dabbelt select GENERIC_IRQ_MULTI_HANDLER 191afc98d90SAlexander Shiyan select SPARSE_IRQ 192afc98d90SAlexander Shiyan default y 193afc98d90SAlexander Shiyan 1949b54470aSStafford Horneconfig OMPIC 1959b54470aSStafford Horne bool 1969b54470aSStafford Horne 1974db8e6d2SStefan Kristianssonconfig OR1K_PIC 1984db8e6d2SStefan Kristiansson bool 1994db8e6d2SStefan Kristiansson select IRQ_DOMAIN 2004db8e6d2SStefan Kristiansson 2018598066cSFelipe Balbiconfig OMAP_IRQCHIP 2028598066cSFelipe Balbi bool 2038598066cSFelipe Balbi select GENERIC_IRQ_CHIP 2048598066cSFelipe Balbi select IRQ_DOMAIN 2058598066cSFelipe Balbi 2069dbd90f1SSebastian Hesselbarthconfig ORION_IRQCHIP 2079dbd90f1SSebastian Hesselbarth bool 2089dbd90f1SSebastian Hesselbarth select IRQ_DOMAIN 2094f7799d9SPalmer Dabbelt select GENERIC_IRQ_MULTI_HANDLER 2109dbd90f1SSebastian Hesselbarth 211aaa8666aSCristian Birsanconfig PIC32_EVIC 212aaa8666aSCristian Birsan bool 213aaa8666aSCristian Birsan select GENERIC_IRQ_CHIP 214aaa8666aSCristian Birsan select IRQ_DOMAIN 215aaa8666aSCristian Birsan 216981b58f6SRich Felkerconfig JCORE_AIC 2173602ffdeSRich Felker bool "J-Core integrated AIC" if COMPILE_TEST 2183602ffdeSRich Felker depends on OF 219981b58f6SRich Felker select IRQ_DOMAIN 220981b58f6SRich Felker help 221981b58f6SRich Felker Support for the J-Core integrated AIC. 222981b58f6SRich Felker 223d852e62aSManivannan Sadhasivamconfig RDA_INTC 224d852e62aSManivannan Sadhasivam bool 225d852e62aSManivannan Sadhasivam select IRQ_DOMAIN 226d852e62aSManivannan Sadhasivam 22744358048SMagnus Dammconfig RENESAS_INTC_IRQPIN 22802d7e041SGeert Uytterhoeven bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST 22944358048SMagnus Damm select IRQ_DOMAIN 23002d7e041SGeert Uytterhoeven help 23102d7e041SGeert Uytterhoeven Enable support for the Renesas Interrupt Controller for external 23202d7e041SGeert Uytterhoeven interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs. 23344358048SMagnus Damm 234fbc83b7fSMagnus Dammconfig RENESAS_IRQC 23572d44c0cSLad Prabhakar bool "Renesas R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} IRQC support" if COMPILE_TEST 23699c221dfSMagnus Damm select GENERIC_IRQ_CHIP 237fbc83b7fSMagnus Damm select IRQ_DOMAIN 23802d7e041SGeert Uytterhoeven help 23902d7e041SGeert Uytterhoeven Enable support for the Renesas Interrupt Controller for external 24072d44c0cSLad Prabhakar devices, as found on R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} SoCs. 241fbc83b7fSMagnus Damm 242a644ccb8SGeert Uytterhoevenconfig RENESAS_RZA1_IRQC 24302d7e041SGeert Uytterhoeven bool "Renesas RZ/A1 IRQC support" if COMPILE_TEST 244a644ccb8SGeert Uytterhoeven select IRQ_DOMAIN_HIERARCHY 24502d7e041SGeert Uytterhoeven help 24602d7e041SGeert Uytterhoeven Enable support for the Renesas RZ/A1 Interrupt Controller, to use up 24702d7e041SGeert Uytterhoeven to 8 external interrupts with configurable sense select. 248a644ccb8SGeert Uytterhoeven 24907088484SLee Jonesconfig ST_IRQCHIP 25007088484SLee Jones bool 25107088484SLee Jones select REGMAP 25207088484SLee Jones select MFD_SYSCON 25307088484SLee Jones help 25407088484SLee Jones Enables SysCfg Controlled IRQs on STi based platforms. 25507088484SLee Jones 2564bba6689SMans Rullgardconfig TANGO_IRQ 2574bba6689SMans Rullgard bool 2584bba6689SMans Rullgard select IRQ_DOMAIN 2594bba6689SMans Rullgard select GENERIC_IRQ_CHIP 2604bba6689SMans Rullgard 261b06eb017SChristian Ruppertconfig TB10X_IRQC 262b06eb017SChristian Ruppert bool 263b06eb017SChristian Ruppert select IRQ_DOMAIN 264b06eb017SChristian Ruppert select GENERIC_IRQ_CHIP 265b06eb017SChristian Ruppert 266d01f8633SDamien Riegelconfig TS4800_IRQ 267d01f8633SDamien Riegel tristate "TS-4800 IRQ controller" 268d01f8633SDamien Riegel select IRQ_DOMAIN 2690df337cfSRichard Weinberger depends on HAS_IOMEM 270d2b383dcSJean Delvare depends on SOC_IMX51 || COMPILE_TEST 271d01f8633SDamien Riegel help 272d01f8633SDamien Riegel Support for the TS-4800 FPGA IRQ controller 273d01f8633SDamien Riegel 2742389d501SLinus Walleijconfig VERSATILE_FPGA_IRQ 2752389d501SLinus Walleij bool 2762389d501SLinus Walleij select IRQ_DOMAIN 2772389d501SLinus Walleij 2782389d501SLinus Walleijconfig VERSATILE_FPGA_IRQ_NR 2792389d501SLinus Walleij int 2802389d501SLinus Walleij default 4 2812389d501SLinus Walleij depends on VERSATILE_FPGA_IRQ 28226a8e96aSMax Filippov 28326a8e96aSMax Filippovconfig XTENSA_MX 28426a8e96aSMax Filippov bool 28526a8e96aSMax Filippov select IRQ_DOMAIN 28650091212SMarc Zyngier select GENERIC_IRQ_EFFECTIVE_AFF_MASK 28796ca848eSSricharan R 2880547dc78SZubair Lutfullah Kakakhelconfig XILINX_INTC 2890547dc78SZubair Lutfullah Kakakhel bool 2900547dc78SZubair Lutfullah Kakakhel select IRQ_DOMAIN 2910547dc78SZubair Lutfullah Kakakhel 29296ca848eSSricharan Rconfig IRQ_CROSSBAR 29396ca848eSSricharan R bool 29496ca848eSSricharan R help 295f54619f2SMasanari Iida Support for a CROSSBAR ip that precedes the main interrupt controller. 29696ca848eSSricharan R The primary irqchip invokes the crossbar's callback which inturn allocates 29796ca848eSSricharan R a free irq and configures the IP. Thus the peripheral interrupts are 29896ca848eSSricharan R routed to one of the free irqchip interrupt lines. 29989323f8cSGrygorii Strashko 30089323f8cSGrygorii Strashkoconfig KEYSTONE_IRQ 30189323f8cSGrygorii Strashko tristate "Keystone 2 IRQ controller IP" 30289323f8cSGrygorii Strashko depends on ARCH_KEYSTONE 30389323f8cSGrygorii Strashko help 30489323f8cSGrygorii Strashko Support for Texas Instruments Keystone 2 IRQ controller IP which 30589323f8cSGrygorii Strashko is part of the Keystone 2 IPC mechanism 3068a19b8f1SAndrew Bresticker 3078a19b8f1SAndrew Brestickerconfig MIPS_GIC 3088a19b8f1SAndrew Bresticker bool 309bb11cff3SQais Yousef select GENERIC_IRQ_IPI 3102af70a96SQais Yousef select IRQ_DOMAIN_HIERARCHY 3118a19b8f1SAndrew Bresticker select MIPS_CM 3128a764482SYoshinori Sato 31344e08e70SPaul Burtonconfig INGENIC_IRQ 31444e08e70SPaul Burton bool 31544e08e70SPaul Burton depends on MACH_INGENIC 31644e08e70SPaul Burton default y 31778c10e55SLinus Torvalds 3189536eba0SPaul Cercueilconfig INGENIC_TCU_IRQ 3199536eba0SPaul Cercueil bool "Ingenic JZ47xx TCU interrupt controller" 3209536eba0SPaul Cercueil default MACH_INGENIC 3219536eba0SPaul Cercueil depends on MIPS || COMPILE_TEST 3229536eba0SPaul Cercueil select MFD_SYSCON 3238084499bSYueHaibing select GENERIC_IRQ_CHIP 3249536eba0SPaul Cercueil help 3259536eba0SPaul Cercueil Support for interrupts in the Timer/Counter Unit (TCU) of the Ingenic 3269536eba0SPaul Cercueil JZ47xx SoCs. 3279536eba0SPaul Cercueil 3289536eba0SPaul Cercueil If unsure, say N. 3299536eba0SPaul Cercueil 3308a764482SYoshinori Satoconfig RENESAS_H8300H_INTC 3318a764482SYoshinori Sato bool 3328a764482SYoshinori Sato select IRQ_DOMAIN 3338a764482SYoshinori Sato 3348a764482SYoshinori Satoconfig RENESAS_H8S_INTC 33502d7e041SGeert Uytterhoeven bool "Renesas H8S Interrupt Controller Support" if COMPILE_TEST 3368a764482SYoshinori Sato select IRQ_DOMAIN 33702d7e041SGeert Uytterhoeven help 33802d7e041SGeert Uytterhoeven Enable support for the Renesas H8/300 Interrupt Controller, as found 33902d7e041SGeert Uytterhoeven on Renesas H8S SoCs. 340e324c4dcSShenwei Wang 341e324c4dcSShenwei Wangconfig IMX_GPCV2 342e324c4dcSShenwei Wang bool 343e324c4dcSShenwei Wang select IRQ_DOMAIN 344e324c4dcSShenwei Wang help 345e324c4dcSShenwei Wang Enables the wakeup IRQs for IMX platforms with GPCv2 block 3467e4ac676SOleksij Rempel 3477e4ac676SOleksij Rempelconfig IRQ_MXS 3487e4ac676SOleksij Rempel def_bool y if MACH_ASM9260 || ARCH_MXS 3497e4ac676SOleksij Rempel select IRQ_DOMAIN 3507e4ac676SOleksij Rempel select STMP_DEVICE 351c27f29bbSThomas Petazzoni 35219d99164SAlexandre Belloniconfig MSCC_OCELOT_IRQ 35319d99164SAlexandre Belloni bool 35419d99164SAlexandre Belloni select IRQ_DOMAIN 35519d99164SAlexandre Belloni select GENERIC_IRQ_CHIP 35619d99164SAlexandre Belloni 357a68a63cbSThomas Petazzoniconfig MVEBU_GICP 358a68a63cbSThomas Petazzoni bool 359a68a63cbSThomas Petazzoni 360e0de91a9SThomas Petazzoniconfig MVEBU_ICU 361e0de91a9SThomas Petazzoni bool 362e0de91a9SThomas Petazzoni 363c27f29bbSThomas Petazzoniconfig MVEBU_ODMI 364c27f29bbSThomas Petazzoni bool 365fa23b9d1SArnd Bergmann select GENERIC_MSI_IRQ_DOMAIN 3669e2c986cSMarc Zyngier 367a109893bSThomas Petazzoniconfig MVEBU_PIC 368a109893bSThomas Petazzoni bool 369a109893bSThomas Petazzoni 37061ce8d8dSMiquel Raynalconfig MVEBU_SEI 37161ce8d8dSMiquel Raynal bool 37261ce8d8dSMiquel Raynal 3730dcd9f87SRasmus Villemoesconfig LS_EXTIRQ 3740dcd9f87SRasmus Villemoes def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 3750dcd9f87SRasmus Villemoes select MFD_SYSCON 3760dcd9f87SRasmus Villemoes 377b8f3ebe6SMinghuan Lianconfig LS_SCFG_MSI 378b8f3ebe6SMinghuan Lian def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 379b8f3ebe6SMinghuan Lian depends on PCI && PCI_MSI 380b8f3ebe6SMinghuan Lian 3819e2c986cSMarc Zyngierconfig PARTITION_PERCPU 3829e2c986cSMarc Zyngier bool 3830efacbbaSLinus Torvalds 38444df427cSNoam Camusconfig EZNPS_GIC 38544df427cSNoam Camus bool "NPS400 Global Interrupt Manager (GIM)" 386ffd565e3SArnd Bergmann depends on ARC || (COMPILE_TEST && !64BIT) 38744df427cSNoam Camus select IRQ_DOMAIN 38844df427cSNoam Camus help 38944df427cSNoam Camus Support the EZchip NPS400 global interrupt controller 390e0720416SAlexandre TORGUE 391e0720416SAlexandre TORGUEconfig STM32_EXTI 392e0720416SAlexandre TORGUE bool 393e0720416SAlexandre TORGUE select IRQ_DOMAIN 3940e7d7807SLudovic Barre select GENERIC_IRQ_CHIP 395f20cc9b0SAgustin Vega-Frias 396f20cc9b0SAgustin Vega-Friasconfig QCOM_IRQ_COMBINER 397f20cc9b0SAgustin Vega-Frias bool "QCOM IRQ combiner support" 398f20cc9b0SAgustin Vega-Frias depends on ARCH_QCOM && ACPI 399f20cc9b0SAgustin Vega-Frias select IRQ_DOMAIN_HIERARCHY 400f20cc9b0SAgustin Vega-Frias help 401f20cc9b0SAgustin Vega-Frias Say yes here to add support for the IRQ combiner devices embedded 402f20cc9b0SAgustin Vega-Frias in Qualcomm Technologies chips. 4035ed34d3aSMasahiro Yamada 4045ed34d3aSMasahiro Yamadaconfig IRQ_UNIPHIER_AIDET 4055ed34d3aSMasahiro Yamada bool "UniPhier AIDET support" if COMPILE_TEST 4065ed34d3aSMasahiro Yamada depends on ARCH_UNIPHIER || COMPILE_TEST 4075ed34d3aSMasahiro Yamada default ARCH_UNIPHIER 4085ed34d3aSMasahiro Yamada select IRQ_DOMAIN_HIERARCHY 4095ed34d3aSMasahiro Yamada help 4105ed34d3aSMasahiro Yamada Support for the UniPhier AIDET (ARM Interrupt Detector). 411c94fb639SRandy Dunlap 412215f4cc0SJerome Brunetconfig MESON_IRQ_GPIO 413215f4cc0SJerome Brunet bool "Meson GPIO Interrupt Multiplexer" 414d9ee91c1SThomas Gleixner depends on ARCH_MESON 415215f4cc0SJerome Brunet select IRQ_DOMAIN_HIERARCHY 416215f4cc0SJerome Brunet help 417215f4cc0SJerome Brunet Support Meson SoC Family GPIO Interrupt Multiplexer 418215f4cc0SJerome Brunet 4194235ff50SMiodrag Dinicconfig GOLDFISH_PIC 4204235ff50SMiodrag Dinic bool "Goldfish programmable interrupt controller" 4214235ff50SMiodrag Dinic depends on MIPS && (GOLDFISH || COMPILE_TEST) 4224235ff50SMiodrag Dinic select IRQ_DOMAIN 4234235ff50SMiodrag Dinic help 4244235ff50SMiodrag Dinic Say yes here to enable Goldfish interrupt controller driver used 4254235ff50SMiodrag Dinic for Goldfish based virtual platforms. 4264235ff50SMiodrag Dinic 427f55c73aeSArchana Sathyakumarconfig QCOM_PDC 428a150dac5SMarc Zyngier bool "QCOM PDC" 429f55c73aeSArchana Sathyakumar depends on ARCH_QCOM 430f55c73aeSArchana Sathyakumar select IRQ_DOMAIN_HIERARCHY 431f55c73aeSArchana Sathyakumar help 432f55c73aeSArchana Sathyakumar Power Domain Controller driver to manage and configure wakeup 433f55c73aeSArchana Sathyakumar IRQs for Qualcomm Technologies Inc (QTI) mobile chips. 434f55c73aeSArchana Sathyakumar 435d8a5f5f7SGuo Renconfig CSKY_MPINTC 436d8a5f5f7SGuo Ren bool "C-SKY Multi Processor Interrupt Controller" 437d8a5f5f7SGuo Ren depends on CSKY 438d8a5f5f7SGuo Ren help 439d8a5f5f7SGuo Ren Say yes here to enable C-SKY SMP interrupt controller driver used 440d8a5f5f7SGuo Ren for C-SKY SMP system. 441656b42deSRandy Dunlap In fact it's not mmio map in hardware and it uses ld/st to visit the 442d8a5f5f7SGuo Ren controller's register inside CPU. 443d8a5f5f7SGuo Ren 444edff1b48SGuo Renconfig CSKY_APB_INTC 445edff1b48SGuo Ren bool "C-SKY APB Interrupt Controller" 446edff1b48SGuo Ren depends on CSKY 447edff1b48SGuo Ren help 448edff1b48SGuo Ren Say yes here to enable C-SKY APB interrupt controller driver used 449656b42deSRandy Dunlap by C-SKY single core SOC system. It uses mmio map apb-bus to visit 450edff1b48SGuo Ren the controller's register. 451edff1b48SGuo Ren 4520136afa0SLucas Stachconfig IMX_IRQSTEER 4530136afa0SLucas Stach bool "i.MX IRQSTEER support" 4540136afa0SLucas Stach depends on ARCH_MXC || COMPILE_TEST 4550136afa0SLucas Stach default ARCH_MXC 4560136afa0SLucas Stach select IRQ_DOMAIN 4570136afa0SLucas Stach help 4580136afa0SLucas Stach Support for the i.MX IRQSTEER interrupt multiplexer/remapper. 4590136afa0SLucas Stach 4602fbb1396SJoakim Zhangconfig IMX_INTMUX 46166968d7dSAnson Huang def_bool y if ARCH_MXC || COMPILE_TEST 4622fbb1396SJoakim Zhang select IRQ_DOMAIN 4632fbb1396SJoakim Zhang help 4642fbb1396SJoakim Zhang Support for the i.MX INTMUX interrupt multiplexer. 4652fbb1396SJoakim Zhang 4669e543e22SJiaxun Yangconfig LS1X_IRQ 4679e543e22SJiaxun Yang bool "Loongson-1 Interrupt Controller" 4689e543e22SJiaxun Yang depends on MACH_LOONGSON32 4699e543e22SJiaxun Yang default y 4709e543e22SJiaxun Yang select IRQ_DOMAIN 4719e543e22SJiaxun Yang select GENERIC_IRQ_CHIP 4729e543e22SJiaxun Yang help 4739e543e22SJiaxun Yang Support for the Loongson-1 platform Interrupt Controller. 4749e543e22SJiaxun Yang 475cd844b07SLokesh Vutlaconfig TI_SCI_INTR_IRQCHIP 476cd844b07SLokesh Vutla bool 477cd844b07SLokesh Vutla depends on TI_SCI_PROTOCOL 478cd844b07SLokesh Vutla select IRQ_DOMAIN_HIERARCHY 479cd844b07SLokesh Vutla help 480cd844b07SLokesh Vutla This enables the irqchip driver support for K3 Interrupt router 481cd844b07SLokesh Vutla over TI System Control Interface available on some new TI's SoCs. 482cd844b07SLokesh Vutla If you wish to use interrupt router irq resources managed by the 483cd844b07SLokesh Vutla TI System Controller, say Y here. Otherwise, say N. 484cd844b07SLokesh Vutla 4859f1463b8SLokesh Vutlaconfig TI_SCI_INTA_IRQCHIP 4869f1463b8SLokesh Vutla bool 4879f1463b8SLokesh Vutla depends on TI_SCI_PROTOCOL 4889f1463b8SLokesh Vutla select IRQ_DOMAIN_HIERARCHY 489f011df61SLokesh Vutla select TI_SCI_INTA_MSI_DOMAIN 4909f1463b8SLokesh Vutla help 4919f1463b8SLokesh Vutla This enables the irqchip driver support for K3 Interrupt aggregator 4929f1463b8SLokesh Vutla over TI System Control Interface available on some new TI's SoCs. 4939f1463b8SLokesh Vutla If you wish to use interrupt aggregator irq resources managed by the 4949f1463b8SLokesh Vutla TI System Controller, say Y here. Otherwise, say N. 4959f1463b8SLokesh Vutla 49604e2d1e0SGrzegorz Jaszczykconfig TI_PRUSS_INTC 49704e2d1e0SGrzegorz Jaszczyk tristate "TI PRU-ICSS Interrupt Controller" 4987e92dee6SSuman Anna depends on ARCH_DAVINCI || SOC_AM33XX || SOC_AM43XX || SOC_DRA7XX || ARCH_KEYSTONE || ARCH_K3 49904e2d1e0SGrzegorz Jaszczyk select IRQ_DOMAIN 50004e2d1e0SGrzegorz Jaszczyk help 50104e2d1e0SGrzegorz Jaszczyk This enables support for the PRU-ICSS Local Interrupt Controller 50204e2d1e0SGrzegorz Jaszczyk present within a PRU-ICSS subsystem present on various TI SoCs. 50304e2d1e0SGrzegorz Jaszczyk The PRUSS INTC enables various interrupts to be routed to multiple 50404e2d1e0SGrzegorz Jaszczyk different processors within the SoC. 50504e2d1e0SGrzegorz Jaszczyk 5066b7ce892SAnup Patelconfig RISCV_INTC 5076b7ce892SAnup Patel bool "RISC-V Local Interrupt Controller" 5086b7ce892SAnup Patel depends on RISCV 5096b7ce892SAnup Patel default y 5106b7ce892SAnup Patel help 5116b7ce892SAnup Patel This enables support for the per-HART local interrupt controller 5126b7ce892SAnup Patel found in standard RISC-V systems. The per-HART local interrupt 5136b7ce892SAnup Patel controller handles timer interrupts, software interrupts, and 5146b7ce892SAnup Patel hardware interrupts. Without a per-HART local interrupt controller, 5156b7ce892SAnup Patel a RISC-V system will be unable to handle any interrupts. 5166b7ce892SAnup Patel 5176b7ce892SAnup Patel If you don't know what to do here, say Y. 5186b7ce892SAnup Patel 5198237f8bcSChristoph Hellwigconfig SIFIVE_PLIC 5208237f8bcSChristoph Hellwig bool "SiFive Platform-Level Interrupt Controller" 5218237f8bcSChristoph Hellwig depends on RISCV 522466008f9SYash Shah select IRQ_DOMAIN_HIERARCHY 5238237f8bcSChristoph Hellwig help 5248237f8bcSChristoph Hellwig This enables support for the PLIC chip found in SiFive (and 5258237f8bcSChristoph Hellwig potentially other) RISC-V systems. The PLIC controls devices 5268237f8bcSChristoph Hellwig interrupts and connects them to each core's local interrupt 5278237f8bcSChristoph Hellwig controller. Aside from timer and software interrupts, all other 5288237f8bcSChristoph Hellwig interrupt sources are subordinate to the PLIC. 5298237f8bcSChristoph Hellwig 5308237f8bcSChristoph Hellwig If you don't know what to do here, say Y. 53101493855SJonathan Neuschäfer 532b74416dbSHyunki Kooconfig EXYNOS_IRQ_COMBINER 533b74416dbSHyunki Koo bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST 534b74416dbSHyunki Koo depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST 535b74416dbSHyunki Koo help 536b74416dbSHyunki Koo Say yes here to add support for the IRQ combiner devices embedded 537b74416dbSHyunki Koo in Samsung Exynos chips. 538b74416dbSHyunki Koo 539dbb15226SJiaxun Yangconfig LOONGSON_LIOINTC 540dbb15226SJiaxun Yang bool "Loongson Local I/O Interrupt Controller" 541dbb15226SJiaxun Yang depends on MACH_LOONGSON64 542dbb15226SJiaxun Yang default y 543dbb15226SJiaxun Yang select IRQ_DOMAIN 544dbb15226SJiaxun Yang select GENERIC_IRQ_CHIP 545dbb15226SJiaxun Yang help 546dbb15226SJiaxun Yang Support for the Loongson Local I/O Interrupt Controller. 547dbb15226SJiaxun Yang 548a93f1d90SJiaxun Yangconfig LOONGSON_HTPIC 549a93f1d90SJiaxun Yang bool "Loongson3 HyperTransport PIC Controller" 550a93f1d90SJiaxun Yang depends on MACH_LOONGSON64 551a93f1d90SJiaxun Yang default y 552a93f1d90SJiaxun Yang select IRQ_DOMAIN 553a93f1d90SJiaxun Yang select GENERIC_IRQ_CHIP 554a93f1d90SJiaxun Yang help 555a93f1d90SJiaxun Yang Support for the Loongson-3 HyperTransport PIC Controller. 556a93f1d90SJiaxun Yang 557818e915fSJiaxun Yangconfig LOONGSON_HTVEC 558818e915fSJiaxun Yang bool "Loongson3 HyperTransport Interrupt Vector Controller" 559d77aeb5dSIngo Molnar depends on MACH_LOONGSON64 560818e915fSJiaxun Yang default MACH_LOONGSON64 561818e915fSJiaxun Yang select IRQ_DOMAIN_HIERARCHY 562818e915fSJiaxun Yang help 563818e915fSJiaxun Yang Support for the Loongson3 HyperTransport Interrupt Vector Controller. 564818e915fSJiaxun Yang 565ef8c01ebSJiaxun Yangconfig LOONGSON_PCH_PIC 566ef8c01ebSJiaxun Yang bool "Loongson PCH PIC Controller" 567ef8c01ebSJiaxun Yang depends on MACH_LOONGSON64 || COMPILE_TEST 568ef8c01ebSJiaxun Yang default MACH_LOONGSON64 569ef8c01ebSJiaxun Yang select IRQ_DOMAIN_HIERARCHY 570ef8c01ebSJiaxun Yang select IRQ_FASTEOI_HIERARCHY_HANDLERS 571ef8c01ebSJiaxun Yang help 572ef8c01ebSJiaxun Yang Support for the Loongson PCH PIC Controller. 573ef8c01ebSJiaxun Yang 574632dcc2cSJiaxun Yangconfig LOONGSON_PCH_MSI 575a23df9a4SJiaxun Yang bool "Loongson PCH MSI Controller" 576632dcc2cSJiaxun Yang depends on MACH_LOONGSON64 || COMPILE_TEST 577632dcc2cSJiaxun Yang depends on PCI 578632dcc2cSJiaxun Yang default MACH_LOONGSON64 579632dcc2cSJiaxun Yang select IRQ_DOMAIN_HIERARCHY 580632dcc2cSJiaxun Yang select PCI_MSI 581632dcc2cSJiaxun Yang help 582632dcc2cSJiaxun Yang Support for the Loongson PCH MSI Controller. 583632dcc2cSJiaxun Yang 584ad4c938cSMark-PK Tsaiconfig MST_IRQ 585ad4c938cSMark-PK Tsai bool "MStar Interrupt Controller" 58661b0648dSGeert Uytterhoeven depends on ARCH_MEDIATEK || ARCH_MSTARV7 || COMPILE_TEST 587ad4c938cSMark-PK Tsai default ARCH_MEDIATEK 588ad4c938cSMark-PK Tsai select IRQ_DOMAIN 589ad4c938cSMark-PK Tsai select IRQ_DOMAIN_HIERARCHY 590ad4c938cSMark-PK Tsai help 591ad4c938cSMark-PK Tsai Support MStar Interrupt Controller. 592ad4c938cSMark-PK Tsai 59301493855SJonathan Neuschäferendmenu 594