1ec8f24b7SThomas Gleixner# SPDX-License-Identifier: GPL-2.0-only 2c94fb639SRandy Dunlapmenu "IRQ chip support" 3c94fb639SRandy Dunlap 4f6e916b8SThomas Petazzoniconfig IRQCHIP 5f6e916b8SThomas Petazzoni def_bool y 6f6e916b8SThomas Petazzoni depends on OF_IRQ 7f6e916b8SThomas Petazzoni 881243e44SRob Herringconfig ARM_GIC 981243e44SRob Herring bool 109a1091efSYingjoe Chen select IRQ_DOMAIN_HIERARCHY 110c9e4982SMarc Zyngier select GENERIC_IRQ_EFFECTIVE_AFF_MASK 1281243e44SRob Herring 139c8edddfSJon Hunterconfig ARM_GIC_PM 149c8edddfSJon Hunter bool 159c8edddfSJon Hunter depends on PM 169c8edddfSJon Hunter select ARM_GIC 179c8edddfSJon Hunter 18a27d21e0SLinus Walleijconfig ARM_GIC_MAX_NR 19a27d21e0SLinus Walleij int 2070265523SJiangfeng Xiao depends on ARM_GIC 21a27d21e0SLinus Walleij default 2 if ARCH_REALVIEW 22a27d21e0SLinus Walleij default 1 23a27d21e0SLinus Walleij 24853a33ceSSuravee Suthikulpanitconfig ARM_GIC_V2M 25853a33ceSSuravee Suthikulpanit bool 263ee80364SArnd Bergmann depends on PCI 273ee80364SArnd Bergmann select ARM_GIC 283ee80364SArnd Bergmann select PCI_MSI 29853a33ceSSuravee Suthikulpanit 3081243e44SRob Herringconfig GIC_NON_BANKED 3181243e44SRob Herring bool 3281243e44SRob Herring 33021f6537SMarc Zyngierconfig ARM_GIC_V3 34021f6537SMarc Zyngier bool 35443acc4fSMarc Zyngier select IRQ_DOMAIN_HIERARCHY 36e3825ba1SMarc Zyngier select PARTITION_PERCPU 37956ae91aSMarc Zyngier select GENERIC_IRQ_EFFECTIVE_AFF_MASK 38021f6537SMarc Zyngier 3919812729SMarc Zyngierconfig ARM_GIC_V3_ITS 4019812729SMarc Zyngier bool 4129f41139SMarc Zyngier select GENERIC_MSI_IRQ_DOMAIN 4229f41139SMarc Zyngier default ARM_GIC_V3 4329f41139SMarc Zyngier 4429f41139SMarc Zyngierconfig ARM_GIC_V3_ITS_PCI 4529f41139SMarc Zyngier bool 4629f41139SMarc Zyngier depends on ARM_GIC_V3_ITS 473ee80364SArnd Bergmann depends on PCI 483ee80364SArnd Bergmann depends on PCI_MSI 4929f41139SMarc Zyngier default ARM_GIC_V3_ITS 50292ec080SUwe Kleine-König 517afe031cSBogdan Purcareataconfig ARM_GIC_V3_ITS_FSL_MC 527afe031cSBogdan Purcareata bool 537afe031cSBogdan Purcareata depends on ARM_GIC_V3_ITS 547afe031cSBogdan Purcareata depends on FSL_MC_BUS 557afe031cSBogdan Purcareata default ARM_GIC_V3_ITS 567afe031cSBogdan Purcareata 5744430ec0SRob Herringconfig ARM_NVIC 5844430ec0SRob Herring bool 592d9f59f7SStefan Agner select IRQ_DOMAIN_HIERARCHY 6044430ec0SRob Herring select GENERIC_IRQ_CHIP 6144430ec0SRob Herring 6244430ec0SRob Herringconfig ARM_VIC 6344430ec0SRob Herring bool 6444430ec0SRob Herring select IRQ_DOMAIN 6544430ec0SRob Herring 6644430ec0SRob Herringconfig ARM_VIC_NR 6744430ec0SRob Herring int 6844430ec0SRob Herring default 4 if ARCH_S5PV210 6944430ec0SRob Herring default 2 7044430ec0SRob Herring depends on ARM_VIC 7144430ec0SRob Herring help 7244430ec0SRob Herring The maximum number of VICs available in the system, for 7344430ec0SRob Herring power management. 7444430ec0SRob Herring 75fed6d336SThomas Petazzoniconfig ARMADA_370_XP_IRQ 76fed6d336SThomas Petazzoni bool 77fed6d336SThomas Petazzoni select GENERIC_IRQ_CHIP 783ee80364SArnd Bergmann select PCI_MSI if PCI 79e31793a3SMarc Zyngier select GENERIC_IRQ_EFFECTIVE_AFF_MASK 80fed6d336SThomas Petazzoni 81e6b78f2cSAntoine Tenartconfig ALPINE_MSI 82e6b78f2cSAntoine Tenart bool 833ee80364SArnd Bergmann depends on PCI 843ee80364SArnd Bergmann select PCI_MSI 85e6b78f2cSAntoine Tenart select GENERIC_IRQ_CHIP 86e6b78f2cSAntoine Tenart 871eb77c3bSTalel Shenharconfig AL_FIC 881eb77c3bSTalel Shenhar bool "Amazon's Annapurna Labs Fabric Interrupt Controller" 891eb77c3bSTalel Shenhar depends on OF || COMPILE_TEST 901eb77c3bSTalel Shenhar select GENERIC_IRQ_CHIP 911eb77c3bSTalel Shenhar select IRQ_DOMAIN 921eb77c3bSTalel Shenhar help 931eb77c3bSTalel Shenhar Support Amazon's Annapurna Labs Fabric Interrupt Controller. 941eb77c3bSTalel Shenhar 95b1479ebbSBoris BREZILLONconfig ATMEL_AIC_IRQ 96b1479ebbSBoris BREZILLON bool 97b1479ebbSBoris BREZILLON select GENERIC_IRQ_CHIP 98b1479ebbSBoris BREZILLON select IRQ_DOMAIN 99b1479ebbSBoris BREZILLON select SPARSE_IRQ 100b1479ebbSBoris BREZILLON 101b1479ebbSBoris BREZILLONconfig ATMEL_AIC5_IRQ 102b1479ebbSBoris BREZILLON bool 103b1479ebbSBoris BREZILLON select GENERIC_IRQ_CHIP 104b1479ebbSBoris BREZILLON select IRQ_DOMAIN 105b1479ebbSBoris BREZILLON select SPARSE_IRQ 106b1479ebbSBoris BREZILLON 1070509cfdeSRalf Baechleconfig I8259 1080509cfdeSRalf Baechle bool 1090509cfdeSRalf Baechle select IRQ_DOMAIN 1100509cfdeSRalf Baechle 111c7c42ec2SSimon Arlottconfig BCM6345_L1_IRQ 112c7c42ec2SSimon Arlott bool 113c7c42ec2SSimon Arlott select GENERIC_IRQ_CHIP 114c7c42ec2SSimon Arlott select IRQ_DOMAIN 115d0ed5e8eSMarc Zyngier select GENERIC_IRQ_EFFECTIVE_AFF_MASK 116c7c42ec2SSimon Arlott 1175f7f0317SKevin Cernekeeconfig BCM7038_L1_IRQ 1185f7f0317SKevin Cernekee bool 1195f7f0317SKevin Cernekee select GENERIC_IRQ_CHIP 1205f7f0317SKevin Cernekee select IRQ_DOMAIN 121b8d9884aSMarc Zyngier select GENERIC_IRQ_EFFECTIVE_AFF_MASK 1225f7f0317SKevin Cernekee 123a4fcbb86SKevin Cernekeeconfig BCM7120_L2_IRQ 124a4fcbb86SKevin Cernekee bool 125a4fcbb86SKevin Cernekee select GENERIC_IRQ_CHIP 126a4fcbb86SKevin Cernekee select IRQ_DOMAIN 127a4fcbb86SKevin Cernekee 1287f646e92SFlorian Fainelliconfig BRCMSTB_L2_IRQ 1297f646e92SFlorian Fainelli bool 1307f646e92SFlorian Fainelli select GENERIC_IRQ_CHIP 1317f646e92SFlorian Fainelli select IRQ_DOMAIN 1327f646e92SFlorian Fainelli 1330145beedSBartosz Golaszewskiconfig DAVINCI_AINTC 1340145beedSBartosz Golaszewski bool 1350145beedSBartosz Golaszewski select GENERIC_IRQ_CHIP 1360145beedSBartosz Golaszewski select IRQ_DOMAIN 1370145beedSBartosz Golaszewski 1380fc3d74cSBartosz Golaszewskiconfig DAVINCI_CP_INTC 1390fc3d74cSBartosz Golaszewski bool 1400fc3d74cSBartosz Golaszewski select GENERIC_IRQ_CHIP 1410fc3d74cSBartosz Golaszewski select IRQ_DOMAIN 1420fc3d74cSBartosz Golaszewski 143350d71b9SSebastian Hesselbarthconfig DW_APB_ICTL 144350d71b9SSebastian Hesselbarth bool 145e1588490SJisheng Zhang select GENERIC_IRQ_CHIP 14654a38440SZhen Lei select IRQ_DOMAIN_HIERARCHY 147350d71b9SSebastian Hesselbarth 1486ee532e2SLinus Walleijconfig FARADAY_FTINTC010 1496ee532e2SLinus Walleij bool 1506ee532e2SLinus Walleij select IRQ_DOMAIN 1516ee532e2SLinus Walleij select SPARSE_IRQ 1526ee532e2SLinus Walleij 1539a7c4abdSMaJunconfig HISILICON_IRQ_MBIGEN 1549a7c4abdSMaJun bool 1559a7c4abdSMaJun select ARM_GIC_V3 1569a7c4abdSMaJun select ARM_GIC_V3_ITS 1579a7c4abdSMaJun 158b6ef9161SJames Hoganconfig IMGPDC_IRQ 159b6ef9161SJames Hogan bool 160b6ef9161SJames Hogan select GENERIC_IRQ_CHIP 161b6ef9161SJames Hogan select IRQ_DOMAIN 162b6ef9161SJames Hogan 1635b978c10SLinus Walleijconfig IXP4XX_IRQ 1645b978c10SLinus Walleij bool 1655b978c10SLinus Walleij select IRQ_DOMAIN 1665b978c10SLinus Walleij select SPARSE_IRQ 1675b978c10SLinus Walleij 168da0abe1aSRichard Fitzgeraldconfig MADERA_IRQ 169da0abe1aSRichard Fitzgerald tristate 170da0abe1aSRichard Fitzgerald 17167e38cf2SRalf Baechleconfig IRQ_MIPS_CPU 17267e38cf2SRalf Baechle bool 17367e38cf2SRalf Baechle select GENERIC_IRQ_CHIP 1743838a547SPaul Burton select GENERIC_IRQ_IPI if SYS_SUPPORTS_MULTITHREADING 17567e38cf2SRalf Baechle select IRQ_DOMAIN 17618416e45SMarc Zyngier select GENERIC_IRQ_EFFECTIVE_AFF_MASK 17767e38cf2SRalf Baechle 178afc98d90SAlexander Shiyanconfig CLPS711X_IRQCHIP 179afc98d90SAlexander Shiyan bool 180afc98d90SAlexander Shiyan depends on ARCH_CLPS711X 181afc98d90SAlexander Shiyan select IRQ_DOMAIN 182afc98d90SAlexander Shiyan select SPARSE_IRQ 183afc98d90SAlexander Shiyan default y 184afc98d90SAlexander Shiyan 1859b54470aSStafford Horneconfig OMPIC 1869b54470aSStafford Horne bool 1879b54470aSStafford Horne 1884db8e6d2SStefan Kristianssonconfig OR1K_PIC 1894db8e6d2SStefan Kristiansson bool 1904db8e6d2SStefan Kristiansson select IRQ_DOMAIN 1914db8e6d2SStefan Kristiansson 1928598066cSFelipe Balbiconfig OMAP_IRQCHIP 1938598066cSFelipe Balbi bool 1948598066cSFelipe Balbi select GENERIC_IRQ_CHIP 1958598066cSFelipe Balbi select IRQ_DOMAIN 1968598066cSFelipe Balbi 1979dbd90f1SSebastian Hesselbarthconfig ORION_IRQCHIP 1989dbd90f1SSebastian Hesselbarth bool 1999dbd90f1SSebastian Hesselbarth select IRQ_DOMAIN 2009dbd90f1SSebastian Hesselbarth 201aaa8666aSCristian Birsanconfig PIC32_EVIC 202aaa8666aSCristian Birsan bool 203aaa8666aSCristian Birsan select GENERIC_IRQ_CHIP 204aaa8666aSCristian Birsan select IRQ_DOMAIN 205aaa8666aSCristian Birsan 206981b58f6SRich Felkerconfig JCORE_AIC 2073602ffdeSRich Felker bool "J-Core integrated AIC" if COMPILE_TEST 2083602ffdeSRich Felker depends on OF 209981b58f6SRich Felker select IRQ_DOMAIN 210981b58f6SRich Felker help 211981b58f6SRich Felker Support for the J-Core integrated AIC. 212981b58f6SRich Felker 213d852e62aSManivannan Sadhasivamconfig RDA_INTC 214d852e62aSManivannan Sadhasivam bool 215d852e62aSManivannan Sadhasivam select IRQ_DOMAIN 216d852e62aSManivannan Sadhasivam 21744358048SMagnus Dammconfig RENESAS_INTC_IRQPIN 21802d7e041SGeert Uytterhoeven bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST 21944358048SMagnus Damm select IRQ_DOMAIN 22002d7e041SGeert Uytterhoeven help 22102d7e041SGeert Uytterhoeven Enable support for the Renesas Interrupt Controller for external 22202d7e041SGeert Uytterhoeven interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs. 22344358048SMagnus Damm 224fbc83b7fSMagnus Dammconfig RENESAS_IRQC 22572d44c0cSLad Prabhakar bool "Renesas R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} IRQC support" if COMPILE_TEST 22699c221dfSMagnus Damm select GENERIC_IRQ_CHIP 227fbc83b7fSMagnus Damm select IRQ_DOMAIN 22802d7e041SGeert Uytterhoeven help 22902d7e041SGeert Uytterhoeven Enable support for the Renesas Interrupt Controller for external 23072d44c0cSLad Prabhakar devices, as found on R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} SoCs. 231fbc83b7fSMagnus Damm 232a644ccb8SGeert Uytterhoevenconfig RENESAS_RZA1_IRQC 23302d7e041SGeert Uytterhoeven bool "Renesas RZ/A1 IRQC support" if COMPILE_TEST 234a644ccb8SGeert Uytterhoeven select IRQ_DOMAIN_HIERARCHY 23502d7e041SGeert Uytterhoeven help 23602d7e041SGeert Uytterhoeven Enable support for the Renesas RZ/A1 Interrupt Controller, to use up 23702d7e041SGeert Uytterhoeven to 8 external interrupts with configurable sense select. 238a644ccb8SGeert Uytterhoeven 23903ac990eSMichael Walleconfig SL28CPLD_INTC 24003ac990eSMichael Walle bool "Kontron sl28cpld IRQ controller" 24103ac990eSMichael Walle depends on MFD_SL28CPLD=y || COMPILE_TEST 24203ac990eSMichael Walle select REGMAP_IRQ 24303ac990eSMichael Walle help 24403ac990eSMichael Walle Interrupt controller driver for the board management controller 24503ac990eSMichael Walle found on the Kontron sl28 CPLD. 24603ac990eSMichael Walle 24707088484SLee Jonesconfig ST_IRQCHIP 24807088484SLee Jones bool 24907088484SLee Jones select REGMAP 25007088484SLee Jones select MFD_SYSCON 25107088484SLee Jones help 25207088484SLee Jones Enables SysCfg Controlled IRQs on STi based platforms. 25307088484SLee Jones 254b06eb017SChristian Ruppertconfig TB10X_IRQC 255b06eb017SChristian Ruppert bool 256b06eb017SChristian Ruppert select IRQ_DOMAIN 257b06eb017SChristian Ruppert select GENERIC_IRQ_CHIP 258b06eb017SChristian Ruppert 259d01f8633SDamien Riegelconfig TS4800_IRQ 260d01f8633SDamien Riegel tristate "TS-4800 IRQ controller" 261d01f8633SDamien Riegel select IRQ_DOMAIN 2620df337cfSRichard Weinberger depends on HAS_IOMEM 263d2b383dcSJean Delvare depends on SOC_IMX51 || COMPILE_TEST 264d01f8633SDamien Riegel help 265d01f8633SDamien Riegel Support for the TS-4800 FPGA IRQ controller 266d01f8633SDamien Riegel 2672389d501SLinus Walleijconfig VERSATILE_FPGA_IRQ 2682389d501SLinus Walleij bool 2692389d501SLinus Walleij select IRQ_DOMAIN 2702389d501SLinus Walleij 2712389d501SLinus Walleijconfig VERSATILE_FPGA_IRQ_NR 2722389d501SLinus Walleij int 2732389d501SLinus Walleij default 4 2742389d501SLinus Walleij depends on VERSATILE_FPGA_IRQ 27526a8e96aSMax Filippov 27626a8e96aSMax Filippovconfig XTENSA_MX 27726a8e96aSMax Filippov bool 27826a8e96aSMax Filippov select IRQ_DOMAIN 27950091212SMarc Zyngier select GENERIC_IRQ_EFFECTIVE_AFF_MASK 28096ca848eSSricharan R 2810547dc78SZubair Lutfullah Kakakhelconfig XILINX_INTC 282debf69cfSRobert Hancock bool "Xilinx Interrupt Controller IP" 283debf69cfSRobert Hancock depends on MICROBLAZE || ARCH_ZYNQ || ARCH_ZYNQMP 2840547dc78SZubair Lutfullah Kakakhel select IRQ_DOMAIN 285debf69cfSRobert Hancock help 286debf69cfSRobert Hancock Support for the Xilinx Interrupt Controller IP core. 287debf69cfSRobert Hancock This is used as a primary controller with MicroBlaze and can also 288debf69cfSRobert Hancock be used as a secondary chained controller on other platforms. 2890547dc78SZubair Lutfullah Kakakhel 29096ca848eSSricharan Rconfig IRQ_CROSSBAR 29196ca848eSSricharan R bool 29296ca848eSSricharan R help 293f54619f2SMasanari Iida Support for a CROSSBAR ip that precedes the main interrupt controller. 29496ca848eSSricharan R The primary irqchip invokes the crossbar's callback which inturn allocates 29596ca848eSSricharan R a free irq and configures the IP. Thus the peripheral interrupts are 29696ca848eSSricharan R routed to one of the free irqchip interrupt lines. 29789323f8cSGrygorii Strashko 29889323f8cSGrygorii Strashkoconfig KEYSTONE_IRQ 29989323f8cSGrygorii Strashko tristate "Keystone 2 IRQ controller IP" 30089323f8cSGrygorii Strashko depends on ARCH_KEYSTONE 30189323f8cSGrygorii Strashko help 30289323f8cSGrygorii Strashko Support for Texas Instruments Keystone 2 IRQ controller IP which 30389323f8cSGrygorii Strashko is part of the Keystone 2 IPC mechanism 3048a19b8f1SAndrew Bresticker 3058a19b8f1SAndrew Brestickerconfig MIPS_GIC 3068a19b8f1SAndrew Bresticker bool 307bb11cff3SQais Yousef select GENERIC_IRQ_IPI 3088a19b8f1SAndrew Bresticker select MIPS_CM 3098a764482SYoshinori Sato 31044e08e70SPaul Burtonconfig INGENIC_IRQ 31144e08e70SPaul Burton bool 31244e08e70SPaul Burton depends on MACH_INGENIC 31344e08e70SPaul Burton default y 31478c10e55SLinus Torvalds 3159536eba0SPaul Cercueilconfig INGENIC_TCU_IRQ 3169536eba0SPaul Cercueil bool "Ingenic JZ47xx TCU interrupt controller" 3179536eba0SPaul Cercueil default MACH_INGENIC 3189536eba0SPaul Cercueil depends on MIPS || COMPILE_TEST 3199536eba0SPaul Cercueil select MFD_SYSCON 3208084499bSYueHaibing select GENERIC_IRQ_CHIP 3219536eba0SPaul Cercueil help 3229536eba0SPaul Cercueil Support for interrupts in the Timer/Counter Unit (TCU) of the Ingenic 3239536eba0SPaul Cercueil JZ47xx SoCs. 3249536eba0SPaul Cercueil 3259536eba0SPaul Cercueil If unsure, say N. 3269536eba0SPaul Cercueil 3278a764482SYoshinori Satoconfig RENESAS_H8300H_INTC 3288a764482SYoshinori Sato bool 3298a764482SYoshinori Sato select IRQ_DOMAIN 3308a764482SYoshinori Sato 3318a764482SYoshinori Satoconfig RENESAS_H8S_INTC 33202d7e041SGeert Uytterhoeven bool "Renesas H8S Interrupt Controller Support" if COMPILE_TEST 3338a764482SYoshinori Sato select IRQ_DOMAIN 33402d7e041SGeert Uytterhoeven help 33502d7e041SGeert Uytterhoeven Enable support for the Renesas H8/300 Interrupt Controller, as found 33602d7e041SGeert Uytterhoeven on Renesas H8S SoCs. 337e324c4dcSShenwei Wang 338e324c4dcSShenwei Wangconfig IMX_GPCV2 339e324c4dcSShenwei Wang bool 340e324c4dcSShenwei Wang select IRQ_DOMAIN 341e324c4dcSShenwei Wang help 342e324c4dcSShenwei Wang Enables the wakeup IRQs for IMX platforms with GPCv2 block 3437e4ac676SOleksij Rempel 3447e4ac676SOleksij Rempelconfig IRQ_MXS 3457e4ac676SOleksij Rempel def_bool y if MACH_ASM9260 || ARCH_MXS 3467e4ac676SOleksij Rempel select IRQ_DOMAIN 3477e4ac676SOleksij Rempel select STMP_DEVICE 348c27f29bbSThomas Petazzoni 34919d99164SAlexandre Belloniconfig MSCC_OCELOT_IRQ 35019d99164SAlexandre Belloni bool 35119d99164SAlexandre Belloni select IRQ_DOMAIN 35219d99164SAlexandre Belloni select GENERIC_IRQ_CHIP 35319d99164SAlexandre Belloni 354a68a63cbSThomas Petazzoniconfig MVEBU_GICP 355a68a63cbSThomas Petazzoni bool 356a68a63cbSThomas Petazzoni 357e0de91a9SThomas Petazzoniconfig MVEBU_ICU 358e0de91a9SThomas Petazzoni bool 359e0de91a9SThomas Petazzoni 360c27f29bbSThomas Petazzoniconfig MVEBU_ODMI 361c27f29bbSThomas Petazzoni bool 362fa23b9d1SArnd Bergmann select GENERIC_MSI_IRQ_DOMAIN 3639e2c986cSMarc Zyngier 364a109893bSThomas Petazzoniconfig MVEBU_PIC 365a109893bSThomas Petazzoni bool 366a109893bSThomas Petazzoni 36761ce8d8dSMiquel Raynalconfig MVEBU_SEI 36861ce8d8dSMiquel Raynal bool 36961ce8d8dSMiquel Raynal 3700dcd9f87SRasmus Villemoesconfig LS_EXTIRQ 3710dcd9f87SRasmus Villemoes def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 3720dcd9f87SRasmus Villemoes select MFD_SYSCON 3730dcd9f87SRasmus Villemoes 374b8f3ebe6SMinghuan Lianconfig LS_SCFG_MSI 375b8f3ebe6SMinghuan Lian def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 376b8f3ebe6SMinghuan Lian depends on PCI && PCI_MSI 377b8f3ebe6SMinghuan Lian 3789e2c986cSMarc Zyngierconfig PARTITION_PERCPU 3799e2c986cSMarc Zyngier bool 3800efacbbaSLinus Torvalds 381e0720416SAlexandre TORGUEconfig STM32_EXTI 382e0720416SAlexandre TORGUE bool 383e0720416SAlexandre TORGUE select IRQ_DOMAIN 3840e7d7807SLudovic Barre select GENERIC_IRQ_CHIP 385f20cc9b0SAgustin Vega-Frias 386f20cc9b0SAgustin Vega-Friasconfig QCOM_IRQ_COMBINER 387f20cc9b0SAgustin Vega-Frias bool "QCOM IRQ combiner support" 388f20cc9b0SAgustin Vega-Frias depends on ARCH_QCOM && ACPI 389f20cc9b0SAgustin Vega-Frias select IRQ_DOMAIN_HIERARCHY 390f20cc9b0SAgustin Vega-Frias help 391f20cc9b0SAgustin Vega-Frias Say yes here to add support for the IRQ combiner devices embedded 392f20cc9b0SAgustin Vega-Frias in Qualcomm Technologies chips. 3935ed34d3aSMasahiro Yamada 3945ed34d3aSMasahiro Yamadaconfig IRQ_UNIPHIER_AIDET 3955ed34d3aSMasahiro Yamada bool "UniPhier AIDET support" if COMPILE_TEST 3965ed34d3aSMasahiro Yamada depends on ARCH_UNIPHIER || COMPILE_TEST 3975ed34d3aSMasahiro Yamada default ARCH_UNIPHIER 3985ed34d3aSMasahiro Yamada select IRQ_DOMAIN_HIERARCHY 3995ed34d3aSMasahiro Yamada help 4005ed34d3aSMasahiro Yamada Support for the UniPhier AIDET (ARM Interrupt Detector). 401c94fb639SRandy Dunlap 402215f4cc0SJerome Brunetconfig MESON_IRQ_GPIO 403215f4cc0SJerome Brunet bool "Meson GPIO Interrupt Multiplexer" 404d9ee91c1SThomas Gleixner depends on ARCH_MESON 405215f4cc0SJerome Brunet select IRQ_DOMAIN_HIERARCHY 406215f4cc0SJerome Brunet help 407215f4cc0SJerome Brunet Support Meson SoC Family GPIO Interrupt Multiplexer 408215f4cc0SJerome Brunet 4094235ff50SMiodrag Dinicconfig GOLDFISH_PIC 4104235ff50SMiodrag Dinic bool "Goldfish programmable interrupt controller" 4114235ff50SMiodrag Dinic depends on MIPS && (GOLDFISH || COMPILE_TEST) 412969ac78dSRandy Dunlap select GENERIC_IRQ_CHIP 4134235ff50SMiodrag Dinic select IRQ_DOMAIN 4144235ff50SMiodrag Dinic help 4154235ff50SMiodrag Dinic Say yes here to enable Goldfish interrupt controller driver used 4164235ff50SMiodrag Dinic for Goldfish based virtual platforms. 4174235ff50SMiodrag Dinic 418f55c73aeSArchana Sathyakumarconfig QCOM_PDC 4194acd8a4bSSaravana Kannan tristate "QCOM PDC" 420f55c73aeSArchana Sathyakumar depends on ARCH_QCOM 421f55c73aeSArchana Sathyakumar select IRQ_DOMAIN_HIERARCHY 422f55c73aeSArchana Sathyakumar help 423f55c73aeSArchana Sathyakumar Power Domain Controller driver to manage and configure wakeup 424f55c73aeSArchana Sathyakumar IRQs for Qualcomm Technologies Inc (QTI) mobile chips. 425f55c73aeSArchana Sathyakumar 426d8a5f5f7SGuo Renconfig CSKY_MPINTC 427be1abc5bSGuo Ren bool 428d8a5f5f7SGuo Ren depends on CSKY 429d8a5f5f7SGuo Ren help 430d8a5f5f7SGuo Ren Say yes here to enable C-SKY SMP interrupt controller driver used 431d8a5f5f7SGuo Ren for C-SKY SMP system. 432656b42deSRandy Dunlap In fact it's not mmio map in hardware and it uses ld/st to visit the 433d8a5f5f7SGuo Ren controller's register inside CPU. 434d8a5f5f7SGuo Ren 435edff1b48SGuo Renconfig CSKY_APB_INTC 436edff1b48SGuo Ren bool "C-SKY APB Interrupt Controller" 437edff1b48SGuo Ren depends on CSKY 438edff1b48SGuo Ren help 439edff1b48SGuo Ren Say yes here to enable C-SKY APB interrupt controller driver used 440656b42deSRandy Dunlap by C-SKY single core SOC system. It uses mmio map apb-bus to visit 441edff1b48SGuo Ren the controller's register. 442edff1b48SGuo Ren 4430136afa0SLucas Stachconfig IMX_IRQSTEER 4440136afa0SLucas Stach bool "i.MX IRQSTEER support" 4450136afa0SLucas Stach depends on ARCH_MXC || COMPILE_TEST 4460136afa0SLucas Stach default ARCH_MXC 4470136afa0SLucas Stach select IRQ_DOMAIN 4480136afa0SLucas Stach help 4490136afa0SLucas Stach Support for the i.MX IRQSTEER interrupt multiplexer/remapper. 4500136afa0SLucas Stach 4512fbb1396SJoakim Zhangconfig IMX_INTMUX 452a890caebSGeert Uytterhoeven bool "i.MX INTMUX support" if COMPILE_TEST 453a890caebSGeert Uytterhoeven default y if ARCH_MXC 4542fbb1396SJoakim Zhang select IRQ_DOMAIN 4552fbb1396SJoakim Zhang help 4562fbb1396SJoakim Zhang Support for the i.MX INTMUX interrupt multiplexer. 4572fbb1396SJoakim Zhang 4589e543e22SJiaxun Yangconfig LS1X_IRQ 4599e543e22SJiaxun Yang bool "Loongson-1 Interrupt Controller" 4609e543e22SJiaxun Yang depends on MACH_LOONGSON32 4619e543e22SJiaxun Yang default y 4629e543e22SJiaxun Yang select IRQ_DOMAIN 4639e543e22SJiaxun Yang select GENERIC_IRQ_CHIP 4649e543e22SJiaxun Yang help 4659e543e22SJiaxun Yang Support for the Loongson-1 platform Interrupt Controller. 4669e543e22SJiaxun Yang 467cd844b07SLokesh Vutlaconfig TI_SCI_INTR_IRQCHIP 468cd844b07SLokesh Vutla bool 469cd844b07SLokesh Vutla depends on TI_SCI_PROTOCOL 470cd844b07SLokesh Vutla select IRQ_DOMAIN_HIERARCHY 471cd844b07SLokesh Vutla help 472cd844b07SLokesh Vutla This enables the irqchip driver support for K3 Interrupt router 473cd844b07SLokesh Vutla over TI System Control Interface available on some new TI's SoCs. 474cd844b07SLokesh Vutla If you wish to use interrupt router irq resources managed by the 475cd844b07SLokesh Vutla TI System Controller, say Y here. Otherwise, say N. 476cd844b07SLokesh Vutla 4779f1463b8SLokesh Vutlaconfig TI_SCI_INTA_IRQCHIP 4789f1463b8SLokesh Vutla bool 4799f1463b8SLokesh Vutla depends on TI_SCI_PROTOCOL 4809f1463b8SLokesh Vutla select IRQ_DOMAIN_HIERARCHY 481f011df61SLokesh Vutla select TI_SCI_INTA_MSI_DOMAIN 4829f1463b8SLokesh Vutla help 4839f1463b8SLokesh Vutla This enables the irqchip driver support for K3 Interrupt aggregator 4849f1463b8SLokesh Vutla over TI System Control Interface available on some new TI's SoCs. 4859f1463b8SLokesh Vutla If you wish to use interrupt aggregator irq resources managed by the 4869f1463b8SLokesh Vutla TI System Controller, say Y here. Otherwise, say N. 4879f1463b8SLokesh Vutla 48804e2d1e0SGrzegorz Jaszczykconfig TI_PRUSS_INTC 489b8e594faSSuman Anna tristate 490b8e594faSSuman Anna depends on TI_PRUSS 491b8e594faSSuman Anna default TI_PRUSS 49204e2d1e0SGrzegorz Jaszczyk select IRQ_DOMAIN 49304e2d1e0SGrzegorz Jaszczyk help 49404e2d1e0SGrzegorz Jaszczyk This enables support for the PRU-ICSS Local Interrupt Controller 49504e2d1e0SGrzegorz Jaszczyk present within a PRU-ICSS subsystem present on various TI SoCs. 49604e2d1e0SGrzegorz Jaszczyk The PRUSS INTC enables various interrupts to be routed to multiple 49704e2d1e0SGrzegorz Jaszczyk different processors within the SoC. 49804e2d1e0SGrzegorz Jaszczyk 4996b7ce892SAnup Patelconfig RISCV_INTC 5006b7ce892SAnup Patel bool "RISC-V Local Interrupt Controller" 5016b7ce892SAnup Patel depends on RISCV 5026b7ce892SAnup Patel default y 5036b7ce892SAnup Patel help 5046b7ce892SAnup Patel This enables support for the per-HART local interrupt controller 5056b7ce892SAnup Patel found in standard RISC-V systems. The per-HART local interrupt 5066b7ce892SAnup Patel controller handles timer interrupts, software interrupts, and 5076b7ce892SAnup Patel hardware interrupts. Without a per-HART local interrupt controller, 5086b7ce892SAnup Patel a RISC-V system will be unable to handle any interrupts. 5096b7ce892SAnup Patel 5106b7ce892SAnup Patel If you don't know what to do here, say Y. 5116b7ce892SAnup Patel 5128237f8bcSChristoph Hellwigconfig SIFIVE_PLIC 5138237f8bcSChristoph Hellwig bool "SiFive Platform-Level Interrupt Controller" 5148237f8bcSChristoph Hellwig depends on RISCV 515466008f9SYash Shah select IRQ_DOMAIN_HIERARCHY 5168237f8bcSChristoph Hellwig help 5178237f8bcSChristoph Hellwig This enables support for the PLIC chip found in SiFive (and 5188237f8bcSChristoph Hellwig potentially other) RISC-V systems. The PLIC controls devices 5198237f8bcSChristoph Hellwig interrupts and connects them to each core's local interrupt 5208237f8bcSChristoph Hellwig controller. Aside from timer and software interrupts, all other 5218237f8bcSChristoph Hellwig interrupt sources are subordinate to the PLIC. 5228237f8bcSChristoph Hellwig 5238237f8bcSChristoph Hellwig If you don't know what to do here, say Y. 52401493855SJonathan Neuschäfer 525b74416dbSHyunki Kooconfig EXYNOS_IRQ_COMBINER 526b74416dbSHyunki Koo bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST 527b74416dbSHyunki Koo depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST 528b74416dbSHyunki Koo help 529b74416dbSHyunki Koo Say yes here to add support for the IRQ combiner devices embedded 530b74416dbSHyunki Koo in Samsung Exynos chips. 531b74416dbSHyunki Koo 532dbb15226SJiaxun Yangconfig LOONGSON_LIOINTC 533dbb15226SJiaxun Yang bool "Loongson Local I/O Interrupt Controller" 534dbb15226SJiaxun Yang depends on MACH_LOONGSON64 535dbb15226SJiaxun Yang default y 536dbb15226SJiaxun Yang select IRQ_DOMAIN 537dbb15226SJiaxun Yang select GENERIC_IRQ_CHIP 538dbb15226SJiaxun Yang help 539dbb15226SJiaxun Yang Support for the Loongson Local I/O Interrupt Controller. 540dbb15226SJiaxun Yang 541a93f1d90SJiaxun Yangconfig LOONGSON_HTPIC 542a93f1d90SJiaxun Yang bool "Loongson3 HyperTransport PIC Controller" 543a93f1d90SJiaxun Yang depends on MACH_LOONGSON64 544a93f1d90SJiaxun Yang default y 545a93f1d90SJiaxun Yang select IRQ_DOMAIN 546a93f1d90SJiaxun Yang select GENERIC_IRQ_CHIP 547a93f1d90SJiaxun Yang help 548a93f1d90SJiaxun Yang Support for the Loongson-3 HyperTransport PIC Controller. 549a93f1d90SJiaxun Yang 550818e915fSJiaxun Yangconfig LOONGSON_HTVEC 551818e915fSJiaxun Yang bool "Loongson3 HyperTransport Interrupt Vector Controller" 552d77aeb5dSIngo Molnar depends on MACH_LOONGSON64 553818e915fSJiaxun Yang default MACH_LOONGSON64 554818e915fSJiaxun Yang select IRQ_DOMAIN_HIERARCHY 555818e915fSJiaxun Yang help 556818e915fSJiaxun Yang Support for the Loongson3 HyperTransport Interrupt Vector Controller. 557818e915fSJiaxun Yang 558ef8c01ebSJiaxun Yangconfig LOONGSON_PCH_PIC 559ef8c01ebSJiaxun Yang bool "Loongson PCH PIC Controller" 560ef8c01ebSJiaxun Yang depends on MACH_LOONGSON64 || COMPILE_TEST 561ef8c01ebSJiaxun Yang default MACH_LOONGSON64 562ef8c01ebSJiaxun Yang select IRQ_DOMAIN_HIERARCHY 563ef8c01ebSJiaxun Yang select IRQ_FASTEOI_HIERARCHY_HANDLERS 564ef8c01ebSJiaxun Yang help 565ef8c01ebSJiaxun Yang Support for the Loongson PCH PIC Controller. 566ef8c01ebSJiaxun Yang 567632dcc2cSJiaxun Yangconfig LOONGSON_PCH_MSI 568a23df9a4SJiaxun Yang bool "Loongson PCH MSI Controller" 569632dcc2cSJiaxun Yang depends on MACH_LOONGSON64 || COMPILE_TEST 570632dcc2cSJiaxun Yang depends on PCI 571632dcc2cSJiaxun Yang default MACH_LOONGSON64 572632dcc2cSJiaxun Yang select IRQ_DOMAIN_HIERARCHY 573632dcc2cSJiaxun Yang select PCI_MSI 574632dcc2cSJiaxun Yang help 575632dcc2cSJiaxun Yang Support for the Loongson PCH MSI Controller. 576632dcc2cSJiaxun Yang 577ad4c938cSMark-PK Tsaiconfig MST_IRQ 578ad4c938cSMark-PK Tsai bool "MStar Interrupt Controller" 57961b0648dSGeert Uytterhoeven depends on ARCH_MEDIATEK || ARCH_MSTARV7 || COMPILE_TEST 580ad4c938cSMark-PK Tsai default ARCH_MEDIATEK 581ad4c938cSMark-PK Tsai select IRQ_DOMAIN 582ad4c938cSMark-PK Tsai select IRQ_DOMAIN_HIERARCHY 583ad4c938cSMark-PK Tsai help 584ad4c938cSMark-PK Tsai Support MStar Interrupt Controller. 585ad4c938cSMark-PK Tsai 586fead4dd4SJonathan Neuschäferconfig WPCM450_AIC 587fead4dd4SJonathan Neuschäfer bool "Nuvoton WPCM450 Advanced Interrupt Controller" 58894bc9420SMarc Zyngier depends on ARCH_WPCM450 589fead4dd4SJonathan Neuschäfer help 590fead4dd4SJonathan Neuschäfer Support for the interrupt controller in the Nuvoton WPCM450 BMC SoC. 591fead4dd4SJonathan Neuschäfer 592529ea368SThomas Bogendoerferconfig IRQ_IDT3243X 593529ea368SThomas Bogendoerfer bool 594529ea368SThomas Bogendoerfer select GENERIC_IRQ_CHIP 595529ea368SThomas Bogendoerfer select IRQ_DOMAIN 596529ea368SThomas Bogendoerfer 59776cde263SHector Martinconfig APPLE_AIC 59876cde263SHector Martin bool "Apple Interrupt Controller (AIC)" 59976cde263SHector Martin depends on ARM64 6005b44955dSGeert Uytterhoeven depends on ARCH_APPLE || COMPILE_TEST 60176cde263SHector Martin help 60276cde263SHector Martin Support for the Apple Interrupt Controller found on Apple Silicon SoCs, 60376cde263SHector Martin such as the M1. 60476cde263SHector Martin 605*00fa3461SClaudiu Bezneaconfig MCHP_EIC 606*00fa3461SClaudiu Beznea bool "Microchip External Interrupt Controller" 607*00fa3461SClaudiu Beznea depends on ARCH_AT91 || COMPILE_TEST 608*00fa3461SClaudiu Beznea select IRQ_DOMAIN 609*00fa3461SClaudiu Beznea select IRQ_DOMAIN_HIERARCHY 610*00fa3461SClaudiu Beznea help 611*00fa3461SClaudiu Beznea Support for Microchip External Interrupt Controller. 612*00fa3461SClaudiu Beznea 61301493855SJonathan Neuschäferendmenu 614