1 /* 2 * IOMMU API for SMMU in Tegra30 3 * 4 * Copyright (c) 2011-2013, NVIDIA CORPORATION. All rights reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program; if not, write to the Free Software Foundation, Inc., 17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 */ 19 20 #define pr_fmt(fmt) "%s(): " fmt, __func__ 21 22 #include <linux/err.h> 23 #include <linux/module.h> 24 #include <linux/platform_device.h> 25 #include <linux/spinlock.h> 26 #include <linux/slab.h> 27 #include <linux/vmalloc.h> 28 #include <linux/mm.h> 29 #include <linux/pagemap.h> 30 #include <linux/device.h> 31 #include <linux/sched.h> 32 #include <linux/iommu.h> 33 #include <linux/io.h> 34 #include <linux/of.h> 35 #include <linux/of_iommu.h> 36 #include <linux/debugfs.h> 37 #include <linux/seq_file.h> 38 39 #include <soc/tegra/ahb.h> 40 41 #include <asm/page.h> 42 #include <asm/cacheflush.h> 43 44 enum smmu_hwgrp { 45 HWGRP_AFI, 46 HWGRP_AVPC, 47 HWGRP_DC, 48 HWGRP_DCB, 49 HWGRP_EPP, 50 HWGRP_G2, 51 HWGRP_HC, 52 HWGRP_HDA, 53 HWGRP_ISP, 54 HWGRP_MPE, 55 HWGRP_NV, 56 HWGRP_NV2, 57 HWGRP_PPCS, 58 HWGRP_SATA, 59 HWGRP_VDE, 60 HWGRP_VI, 61 62 HWGRP_COUNT, 63 64 HWGRP_END = ~0, 65 }; 66 67 #define HWG_AFI (1 << HWGRP_AFI) 68 #define HWG_AVPC (1 << HWGRP_AVPC) 69 #define HWG_DC (1 << HWGRP_DC) 70 #define HWG_DCB (1 << HWGRP_DCB) 71 #define HWG_EPP (1 << HWGRP_EPP) 72 #define HWG_G2 (1 << HWGRP_G2) 73 #define HWG_HC (1 << HWGRP_HC) 74 #define HWG_HDA (1 << HWGRP_HDA) 75 #define HWG_ISP (1 << HWGRP_ISP) 76 #define HWG_MPE (1 << HWGRP_MPE) 77 #define HWG_NV (1 << HWGRP_NV) 78 #define HWG_NV2 (1 << HWGRP_NV2) 79 #define HWG_PPCS (1 << HWGRP_PPCS) 80 #define HWG_SATA (1 << HWGRP_SATA) 81 #define HWG_VDE (1 << HWGRP_VDE) 82 #define HWG_VI (1 << HWGRP_VI) 83 84 /* bitmap of the page sizes currently supported */ 85 #define SMMU_IOMMU_PGSIZES (SZ_4K) 86 87 #define SMMU_CONFIG 0x10 88 #define SMMU_CONFIG_DISABLE 0 89 #define SMMU_CONFIG_ENABLE 1 90 91 /* REVISIT: To support multiple MCs */ 92 enum { 93 _MC = 0, 94 }; 95 96 enum { 97 _TLB = 0, 98 _PTC, 99 }; 100 101 #define SMMU_CACHE_CONFIG_BASE 0x14 102 #define __SMMU_CACHE_CONFIG(mc, cache) (SMMU_CACHE_CONFIG_BASE + 4 * cache) 103 #define SMMU_CACHE_CONFIG(cache) __SMMU_CACHE_CONFIG(_MC, cache) 104 105 #define SMMU_CACHE_CONFIG_STATS_SHIFT 31 106 #define SMMU_CACHE_CONFIG_STATS_ENABLE (1 << SMMU_CACHE_CONFIG_STATS_SHIFT) 107 #define SMMU_CACHE_CONFIG_STATS_TEST_SHIFT 30 108 #define SMMU_CACHE_CONFIG_STATS_TEST (1 << SMMU_CACHE_CONFIG_STATS_TEST_SHIFT) 109 110 #define SMMU_TLB_CONFIG_HIT_UNDER_MISS__ENABLE (1 << 29) 111 #define SMMU_TLB_CONFIG_ACTIVE_LINES__VALUE 0x10 112 #define SMMU_TLB_CONFIG_RESET_VAL 0x20000010 113 114 #define SMMU_PTC_CONFIG_CACHE__ENABLE (1 << 29) 115 #define SMMU_PTC_CONFIG_INDEX_MAP__PATTERN 0x3f 116 #define SMMU_PTC_CONFIG_RESET_VAL 0x2000003f 117 118 #define SMMU_PTB_ASID 0x1c 119 #define SMMU_PTB_ASID_CURRENT_SHIFT 0 120 121 #define SMMU_PTB_DATA 0x20 122 #define SMMU_PTB_DATA_RESET_VAL 0 123 #define SMMU_PTB_DATA_ASID_NONSECURE_SHIFT 29 124 #define SMMU_PTB_DATA_ASID_WRITABLE_SHIFT 30 125 #define SMMU_PTB_DATA_ASID_READABLE_SHIFT 31 126 127 #define SMMU_TLB_FLUSH 0x30 128 #define SMMU_TLB_FLUSH_VA_MATCH_ALL 0 129 #define SMMU_TLB_FLUSH_VA_MATCH_SECTION 2 130 #define SMMU_TLB_FLUSH_VA_MATCH_GROUP 3 131 #define SMMU_TLB_FLUSH_ASID_SHIFT 29 132 #define SMMU_TLB_FLUSH_ASID_MATCH_DISABLE 0 133 #define SMMU_TLB_FLUSH_ASID_MATCH_ENABLE 1 134 #define SMMU_TLB_FLUSH_ASID_MATCH_SHIFT 31 135 136 #define SMMU_PTC_FLUSH 0x34 137 #define SMMU_PTC_FLUSH_TYPE_ALL 0 138 #define SMMU_PTC_FLUSH_TYPE_ADR 1 139 #define SMMU_PTC_FLUSH_ADR_SHIFT 4 140 141 #define SMMU_ASID_SECURITY 0x38 142 143 #define SMMU_STATS_CACHE_COUNT_BASE 0x1f0 144 145 #define SMMU_STATS_CACHE_COUNT(mc, cache, hitmiss) \ 146 (SMMU_STATS_CACHE_COUNT_BASE + 8 * cache + 4 * hitmiss) 147 148 #define SMMU_TRANSLATION_ENABLE_0 0x228 149 #define SMMU_TRANSLATION_ENABLE_1 0x22c 150 #define SMMU_TRANSLATION_ENABLE_2 0x230 151 152 #define SMMU_AFI_ASID 0x238 /* PCIE */ 153 #define SMMU_AVPC_ASID 0x23c /* AVP */ 154 #define SMMU_DC_ASID 0x240 /* Display controller */ 155 #define SMMU_DCB_ASID 0x244 /* Display controller B */ 156 #define SMMU_EPP_ASID 0x248 /* Encoder pre-processor */ 157 #define SMMU_G2_ASID 0x24c /* 2D engine */ 158 #define SMMU_HC_ASID 0x250 /* Host1x */ 159 #define SMMU_HDA_ASID 0x254 /* High-def audio */ 160 #define SMMU_ISP_ASID 0x258 /* Image signal processor */ 161 #define SMMU_MPE_ASID 0x264 /* MPEG encoder */ 162 #define SMMU_NV_ASID 0x268 /* (3D) */ 163 #define SMMU_NV2_ASID 0x26c /* (3D) */ 164 #define SMMU_PPCS_ASID 0x270 /* AHB */ 165 #define SMMU_SATA_ASID 0x278 /* SATA */ 166 #define SMMU_VDE_ASID 0x27c /* Video decoder */ 167 #define SMMU_VI_ASID 0x280 /* Video input */ 168 169 #define SMMU_PDE_NEXT_SHIFT 28 170 171 #define SMMU_TLB_FLUSH_VA_SECTION__MASK 0xffc00000 172 #define SMMU_TLB_FLUSH_VA_SECTION__SHIFT 12 /* right shift */ 173 #define SMMU_TLB_FLUSH_VA_GROUP__MASK 0xffffc000 174 #define SMMU_TLB_FLUSH_VA_GROUP__SHIFT 12 /* right shift */ 175 #define SMMU_TLB_FLUSH_VA(iova, which) \ 176 ((((iova) & SMMU_TLB_FLUSH_VA_##which##__MASK) >> \ 177 SMMU_TLB_FLUSH_VA_##which##__SHIFT) | \ 178 SMMU_TLB_FLUSH_VA_MATCH_##which) 179 #define SMMU_PTB_ASID_CUR(n) \ 180 ((n) << SMMU_PTB_ASID_CURRENT_SHIFT) 181 #define SMMU_TLB_FLUSH_ASID_MATCH_disable \ 182 (SMMU_TLB_FLUSH_ASID_MATCH_DISABLE << \ 183 SMMU_TLB_FLUSH_ASID_MATCH_SHIFT) 184 #define SMMU_TLB_FLUSH_ASID_MATCH__ENABLE \ 185 (SMMU_TLB_FLUSH_ASID_MATCH_ENABLE << \ 186 SMMU_TLB_FLUSH_ASID_MATCH_SHIFT) 187 188 #define SMMU_PAGE_SHIFT 12 189 #define SMMU_PAGE_SIZE (1 << SMMU_PAGE_SHIFT) 190 #define SMMU_PAGE_MASK ((1 << SMMU_PAGE_SHIFT) - 1) 191 192 #define SMMU_PDIR_COUNT 1024 193 #define SMMU_PDIR_SIZE (sizeof(unsigned long) * SMMU_PDIR_COUNT) 194 #define SMMU_PTBL_COUNT 1024 195 #define SMMU_PTBL_SIZE (sizeof(unsigned long) * SMMU_PTBL_COUNT) 196 #define SMMU_PDIR_SHIFT 12 197 #define SMMU_PDE_SHIFT 12 198 #define SMMU_PTE_SHIFT 12 199 #define SMMU_PFN_MASK 0x000fffff 200 201 #define SMMU_ADDR_TO_PFN(addr) ((addr) >> 12) 202 #define SMMU_ADDR_TO_PDN(addr) ((addr) >> 22) 203 #define SMMU_PDN_TO_ADDR(pdn) ((pdn) << 22) 204 205 #define _READABLE (1 << SMMU_PTB_DATA_ASID_READABLE_SHIFT) 206 #define _WRITABLE (1 << SMMU_PTB_DATA_ASID_WRITABLE_SHIFT) 207 #define _NONSECURE (1 << SMMU_PTB_DATA_ASID_NONSECURE_SHIFT) 208 #define _PDE_NEXT (1 << SMMU_PDE_NEXT_SHIFT) 209 #define _MASK_ATTR (_READABLE | _WRITABLE | _NONSECURE) 210 211 #define _PDIR_ATTR (_READABLE | _WRITABLE | _NONSECURE) 212 213 #define _PDE_ATTR (_READABLE | _WRITABLE | _NONSECURE) 214 #define _PDE_ATTR_N (_PDE_ATTR | _PDE_NEXT) 215 #define _PDE_VACANT(pdn) (((pdn) << 10) | _PDE_ATTR) 216 217 #define _PTE_ATTR (_READABLE | _WRITABLE | _NONSECURE) 218 #define _PTE_VACANT(addr) (((addr) >> SMMU_PAGE_SHIFT) | _PTE_ATTR) 219 220 #define SMMU_MK_PDIR(page, attr) \ 221 ((page_to_phys(page) >> SMMU_PDIR_SHIFT) | (attr)) 222 #define SMMU_MK_PDE(page, attr) \ 223 (unsigned long)((page_to_phys(page) >> SMMU_PDE_SHIFT) | (attr)) 224 #define SMMU_EX_PTBL_PAGE(pde) \ 225 pfn_to_page((unsigned long)(pde) & SMMU_PFN_MASK) 226 #define SMMU_PFN_TO_PTE(pfn, attr) (unsigned long)((pfn) | (attr)) 227 228 #define SMMU_ASID_ENABLE(asid) ((asid) | (1 << 31)) 229 #define SMMU_ASID_DISABLE 0 230 #define SMMU_ASID_ASID(n) ((n) & ~SMMU_ASID_ENABLE(0)) 231 232 #define NUM_SMMU_REG_BANKS 3 233 234 #define smmu_client_enable_hwgrp(c, m) smmu_client_set_hwgrp(c, m, 1) 235 #define smmu_client_disable_hwgrp(c) smmu_client_set_hwgrp(c, 0, 0) 236 #define __smmu_client_enable_hwgrp(c, m) __smmu_client_set_hwgrp(c, m, 1) 237 #define __smmu_client_disable_hwgrp(c) __smmu_client_set_hwgrp(c, 0, 0) 238 239 #define HWGRP_INIT(client) [HWGRP_##client] = SMMU_##client##_ASID 240 241 static const u32 smmu_hwgrp_asid_reg[] = { 242 HWGRP_INIT(AFI), 243 HWGRP_INIT(AVPC), 244 HWGRP_INIT(DC), 245 HWGRP_INIT(DCB), 246 HWGRP_INIT(EPP), 247 HWGRP_INIT(G2), 248 HWGRP_INIT(HC), 249 HWGRP_INIT(HDA), 250 HWGRP_INIT(ISP), 251 HWGRP_INIT(MPE), 252 HWGRP_INIT(NV), 253 HWGRP_INIT(NV2), 254 HWGRP_INIT(PPCS), 255 HWGRP_INIT(SATA), 256 HWGRP_INIT(VDE), 257 HWGRP_INIT(VI), 258 }; 259 #define HWGRP_ASID_REG(x) (smmu_hwgrp_asid_reg[x]) 260 261 /* 262 * Per client for address space 263 */ 264 struct smmu_client { 265 struct device *dev; 266 struct list_head list; 267 struct smmu_as *as; 268 u32 hwgrp; 269 }; 270 271 /* 272 * Per address space 273 */ 274 struct smmu_as { 275 struct smmu_device *smmu; /* back pointer to container */ 276 unsigned int asid; 277 spinlock_t lock; /* for pagetable */ 278 struct page *pdir_page; 279 unsigned long pdir_attr; 280 unsigned long pde_attr; 281 unsigned long pte_attr; 282 unsigned int *pte_count; 283 284 struct list_head client; 285 spinlock_t client_lock; /* for client list */ 286 }; 287 288 struct smmu_debugfs_info { 289 struct smmu_device *smmu; 290 int mc; 291 int cache; 292 }; 293 294 /* 295 * Per SMMU device - IOMMU device 296 */ 297 struct smmu_device { 298 void __iomem *regbase; /* register offset base */ 299 void __iomem **regs; /* register block start address array */ 300 void __iomem **rege; /* register block end address array */ 301 int nregs; /* number of register blocks */ 302 303 unsigned long iovmm_base; /* remappable base address */ 304 unsigned long page_count; /* total remappable size */ 305 spinlock_t lock; 306 char *name; 307 struct device *dev; 308 struct page *avp_vector_page; /* dummy page shared by all AS's */ 309 310 /* 311 * Register image savers for suspend/resume 312 */ 313 unsigned long translation_enable_0; 314 unsigned long translation_enable_1; 315 unsigned long translation_enable_2; 316 unsigned long asid_security; 317 318 struct dentry *debugfs_root; 319 struct smmu_debugfs_info *debugfs_info; 320 321 struct device_node *ahb; 322 323 int num_as; 324 struct smmu_as as[0]; /* Run-time allocated array */ 325 }; 326 327 static struct smmu_device *smmu_handle; /* unique for a system */ 328 329 /* 330 * SMMU register accessors 331 */ 332 static bool inline smmu_valid_reg(struct smmu_device *smmu, 333 void __iomem *addr) 334 { 335 int i; 336 337 for (i = 0; i < smmu->nregs; i++) { 338 if (addr < smmu->regs[i]) 339 break; 340 if (addr <= smmu->rege[i]) 341 return true; 342 } 343 344 return false; 345 } 346 347 static inline u32 smmu_read(struct smmu_device *smmu, size_t offs) 348 { 349 void __iomem *addr = smmu->regbase + offs; 350 351 BUG_ON(!smmu_valid_reg(smmu, addr)); 352 353 return readl(addr); 354 } 355 356 static inline void smmu_write(struct smmu_device *smmu, u32 val, size_t offs) 357 { 358 void __iomem *addr = smmu->regbase + offs; 359 360 BUG_ON(!smmu_valid_reg(smmu, addr)); 361 362 writel(val, addr); 363 } 364 365 #define VA_PAGE_TO_PA(va, page) \ 366 (page_to_phys(page) + ((unsigned long)(va) & ~PAGE_MASK)) 367 368 #define FLUSH_CPU_DCACHE(va, page, size) \ 369 do { \ 370 unsigned long _pa_ = VA_PAGE_TO_PA(va, page); \ 371 __cpuc_flush_dcache_area((void *)(va), (size_t)(size)); \ 372 outer_flush_range(_pa_, _pa_+(size_t)(size)); \ 373 } while (0) 374 375 /* 376 * Any interaction between any block on PPSB and a block on APB or AHB 377 * must have these read-back barriers to ensure the APB/AHB bus 378 * transaction is complete before initiating activity on the PPSB 379 * block. 380 */ 381 #define FLUSH_SMMU_REGS(smmu) smmu_read(smmu, SMMU_CONFIG) 382 383 #define smmu_client_hwgrp(c) (u32)((c)->dev->platform_data) 384 385 static int __smmu_client_set_hwgrp(struct smmu_client *c, 386 unsigned long map, int on) 387 { 388 int i; 389 struct smmu_as *as = c->as; 390 u32 val, offs, mask = SMMU_ASID_ENABLE(as->asid); 391 struct smmu_device *smmu = as->smmu; 392 393 WARN_ON(!on && map); 394 if (on && !map) 395 return -EINVAL; 396 if (!on) 397 map = smmu_client_hwgrp(c); 398 399 for_each_set_bit(i, &map, HWGRP_COUNT) { 400 offs = HWGRP_ASID_REG(i); 401 val = smmu_read(smmu, offs); 402 if (on) { 403 if (WARN_ON(val & mask)) 404 goto err_hw_busy; 405 val |= mask; 406 } else { 407 WARN_ON((val & mask) == mask); 408 val &= ~mask; 409 } 410 smmu_write(smmu, val, offs); 411 } 412 FLUSH_SMMU_REGS(smmu); 413 c->hwgrp = map; 414 return 0; 415 416 err_hw_busy: 417 for_each_set_bit(i, &map, HWGRP_COUNT) { 418 offs = HWGRP_ASID_REG(i); 419 val = smmu_read(smmu, offs); 420 val &= ~mask; 421 smmu_write(smmu, val, offs); 422 } 423 return -EBUSY; 424 } 425 426 static int smmu_client_set_hwgrp(struct smmu_client *c, u32 map, int on) 427 { 428 u32 val; 429 unsigned long flags; 430 struct smmu_as *as = c->as; 431 struct smmu_device *smmu = as->smmu; 432 433 spin_lock_irqsave(&smmu->lock, flags); 434 val = __smmu_client_set_hwgrp(c, map, on); 435 spin_unlock_irqrestore(&smmu->lock, flags); 436 return val; 437 } 438 439 /* 440 * Flush all TLB entries and all PTC entries 441 * Caller must lock smmu 442 */ 443 static void smmu_flush_regs(struct smmu_device *smmu, int enable) 444 { 445 u32 val; 446 447 smmu_write(smmu, SMMU_PTC_FLUSH_TYPE_ALL, SMMU_PTC_FLUSH); 448 FLUSH_SMMU_REGS(smmu); 449 val = SMMU_TLB_FLUSH_VA_MATCH_ALL | 450 SMMU_TLB_FLUSH_ASID_MATCH_disable; 451 smmu_write(smmu, val, SMMU_TLB_FLUSH); 452 453 if (enable) 454 smmu_write(smmu, SMMU_CONFIG_ENABLE, SMMU_CONFIG); 455 FLUSH_SMMU_REGS(smmu); 456 } 457 458 static int smmu_setup_regs(struct smmu_device *smmu) 459 { 460 int i; 461 u32 val; 462 463 for (i = 0; i < smmu->num_as; i++) { 464 struct smmu_as *as = &smmu->as[i]; 465 struct smmu_client *c; 466 467 smmu_write(smmu, SMMU_PTB_ASID_CUR(as->asid), SMMU_PTB_ASID); 468 val = as->pdir_page ? 469 SMMU_MK_PDIR(as->pdir_page, as->pdir_attr) : 470 SMMU_PTB_DATA_RESET_VAL; 471 smmu_write(smmu, val, SMMU_PTB_DATA); 472 473 list_for_each_entry(c, &as->client, list) 474 __smmu_client_set_hwgrp(c, c->hwgrp, 1); 475 } 476 477 smmu_write(smmu, smmu->translation_enable_0, SMMU_TRANSLATION_ENABLE_0); 478 smmu_write(smmu, smmu->translation_enable_1, SMMU_TRANSLATION_ENABLE_1); 479 smmu_write(smmu, smmu->translation_enable_2, SMMU_TRANSLATION_ENABLE_2); 480 smmu_write(smmu, smmu->asid_security, SMMU_ASID_SECURITY); 481 smmu_write(smmu, SMMU_TLB_CONFIG_RESET_VAL, SMMU_CACHE_CONFIG(_TLB)); 482 smmu_write(smmu, SMMU_PTC_CONFIG_RESET_VAL, SMMU_CACHE_CONFIG(_PTC)); 483 484 smmu_flush_regs(smmu, 1); 485 486 return tegra_ahb_enable_smmu(smmu->ahb); 487 } 488 489 static void flush_ptc_and_tlb(struct smmu_device *smmu, 490 struct smmu_as *as, dma_addr_t iova, 491 unsigned long *pte, struct page *page, int is_pde) 492 { 493 u32 val; 494 unsigned long tlb_flush_va = is_pde 495 ? SMMU_TLB_FLUSH_VA(iova, SECTION) 496 : SMMU_TLB_FLUSH_VA(iova, GROUP); 497 498 val = SMMU_PTC_FLUSH_TYPE_ADR | VA_PAGE_TO_PA(pte, page); 499 smmu_write(smmu, val, SMMU_PTC_FLUSH); 500 FLUSH_SMMU_REGS(smmu); 501 val = tlb_flush_va | 502 SMMU_TLB_FLUSH_ASID_MATCH__ENABLE | 503 (as->asid << SMMU_TLB_FLUSH_ASID_SHIFT); 504 smmu_write(smmu, val, SMMU_TLB_FLUSH); 505 FLUSH_SMMU_REGS(smmu); 506 } 507 508 static void free_ptbl(struct smmu_as *as, dma_addr_t iova) 509 { 510 unsigned long pdn = SMMU_ADDR_TO_PDN(iova); 511 unsigned long *pdir = (unsigned long *)page_address(as->pdir_page); 512 513 if (pdir[pdn] != _PDE_VACANT(pdn)) { 514 dev_dbg(as->smmu->dev, "pdn: %lx\n", pdn); 515 516 ClearPageReserved(SMMU_EX_PTBL_PAGE(pdir[pdn])); 517 __free_page(SMMU_EX_PTBL_PAGE(pdir[pdn])); 518 pdir[pdn] = _PDE_VACANT(pdn); 519 FLUSH_CPU_DCACHE(&pdir[pdn], as->pdir_page, sizeof pdir[pdn]); 520 flush_ptc_and_tlb(as->smmu, as, iova, &pdir[pdn], 521 as->pdir_page, 1); 522 } 523 } 524 525 static void free_pdir(struct smmu_as *as) 526 { 527 unsigned addr; 528 int count; 529 struct device *dev = as->smmu->dev; 530 531 if (!as->pdir_page) 532 return; 533 534 addr = as->smmu->iovmm_base; 535 count = as->smmu->page_count; 536 while (count-- > 0) { 537 free_ptbl(as, addr); 538 addr += SMMU_PAGE_SIZE * SMMU_PTBL_COUNT; 539 } 540 ClearPageReserved(as->pdir_page); 541 __free_page(as->pdir_page); 542 as->pdir_page = NULL; 543 devm_kfree(dev, as->pte_count); 544 as->pte_count = NULL; 545 } 546 547 /* 548 * Maps PTBL for given iova and returns the PTE address 549 * Caller must unmap the mapped PTBL returned in *ptbl_page_p 550 */ 551 static unsigned long *locate_pte(struct smmu_as *as, 552 dma_addr_t iova, bool allocate, 553 struct page **ptbl_page_p, 554 unsigned int **count) 555 { 556 unsigned long ptn = SMMU_ADDR_TO_PFN(iova); 557 unsigned long pdn = SMMU_ADDR_TO_PDN(iova); 558 unsigned long *pdir = page_address(as->pdir_page); 559 unsigned long *ptbl; 560 561 if (pdir[pdn] != _PDE_VACANT(pdn)) { 562 /* Mapped entry table already exists */ 563 *ptbl_page_p = SMMU_EX_PTBL_PAGE(pdir[pdn]); 564 ptbl = page_address(*ptbl_page_p); 565 } else if (!allocate) { 566 return NULL; 567 } else { 568 int pn; 569 unsigned long addr = SMMU_PDN_TO_ADDR(pdn); 570 571 /* Vacant - allocate a new page table */ 572 dev_dbg(as->smmu->dev, "New PTBL pdn: %lx\n", pdn); 573 574 *ptbl_page_p = alloc_page(GFP_ATOMIC); 575 if (!*ptbl_page_p) { 576 dev_err(as->smmu->dev, 577 "failed to allocate smmu_device page table\n"); 578 return NULL; 579 } 580 SetPageReserved(*ptbl_page_p); 581 ptbl = (unsigned long *)page_address(*ptbl_page_p); 582 for (pn = 0; pn < SMMU_PTBL_COUNT; 583 pn++, addr += SMMU_PAGE_SIZE) { 584 ptbl[pn] = _PTE_VACANT(addr); 585 } 586 FLUSH_CPU_DCACHE(ptbl, *ptbl_page_p, SMMU_PTBL_SIZE); 587 pdir[pdn] = SMMU_MK_PDE(*ptbl_page_p, 588 as->pde_attr | _PDE_NEXT); 589 FLUSH_CPU_DCACHE(&pdir[pdn], as->pdir_page, sizeof pdir[pdn]); 590 flush_ptc_and_tlb(as->smmu, as, iova, &pdir[pdn], 591 as->pdir_page, 1); 592 } 593 *count = &as->pte_count[pdn]; 594 595 return &ptbl[ptn % SMMU_PTBL_COUNT]; 596 } 597 598 #ifdef CONFIG_SMMU_SIG_DEBUG 599 static void put_signature(struct smmu_as *as, 600 dma_addr_t iova, unsigned long pfn) 601 { 602 struct page *page; 603 unsigned long *vaddr; 604 605 page = pfn_to_page(pfn); 606 vaddr = page_address(page); 607 if (!vaddr) 608 return; 609 610 vaddr[0] = iova; 611 vaddr[1] = pfn << PAGE_SHIFT; 612 FLUSH_CPU_DCACHE(vaddr, page, sizeof(vaddr[0]) * 2); 613 } 614 #else 615 static inline void put_signature(struct smmu_as *as, 616 unsigned long addr, unsigned long pfn) 617 { 618 } 619 #endif 620 621 /* 622 * Caller must not hold as->lock 623 */ 624 static int alloc_pdir(struct smmu_as *as) 625 { 626 unsigned long *pdir, flags; 627 int pdn, err = 0; 628 u32 val; 629 struct smmu_device *smmu = as->smmu; 630 struct page *page; 631 unsigned int *cnt; 632 633 /* 634 * do the allocation, then grab as->lock 635 */ 636 cnt = devm_kzalloc(smmu->dev, 637 sizeof(cnt[0]) * SMMU_PDIR_COUNT, 638 GFP_KERNEL); 639 page = alloc_page(GFP_KERNEL | __GFP_DMA); 640 641 spin_lock_irqsave(&as->lock, flags); 642 643 if (as->pdir_page) { 644 /* We raced, free the redundant */ 645 err = -EAGAIN; 646 goto err_out; 647 } 648 649 if (!page || !cnt) { 650 dev_err(smmu->dev, "failed to allocate at %s\n", __func__); 651 err = -ENOMEM; 652 goto err_out; 653 } 654 655 as->pdir_page = page; 656 as->pte_count = cnt; 657 658 SetPageReserved(as->pdir_page); 659 pdir = page_address(as->pdir_page); 660 661 for (pdn = 0; pdn < SMMU_PDIR_COUNT; pdn++) 662 pdir[pdn] = _PDE_VACANT(pdn); 663 FLUSH_CPU_DCACHE(pdir, as->pdir_page, SMMU_PDIR_SIZE); 664 val = SMMU_PTC_FLUSH_TYPE_ADR | VA_PAGE_TO_PA(pdir, as->pdir_page); 665 smmu_write(smmu, val, SMMU_PTC_FLUSH); 666 FLUSH_SMMU_REGS(as->smmu); 667 val = SMMU_TLB_FLUSH_VA_MATCH_ALL | 668 SMMU_TLB_FLUSH_ASID_MATCH__ENABLE | 669 (as->asid << SMMU_TLB_FLUSH_ASID_SHIFT); 670 smmu_write(smmu, val, SMMU_TLB_FLUSH); 671 FLUSH_SMMU_REGS(as->smmu); 672 673 spin_unlock_irqrestore(&as->lock, flags); 674 675 return 0; 676 677 err_out: 678 spin_unlock_irqrestore(&as->lock, flags); 679 680 devm_kfree(smmu->dev, cnt); 681 if (page) 682 __free_page(page); 683 return err; 684 } 685 686 static void __smmu_iommu_unmap(struct smmu_as *as, dma_addr_t iova) 687 { 688 unsigned long *pte; 689 struct page *page; 690 unsigned int *count; 691 692 pte = locate_pte(as, iova, false, &page, &count); 693 if (WARN_ON(!pte)) 694 return; 695 696 if (WARN_ON(*pte == _PTE_VACANT(iova))) 697 return; 698 699 *pte = _PTE_VACANT(iova); 700 FLUSH_CPU_DCACHE(pte, page, sizeof(*pte)); 701 flush_ptc_and_tlb(as->smmu, as, iova, pte, page, 0); 702 if (!--(*count)) 703 free_ptbl(as, iova); 704 } 705 706 static void __smmu_iommu_map_pfn(struct smmu_as *as, dma_addr_t iova, 707 unsigned long pfn) 708 { 709 struct smmu_device *smmu = as->smmu; 710 unsigned long *pte; 711 unsigned int *count; 712 struct page *page; 713 714 pte = locate_pte(as, iova, true, &page, &count); 715 if (WARN_ON(!pte)) 716 return; 717 718 if (*pte == _PTE_VACANT(iova)) 719 (*count)++; 720 *pte = SMMU_PFN_TO_PTE(pfn, as->pte_attr); 721 if (unlikely((*pte == _PTE_VACANT(iova)))) 722 (*count)--; 723 FLUSH_CPU_DCACHE(pte, page, sizeof(*pte)); 724 flush_ptc_and_tlb(smmu, as, iova, pte, page, 0); 725 put_signature(as, iova, pfn); 726 } 727 728 static int smmu_iommu_map(struct iommu_domain *domain, unsigned long iova, 729 phys_addr_t pa, size_t bytes, int prot) 730 { 731 struct smmu_as *as = domain->priv; 732 unsigned long pfn = __phys_to_pfn(pa); 733 unsigned long flags; 734 735 dev_dbg(as->smmu->dev, "[%d] %08lx:%pa\n", as->asid, iova, &pa); 736 737 if (!pfn_valid(pfn)) 738 return -ENOMEM; 739 740 spin_lock_irqsave(&as->lock, flags); 741 __smmu_iommu_map_pfn(as, iova, pfn); 742 spin_unlock_irqrestore(&as->lock, flags); 743 return 0; 744 } 745 746 static size_t smmu_iommu_unmap(struct iommu_domain *domain, unsigned long iova, 747 size_t bytes) 748 { 749 struct smmu_as *as = domain->priv; 750 unsigned long flags; 751 752 dev_dbg(as->smmu->dev, "[%d] %08lx\n", as->asid, iova); 753 754 spin_lock_irqsave(&as->lock, flags); 755 __smmu_iommu_unmap(as, iova); 756 spin_unlock_irqrestore(&as->lock, flags); 757 return SMMU_PAGE_SIZE; 758 } 759 760 static phys_addr_t smmu_iommu_iova_to_phys(struct iommu_domain *domain, 761 dma_addr_t iova) 762 { 763 struct smmu_as *as = domain->priv; 764 unsigned long *pte; 765 unsigned int *count; 766 struct page *page; 767 unsigned long pfn; 768 unsigned long flags; 769 770 spin_lock_irqsave(&as->lock, flags); 771 772 pte = locate_pte(as, iova, true, &page, &count); 773 pfn = *pte & SMMU_PFN_MASK; 774 WARN_ON(!pfn_valid(pfn)); 775 dev_dbg(as->smmu->dev, 776 "iova:%08llx pfn:%08lx asid:%d\n", (unsigned long long)iova, 777 pfn, as->asid); 778 779 spin_unlock_irqrestore(&as->lock, flags); 780 return PFN_PHYS(pfn); 781 } 782 783 static int smmu_iommu_domain_has_cap(struct iommu_domain *domain, 784 unsigned long cap) 785 { 786 return 0; 787 } 788 789 static int smmu_iommu_attach_dev(struct iommu_domain *domain, 790 struct device *dev) 791 { 792 struct smmu_as *as = domain->priv; 793 struct smmu_device *smmu = as->smmu; 794 struct smmu_client *client, *c; 795 u32 map; 796 int err; 797 798 client = devm_kzalloc(smmu->dev, sizeof(*c), GFP_KERNEL); 799 if (!client) 800 return -ENOMEM; 801 client->dev = dev; 802 client->as = as; 803 map = (unsigned long)dev->platform_data; 804 if (!map) 805 return -EINVAL; 806 807 err = smmu_client_enable_hwgrp(client, map); 808 if (err) 809 goto err_hwgrp; 810 811 spin_lock(&as->client_lock); 812 list_for_each_entry(c, &as->client, list) { 813 if (c->dev == dev) { 814 dev_err(smmu->dev, 815 "%s is already attached\n", dev_name(c->dev)); 816 err = -EINVAL; 817 goto err_client; 818 } 819 } 820 list_add(&client->list, &as->client); 821 spin_unlock(&as->client_lock); 822 823 /* 824 * Reserve "page zero" for AVP vectors using a common dummy 825 * page. 826 */ 827 if (map & HWG_AVPC) { 828 struct page *page; 829 830 page = as->smmu->avp_vector_page; 831 __smmu_iommu_map_pfn(as, 0, page_to_pfn(page)); 832 833 pr_info("Reserve \"page zero\" for AVP vectors using a common dummy\n"); 834 } 835 836 dev_dbg(smmu->dev, "%s is attached\n", dev_name(dev)); 837 return 0; 838 839 err_client: 840 smmu_client_disable_hwgrp(client); 841 spin_unlock(&as->client_lock); 842 err_hwgrp: 843 devm_kfree(smmu->dev, client); 844 return err; 845 } 846 847 static void smmu_iommu_detach_dev(struct iommu_domain *domain, 848 struct device *dev) 849 { 850 struct smmu_as *as = domain->priv; 851 struct smmu_device *smmu = as->smmu; 852 struct smmu_client *c; 853 854 spin_lock(&as->client_lock); 855 856 list_for_each_entry(c, &as->client, list) { 857 if (c->dev == dev) { 858 smmu_client_disable_hwgrp(c); 859 list_del(&c->list); 860 devm_kfree(smmu->dev, c); 861 c->as = NULL; 862 dev_dbg(smmu->dev, 863 "%s is detached\n", dev_name(c->dev)); 864 goto out; 865 } 866 } 867 dev_err(smmu->dev, "Couldn't find %s\n", dev_name(dev)); 868 out: 869 spin_unlock(&as->client_lock); 870 } 871 872 static int smmu_iommu_domain_init(struct iommu_domain *domain) 873 { 874 int i, err = -EAGAIN; 875 unsigned long flags; 876 struct smmu_as *as; 877 struct smmu_device *smmu = smmu_handle; 878 879 /* Look for a free AS with lock held */ 880 for (i = 0; i < smmu->num_as; i++) { 881 as = &smmu->as[i]; 882 883 if (as->pdir_page) 884 continue; 885 886 err = alloc_pdir(as); 887 if (!err) 888 goto found; 889 890 if (err != -EAGAIN) 891 break; 892 } 893 if (i == smmu->num_as) 894 dev_err(smmu->dev, "no free AS\n"); 895 return err; 896 897 found: 898 spin_lock_irqsave(&smmu->lock, flags); 899 900 /* Update PDIR register */ 901 smmu_write(smmu, SMMU_PTB_ASID_CUR(as->asid), SMMU_PTB_ASID); 902 smmu_write(smmu, 903 SMMU_MK_PDIR(as->pdir_page, as->pdir_attr), SMMU_PTB_DATA); 904 FLUSH_SMMU_REGS(smmu); 905 906 spin_unlock_irqrestore(&smmu->lock, flags); 907 908 domain->priv = as; 909 910 domain->geometry.aperture_start = smmu->iovmm_base; 911 domain->geometry.aperture_end = smmu->iovmm_base + 912 smmu->page_count * SMMU_PAGE_SIZE - 1; 913 domain->geometry.force_aperture = true; 914 915 dev_dbg(smmu->dev, "smmu_as@%p\n", as); 916 917 return 0; 918 } 919 920 static void smmu_iommu_domain_destroy(struct iommu_domain *domain) 921 { 922 struct smmu_as *as = domain->priv; 923 struct smmu_device *smmu = as->smmu; 924 unsigned long flags; 925 926 spin_lock_irqsave(&as->lock, flags); 927 928 if (as->pdir_page) { 929 spin_lock(&smmu->lock); 930 smmu_write(smmu, SMMU_PTB_ASID_CUR(as->asid), SMMU_PTB_ASID); 931 smmu_write(smmu, SMMU_PTB_DATA_RESET_VAL, SMMU_PTB_DATA); 932 FLUSH_SMMU_REGS(smmu); 933 spin_unlock(&smmu->lock); 934 935 free_pdir(as); 936 } 937 938 if (!list_empty(&as->client)) { 939 struct smmu_client *c; 940 941 list_for_each_entry(c, &as->client, list) 942 smmu_iommu_detach_dev(domain, c->dev); 943 } 944 945 spin_unlock_irqrestore(&as->lock, flags); 946 947 domain->priv = NULL; 948 dev_dbg(smmu->dev, "smmu_as@%p\n", as); 949 } 950 951 static const struct iommu_ops smmu_iommu_ops = { 952 .domain_init = smmu_iommu_domain_init, 953 .domain_destroy = smmu_iommu_domain_destroy, 954 .attach_dev = smmu_iommu_attach_dev, 955 .detach_dev = smmu_iommu_detach_dev, 956 .map = smmu_iommu_map, 957 .unmap = smmu_iommu_unmap, 958 .iova_to_phys = smmu_iommu_iova_to_phys, 959 .domain_has_cap = smmu_iommu_domain_has_cap, 960 .pgsize_bitmap = SMMU_IOMMU_PGSIZES, 961 }; 962 963 /* Should be in the order of enum */ 964 static const char * const smmu_debugfs_mc[] = { "mc", }; 965 static const char * const smmu_debugfs_cache[] = { "tlb", "ptc", }; 966 967 static ssize_t smmu_debugfs_stats_write(struct file *file, 968 const char __user *buffer, 969 size_t count, loff_t *pos) 970 { 971 struct smmu_debugfs_info *info; 972 struct smmu_device *smmu; 973 int i; 974 enum { 975 _OFF = 0, 976 _ON, 977 _RESET, 978 }; 979 const char * const command[] = { 980 [_OFF] = "off", 981 [_ON] = "on", 982 [_RESET] = "reset", 983 }; 984 char str[] = "reset"; 985 u32 val; 986 size_t offs; 987 988 count = min_t(size_t, count, sizeof(str)); 989 if (copy_from_user(str, buffer, count)) 990 return -EINVAL; 991 992 for (i = 0; i < ARRAY_SIZE(command); i++) 993 if (strncmp(str, command[i], 994 strlen(command[i])) == 0) 995 break; 996 997 if (i == ARRAY_SIZE(command)) 998 return -EINVAL; 999 1000 info = file_inode(file)->i_private; 1001 smmu = info->smmu; 1002 1003 offs = SMMU_CACHE_CONFIG(info->cache); 1004 val = smmu_read(smmu, offs); 1005 switch (i) { 1006 case _OFF: 1007 val &= ~SMMU_CACHE_CONFIG_STATS_ENABLE; 1008 val &= ~SMMU_CACHE_CONFIG_STATS_TEST; 1009 smmu_write(smmu, val, offs); 1010 break; 1011 case _ON: 1012 val |= SMMU_CACHE_CONFIG_STATS_ENABLE; 1013 val &= ~SMMU_CACHE_CONFIG_STATS_TEST; 1014 smmu_write(smmu, val, offs); 1015 break; 1016 case _RESET: 1017 val |= SMMU_CACHE_CONFIG_STATS_TEST; 1018 smmu_write(smmu, val, offs); 1019 val &= ~SMMU_CACHE_CONFIG_STATS_TEST; 1020 smmu_write(smmu, val, offs); 1021 break; 1022 default: 1023 BUG(); 1024 break; 1025 } 1026 1027 dev_dbg(smmu->dev, "%s() %08x, %08x @%08x\n", __func__, 1028 val, smmu_read(smmu, offs), offs); 1029 1030 return count; 1031 } 1032 1033 static int smmu_debugfs_stats_show(struct seq_file *s, void *v) 1034 { 1035 struct smmu_debugfs_info *info = s->private; 1036 struct smmu_device *smmu = info->smmu; 1037 int i; 1038 const char * const stats[] = { "hit", "miss", }; 1039 1040 1041 for (i = 0; i < ARRAY_SIZE(stats); i++) { 1042 u32 val; 1043 size_t offs; 1044 1045 offs = SMMU_STATS_CACHE_COUNT(info->mc, info->cache, i); 1046 val = smmu_read(smmu, offs); 1047 seq_printf(s, "%s:%08x ", stats[i], val); 1048 1049 dev_dbg(smmu->dev, "%s() %s %08x @%08x\n", __func__, 1050 stats[i], val, offs); 1051 } 1052 seq_printf(s, "\n"); 1053 return 0; 1054 } 1055 1056 static int smmu_debugfs_stats_open(struct inode *inode, struct file *file) 1057 { 1058 return single_open(file, smmu_debugfs_stats_show, inode->i_private); 1059 } 1060 1061 static const struct file_operations smmu_debugfs_stats_fops = { 1062 .open = smmu_debugfs_stats_open, 1063 .read = seq_read, 1064 .llseek = seq_lseek, 1065 .release = single_release, 1066 .write = smmu_debugfs_stats_write, 1067 }; 1068 1069 static void smmu_debugfs_delete(struct smmu_device *smmu) 1070 { 1071 debugfs_remove_recursive(smmu->debugfs_root); 1072 kfree(smmu->debugfs_info); 1073 } 1074 1075 static void smmu_debugfs_create(struct smmu_device *smmu) 1076 { 1077 int i; 1078 size_t bytes; 1079 struct dentry *root; 1080 1081 bytes = ARRAY_SIZE(smmu_debugfs_mc) * ARRAY_SIZE(smmu_debugfs_cache) * 1082 sizeof(*smmu->debugfs_info); 1083 smmu->debugfs_info = kmalloc(bytes, GFP_KERNEL); 1084 if (!smmu->debugfs_info) 1085 return; 1086 1087 root = debugfs_create_dir(dev_name(smmu->dev), NULL); 1088 if (!root) 1089 goto err_out; 1090 smmu->debugfs_root = root; 1091 1092 for (i = 0; i < ARRAY_SIZE(smmu_debugfs_mc); i++) { 1093 int j; 1094 struct dentry *mc; 1095 1096 mc = debugfs_create_dir(smmu_debugfs_mc[i], root); 1097 if (!mc) 1098 goto err_out; 1099 1100 for (j = 0; j < ARRAY_SIZE(smmu_debugfs_cache); j++) { 1101 struct dentry *cache; 1102 struct smmu_debugfs_info *info; 1103 1104 info = smmu->debugfs_info; 1105 info += i * ARRAY_SIZE(smmu_debugfs_mc) + j; 1106 info->smmu = smmu; 1107 info->mc = i; 1108 info->cache = j; 1109 1110 cache = debugfs_create_file(smmu_debugfs_cache[j], 1111 S_IWUGO | S_IRUGO, mc, 1112 (void *)info, 1113 &smmu_debugfs_stats_fops); 1114 if (!cache) 1115 goto err_out; 1116 } 1117 } 1118 1119 return; 1120 1121 err_out: 1122 smmu_debugfs_delete(smmu); 1123 } 1124 1125 static int tegra_smmu_suspend(struct device *dev) 1126 { 1127 struct smmu_device *smmu = dev_get_drvdata(dev); 1128 1129 smmu->translation_enable_0 = smmu_read(smmu, SMMU_TRANSLATION_ENABLE_0); 1130 smmu->translation_enable_1 = smmu_read(smmu, SMMU_TRANSLATION_ENABLE_1); 1131 smmu->translation_enable_2 = smmu_read(smmu, SMMU_TRANSLATION_ENABLE_2); 1132 smmu->asid_security = smmu_read(smmu, SMMU_ASID_SECURITY); 1133 return 0; 1134 } 1135 1136 static int tegra_smmu_resume(struct device *dev) 1137 { 1138 struct smmu_device *smmu = dev_get_drvdata(dev); 1139 unsigned long flags; 1140 int err; 1141 1142 spin_lock_irqsave(&smmu->lock, flags); 1143 err = smmu_setup_regs(smmu); 1144 spin_unlock_irqrestore(&smmu->lock, flags); 1145 return err; 1146 } 1147 1148 static int tegra_smmu_probe(struct platform_device *pdev) 1149 { 1150 struct smmu_device *smmu; 1151 struct device *dev = &pdev->dev; 1152 int i, asids, err = 0; 1153 dma_addr_t uninitialized_var(base); 1154 size_t bytes, uninitialized_var(size); 1155 1156 if (smmu_handle) 1157 return -EIO; 1158 1159 BUILD_BUG_ON(PAGE_SHIFT != SMMU_PAGE_SHIFT); 1160 1161 if (of_property_read_u32(dev->of_node, "nvidia,#asids", &asids)) 1162 return -ENODEV; 1163 1164 bytes = sizeof(*smmu) + asids * sizeof(*smmu->as); 1165 smmu = devm_kzalloc(dev, bytes, GFP_KERNEL); 1166 if (!smmu) { 1167 dev_err(dev, "failed to allocate smmu_device\n"); 1168 return -ENOMEM; 1169 } 1170 1171 smmu->nregs = pdev->num_resources; 1172 smmu->regs = devm_kzalloc(dev, 2 * smmu->nregs * sizeof(*smmu->regs), 1173 GFP_KERNEL); 1174 smmu->rege = smmu->regs + smmu->nregs; 1175 if (!smmu->regs) 1176 return -ENOMEM; 1177 for (i = 0; i < smmu->nregs; i++) { 1178 struct resource *res; 1179 1180 res = platform_get_resource(pdev, IORESOURCE_MEM, i); 1181 smmu->regs[i] = devm_ioremap_resource(&pdev->dev, res); 1182 if (IS_ERR(smmu->regs[i])) 1183 return PTR_ERR(smmu->regs[i]); 1184 smmu->rege[i] = smmu->regs[i] + resource_size(res) - 1; 1185 } 1186 /* Same as "mc" 1st regiter block start address */ 1187 smmu->regbase = (void __iomem *)((u32)smmu->regs[0] & PAGE_MASK); 1188 1189 err = of_get_dma_window(dev->of_node, NULL, 0, NULL, &base, &size); 1190 if (err) 1191 return -ENODEV; 1192 1193 if (size & SMMU_PAGE_MASK) 1194 return -EINVAL; 1195 1196 size >>= SMMU_PAGE_SHIFT; 1197 if (!size) 1198 return -EINVAL; 1199 1200 smmu->ahb = of_parse_phandle(dev->of_node, "nvidia,ahb", 0); 1201 if (!smmu->ahb) 1202 return -ENODEV; 1203 1204 smmu->dev = dev; 1205 smmu->num_as = asids; 1206 smmu->iovmm_base = base; 1207 smmu->page_count = size; 1208 1209 smmu->translation_enable_0 = ~0; 1210 smmu->translation_enable_1 = ~0; 1211 smmu->translation_enable_2 = ~0; 1212 smmu->asid_security = 0; 1213 1214 for (i = 0; i < smmu->num_as; i++) { 1215 struct smmu_as *as = &smmu->as[i]; 1216 1217 as->smmu = smmu; 1218 as->asid = i; 1219 as->pdir_attr = _PDIR_ATTR; 1220 as->pde_attr = _PDE_ATTR; 1221 as->pte_attr = _PTE_ATTR; 1222 1223 spin_lock_init(&as->lock); 1224 spin_lock_init(&as->client_lock); 1225 INIT_LIST_HEAD(&as->client); 1226 } 1227 spin_lock_init(&smmu->lock); 1228 err = smmu_setup_regs(smmu); 1229 if (err) 1230 return err; 1231 platform_set_drvdata(pdev, smmu); 1232 1233 smmu->avp_vector_page = alloc_page(GFP_KERNEL); 1234 if (!smmu->avp_vector_page) 1235 return -ENOMEM; 1236 1237 smmu_debugfs_create(smmu); 1238 smmu_handle = smmu; 1239 bus_set_iommu(&platform_bus_type, &smmu_iommu_ops); 1240 return 0; 1241 } 1242 1243 static int tegra_smmu_remove(struct platform_device *pdev) 1244 { 1245 struct smmu_device *smmu = platform_get_drvdata(pdev); 1246 int i; 1247 1248 smmu_debugfs_delete(smmu); 1249 1250 smmu_write(smmu, SMMU_CONFIG_DISABLE, SMMU_CONFIG); 1251 for (i = 0; i < smmu->num_as; i++) 1252 free_pdir(&smmu->as[i]); 1253 __free_page(smmu->avp_vector_page); 1254 smmu_handle = NULL; 1255 return 0; 1256 } 1257 1258 static const struct dev_pm_ops tegra_smmu_pm_ops = { 1259 .suspend = tegra_smmu_suspend, 1260 .resume = tegra_smmu_resume, 1261 }; 1262 1263 static struct of_device_id tegra_smmu_of_match[] = { 1264 { .compatible = "nvidia,tegra30-smmu", }, 1265 { }, 1266 }; 1267 MODULE_DEVICE_TABLE(of, tegra_smmu_of_match); 1268 1269 static struct platform_driver tegra_smmu_driver = { 1270 .probe = tegra_smmu_probe, 1271 .remove = tegra_smmu_remove, 1272 .driver = { 1273 .owner = THIS_MODULE, 1274 .name = "tegra-smmu", 1275 .pm = &tegra_smmu_pm_ops, 1276 .of_match_table = tegra_smmu_of_match, 1277 }, 1278 }; 1279 1280 static int tegra_smmu_init(void) 1281 { 1282 return platform_driver_register(&tegra_smmu_driver); 1283 } 1284 1285 static void __exit tegra_smmu_exit(void) 1286 { 1287 platform_driver_unregister(&tegra_smmu_driver); 1288 } 1289 1290 subsys_initcall(tegra_smmu_init); 1291 module_exit(tegra_smmu_exit); 1292 1293 MODULE_DESCRIPTION("IOMMU API for SMMU in Tegra30"); 1294 MODULE_AUTHOR("Hiroshi DOYU <hdoyu@nvidia.com>"); 1295 MODULE_ALIAS("platform:tegra-smmu"); 1296 MODULE_LICENSE("GPL v2"); 1297