1 /* 2 * IOMMU API for SMMU in Tegra30 3 * 4 * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program; if not, write to the Free Software Foundation, Inc., 17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 */ 19 20 #define pr_fmt(fmt) "%s(): " fmt, __func__ 21 22 #include <linux/module.h> 23 #include <linux/platform_device.h> 24 #include <linux/spinlock.h> 25 #include <linux/slab.h> 26 #include <linux/vmalloc.h> 27 #include <linux/mm.h> 28 #include <linux/pagemap.h> 29 #include <linux/device.h> 30 #include <linux/sched.h> 31 #include <linux/iommu.h> 32 #include <linux/io.h> 33 #include <linux/of.h> 34 #include <linux/of_iommu.h> 35 #include <linux/debugfs.h> 36 #include <linux/seq_file.h> 37 38 #include <asm/page.h> 39 #include <asm/cacheflush.h> 40 41 #include <mach/iomap.h> 42 #include <mach/tegra-ahb.h> 43 44 enum smmu_hwgrp { 45 HWGRP_AFI, 46 HWGRP_AVPC, 47 HWGRP_DC, 48 HWGRP_DCB, 49 HWGRP_EPP, 50 HWGRP_G2, 51 HWGRP_HC, 52 HWGRP_HDA, 53 HWGRP_ISP, 54 HWGRP_MPE, 55 HWGRP_NV, 56 HWGRP_NV2, 57 HWGRP_PPCS, 58 HWGRP_SATA, 59 HWGRP_VDE, 60 HWGRP_VI, 61 62 HWGRP_COUNT, 63 64 HWGRP_END = ~0, 65 }; 66 67 #define HWG_AFI (1 << HWGRP_AFI) 68 #define HWG_AVPC (1 << HWGRP_AVPC) 69 #define HWG_DC (1 << HWGRP_DC) 70 #define HWG_DCB (1 << HWGRP_DCB) 71 #define HWG_EPP (1 << HWGRP_EPP) 72 #define HWG_G2 (1 << HWGRP_G2) 73 #define HWG_HC (1 << HWGRP_HC) 74 #define HWG_HDA (1 << HWGRP_HDA) 75 #define HWG_ISP (1 << HWGRP_ISP) 76 #define HWG_MPE (1 << HWGRP_MPE) 77 #define HWG_NV (1 << HWGRP_NV) 78 #define HWG_NV2 (1 << HWGRP_NV2) 79 #define HWG_PPCS (1 << HWGRP_PPCS) 80 #define HWG_SATA (1 << HWGRP_SATA) 81 #define HWG_VDE (1 << HWGRP_VDE) 82 #define HWG_VI (1 << HWGRP_VI) 83 84 /* bitmap of the page sizes currently supported */ 85 #define SMMU_IOMMU_PGSIZES (SZ_4K) 86 87 #define SMMU_CONFIG 0x10 88 #define SMMU_CONFIG_DISABLE 0 89 #define SMMU_CONFIG_ENABLE 1 90 91 /* REVISIT: To support multiple MCs */ 92 enum { 93 _MC = 0, 94 }; 95 96 enum { 97 _TLB = 0, 98 _PTC, 99 }; 100 101 #define SMMU_CACHE_CONFIG_BASE 0x14 102 #define __SMMU_CACHE_CONFIG(mc, cache) (SMMU_CACHE_CONFIG_BASE + 4 * cache) 103 #define SMMU_CACHE_CONFIG(cache) __SMMU_CACHE_CONFIG(_MC, cache) 104 105 #define SMMU_CACHE_CONFIG_STATS_SHIFT 31 106 #define SMMU_CACHE_CONFIG_STATS_ENABLE (1 << SMMU_CACHE_CONFIG_STATS_SHIFT) 107 #define SMMU_CACHE_CONFIG_STATS_TEST_SHIFT 30 108 #define SMMU_CACHE_CONFIG_STATS_TEST (1 << SMMU_CACHE_CONFIG_STATS_TEST_SHIFT) 109 110 #define SMMU_TLB_CONFIG_HIT_UNDER_MISS__ENABLE (1 << 29) 111 #define SMMU_TLB_CONFIG_ACTIVE_LINES__VALUE 0x10 112 #define SMMU_TLB_CONFIG_RESET_VAL 0x20000010 113 114 #define SMMU_PTC_CONFIG_CACHE__ENABLE (1 << 29) 115 #define SMMU_PTC_CONFIG_INDEX_MAP__PATTERN 0x3f 116 #define SMMU_PTC_CONFIG_RESET_VAL 0x2000003f 117 118 #define SMMU_PTB_ASID 0x1c 119 #define SMMU_PTB_ASID_CURRENT_SHIFT 0 120 121 #define SMMU_PTB_DATA 0x20 122 #define SMMU_PTB_DATA_RESET_VAL 0 123 #define SMMU_PTB_DATA_ASID_NONSECURE_SHIFT 29 124 #define SMMU_PTB_DATA_ASID_WRITABLE_SHIFT 30 125 #define SMMU_PTB_DATA_ASID_READABLE_SHIFT 31 126 127 #define SMMU_TLB_FLUSH 0x30 128 #define SMMU_TLB_FLUSH_VA_MATCH_ALL 0 129 #define SMMU_TLB_FLUSH_VA_MATCH_SECTION 2 130 #define SMMU_TLB_FLUSH_VA_MATCH_GROUP 3 131 #define SMMU_TLB_FLUSH_ASID_SHIFT 29 132 #define SMMU_TLB_FLUSH_ASID_MATCH_DISABLE 0 133 #define SMMU_TLB_FLUSH_ASID_MATCH_ENABLE 1 134 #define SMMU_TLB_FLUSH_ASID_MATCH_SHIFT 31 135 136 #define SMMU_PTC_FLUSH 0x34 137 #define SMMU_PTC_FLUSH_TYPE_ALL 0 138 #define SMMU_PTC_FLUSH_TYPE_ADR 1 139 #define SMMU_PTC_FLUSH_ADR_SHIFT 4 140 141 #define SMMU_ASID_SECURITY 0x38 142 143 #define SMMU_STATS_CACHE_COUNT_BASE 0x1f0 144 145 #define SMMU_STATS_CACHE_COUNT(mc, cache, hitmiss) \ 146 (SMMU_STATS_CACHE_COUNT_BASE + 8 * cache + 4 * hitmiss) 147 148 #define SMMU_TRANSLATION_ENABLE_0 0x228 149 #define SMMU_TRANSLATION_ENABLE_1 0x22c 150 #define SMMU_TRANSLATION_ENABLE_2 0x230 151 152 #define SMMU_AFI_ASID 0x238 /* PCIE */ 153 #define SMMU_AVPC_ASID 0x23c /* AVP */ 154 #define SMMU_DC_ASID 0x240 /* Display controller */ 155 #define SMMU_DCB_ASID 0x244 /* Display controller B */ 156 #define SMMU_EPP_ASID 0x248 /* Encoder pre-processor */ 157 #define SMMU_G2_ASID 0x24c /* 2D engine */ 158 #define SMMU_HC_ASID 0x250 /* Host1x */ 159 #define SMMU_HDA_ASID 0x254 /* High-def audio */ 160 #define SMMU_ISP_ASID 0x258 /* Image signal processor */ 161 #define SMMU_MPE_ASID 0x264 /* MPEG encoder */ 162 #define SMMU_NV_ASID 0x268 /* (3D) */ 163 #define SMMU_NV2_ASID 0x26c /* (3D) */ 164 #define SMMU_PPCS_ASID 0x270 /* AHB */ 165 #define SMMU_SATA_ASID 0x278 /* SATA */ 166 #define SMMU_VDE_ASID 0x27c /* Video decoder */ 167 #define SMMU_VI_ASID 0x280 /* Video input */ 168 169 #define SMMU_PDE_NEXT_SHIFT 28 170 171 #define SMMU_TLB_FLUSH_VA_SECTION__MASK 0xffc00000 172 #define SMMU_TLB_FLUSH_VA_SECTION__SHIFT 12 /* right shift */ 173 #define SMMU_TLB_FLUSH_VA_GROUP__MASK 0xffffc000 174 #define SMMU_TLB_FLUSH_VA_GROUP__SHIFT 12 /* right shift */ 175 #define SMMU_TLB_FLUSH_VA(iova, which) \ 176 ((((iova) & SMMU_TLB_FLUSH_VA_##which##__MASK) >> \ 177 SMMU_TLB_FLUSH_VA_##which##__SHIFT) | \ 178 SMMU_TLB_FLUSH_VA_MATCH_##which) 179 #define SMMU_PTB_ASID_CUR(n) \ 180 ((n) << SMMU_PTB_ASID_CURRENT_SHIFT) 181 #define SMMU_TLB_FLUSH_ASID_MATCH_disable \ 182 (SMMU_TLB_FLUSH_ASID_MATCH_DISABLE << \ 183 SMMU_TLB_FLUSH_ASID_MATCH_SHIFT) 184 #define SMMU_TLB_FLUSH_ASID_MATCH__ENABLE \ 185 (SMMU_TLB_FLUSH_ASID_MATCH_ENABLE << \ 186 SMMU_TLB_FLUSH_ASID_MATCH_SHIFT) 187 188 #define SMMU_PAGE_SHIFT 12 189 #define SMMU_PAGE_SIZE (1 << SMMU_PAGE_SHIFT) 190 #define SMMU_PAGE_MASK ((1 << SMMU_PAGE_SHIFT) - 1) 191 192 #define SMMU_PDIR_COUNT 1024 193 #define SMMU_PDIR_SIZE (sizeof(unsigned long) * SMMU_PDIR_COUNT) 194 #define SMMU_PTBL_COUNT 1024 195 #define SMMU_PTBL_SIZE (sizeof(unsigned long) * SMMU_PTBL_COUNT) 196 #define SMMU_PDIR_SHIFT 12 197 #define SMMU_PDE_SHIFT 12 198 #define SMMU_PTE_SHIFT 12 199 #define SMMU_PFN_MASK 0x000fffff 200 201 #define SMMU_ADDR_TO_PFN(addr) ((addr) >> 12) 202 #define SMMU_ADDR_TO_PDN(addr) ((addr) >> 22) 203 #define SMMU_PDN_TO_ADDR(pdn) ((pdn) << 22) 204 205 #define _READABLE (1 << SMMU_PTB_DATA_ASID_READABLE_SHIFT) 206 #define _WRITABLE (1 << SMMU_PTB_DATA_ASID_WRITABLE_SHIFT) 207 #define _NONSECURE (1 << SMMU_PTB_DATA_ASID_NONSECURE_SHIFT) 208 #define _PDE_NEXT (1 << SMMU_PDE_NEXT_SHIFT) 209 #define _MASK_ATTR (_READABLE | _WRITABLE | _NONSECURE) 210 211 #define _PDIR_ATTR (_READABLE | _WRITABLE | _NONSECURE) 212 213 #define _PDE_ATTR (_READABLE | _WRITABLE | _NONSECURE) 214 #define _PDE_ATTR_N (_PDE_ATTR | _PDE_NEXT) 215 #define _PDE_VACANT(pdn) (((pdn) << 10) | _PDE_ATTR) 216 217 #define _PTE_ATTR (_READABLE | _WRITABLE | _NONSECURE) 218 #define _PTE_VACANT(addr) (((addr) >> SMMU_PAGE_SHIFT) | _PTE_ATTR) 219 220 #define SMMU_MK_PDIR(page, attr) \ 221 ((page_to_phys(page) >> SMMU_PDIR_SHIFT) | (attr)) 222 #define SMMU_MK_PDE(page, attr) \ 223 (unsigned long)((page_to_phys(page) >> SMMU_PDE_SHIFT) | (attr)) 224 #define SMMU_EX_PTBL_PAGE(pde) \ 225 pfn_to_page((unsigned long)(pde) & SMMU_PFN_MASK) 226 #define SMMU_PFN_TO_PTE(pfn, attr) (unsigned long)((pfn) | (attr)) 227 228 #define SMMU_ASID_ENABLE(asid) ((asid) | (1 << 31)) 229 #define SMMU_ASID_DISABLE 0 230 #define SMMU_ASID_ASID(n) ((n) & ~SMMU_ASID_ENABLE(0)) 231 232 #define NUM_SMMU_REG_BANKS 3 233 234 #define smmu_client_enable_hwgrp(c, m) smmu_client_set_hwgrp(c, m, 1) 235 #define smmu_client_disable_hwgrp(c) smmu_client_set_hwgrp(c, 0, 0) 236 #define __smmu_client_enable_hwgrp(c, m) __smmu_client_set_hwgrp(c, m, 1) 237 #define __smmu_client_disable_hwgrp(c) __smmu_client_set_hwgrp(c, 0, 0) 238 239 #define HWGRP_INIT(client) [HWGRP_##client] = SMMU_##client##_ASID 240 241 static const u32 smmu_hwgrp_asid_reg[] = { 242 HWGRP_INIT(AFI), 243 HWGRP_INIT(AVPC), 244 HWGRP_INIT(DC), 245 HWGRP_INIT(DCB), 246 HWGRP_INIT(EPP), 247 HWGRP_INIT(G2), 248 HWGRP_INIT(HC), 249 HWGRP_INIT(HDA), 250 HWGRP_INIT(ISP), 251 HWGRP_INIT(MPE), 252 HWGRP_INIT(NV), 253 HWGRP_INIT(NV2), 254 HWGRP_INIT(PPCS), 255 HWGRP_INIT(SATA), 256 HWGRP_INIT(VDE), 257 HWGRP_INIT(VI), 258 }; 259 #define HWGRP_ASID_REG(x) (smmu_hwgrp_asid_reg[x]) 260 261 /* 262 * Per client for address space 263 */ 264 struct smmu_client { 265 struct device *dev; 266 struct list_head list; 267 struct smmu_as *as; 268 u32 hwgrp; 269 }; 270 271 /* 272 * Per address space 273 */ 274 struct smmu_as { 275 struct smmu_device *smmu; /* back pointer to container */ 276 unsigned int asid; 277 spinlock_t lock; /* for pagetable */ 278 struct page *pdir_page; 279 unsigned long pdir_attr; 280 unsigned long pde_attr; 281 unsigned long pte_attr; 282 unsigned int *pte_count; 283 284 struct list_head client; 285 spinlock_t client_lock; /* for client list */ 286 }; 287 288 struct smmu_debugfs_info { 289 struct smmu_device *smmu; 290 int mc; 291 int cache; 292 }; 293 294 /* 295 * Per SMMU device - IOMMU device 296 */ 297 struct smmu_device { 298 void __iomem *regs[NUM_SMMU_REG_BANKS]; 299 unsigned long iovmm_base; /* remappable base address */ 300 unsigned long page_count; /* total remappable size */ 301 spinlock_t lock; 302 char *name; 303 struct device *dev; 304 struct page *avp_vector_page; /* dummy page shared by all AS's */ 305 306 /* 307 * Register image savers for suspend/resume 308 */ 309 unsigned long translation_enable_0; 310 unsigned long translation_enable_1; 311 unsigned long translation_enable_2; 312 unsigned long asid_security; 313 314 struct dentry *debugfs_root; 315 struct smmu_debugfs_info *debugfs_info; 316 317 struct device_node *ahb; 318 319 int num_as; 320 struct smmu_as as[0]; /* Run-time allocated array */ 321 }; 322 323 static struct smmu_device *smmu_handle; /* unique for a system */ 324 325 /* 326 * SMMU register accessors 327 */ 328 static inline u32 smmu_read(struct smmu_device *smmu, size_t offs) 329 { 330 BUG_ON(offs < 0x10); 331 if (offs < 0x3c) 332 return readl(smmu->regs[0] + offs - 0x10); 333 BUG_ON(offs < 0x1f0); 334 if (offs < 0x200) 335 return readl(smmu->regs[1] + offs - 0x1f0); 336 BUG_ON(offs < 0x228); 337 if (offs < 0x284) 338 return readl(smmu->regs[2] + offs - 0x228); 339 BUG(); 340 } 341 342 static inline void smmu_write(struct smmu_device *smmu, u32 val, size_t offs) 343 { 344 BUG_ON(offs < 0x10); 345 if (offs < 0x3c) { 346 writel(val, smmu->regs[0] + offs - 0x10); 347 return; 348 } 349 BUG_ON(offs < 0x1f0); 350 if (offs < 0x200) { 351 writel(val, smmu->regs[1] + offs - 0x1f0); 352 return; 353 } 354 BUG_ON(offs < 0x228); 355 if (offs < 0x284) { 356 writel(val, smmu->regs[2] + offs - 0x228); 357 return; 358 } 359 BUG(); 360 } 361 362 #define VA_PAGE_TO_PA(va, page) \ 363 (page_to_phys(page) + ((unsigned long)(va) & ~PAGE_MASK)) 364 365 #define FLUSH_CPU_DCACHE(va, page, size) \ 366 do { \ 367 unsigned long _pa_ = VA_PAGE_TO_PA(va, page); \ 368 __cpuc_flush_dcache_area((void *)(va), (size_t)(size)); \ 369 outer_flush_range(_pa_, _pa_+(size_t)(size)); \ 370 } while (0) 371 372 /* 373 * Any interaction between any block on PPSB and a block on APB or AHB 374 * must have these read-back barriers to ensure the APB/AHB bus 375 * transaction is complete before initiating activity on the PPSB 376 * block. 377 */ 378 #define FLUSH_SMMU_REGS(smmu) smmu_read(smmu, SMMU_CONFIG) 379 380 #define smmu_client_hwgrp(c) (u32)((c)->dev->platform_data) 381 382 static int __smmu_client_set_hwgrp(struct smmu_client *c, 383 unsigned long map, int on) 384 { 385 int i; 386 struct smmu_as *as = c->as; 387 u32 val, offs, mask = SMMU_ASID_ENABLE(as->asid); 388 struct smmu_device *smmu = as->smmu; 389 390 WARN_ON(!on && map); 391 if (on && !map) 392 return -EINVAL; 393 if (!on) 394 map = smmu_client_hwgrp(c); 395 396 for_each_set_bit(i, &map, HWGRP_COUNT) { 397 offs = HWGRP_ASID_REG(i); 398 val = smmu_read(smmu, offs); 399 if (on) { 400 if (WARN_ON(val & mask)) 401 goto err_hw_busy; 402 val |= mask; 403 } else { 404 WARN_ON((val & mask) == mask); 405 val &= ~mask; 406 } 407 smmu_write(smmu, val, offs); 408 } 409 FLUSH_SMMU_REGS(smmu); 410 c->hwgrp = map; 411 return 0; 412 413 err_hw_busy: 414 for_each_set_bit(i, &map, HWGRP_COUNT) { 415 offs = HWGRP_ASID_REG(i); 416 val = smmu_read(smmu, offs); 417 val &= ~mask; 418 smmu_write(smmu, val, offs); 419 } 420 return -EBUSY; 421 } 422 423 static int smmu_client_set_hwgrp(struct smmu_client *c, u32 map, int on) 424 { 425 u32 val; 426 unsigned long flags; 427 struct smmu_as *as = c->as; 428 struct smmu_device *smmu = as->smmu; 429 430 spin_lock_irqsave(&smmu->lock, flags); 431 val = __smmu_client_set_hwgrp(c, map, on); 432 spin_unlock_irqrestore(&smmu->lock, flags); 433 return val; 434 } 435 436 /* 437 * Flush all TLB entries and all PTC entries 438 * Caller must lock smmu 439 */ 440 static void smmu_flush_regs(struct smmu_device *smmu, int enable) 441 { 442 u32 val; 443 444 smmu_write(smmu, SMMU_PTC_FLUSH_TYPE_ALL, SMMU_PTC_FLUSH); 445 FLUSH_SMMU_REGS(smmu); 446 val = SMMU_TLB_FLUSH_VA_MATCH_ALL | 447 SMMU_TLB_FLUSH_ASID_MATCH_disable; 448 smmu_write(smmu, val, SMMU_TLB_FLUSH); 449 450 if (enable) 451 smmu_write(smmu, SMMU_CONFIG_ENABLE, SMMU_CONFIG); 452 FLUSH_SMMU_REGS(smmu); 453 } 454 455 static int smmu_setup_regs(struct smmu_device *smmu) 456 { 457 int i; 458 u32 val; 459 460 for (i = 0; i < smmu->num_as; i++) { 461 struct smmu_as *as = &smmu->as[i]; 462 struct smmu_client *c; 463 464 smmu_write(smmu, SMMU_PTB_ASID_CUR(as->asid), SMMU_PTB_ASID); 465 val = as->pdir_page ? 466 SMMU_MK_PDIR(as->pdir_page, as->pdir_attr) : 467 SMMU_PTB_DATA_RESET_VAL; 468 smmu_write(smmu, val, SMMU_PTB_DATA); 469 470 list_for_each_entry(c, &as->client, list) 471 __smmu_client_set_hwgrp(c, c->hwgrp, 1); 472 } 473 474 smmu_write(smmu, smmu->translation_enable_0, SMMU_TRANSLATION_ENABLE_0); 475 smmu_write(smmu, smmu->translation_enable_1, SMMU_TRANSLATION_ENABLE_1); 476 smmu_write(smmu, smmu->translation_enable_2, SMMU_TRANSLATION_ENABLE_2); 477 smmu_write(smmu, smmu->asid_security, SMMU_ASID_SECURITY); 478 smmu_write(smmu, SMMU_TLB_CONFIG_RESET_VAL, SMMU_CACHE_CONFIG(_TLB)); 479 smmu_write(smmu, SMMU_PTC_CONFIG_RESET_VAL, SMMU_CACHE_CONFIG(_PTC)); 480 481 smmu_flush_regs(smmu, 1); 482 483 return tegra_ahb_enable_smmu(smmu->ahb); 484 } 485 486 static void flush_ptc_and_tlb(struct smmu_device *smmu, 487 struct smmu_as *as, dma_addr_t iova, 488 unsigned long *pte, struct page *page, int is_pde) 489 { 490 u32 val; 491 unsigned long tlb_flush_va = is_pde 492 ? SMMU_TLB_FLUSH_VA(iova, SECTION) 493 : SMMU_TLB_FLUSH_VA(iova, GROUP); 494 495 val = SMMU_PTC_FLUSH_TYPE_ADR | VA_PAGE_TO_PA(pte, page); 496 smmu_write(smmu, val, SMMU_PTC_FLUSH); 497 FLUSH_SMMU_REGS(smmu); 498 val = tlb_flush_va | 499 SMMU_TLB_FLUSH_ASID_MATCH__ENABLE | 500 (as->asid << SMMU_TLB_FLUSH_ASID_SHIFT); 501 smmu_write(smmu, val, SMMU_TLB_FLUSH); 502 FLUSH_SMMU_REGS(smmu); 503 } 504 505 static void free_ptbl(struct smmu_as *as, dma_addr_t iova) 506 { 507 unsigned long pdn = SMMU_ADDR_TO_PDN(iova); 508 unsigned long *pdir = (unsigned long *)page_address(as->pdir_page); 509 510 if (pdir[pdn] != _PDE_VACANT(pdn)) { 511 dev_dbg(as->smmu->dev, "pdn: %lx\n", pdn); 512 513 ClearPageReserved(SMMU_EX_PTBL_PAGE(pdir[pdn])); 514 __free_page(SMMU_EX_PTBL_PAGE(pdir[pdn])); 515 pdir[pdn] = _PDE_VACANT(pdn); 516 FLUSH_CPU_DCACHE(&pdir[pdn], as->pdir_page, sizeof pdir[pdn]); 517 flush_ptc_and_tlb(as->smmu, as, iova, &pdir[pdn], 518 as->pdir_page, 1); 519 } 520 } 521 522 static void free_pdir(struct smmu_as *as) 523 { 524 unsigned addr; 525 int count; 526 struct device *dev = as->smmu->dev; 527 528 if (!as->pdir_page) 529 return; 530 531 addr = as->smmu->iovmm_base; 532 count = as->smmu->page_count; 533 while (count-- > 0) { 534 free_ptbl(as, addr); 535 addr += SMMU_PAGE_SIZE * SMMU_PTBL_COUNT; 536 } 537 ClearPageReserved(as->pdir_page); 538 __free_page(as->pdir_page); 539 as->pdir_page = NULL; 540 devm_kfree(dev, as->pte_count); 541 as->pte_count = NULL; 542 } 543 544 /* 545 * Maps PTBL for given iova and returns the PTE address 546 * Caller must unmap the mapped PTBL returned in *ptbl_page_p 547 */ 548 static unsigned long *locate_pte(struct smmu_as *as, 549 dma_addr_t iova, bool allocate, 550 struct page **ptbl_page_p, 551 unsigned int **count) 552 { 553 unsigned long ptn = SMMU_ADDR_TO_PFN(iova); 554 unsigned long pdn = SMMU_ADDR_TO_PDN(iova); 555 unsigned long *pdir = page_address(as->pdir_page); 556 unsigned long *ptbl; 557 558 if (pdir[pdn] != _PDE_VACANT(pdn)) { 559 /* Mapped entry table already exists */ 560 *ptbl_page_p = SMMU_EX_PTBL_PAGE(pdir[pdn]); 561 ptbl = page_address(*ptbl_page_p); 562 } else if (!allocate) { 563 return NULL; 564 } else { 565 int pn; 566 unsigned long addr = SMMU_PDN_TO_ADDR(pdn); 567 568 /* Vacant - allocate a new page table */ 569 dev_dbg(as->smmu->dev, "New PTBL pdn: %lx\n", pdn); 570 571 *ptbl_page_p = alloc_page(GFP_ATOMIC); 572 if (!*ptbl_page_p) { 573 dev_err(as->smmu->dev, 574 "failed to allocate smmu_device page table\n"); 575 return NULL; 576 } 577 SetPageReserved(*ptbl_page_p); 578 ptbl = (unsigned long *)page_address(*ptbl_page_p); 579 for (pn = 0; pn < SMMU_PTBL_COUNT; 580 pn++, addr += SMMU_PAGE_SIZE) { 581 ptbl[pn] = _PTE_VACANT(addr); 582 } 583 FLUSH_CPU_DCACHE(ptbl, *ptbl_page_p, SMMU_PTBL_SIZE); 584 pdir[pdn] = SMMU_MK_PDE(*ptbl_page_p, 585 as->pde_attr | _PDE_NEXT); 586 FLUSH_CPU_DCACHE(&pdir[pdn], as->pdir_page, sizeof pdir[pdn]); 587 flush_ptc_and_tlb(as->smmu, as, iova, &pdir[pdn], 588 as->pdir_page, 1); 589 } 590 *count = &as->pte_count[pdn]; 591 592 return &ptbl[ptn % SMMU_PTBL_COUNT]; 593 } 594 595 #ifdef CONFIG_SMMU_SIG_DEBUG 596 static void put_signature(struct smmu_as *as, 597 dma_addr_t iova, unsigned long pfn) 598 { 599 struct page *page; 600 unsigned long *vaddr; 601 602 page = pfn_to_page(pfn); 603 vaddr = page_address(page); 604 if (!vaddr) 605 return; 606 607 vaddr[0] = iova; 608 vaddr[1] = pfn << PAGE_SHIFT; 609 FLUSH_CPU_DCACHE(vaddr, page, sizeof(vaddr[0]) * 2); 610 } 611 #else 612 static inline void put_signature(struct smmu_as *as, 613 unsigned long addr, unsigned long pfn) 614 { 615 } 616 #endif 617 618 /* 619 * Caller must not hold as->lock 620 */ 621 static int alloc_pdir(struct smmu_as *as) 622 { 623 unsigned long *pdir, flags; 624 int pdn, err = 0; 625 u32 val; 626 struct smmu_device *smmu = as->smmu; 627 struct page *page; 628 unsigned int *cnt; 629 630 /* 631 * do the allocation, then grab as->lock 632 */ 633 cnt = devm_kzalloc(smmu->dev, 634 sizeof(cnt[0]) * SMMU_PDIR_COUNT, 635 GFP_KERNEL); 636 page = alloc_page(GFP_KERNEL | __GFP_DMA); 637 638 spin_lock_irqsave(&as->lock, flags); 639 640 if (as->pdir_page) { 641 /* We raced, free the redundant */ 642 err = -EAGAIN; 643 goto err_out; 644 } 645 646 if (!page || !cnt) { 647 dev_err(smmu->dev, "failed to allocate at %s\n", __func__); 648 err = -ENOMEM; 649 goto err_out; 650 } 651 652 as->pdir_page = page; 653 as->pte_count = cnt; 654 655 SetPageReserved(as->pdir_page); 656 pdir = page_address(as->pdir_page); 657 658 for (pdn = 0; pdn < SMMU_PDIR_COUNT; pdn++) 659 pdir[pdn] = _PDE_VACANT(pdn); 660 FLUSH_CPU_DCACHE(pdir, as->pdir_page, SMMU_PDIR_SIZE); 661 val = SMMU_PTC_FLUSH_TYPE_ADR | VA_PAGE_TO_PA(pdir, as->pdir_page); 662 smmu_write(smmu, val, SMMU_PTC_FLUSH); 663 FLUSH_SMMU_REGS(as->smmu); 664 val = SMMU_TLB_FLUSH_VA_MATCH_ALL | 665 SMMU_TLB_FLUSH_ASID_MATCH__ENABLE | 666 (as->asid << SMMU_TLB_FLUSH_ASID_SHIFT); 667 smmu_write(smmu, val, SMMU_TLB_FLUSH); 668 FLUSH_SMMU_REGS(as->smmu); 669 670 spin_unlock_irqrestore(&as->lock, flags); 671 672 return 0; 673 674 err_out: 675 spin_unlock_irqrestore(&as->lock, flags); 676 677 devm_kfree(smmu->dev, cnt); 678 if (page) 679 __free_page(page); 680 return err; 681 } 682 683 static void __smmu_iommu_unmap(struct smmu_as *as, dma_addr_t iova) 684 { 685 unsigned long *pte; 686 struct page *page; 687 unsigned int *count; 688 689 pte = locate_pte(as, iova, false, &page, &count); 690 if (WARN_ON(!pte)) 691 return; 692 693 if (WARN_ON(*pte == _PTE_VACANT(iova))) 694 return; 695 696 *pte = _PTE_VACANT(iova); 697 FLUSH_CPU_DCACHE(pte, page, sizeof(*pte)); 698 flush_ptc_and_tlb(as->smmu, as, iova, pte, page, 0); 699 if (!--(*count)) { 700 free_ptbl(as, iova); 701 smmu_flush_regs(as->smmu, 0); 702 } 703 } 704 705 static void __smmu_iommu_map_pfn(struct smmu_as *as, dma_addr_t iova, 706 unsigned long pfn) 707 { 708 struct smmu_device *smmu = as->smmu; 709 unsigned long *pte; 710 unsigned int *count; 711 struct page *page; 712 713 pte = locate_pte(as, iova, true, &page, &count); 714 if (WARN_ON(!pte)) 715 return; 716 717 if (*pte == _PTE_VACANT(iova)) 718 (*count)++; 719 *pte = SMMU_PFN_TO_PTE(pfn, as->pte_attr); 720 if (unlikely((*pte == _PTE_VACANT(iova)))) 721 (*count)--; 722 FLUSH_CPU_DCACHE(pte, page, sizeof(*pte)); 723 flush_ptc_and_tlb(smmu, as, iova, pte, page, 0); 724 put_signature(as, iova, pfn); 725 } 726 727 static int smmu_iommu_map(struct iommu_domain *domain, unsigned long iova, 728 phys_addr_t pa, size_t bytes, int prot) 729 { 730 struct smmu_as *as = domain->priv; 731 unsigned long pfn = __phys_to_pfn(pa); 732 unsigned long flags; 733 734 dev_dbg(as->smmu->dev, "[%d] %08lx:%08x\n", as->asid, iova, pa); 735 736 if (!pfn_valid(pfn)) 737 return -ENOMEM; 738 739 spin_lock_irqsave(&as->lock, flags); 740 __smmu_iommu_map_pfn(as, iova, pfn); 741 spin_unlock_irqrestore(&as->lock, flags); 742 return 0; 743 } 744 745 static size_t smmu_iommu_unmap(struct iommu_domain *domain, unsigned long iova, 746 size_t bytes) 747 { 748 struct smmu_as *as = domain->priv; 749 unsigned long flags; 750 751 dev_dbg(as->smmu->dev, "[%d] %08lx\n", as->asid, iova); 752 753 spin_lock_irqsave(&as->lock, flags); 754 __smmu_iommu_unmap(as, iova); 755 spin_unlock_irqrestore(&as->lock, flags); 756 return SMMU_PAGE_SIZE; 757 } 758 759 static phys_addr_t smmu_iommu_iova_to_phys(struct iommu_domain *domain, 760 unsigned long iova) 761 { 762 struct smmu_as *as = domain->priv; 763 unsigned long *pte; 764 unsigned int *count; 765 struct page *page; 766 unsigned long pfn; 767 unsigned long flags; 768 769 spin_lock_irqsave(&as->lock, flags); 770 771 pte = locate_pte(as, iova, true, &page, &count); 772 pfn = *pte & SMMU_PFN_MASK; 773 WARN_ON(!pfn_valid(pfn)); 774 dev_dbg(as->smmu->dev, 775 "iova:%08lx pfn:%08lx asid:%d\n", iova, pfn, as->asid); 776 777 spin_unlock_irqrestore(&as->lock, flags); 778 return PFN_PHYS(pfn); 779 } 780 781 static int smmu_iommu_domain_has_cap(struct iommu_domain *domain, 782 unsigned long cap) 783 { 784 return 0; 785 } 786 787 static int smmu_iommu_attach_dev(struct iommu_domain *domain, 788 struct device *dev) 789 { 790 struct smmu_as *as = domain->priv; 791 struct smmu_device *smmu = as->smmu; 792 struct smmu_client *client, *c; 793 u32 map; 794 int err; 795 796 client = devm_kzalloc(smmu->dev, sizeof(*c), GFP_KERNEL); 797 if (!client) 798 return -ENOMEM; 799 client->dev = dev; 800 client->as = as; 801 map = (unsigned long)dev->platform_data; 802 if (!map) 803 return -EINVAL; 804 805 err = smmu_client_enable_hwgrp(client, map); 806 if (err) 807 goto err_hwgrp; 808 809 spin_lock(&as->client_lock); 810 list_for_each_entry(c, &as->client, list) { 811 if (c->dev == dev) { 812 dev_err(smmu->dev, 813 "%s is already attached\n", dev_name(c->dev)); 814 err = -EINVAL; 815 goto err_client; 816 } 817 } 818 list_add(&client->list, &as->client); 819 spin_unlock(&as->client_lock); 820 821 /* 822 * Reserve "page zero" for AVP vectors using a common dummy 823 * page. 824 */ 825 if (map & HWG_AVPC) { 826 struct page *page; 827 828 page = as->smmu->avp_vector_page; 829 __smmu_iommu_map_pfn(as, 0, page_to_pfn(page)); 830 831 pr_info("Reserve \"page zero\" for AVP vectors using a common dummy\n"); 832 } 833 834 dev_dbg(smmu->dev, "%s is attached\n", dev_name(dev)); 835 return 0; 836 837 err_client: 838 smmu_client_disable_hwgrp(client); 839 spin_unlock(&as->client_lock); 840 err_hwgrp: 841 devm_kfree(smmu->dev, client); 842 return err; 843 } 844 845 static void smmu_iommu_detach_dev(struct iommu_domain *domain, 846 struct device *dev) 847 { 848 struct smmu_as *as = domain->priv; 849 struct smmu_device *smmu = as->smmu; 850 struct smmu_client *c; 851 852 spin_lock(&as->client_lock); 853 854 list_for_each_entry(c, &as->client, list) { 855 if (c->dev == dev) { 856 smmu_client_disable_hwgrp(c); 857 list_del(&c->list); 858 devm_kfree(smmu->dev, c); 859 c->as = NULL; 860 dev_dbg(smmu->dev, 861 "%s is detached\n", dev_name(c->dev)); 862 goto out; 863 } 864 } 865 dev_err(smmu->dev, "Couldn't find %s\n", dev_name(dev)); 866 out: 867 spin_unlock(&as->client_lock); 868 } 869 870 static int smmu_iommu_domain_init(struct iommu_domain *domain) 871 { 872 int i, err = -EAGAIN; 873 unsigned long flags; 874 struct smmu_as *as; 875 struct smmu_device *smmu = smmu_handle; 876 877 /* Look for a free AS with lock held */ 878 for (i = 0; i < smmu->num_as; i++) { 879 as = &smmu->as[i]; 880 881 if (as->pdir_page) 882 continue; 883 884 err = alloc_pdir(as); 885 if (!err) 886 goto found; 887 888 if (err != -EAGAIN) 889 break; 890 } 891 if (i == smmu->num_as) 892 dev_err(smmu->dev, "no free AS\n"); 893 return err; 894 895 found: 896 spin_lock_irqsave(&smmu->lock, flags); 897 898 /* Update PDIR register */ 899 smmu_write(smmu, SMMU_PTB_ASID_CUR(as->asid), SMMU_PTB_ASID); 900 smmu_write(smmu, 901 SMMU_MK_PDIR(as->pdir_page, as->pdir_attr), SMMU_PTB_DATA); 902 FLUSH_SMMU_REGS(smmu); 903 904 spin_unlock_irqrestore(&smmu->lock, flags); 905 906 domain->priv = as; 907 908 domain->geometry.aperture_start = smmu->iovmm_base; 909 domain->geometry.aperture_end = smmu->iovmm_base + 910 smmu->page_count * SMMU_PAGE_SIZE - 1; 911 domain->geometry.force_aperture = true; 912 913 dev_dbg(smmu->dev, "smmu_as@%p\n", as); 914 915 return 0; 916 } 917 918 static void smmu_iommu_domain_destroy(struct iommu_domain *domain) 919 { 920 struct smmu_as *as = domain->priv; 921 struct smmu_device *smmu = as->smmu; 922 unsigned long flags; 923 924 spin_lock_irqsave(&as->lock, flags); 925 926 if (as->pdir_page) { 927 spin_lock(&smmu->lock); 928 smmu_write(smmu, SMMU_PTB_ASID_CUR(as->asid), SMMU_PTB_ASID); 929 smmu_write(smmu, SMMU_PTB_DATA_RESET_VAL, SMMU_PTB_DATA); 930 FLUSH_SMMU_REGS(smmu); 931 spin_unlock(&smmu->lock); 932 933 free_pdir(as); 934 } 935 936 if (!list_empty(&as->client)) { 937 struct smmu_client *c; 938 939 list_for_each_entry(c, &as->client, list) 940 smmu_iommu_detach_dev(domain, c->dev); 941 } 942 943 spin_unlock_irqrestore(&as->lock, flags); 944 945 domain->priv = NULL; 946 dev_dbg(smmu->dev, "smmu_as@%p\n", as); 947 } 948 949 static struct iommu_ops smmu_iommu_ops = { 950 .domain_init = smmu_iommu_domain_init, 951 .domain_destroy = smmu_iommu_domain_destroy, 952 .attach_dev = smmu_iommu_attach_dev, 953 .detach_dev = smmu_iommu_detach_dev, 954 .map = smmu_iommu_map, 955 .unmap = smmu_iommu_unmap, 956 .iova_to_phys = smmu_iommu_iova_to_phys, 957 .domain_has_cap = smmu_iommu_domain_has_cap, 958 .pgsize_bitmap = SMMU_IOMMU_PGSIZES, 959 }; 960 961 /* Should be in the order of enum */ 962 static const char * const smmu_debugfs_mc[] = { "mc", }; 963 static const char * const smmu_debugfs_cache[] = { "tlb", "ptc", }; 964 965 static ssize_t smmu_debugfs_stats_write(struct file *file, 966 const char __user *buffer, 967 size_t count, loff_t *pos) 968 { 969 struct smmu_debugfs_info *info; 970 struct smmu_device *smmu; 971 struct dentry *dent; 972 int i; 973 enum { 974 _OFF = 0, 975 _ON, 976 _RESET, 977 }; 978 const char * const command[] = { 979 [_OFF] = "off", 980 [_ON] = "on", 981 [_RESET] = "reset", 982 }; 983 char str[] = "reset"; 984 u32 val; 985 size_t offs; 986 987 count = min_t(size_t, count, sizeof(str)); 988 if (copy_from_user(str, buffer, count)) 989 return -EINVAL; 990 991 for (i = 0; i < ARRAY_SIZE(command); i++) 992 if (strncmp(str, command[i], 993 strlen(command[i])) == 0) 994 break; 995 996 if (i == ARRAY_SIZE(command)) 997 return -EINVAL; 998 999 dent = file->f_dentry; 1000 info = dent->d_inode->i_private; 1001 smmu = info->smmu; 1002 1003 offs = SMMU_CACHE_CONFIG(info->cache); 1004 val = smmu_read(smmu, offs); 1005 switch (i) { 1006 case _OFF: 1007 val &= ~SMMU_CACHE_CONFIG_STATS_ENABLE; 1008 val &= ~SMMU_CACHE_CONFIG_STATS_TEST; 1009 smmu_write(smmu, val, offs); 1010 break; 1011 case _ON: 1012 val |= SMMU_CACHE_CONFIG_STATS_ENABLE; 1013 val &= ~SMMU_CACHE_CONFIG_STATS_TEST; 1014 smmu_write(smmu, val, offs); 1015 break; 1016 case _RESET: 1017 val |= SMMU_CACHE_CONFIG_STATS_TEST; 1018 smmu_write(smmu, val, offs); 1019 val &= ~SMMU_CACHE_CONFIG_STATS_TEST; 1020 smmu_write(smmu, val, offs); 1021 break; 1022 default: 1023 BUG(); 1024 break; 1025 } 1026 1027 dev_dbg(smmu->dev, "%s() %08x, %08x @%08x\n", __func__, 1028 val, smmu_read(smmu, offs), offs); 1029 1030 return count; 1031 } 1032 1033 static int smmu_debugfs_stats_show(struct seq_file *s, void *v) 1034 { 1035 struct smmu_debugfs_info *info; 1036 struct smmu_device *smmu; 1037 struct dentry *dent; 1038 int i; 1039 const char * const stats[] = { "hit", "miss", }; 1040 1041 dent = d_find_alias(s->private); 1042 info = dent->d_inode->i_private; 1043 smmu = info->smmu; 1044 1045 for (i = 0; i < ARRAY_SIZE(stats); i++) { 1046 u32 val; 1047 size_t offs; 1048 1049 offs = SMMU_STATS_CACHE_COUNT(info->mc, info->cache, i); 1050 val = smmu_read(smmu, offs); 1051 seq_printf(s, "%s:%08x ", stats[i], val); 1052 1053 dev_dbg(smmu->dev, "%s() %s %08x @%08x\n", __func__, 1054 stats[i], val, offs); 1055 } 1056 seq_printf(s, "\n"); 1057 dput(dent); 1058 1059 return 0; 1060 } 1061 1062 static int smmu_debugfs_stats_open(struct inode *inode, struct file *file) 1063 { 1064 return single_open(file, smmu_debugfs_stats_show, inode); 1065 } 1066 1067 static const struct file_operations smmu_debugfs_stats_fops = { 1068 .open = smmu_debugfs_stats_open, 1069 .read = seq_read, 1070 .llseek = seq_lseek, 1071 .release = single_release, 1072 .write = smmu_debugfs_stats_write, 1073 }; 1074 1075 static void smmu_debugfs_delete(struct smmu_device *smmu) 1076 { 1077 debugfs_remove_recursive(smmu->debugfs_root); 1078 kfree(smmu->debugfs_info); 1079 } 1080 1081 static void smmu_debugfs_create(struct smmu_device *smmu) 1082 { 1083 int i; 1084 size_t bytes; 1085 struct dentry *root; 1086 1087 bytes = ARRAY_SIZE(smmu_debugfs_mc) * ARRAY_SIZE(smmu_debugfs_cache) * 1088 sizeof(*smmu->debugfs_info); 1089 smmu->debugfs_info = kmalloc(bytes, GFP_KERNEL); 1090 if (!smmu->debugfs_info) 1091 return; 1092 1093 root = debugfs_create_dir(dev_name(smmu->dev), NULL); 1094 if (!root) 1095 goto err_out; 1096 smmu->debugfs_root = root; 1097 1098 for (i = 0; i < ARRAY_SIZE(smmu_debugfs_mc); i++) { 1099 int j; 1100 struct dentry *mc; 1101 1102 mc = debugfs_create_dir(smmu_debugfs_mc[i], root); 1103 if (!mc) 1104 goto err_out; 1105 1106 for (j = 0; j < ARRAY_SIZE(smmu_debugfs_cache); j++) { 1107 struct dentry *cache; 1108 struct smmu_debugfs_info *info; 1109 1110 info = smmu->debugfs_info; 1111 info += i * ARRAY_SIZE(smmu_debugfs_mc) + j; 1112 info->smmu = smmu; 1113 info->mc = i; 1114 info->cache = j; 1115 1116 cache = debugfs_create_file(smmu_debugfs_cache[j], 1117 S_IWUGO | S_IRUGO, mc, 1118 (void *)info, 1119 &smmu_debugfs_stats_fops); 1120 if (!cache) 1121 goto err_out; 1122 } 1123 } 1124 1125 return; 1126 1127 err_out: 1128 smmu_debugfs_delete(smmu); 1129 } 1130 1131 static int tegra_smmu_suspend(struct device *dev) 1132 { 1133 struct smmu_device *smmu = dev_get_drvdata(dev); 1134 1135 smmu->translation_enable_0 = smmu_read(smmu, SMMU_TRANSLATION_ENABLE_0); 1136 smmu->translation_enable_1 = smmu_read(smmu, SMMU_TRANSLATION_ENABLE_1); 1137 smmu->translation_enable_2 = smmu_read(smmu, SMMU_TRANSLATION_ENABLE_2); 1138 smmu->asid_security = smmu_read(smmu, SMMU_ASID_SECURITY); 1139 return 0; 1140 } 1141 1142 static int tegra_smmu_resume(struct device *dev) 1143 { 1144 struct smmu_device *smmu = dev_get_drvdata(dev); 1145 unsigned long flags; 1146 int err; 1147 1148 spin_lock_irqsave(&smmu->lock, flags); 1149 err = smmu_setup_regs(smmu); 1150 spin_unlock_irqrestore(&smmu->lock, flags); 1151 return err; 1152 } 1153 1154 static int tegra_smmu_probe(struct platform_device *pdev) 1155 { 1156 struct smmu_device *smmu; 1157 struct device *dev = &pdev->dev; 1158 int i, asids, err = 0; 1159 dma_addr_t uninitialized_var(base); 1160 size_t bytes, uninitialized_var(size); 1161 1162 if (smmu_handle) 1163 return -EIO; 1164 1165 BUILD_BUG_ON(PAGE_SHIFT != SMMU_PAGE_SHIFT); 1166 1167 if (of_property_read_u32(dev->of_node, "nvidia,#asids", &asids)) 1168 return -ENODEV; 1169 1170 bytes = sizeof(*smmu) + asids * sizeof(*smmu->as); 1171 smmu = devm_kzalloc(dev, bytes, GFP_KERNEL); 1172 if (!smmu) { 1173 dev_err(dev, "failed to allocate smmu_device\n"); 1174 return -ENOMEM; 1175 } 1176 1177 for (i = 0; i < ARRAY_SIZE(smmu->regs); i++) { 1178 struct resource *res; 1179 1180 res = platform_get_resource(pdev, IORESOURCE_MEM, i); 1181 if (!res) 1182 return -ENODEV; 1183 smmu->regs[i] = devm_request_and_ioremap(&pdev->dev, res); 1184 if (!smmu->regs[i]) 1185 return -EBUSY; 1186 } 1187 1188 err = of_get_dma_window(dev->of_node, NULL, 0, NULL, &base, &size); 1189 if (err) 1190 return -ENODEV; 1191 1192 if (size & SMMU_PAGE_MASK) 1193 return -EINVAL; 1194 1195 size >>= SMMU_PAGE_SHIFT; 1196 if (!size) 1197 return -EINVAL; 1198 1199 smmu->ahb = of_parse_phandle(dev->of_node, "nvidia,ahb", 0); 1200 if (!smmu->ahb) 1201 return -ENODEV; 1202 1203 smmu->dev = dev; 1204 smmu->num_as = asids; 1205 smmu->iovmm_base = base; 1206 smmu->page_count = size; 1207 1208 smmu->translation_enable_0 = ~0; 1209 smmu->translation_enable_1 = ~0; 1210 smmu->translation_enable_2 = ~0; 1211 smmu->asid_security = 0; 1212 1213 for (i = 0; i < smmu->num_as; i++) { 1214 struct smmu_as *as = &smmu->as[i]; 1215 1216 as->smmu = smmu; 1217 as->asid = i; 1218 as->pdir_attr = _PDIR_ATTR; 1219 as->pde_attr = _PDE_ATTR; 1220 as->pte_attr = _PTE_ATTR; 1221 1222 spin_lock_init(&as->lock); 1223 INIT_LIST_HEAD(&as->client); 1224 } 1225 spin_lock_init(&smmu->lock); 1226 err = smmu_setup_regs(smmu); 1227 if (err) 1228 return err; 1229 platform_set_drvdata(pdev, smmu); 1230 1231 smmu->avp_vector_page = alloc_page(GFP_KERNEL); 1232 if (!smmu->avp_vector_page) 1233 return -ENOMEM; 1234 1235 smmu_debugfs_create(smmu); 1236 smmu_handle = smmu; 1237 return 0; 1238 } 1239 1240 static int tegra_smmu_remove(struct platform_device *pdev) 1241 { 1242 struct smmu_device *smmu = platform_get_drvdata(pdev); 1243 int i; 1244 1245 smmu_debugfs_delete(smmu); 1246 1247 smmu_write(smmu, SMMU_CONFIG_DISABLE, SMMU_CONFIG); 1248 for (i = 0; i < smmu->num_as; i++) 1249 free_pdir(&smmu->as[i]); 1250 __free_page(smmu->avp_vector_page); 1251 smmu_handle = NULL; 1252 return 0; 1253 } 1254 1255 const struct dev_pm_ops tegra_smmu_pm_ops = { 1256 .suspend = tegra_smmu_suspend, 1257 .resume = tegra_smmu_resume, 1258 }; 1259 1260 #ifdef CONFIG_OF 1261 static struct of_device_id tegra_smmu_of_match[] __devinitdata = { 1262 { .compatible = "nvidia,tegra30-smmu", }, 1263 { }, 1264 }; 1265 MODULE_DEVICE_TABLE(of, tegra_smmu_of_match); 1266 #endif 1267 1268 static struct platform_driver tegra_smmu_driver = { 1269 .probe = tegra_smmu_probe, 1270 .remove = tegra_smmu_remove, 1271 .driver = { 1272 .owner = THIS_MODULE, 1273 .name = "tegra-smmu", 1274 .pm = &tegra_smmu_pm_ops, 1275 .of_match_table = of_match_ptr(tegra_smmu_of_match), 1276 }, 1277 }; 1278 1279 static int __devinit tegra_smmu_init(void) 1280 { 1281 bus_set_iommu(&platform_bus_type, &smmu_iommu_ops); 1282 return platform_driver_register(&tegra_smmu_driver); 1283 } 1284 1285 static void __exit tegra_smmu_exit(void) 1286 { 1287 platform_driver_unregister(&tegra_smmu_driver); 1288 } 1289 1290 subsys_initcall(tegra_smmu_init); 1291 module_exit(tegra_smmu_exit); 1292 1293 MODULE_DESCRIPTION("IOMMU API for SMMU in Tegra30"); 1294 MODULE_AUTHOR("Hiroshi DOYU <hdoyu@nvidia.com>"); 1295 MODULE_ALIAS("platform:tegra-smmu"); 1296 MODULE_LICENSE("GPL v2"); 1297